1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "llvm/Analysis/TargetTransformInfo.h" 10 #include "llvm/Analysis/CFG.h" 11 #include "llvm/Analysis/LoopIterator.h" 12 #include "llvm/Analysis/TargetTransformInfoImpl.h" 13 #include "llvm/IR/CFG.h" 14 #include "llvm/IR/Dominators.h" 15 #include "llvm/IR/Instruction.h" 16 #include "llvm/IR/Instructions.h" 17 #include "llvm/IR/IntrinsicInst.h" 18 #include "llvm/IR/Module.h" 19 #include "llvm/IR/Operator.h" 20 #include "llvm/IR/PatternMatch.h" 21 #include "llvm/InitializePasses.h" 22 #include "llvm/Support/CommandLine.h" 23 #include <utility> 24 25 using namespace llvm; 26 using namespace PatternMatch; 27 28 #define DEBUG_TYPE "tti" 29 30 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false), 31 cl::Hidden, 32 cl::desc("Recognize reduction patterns.")); 33 34 namespace { 35 /// No-op implementation of the TTI interface using the utility base 36 /// classes. 37 /// 38 /// This is used when no target specific information is available. 39 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> { 40 explicit NoTTIImpl(const DataLayout &DL) 41 : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {} 42 }; 43 } // namespace 44 45 bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) { 46 // If the loop has irreducible control flow, it can not be converted to 47 // Hardware loop. 48 LoopBlocksRPO RPOT(L); 49 RPOT.perform(&LI); 50 if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI)) 51 return false; 52 return true; 53 } 54 55 IntrinsicCostAttributes::IntrinsicCostAttributes( 56 Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost) 57 : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id), 58 ScalarizationCost(ScalarizationCost) { 59 60 if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI)) 61 FMF = FPMO->getFastMathFlags(); 62 63 Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end()); 64 FunctionType *FTy = CI.getCalledFunction()->getFunctionType(); 65 ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end()); 66 } 67 68 IntrinsicCostAttributes::IntrinsicCostAttributes(Intrinsic::ID Id, Type *RTy, 69 ArrayRef<Type *> Tys, 70 FastMathFlags Flags, 71 const IntrinsicInst *I, 72 InstructionCost ScalarCost) 73 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) { 74 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end()); 75 } 76 77 IntrinsicCostAttributes::IntrinsicCostAttributes(Intrinsic::ID Id, Type *Ty, 78 ArrayRef<const Value *> Args) 79 : RetTy(Ty), IID(Id) { 80 81 Arguments.insert(Arguments.begin(), Args.begin(), Args.end()); 82 ParamTys.reserve(Arguments.size()); 83 for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx) 84 ParamTys.push_back(Arguments[Idx]->getType()); 85 } 86 87 IntrinsicCostAttributes::IntrinsicCostAttributes(Intrinsic::ID Id, Type *RTy, 88 ArrayRef<const Value *> Args, 89 ArrayRef<Type *> Tys, 90 FastMathFlags Flags, 91 const IntrinsicInst *I, 92 InstructionCost ScalarCost) 93 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) { 94 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end()); 95 Arguments.insert(Arguments.begin(), Args.begin(), Args.end()); 96 } 97 98 bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE, 99 LoopInfo &LI, DominatorTree &DT, 100 bool ForceNestedLoop, 101 bool ForceHardwareLoopPHI) { 102 SmallVector<BasicBlock *, 4> ExitingBlocks; 103 L->getExitingBlocks(ExitingBlocks); 104 105 for (BasicBlock *BB : ExitingBlocks) { 106 // If we pass the updated counter back through a phi, we need to know 107 // which latch the updated value will be coming from. 108 if (!L->isLoopLatch(BB)) { 109 if (ForceHardwareLoopPHI || CounterInReg) 110 continue; 111 } 112 113 const SCEV *EC = SE.getExitCount(L, BB); 114 if (isa<SCEVCouldNotCompute>(EC)) 115 continue; 116 if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) { 117 if (ConstEC->getValue()->isZero()) 118 continue; 119 } else if (!SE.isLoopInvariant(EC, L)) 120 continue; 121 122 if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth()) 123 continue; 124 125 // If this exiting block is contained in a nested loop, it is not eligible 126 // for insertion of the branch-and-decrement since the inner loop would 127 // end up messing up the value in the CTR. 128 if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop) 129 continue; 130 131 // We now have a loop-invariant count of loop iterations (which is not the 132 // constant zero) for which we know that this loop will not exit via this 133 // existing block. 134 135 // We need to make sure that this block will run on every loop iteration. 136 // For this to be true, we must dominate all blocks with backedges. Such 137 // blocks are in-loop predecessors to the header block. 138 bool NotAlways = false; 139 for (BasicBlock *Pred : predecessors(L->getHeader())) { 140 if (!L->contains(Pred)) 141 continue; 142 143 if (!DT.dominates(BB, Pred)) { 144 NotAlways = true; 145 break; 146 } 147 } 148 149 if (NotAlways) 150 continue; 151 152 // Make sure this blocks ends with a conditional branch. 153 Instruction *TI = BB->getTerminator(); 154 if (!TI) 155 continue; 156 157 if (BranchInst *BI = dyn_cast<BranchInst>(TI)) { 158 if (!BI->isConditional()) 159 continue; 160 161 ExitBranch = BI; 162 } else 163 continue; 164 165 // Note that this block may not be the loop latch block, even if the loop 166 // has a latch block. 167 ExitBlock = BB; 168 ExitCount = EC; 169 break; 170 } 171 172 if (!ExitBlock) 173 return false; 174 return true; 175 } 176 177 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL) 178 : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {} 179 180 TargetTransformInfo::~TargetTransformInfo() = default; 181 182 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg) 183 : TTIImpl(std::move(Arg.TTIImpl)) {} 184 185 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) { 186 TTIImpl = std::move(RHS.TTIImpl); 187 return *this; 188 } 189 190 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const { 191 return TTIImpl->getInliningThresholdMultiplier(); 192 } 193 194 unsigned 195 TargetTransformInfo::adjustInliningThreshold(const CallBase *CB) const { 196 return TTIImpl->adjustInliningThreshold(CB); 197 } 198 199 int TargetTransformInfo::getInlinerVectorBonusPercent() const { 200 return TTIImpl->getInlinerVectorBonusPercent(); 201 } 202 203 InstructionCost 204 TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr, 205 ArrayRef<const Value *> Operands, 206 TTI::TargetCostKind CostKind) const { 207 return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind); 208 } 209 210 unsigned TargetTransformInfo::getEstimatedNumberOfCaseClusters( 211 const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, 212 BlockFrequencyInfo *BFI) const { 213 return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI); 214 } 215 216 InstructionCost 217 TargetTransformInfo::getUserCost(const User *U, 218 ArrayRef<const Value *> Operands, 219 enum TargetCostKind CostKind) const { 220 InstructionCost Cost = TTIImpl->getUserCost(U, Operands, CostKind); 221 assert((CostKind == TTI::TCK_RecipThroughput || Cost >= 0) && 222 "TTI should not produce negative costs!"); 223 return Cost; 224 } 225 226 BranchProbability TargetTransformInfo::getPredictableBranchThreshold() const { 227 return TTIImpl->getPredictableBranchThreshold(); 228 } 229 230 bool TargetTransformInfo::hasBranchDivergence() const { 231 return TTIImpl->hasBranchDivergence(); 232 } 233 234 bool TargetTransformInfo::useGPUDivergenceAnalysis() const { 235 return TTIImpl->useGPUDivergenceAnalysis(); 236 } 237 238 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const { 239 return TTIImpl->isSourceOfDivergence(V); 240 } 241 242 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const { 243 return TTIImpl->isAlwaysUniform(V); 244 } 245 246 unsigned TargetTransformInfo::getFlatAddressSpace() const { 247 return TTIImpl->getFlatAddressSpace(); 248 } 249 250 bool TargetTransformInfo::collectFlatAddressOperands( 251 SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const { 252 return TTIImpl->collectFlatAddressOperands(OpIndexes, IID); 253 } 254 255 bool TargetTransformInfo::isNoopAddrSpaceCast(unsigned FromAS, 256 unsigned ToAS) const { 257 return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS); 258 } 259 260 bool TargetTransformInfo::canHaveNonUndefGlobalInitializerInAddressSpace( 261 unsigned AS) const { 262 return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS); 263 } 264 265 unsigned TargetTransformInfo::getAssumedAddrSpace(const Value *V) const { 266 return TTIImpl->getAssumedAddrSpace(V); 267 } 268 269 std::pair<const Value *, unsigned> 270 TargetTransformInfo::getPredicatedAddrSpace(const Value *V) const { 271 return TTIImpl->getPredicatedAddrSpace(V); 272 } 273 274 Value *TargetTransformInfo::rewriteIntrinsicWithAddressSpace( 275 IntrinsicInst *II, Value *OldV, Value *NewV) const { 276 return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV); 277 } 278 279 bool TargetTransformInfo::isLoweredToCall(const Function *F) const { 280 return TTIImpl->isLoweredToCall(F); 281 } 282 283 bool TargetTransformInfo::isHardwareLoopProfitable( 284 Loop *L, ScalarEvolution &SE, AssumptionCache &AC, 285 TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const { 286 return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo); 287 } 288 289 bool TargetTransformInfo::preferPredicateOverEpilogue( 290 Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, 291 TargetLibraryInfo *TLI, DominatorTree *DT, 292 const LoopAccessInfo *LAI) const { 293 return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LAI); 294 } 295 296 bool TargetTransformInfo::emitGetActiveLaneMask() const { 297 return TTIImpl->emitGetActiveLaneMask(); 298 } 299 300 Optional<Instruction *> 301 TargetTransformInfo::instCombineIntrinsic(InstCombiner &IC, 302 IntrinsicInst &II) const { 303 return TTIImpl->instCombineIntrinsic(IC, II); 304 } 305 306 Optional<Value *> TargetTransformInfo::simplifyDemandedUseBitsIntrinsic( 307 InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, 308 bool &KnownBitsComputed) const { 309 return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known, 310 KnownBitsComputed); 311 } 312 313 Optional<Value *> TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic( 314 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, 315 APInt &UndefElts2, APInt &UndefElts3, 316 std::function<void(Instruction *, unsigned, APInt, APInt &)> 317 SimplifyAndSetOp) const { 318 return TTIImpl->simplifyDemandedVectorEltsIntrinsic( 319 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3, 320 SimplifyAndSetOp); 321 } 322 323 void TargetTransformInfo::getUnrollingPreferences( 324 Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP, 325 OptimizationRemarkEmitter *ORE) const { 326 return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE); 327 } 328 329 void TargetTransformInfo::getPeelingPreferences(Loop *L, ScalarEvolution &SE, 330 PeelingPreferences &PP) const { 331 return TTIImpl->getPeelingPreferences(L, SE, PP); 332 } 333 334 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const { 335 return TTIImpl->isLegalAddImmediate(Imm); 336 } 337 338 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const { 339 return TTIImpl->isLegalICmpImmediate(Imm); 340 } 341 342 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, 343 int64_t BaseOffset, 344 bool HasBaseReg, int64_t Scale, 345 unsigned AddrSpace, 346 Instruction *I) const { 347 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, 348 Scale, AddrSpace, I); 349 } 350 351 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const { 352 return TTIImpl->isLSRCostLess(C1, C2); 353 } 354 355 bool TargetTransformInfo::isNumRegsMajorCostOfLSR() const { 356 return TTIImpl->isNumRegsMajorCostOfLSR(); 357 } 358 359 bool TargetTransformInfo::isProfitableLSRChainElement(Instruction *I) const { 360 return TTIImpl->isProfitableLSRChainElement(I); 361 } 362 363 bool TargetTransformInfo::canMacroFuseCmp() const { 364 return TTIImpl->canMacroFuseCmp(); 365 } 366 367 bool TargetTransformInfo::canSaveCmp(Loop *L, BranchInst **BI, 368 ScalarEvolution *SE, LoopInfo *LI, 369 DominatorTree *DT, AssumptionCache *AC, 370 TargetLibraryInfo *LibInfo) const { 371 return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo); 372 } 373 374 TTI::AddressingModeKind 375 TargetTransformInfo::getPreferredAddressingMode(const Loop *L, 376 ScalarEvolution *SE) const { 377 return TTIImpl->getPreferredAddressingMode(L, SE); 378 } 379 380 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType, 381 Align Alignment) const { 382 return TTIImpl->isLegalMaskedStore(DataType, Alignment); 383 } 384 385 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType, 386 Align Alignment) const { 387 return TTIImpl->isLegalMaskedLoad(DataType, Alignment); 388 } 389 390 bool TargetTransformInfo::isLegalNTStore(Type *DataType, 391 Align Alignment) const { 392 return TTIImpl->isLegalNTStore(DataType, Alignment); 393 } 394 395 bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const { 396 return TTIImpl->isLegalNTLoad(DataType, Alignment); 397 } 398 399 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType, 400 Align Alignment) const { 401 return TTIImpl->isLegalMaskedGather(DataType, Alignment); 402 } 403 404 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType, 405 Align Alignment) const { 406 return TTIImpl->isLegalMaskedScatter(DataType, Alignment); 407 } 408 409 bool TargetTransformInfo::forceScalarizeMaskedGather(VectorType *DataType, 410 Align Alignment) const { 411 return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment); 412 } 413 414 bool TargetTransformInfo::forceScalarizeMaskedScatter(VectorType *DataType, 415 Align Alignment) const { 416 return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment); 417 } 418 419 bool TargetTransformInfo::isLegalMaskedCompressStore(Type *DataType) const { 420 return TTIImpl->isLegalMaskedCompressStore(DataType); 421 } 422 423 bool TargetTransformInfo::isLegalMaskedExpandLoad(Type *DataType) const { 424 return TTIImpl->isLegalMaskedExpandLoad(DataType); 425 } 426 427 bool TargetTransformInfo::enableOrderedReductions() const { 428 return TTIImpl->enableOrderedReductions(); 429 } 430 431 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const { 432 return TTIImpl->hasDivRemOp(DataType, IsSigned); 433 } 434 435 bool TargetTransformInfo::hasVolatileVariant(Instruction *I, 436 unsigned AddrSpace) const { 437 return TTIImpl->hasVolatileVariant(I, AddrSpace); 438 } 439 440 bool TargetTransformInfo::prefersVectorizedAddressing() const { 441 return TTIImpl->prefersVectorizedAddressing(); 442 } 443 444 InstructionCost TargetTransformInfo::getScalingFactorCost( 445 Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, 446 int64_t Scale, unsigned AddrSpace) const { 447 InstructionCost Cost = TTIImpl->getScalingFactorCost( 448 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace); 449 assert(Cost >= 0 && "TTI should not produce negative costs!"); 450 return Cost; 451 } 452 453 bool TargetTransformInfo::LSRWithInstrQueries() const { 454 return TTIImpl->LSRWithInstrQueries(); 455 } 456 457 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const { 458 return TTIImpl->isTruncateFree(Ty1, Ty2); 459 } 460 461 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const { 462 return TTIImpl->isProfitableToHoist(I); 463 } 464 465 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); } 466 467 bool TargetTransformInfo::isTypeLegal(Type *Ty) const { 468 return TTIImpl->isTypeLegal(Ty); 469 } 470 471 InstructionCost TargetTransformInfo::getRegUsageForType(Type *Ty) const { 472 return TTIImpl->getRegUsageForType(Ty); 473 } 474 475 bool TargetTransformInfo::shouldBuildLookupTables() const { 476 return TTIImpl->shouldBuildLookupTables(); 477 } 478 479 bool TargetTransformInfo::shouldBuildLookupTablesForConstant( 480 Constant *C) const { 481 return TTIImpl->shouldBuildLookupTablesForConstant(C); 482 } 483 484 bool TargetTransformInfo::shouldBuildRelLookupTables() const { 485 return TTIImpl->shouldBuildRelLookupTables(); 486 } 487 488 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const { 489 return TTIImpl->useColdCCForColdCall(F); 490 } 491 492 InstructionCost 493 TargetTransformInfo::getScalarizationOverhead(VectorType *Ty, 494 const APInt &DemandedElts, 495 bool Insert, bool Extract) const { 496 return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract); 497 } 498 499 InstructionCost TargetTransformInfo::getOperandsScalarizationOverhead( 500 ArrayRef<const Value *> Args, ArrayRef<Type *> Tys) const { 501 return TTIImpl->getOperandsScalarizationOverhead(Args, Tys); 502 } 503 504 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const { 505 return TTIImpl->supportsEfficientVectorElementLoadStore(); 506 } 507 508 bool TargetTransformInfo::enableAggressiveInterleaving( 509 bool LoopHasReductions) const { 510 return TTIImpl->enableAggressiveInterleaving(LoopHasReductions); 511 } 512 513 TargetTransformInfo::MemCmpExpansionOptions 514 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 515 return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp); 516 } 517 518 bool TargetTransformInfo::enableInterleavedAccessVectorization() const { 519 return TTIImpl->enableInterleavedAccessVectorization(); 520 } 521 522 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const { 523 return TTIImpl->enableMaskedInterleavedAccessVectorization(); 524 } 525 526 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const { 527 return TTIImpl->isFPVectorizationPotentiallyUnsafe(); 528 } 529 530 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context, 531 unsigned BitWidth, 532 unsigned AddressSpace, 533 Align Alignment, 534 bool *Fast) const { 535 return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, 536 AddressSpace, Alignment, Fast); 537 } 538 539 TargetTransformInfo::PopcntSupportKind 540 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const { 541 return TTIImpl->getPopcntSupport(IntTyWidthInBit); 542 } 543 544 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const { 545 return TTIImpl->haveFastSqrt(Ty); 546 } 547 548 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { 549 return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty); 550 } 551 552 InstructionCost TargetTransformInfo::getFPOpCost(Type *Ty) const { 553 InstructionCost Cost = TTIImpl->getFPOpCost(Ty); 554 assert(Cost >= 0 && "TTI should not produce negative costs!"); 555 return Cost; 556 } 557 558 InstructionCost TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, 559 unsigned Idx, 560 const APInt &Imm, 561 Type *Ty) const { 562 InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty); 563 assert(Cost >= 0 && "TTI should not produce negative costs!"); 564 return Cost; 565 } 566 567 InstructionCost 568 TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty, 569 TTI::TargetCostKind CostKind) const { 570 InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind); 571 assert(Cost >= 0 && "TTI should not produce negative costs!"); 572 return Cost; 573 } 574 575 InstructionCost TargetTransformInfo::getIntImmCostInst( 576 unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, 577 TTI::TargetCostKind CostKind, Instruction *Inst) const { 578 InstructionCost Cost = 579 TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst); 580 assert(Cost >= 0 && "TTI should not produce negative costs!"); 581 return Cost; 582 } 583 584 InstructionCost 585 TargetTransformInfo::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 586 const APInt &Imm, Type *Ty, 587 TTI::TargetCostKind CostKind) const { 588 InstructionCost Cost = 589 TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind); 590 assert(Cost >= 0 && "TTI should not produce negative costs!"); 591 return Cost; 592 } 593 594 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const { 595 return TTIImpl->getNumberOfRegisters(ClassID); 596 } 597 598 unsigned TargetTransformInfo::getRegisterClassForType(bool Vector, 599 Type *Ty) const { 600 return TTIImpl->getRegisterClassForType(Vector, Ty); 601 } 602 603 const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const { 604 return TTIImpl->getRegisterClassName(ClassID); 605 } 606 607 TypeSize TargetTransformInfo::getRegisterBitWidth( 608 TargetTransformInfo::RegisterKind K) const { 609 return TTIImpl->getRegisterBitWidth(K); 610 } 611 612 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const { 613 return TTIImpl->getMinVectorRegisterBitWidth(); 614 } 615 616 Optional<unsigned> TargetTransformInfo::getMaxVScale() const { 617 return TTIImpl->getMaxVScale(); 618 } 619 620 Optional<unsigned> TargetTransformInfo::getVScaleForTuning() const { 621 return TTIImpl->getVScaleForTuning(); 622 } 623 624 bool TargetTransformInfo::shouldMaximizeVectorBandwidth() const { 625 return TTIImpl->shouldMaximizeVectorBandwidth(); 626 } 627 628 ElementCount TargetTransformInfo::getMinimumVF(unsigned ElemWidth, 629 bool IsScalable) const { 630 return TTIImpl->getMinimumVF(ElemWidth, IsScalable); 631 } 632 633 unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth, 634 unsigned Opcode) const { 635 return TTIImpl->getMaximumVF(ElemWidth, Opcode); 636 } 637 638 bool TargetTransformInfo::shouldConsiderAddressTypePromotion( 639 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const { 640 return TTIImpl->shouldConsiderAddressTypePromotion( 641 I, AllowPromotionWithoutCommonHeader); 642 } 643 644 unsigned TargetTransformInfo::getCacheLineSize() const { 645 return TTIImpl->getCacheLineSize(); 646 } 647 648 llvm::Optional<unsigned> 649 TargetTransformInfo::getCacheSize(CacheLevel Level) const { 650 return TTIImpl->getCacheSize(Level); 651 } 652 653 llvm::Optional<unsigned> 654 TargetTransformInfo::getCacheAssociativity(CacheLevel Level) const { 655 return TTIImpl->getCacheAssociativity(Level); 656 } 657 658 unsigned TargetTransformInfo::getPrefetchDistance() const { 659 return TTIImpl->getPrefetchDistance(); 660 } 661 662 unsigned TargetTransformInfo::getMinPrefetchStride( 663 unsigned NumMemAccesses, unsigned NumStridedMemAccesses, 664 unsigned NumPrefetches, bool HasCall) const { 665 return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses, 666 NumPrefetches, HasCall); 667 } 668 669 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const { 670 return TTIImpl->getMaxPrefetchIterationsAhead(); 671 } 672 673 bool TargetTransformInfo::enableWritePrefetching() const { 674 return TTIImpl->enableWritePrefetching(); 675 } 676 677 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const { 678 return TTIImpl->getMaxInterleaveFactor(VF); 679 } 680 681 TargetTransformInfo::OperandValueKind 682 TargetTransformInfo::getOperandInfo(const Value *V, 683 OperandValueProperties &OpProps) { 684 OperandValueKind OpInfo = OK_AnyValue; 685 OpProps = OP_None; 686 687 if (const auto *CI = dyn_cast<ConstantInt>(V)) { 688 if (CI->getValue().isPowerOf2()) 689 OpProps = OP_PowerOf2; 690 return OK_UniformConstantValue; 691 } 692 693 // A broadcast shuffle creates a uniform value. 694 // TODO: Add support for non-zero index broadcasts. 695 // TODO: Add support for different source vector width. 696 if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V)) 697 if (ShuffleInst->isZeroEltSplat()) 698 OpInfo = OK_UniformValue; 699 700 const Value *Splat = getSplatValue(V); 701 702 // Check for a splat of a constant or for a non uniform vector of constants 703 // and check if the constant(s) are all powers of two. 704 if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) { 705 OpInfo = OK_NonUniformConstantValue; 706 if (Splat) { 707 OpInfo = OK_UniformConstantValue; 708 if (auto *CI = dyn_cast<ConstantInt>(Splat)) 709 if (CI->getValue().isPowerOf2()) 710 OpProps = OP_PowerOf2; 711 } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) { 712 OpProps = OP_PowerOf2; 713 for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) { 714 if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I))) 715 if (CI->getValue().isPowerOf2()) 716 continue; 717 OpProps = OP_None; 718 break; 719 } 720 } 721 } 722 723 // Check for a splat of a uniform value. This is not loop aware, so return 724 // true only for the obviously uniform cases (argument, globalvalue) 725 if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat))) 726 OpInfo = OK_UniformValue; 727 728 return OpInfo; 729 } 730 731 InstructionCost TargetTransformInfo::getArithmeticInstrCost( 732 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 733 OperandValueKind Opd1Info, OperandValueKind Opd2Info, 734 OperandValueProperties Opd1PropInfo, OperandValueProperties Opd2PropInfo, 735 ArrayRef<const Value *> Args, const Instruction *CxtI) const { 736 InstructionCost Cost = 737 TTIImpl->getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info, 738 Opd1PropInfo, Opd2PropInfo, Args, CxtI); 739 assert(Cost >= 0 && "TTI should not produce negative costs!"); 740 return Cost; 741 } 742 743 InstructionCost TargetTransformInfo::getShuffleCost(ShuffleKind Kind, 744 VectorType *Ty, 745 ArrayRef<int> Mask, 746 int Index, 747 VectorType *SubTp) const { 748 InstructionCost Cost = TTIImpl->getShuffleCost(Kind, Ty, Mask, Index, SubTp); 749 assert(Cost >= 0 && "TTI should not produce negative costs!"); 750 return Cost; 751 } 752 753 TTI::CastContextHint 754 TargetTransformInfo::getCastContextHint(const Instruction *I) { 755 if (!I) 756 return CastContextHint::None; 757 758 auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp, 759 unsigned GatScatOp) { 760 const Instruction *I = dyn_cast<Instruction>(V); 761 if (!I) 762 return CastContextHint::None; 763 764 if (I->getOpcode() == LdStOp) 765 return CastContextHint::Normal; 766 767 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) { 768 if (II->getIntrinsicID() == MaskedOp) 769 return TTI::CastContextHint::Masked; 770 if (II->getIntrinsicID() == GatScatOp) 771 return TTI::CastContextHint::GatherScatter; 772 } 773 774 return TTI::CastContextHint::None; 775 }; 776 777 switch (I->getOpcode()) { 778 case Instruction::ZExt: 779 case Instruction::SExt: 780 case Instruction::FPExt: 781 return getLoadStoreKind(I->getOperand(0), Instruction::Load, 782 Intrinsic::masked_load, Intrinsic::masked_gather); 783 case Instruction::Trunc: 784 case Instruction::FPTrunc: 785 if (I->hasOneUse()) 786 return getLoadStoreKind(*I->user_begin(), Instruction::Store, 787 Intrinsic::masked_store, 788 Intrinsic::masked_scatter); 789 break; 790 default: 791 return CastContextHint::None; 792 } 793 794 return TTI::CastContextHint::None; 795 } 796 797 InstructionCost TargetTransformInfo::getCastInstrCost( 798 unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH, 799 TTI::TargetCostKind CostKind, const Instruction *I) const { 800 assert((I == nullptr || I->getOpcode() == Opcode) && 801 "Opcode should reflect passed instruction."); 802 InstructionCost Cost = 803 TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I); 804 assert(Cost >= 0 && "TTI should not produce negative costs!"); 805 return Cost; 806 } 807 808 InstructionCost TargetTransformInfo::getExtractWithExtendCost( 809 unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const { 810 InstructionCost Cost = 811 TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index); 812 assert(Cost >= 0 && "TTI should not produce negative costs!"); 813 return Cost; 814 } 815 816 InstructionCost TargetTransformInfo::getCFInstrCost( 817 unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const { 818 assert((I == nullptr || I->getOpcode() == Opcode) && 819 "Opcode should reflect passed instruction."); 820 InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I); 821 assert(Cost >= 0 && "TTI should not produce negative costs!"); 822 return Cost; 823 } 824 825 InstructionCost TargetTransformInfo::getCmpSelInstrCost( 826 unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, 827 TTI::TargetCostKind CostKind, const Instruction *I) const { 828 assert((I == nullptr || I->getOpcode() == Opcode) && 829 "Opcode should reflect passed instruction."); 830 InstructionCost Cost = 831 TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 832 assert(Cost >= 0 && "TTI should not produce negative costs!"); 833 return Cost; 834 } 835 836 InstructionCost TargetTransformInfo::getVectorInstrCost(unsigned Opcode, 837 Type *Val, 838 unsigned Index) const { 839 InstructionCost Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index); 840 assert(Cost >= 0 && "TTI should not produce negative costs!"); 841 return Cost; 842 } 843 844 InstructionCost TargetTransformInfo::getReplicationShuffleCost( 845 Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, 846 TTI::TargetCostKind CostKind) { 847 InstructionCost Cost = TTIImpl->getReplicationShuffleCost( 848 EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind); 849 assert(Cost >= 0 && "TTI should not produce negative costs!"); 850 return Cost; 851 } 852 853 InstructionCost TargetTransformInfo::getMemoryOpCost( 854 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, 855 TTI::TargetCostKind CostKind, const Instruction *I) const { 856 assert((I == nullptr || I->getOpcode() == Opcode) && 857 "Opcode should reflect passed instruction."); 858 InstructionCost Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, 859 AddressSpace, CostKind, I); 860 assert(Cost >= 0 && "TTI should not produce negative costs!"); 861 return Cost; 862 } 863 864 InstructionCost TargetTransformInfo::getMaskedMemoryOpCost( 865 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, 866 TTI::TargetCostKind CostKind) const { 867 InstructionCost Cost = TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, 868 AddressSpace, CostKind); 869 assert(Cost >= 0 && "TTI should not produce negative costs!"); 870 return Cost; 871 } 872 873 InstructionCost TargetTransformInfo::getGatherScatterOpCost( 874 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, 875 Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const { 876 InstructionCost Cost = TTIImpl->getGatherScatterOpCost( 877 Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I); 878 assert(Cost >= 0 && "TTI should not produce negative costs!"); 879 return Cost; 880 } 881 882 InstructionCost TargetTransformInfo::getInterleavedMemoryOpCost( 883 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 884 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 885 bool UseMaskForCond, bool UseMaskForGaps) const { 886 InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost( 887 Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind, 888 UseMaskForCond, UseMaskForGaps); 889 assert(Cost >= 0 && "TTI should not produce negative costs!"); 890 return Cost; 891 } 892 893 InstructionCost 894 TargetTransformInfo::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 895 TTI::TargetCostKind CostKind) const { 896 InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind); 897 assert(Cost >= 0 && "TTI should not produce negative costs!"); 898 return Cost; 899 } 900 901 InstructionCost 902 TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy, 903 ArrayRef<Type *> Tys, 904 TTI::TargetCostKind CostKind) const { 905 InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind); 906 assert(Cost >= 0 && "TTI should not produce negative costs!"); 907 return Cost; 908 } 909 910 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const { 911 return TTIImpl->getNumberOfParts(Tp); 912 } 913 914 InstructionCost 915 TargetTransformInfo::getAddressComputationCost(Type *Tp, ScalarEvolution *SE, 916 const SCEV *Ptr) const { 917 InstructionCost Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr); 918 assert(Cost >= 0 && "TTI should not produce negative costs!"); 919 return Cost; 920 } 921 922 InstructionCost TargetTransformInfo::getMemcpyCost(const Instruction *I) const { 923 InstructionCost Cost = TTIImpl->getMemcpyCost(I); 924 assert(Cost >= 0 && "TTI should not produce negative costs!"); 925 return Cost; 926 } 927 928 InstructionCost TargetTransformInfo::getArithmeticReductionCost( 929 unsigned Opcode, VectorType *Ty, Optional<FastMathFlags> FMF, 930 TTI::TargetCostKind CostKind) const { 931 InstructionCost Cost = 932 TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind); 933 assert(Cost >= 0 && "TTI should not produce negative costs!"); 934 return Cost; 935 } 936 937 InstructionCost TargetTransformInfo::getMinMaxReductionCost( 938 VectorType *Ty, VectorType *CondTy, bool IsUnsigned, 939 TTI::TargetCostKind CostKind) const { 940 InstructionCost Cost = 941 TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind); 942 assert(Cost >= 0 && "TTI should not produce negative costs!"); 943 return Cost; 944 } 945 946 InstructionCost TargetTransformInfo::getExtendedAddReductionCost( 947 bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, 948 TTI::TargetCostKind CostKind) const { 949 return TTIImpl->getExtendedAddReductionCost(IsMLA, IsUnsigned, ResTy, Ty, 950 CostKind); 951 } 952 953 InstructionCost 954 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const { 955 return TTIImpl->getCostOfKeepingLiveOverCall(Tys); 956 } 957 958 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst, 959 MemIntrinsicInfo &Info) const { 960 return TTIImpl->getTgtMemIntrinsic(Inst, Info); 961 } 962 963 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const { 964 return TTIImpl->getAtomicMemIntrinsicMaxElementSize(); 965 } 966 967 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic( 968 IntrinsicInst *Inst, Type *ExpectedType) const { 969 return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType); 970 } 971 972 Type *TargetTransformInfo::getMemcpyLoopLoweringType( 973 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, 974 unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const { 975 return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace, 976 DestAddrSpace, SrcAlign, DestAlign); 977 } 978 979 void TargetTransformInfo::getMemcpyLoopResidualLoweringType( 980 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context, 981 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, 982 unsigned SrcAlign, unsigned DestAlign) const { 983 TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes, 984 SrcAddrSpace, DestAddrSpace, 985 SrcAlign, DestAlign); 986 } 987 988 bool TargetTransformInfo::areInlineCompatible(const Function *Caller, 989 const Function *Callee) const { 990 return TTIImpl->areInlineCompatible(Caller, Callee); 991 } 992 993 bool TargetTransformInfo::areTypesABICompatible( 994 const Function *Caller, const Function *Callee, 995 const ArrayRef<Type *> &Types) const { 996 return TTIImpl->areTypesABICompatible(Caller, Callee, Types); 997 } 998 999 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode, 1000 Type *Ty) const { 1001 return TTIImpl->isIndexedLoadLegal(Mode, Ty); 1002 } 1003 1004 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode, 1005 Type *Ty) const { 1006 return TTIImpl->isIndexedStoreLegal(Mode, Ty); 1007 } 1008 1009 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const { 1010 return TTIImpl->getLoadStoreVecRegBitWidth(AS); 1011 } 1012 1013 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const { 1014 return TTIImpl->isLegalToVectorizeLoad(LI); 1015 } 1016 1017 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const { 1018 return TTIImpl->isLegalToVectorizeStore(SI); 1019 } 1020 1021 bool TargetTransformInfo::isLegalToVectorizeLoadChain( 1022 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const { 1023 return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment, 1024 AddrSpace); 1025 } 1026 1027 bool TargetTransformInfo::isLegalToVectorizeStoreChain( 1028 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const { 1029 return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment, 1030 AddrSpace); 1031 } 1032 1033 bool TargetTransformInfo::isLegalToVectorizeReduction( 1034 const RecurrenceDescriptor &RdxDesc, ElementCount VF) const { 1035 return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF); 1036 } 1037 1038 bool TargetTransformInfo::isElementTypeLegalForScalableVector(Type *Ty) const { 1039 return TTIImpl->isElementTypeLegalForScalableVector(Ty); 1040 } 1041 1042 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF, 1043 unsigned LoadSize, 1044 unsigned ChainSizeInBytes, 1045 VectorType *VecTy) const { 1046 return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy); 1047 } 1048 1049 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF, 1050 unsigned StoreSize, 1051 unsigned ChainSizeInBytes, 1052 VectorType *VecTy) const { 1053 return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy); 1054 } 1055 1056 bool TargetTransformInfo::preferInLoopReduction(unsigned Opcode, Type *Ty, 1057 ReductionFlags Flags) const { 1058 return TTIImpl->preferInLoopReduction(Opcode, Ty, Flags); 1059 } 1060 1061 bool TargetTransformInfo::preferPredicatedReductionSelect( 1062 unsigned Opcode, Type *Ty, ReductionFlags Flags) const { 1063 return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags); 1064 } 1065 1066 TargetTransformInfo::VPLegalization 1067 TargetTransformInfo::getVPLegalizationStrategy(const VPIntrinsic &VPI) const { 1068 return TTIImpl->getVPLegalizationStrategy(VPI); 1069 } 1070 1071 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const { 1072 return TTIImpl->shouldExpandReduction(II); 1073 } 1074 1075 unsigned TargetTransformInfo::getGISelRematGlobalCost() const { 1076 return TTIImpl->getGISelRematGlobalCost(); 1077 } 1078 1079 bool TargetTransformInfo::supportsScalableVectors() const { 1080 return TTIImpl->supportsScalableVectors(); 1081 } 1082 1083 bool TargetTransformInfo::enableScalableVectorization() const { 1084 return TTIImpl->enableScalableVectorization(); 1085 } 1086 1087 bool TargetTransformInfo::hasActiveVectorLength(unsigned Opcode, Type *DataType, 1088 Align Alignment) const { 1089 return TTIImpl->hasActiveVectorLength(Opcode, DataType, Alignment); 1090 } 1091 1092 InstructionCost 1093 TargetTransformInfo::getInstructionLatency(const Instruction *I) const { 1094 return TTIImpl->getInstructionLatency(I); 1095 } 1096 1097 InstructionCost 1098 TargetTransformInfo::getInstructionThroughput(const Instruction *I) const { 1099 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 1100 1101 switch (I->getOpcode()) { 1102 case Instruction::GetElementPtr: 1103 case Instruction::Ret: 1104 case Instruction::PHI: 1105 case Instruction::Br: 1106 case Instruction::Add: 1107 case Instruction::FAdd: 1108 case Instruction::Sub: 1109 case Instruction::FSub: 1110 case Instruction::Mul: 1111 case Instruction::FMul: 1112 case Instruction::UDiv: 1113 case Instruction::SDiv: 1114 case Instruction::FDiv: 1115 case Instruction::URem: 1116 case Instruction::SRem: 1117 case Instruction::FRem: 1118 case Instruction::Shl: 1119 case Instruction::LShr: 1120 case Instruction::AShr: 1121 case Instruction::And: 1122 case Instruction::Or: 1123 case Instruction::Xor: 1124 case Instruction::FNeg: 1125 case Instruction::Select: 1126 case Instruction::ICmp: 1127 case Instruction::FCmp: 1128 case Instruction::Store: 1129 case Instruction::Load: 1130 case Instruction::ZExt: 1131 case Instruction::SExt: 1132 case Instruction::FPToUI: 1133 case Instruction::FPToSI: 1134 case Instruction::FPExt: 1135 case Instruction::PtrToInt: 1136 case Instruction::IntToPtr: 1137 case Instruction::SIToFP: 1138 case Instruction::UIToFP: 1139 case Instruction::Trunc: 1140 case Instruction::FPTrunc: 1141 case Instruction::BitCast: 1142 case Instruction::AddrSpaceCast: 1143 case Instruction::ExtractElement: 1144 case Instruction::InsertElement: 1145 case Instruction::ExtractValue: 1146 case Instruction::ShuffleVector: 1147 case Instruction::Call: 1148 case Instruction::Switch: 1149 return getUserCost(I, CostKind); 1150 default: 1151 // We don't have any information on this instruction. 1152 return -1; 1153 } 1154 } 1155 1156 TargetTransformInfo::Concept::~Concept() = default; 1157 1158 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {} 1159 1160 TargetIRAnalysis::TargetIRAnalysis( 1161 std::function<Result(const Function &)> TTICallback) 1162 : TTICallback(std::move(TTICallback)) {} 1163 1164 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F, 1165 FunctionAnalysisManager &) { 1166 return TTICallback(F); 1167 } 1168 1169 AnalysisKey TargetIRAnalysis::Key; 1170 1171 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) { 1172 return Result(F.getParent()->getDataLayout()); 1173 } 1174 1175 // Register the basic pass. 1176 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti", 1177 "Target Transform Information", false, true) 1178 char TargetTransformInfoWrapperPass::ID = 0; 1179 1180 void TargetTransformInfoWrapperPass::anchor() {} 1181 1182 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass() 1183 : ImmutablePass(ID) { 1184 initializeTargetTransformInfoWrapperPassPass( 1185 *PassRegistry::getPassRegistry()); 1186 } 1187 1188 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass( 1189 TargetIRAnalysis TIRA) 1190 : ImmutablePass(ID), TIRA(std::move(TIRA)) { 1191 initializeTargetTransformInfoWrapperPassPass( 1192 *PassRegistry::getPassRegistry()); 1193 } 1194 1195 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) { 1196 FunctionAnalysisManager DummyFAM; 1197 TTI = TIRA.run(F, DummyFAM); 1198 return *TTI; 1199 } 1200 1201 ImmutablePass * 1202 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) { 1203 return new TargetTransformInfoWrapperPass(std::move(TIRA)); 1204 } 1205