1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/Analysis/TargetTransformInfo.h"
10 #include "llvm/Analysis/CFG.h"
11 #include "llvm/Analysis/LoopIterator.h"
12 #include "llvm/Analysis/TargetTransformInfoImpl.h"
13 #include "llvm/IR/CFG.h"
14 #include "llvm/IR/CallSite.h"
15 #include "llvm/IR/DataLayout.h"
16 #include "llvm/IR/Instruction.h"
17 #include "llvm/IR/Instructions.h"
18 #include "llvm/IR/IntrinsicInst.h"
19 #include "llvm/IR/Module.h"
20 #include "llvm/IR/Operator.h"
21 #include "llvm/IR/PatternMatch.h"
22 #include "llvm/InitializePasses.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include <utility>
26 
27 using namespace llvm;
28 using namespace PatternMatch;
29 
30 #define DEBUG_TYPE "tti"
31 
32 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
33                                      cl::Hidden,
34                                      cl::desc("Recognize reduction patterns."));
35 
36 namespace {
37 /// No-op implementation of the TTI interface using the utility base
38 /// classes.
39 ///
40 /// This is used when no target specific information is available.
41 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
42   explicit NoTTIImpl(const DataLayout &DL)
43       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
44 };
45 }
46 
47 bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) {
48   // If the loop has irreducible control flow, it can not be converted to
49   // Hardware loop.
50   LoopBlocksRPO RPOT(L);
51   RPOT.perform(&LI);
52   if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
53     return false;
54   return true;
55 }
56 
57 bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
58                                                LoopInfo &LI, DominatorTree &DT,
59                                                bool ForceNestedLoop,
60                                                bool ForceHardwareLoopPHI) {
61   SmallVector<BasicBlock *, 4> ExitingBlocks;
62   L->getExitingBlocks(ExitingBlocks);
63 
64   for (BasicBlock *BB : ExitingBlocks) {
65     // If we pass the updated counter back through a phi, we need to know
66     // which latch the updated value will be coming from.
67     if (!L->isLoopLatch(BB)) {
68       if (ForceHardwareLoopPHI || CounterInReg)
69         continue;
70     }
71 
72     const SCEV *EC = SE.getExitCount(L, BB);
73     if (isa<SCEVCouldNotCompute>(EC))
74       continue;
75     if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
76       if (ConstEC->getValue()->isZero())
77         continue;
78     } else if (!SE.isLoopInvariant(EC, L))
79       continue;
80 
81     if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
82       continue;
83 
84     // If this exiting block is contained in a nested loop, it is not eligible
85     // for insertion of the branch-and-decrement since the inner loop would
86     // end up messing up the value in the CTR.
87     if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
88       continue;
89 
90     // We now have a loop-invariant count of loop iterations (which is not the
91     // constant zero) for which we know that this loop will not exit via this
92     // existing block.
93 
94     // We need to make sure that this block will run on every loop iteration.
95     // For this to be true, we must dominate all blocks with backedges. Such
96     // blocks are in-loop predecessors to the header block.
97     bool NotAlways = false;
98     for (BasicBlock *Pred : predecessors(L->getHeader())) {
99       if (!L->contains(Pred))
100         continue;
101 
102       if (!DT.dominates(BB, Pred)) {
103         NotAlways = true;
104         break;
105       }
106     }
107 
108     if (NotAlways)
109       continue;
110 
111     // Make sure this blocks ends with a conditional branch.
112     Instruction *TI = BB->getTerminator();
113     if (!TI)
114       continue;
115 
116     if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
117       if (!BI->isConditional())
118         continue;
119 
120       ExitBranch = BI;
121     } else
122       continue;
123 
124     // Note that this block may not be the loop latch block, even if the loop
125     // has a latch block.
126     ExitBlock = BB;
127     ExitCount = EC;
128     break;
129   }
130 
131   if (!ExitBlock)
132     return false;
133   return true;
134 }
135 
136 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
137     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
138 
139 TargetTransformInfo::~TargetTransformInfo() {}
140 
141 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
142     : TTIImpl(std::move(Arg.TTIImpl)) {}
143 
144 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
145   TTIImpl = std::move(RHS.TTIImpl);
146   return *this;
147 }
148 
149 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
150                                           Type *OpTy) const {
151   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
152   assert(Cost >= 0 && "TTI should not produce negative costs!");
153   return Cost;
154 }
155 
156 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
157   return TTIImpl->getInliningThresholdMultiplier();
158 }
159 
160 int TargetTransformInfo::getInlinerVectorBonusPercent() const {
161   return TTIImpl->getInlinerVectorBonusPercent();
162 }
163 
164 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
165                                     ArrayRef<const Value *> Operands) const {
166   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
167 }
168 
169 int TargetTransformInfo::getExtCost(const Instruction *I,
170                                     const Value *Src) const {
171   return TTIImpl->getExtCost(I, Src);
172 }
173 
174 int TargetTransformInfo::getIntrinsicCost(
175     Intrinsic::ID IID, Type *RetTy, ArrayRef<const Value *> Arguments,
176     const User *U) const {
177   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments, U);
178   assert(Cost >= 0 && "TTI should not produce negative costs!");
179   return Cost;
180 }
181 
182 unsigned
183 TargetTransformInfo::getEstimatedNumberOfCaseClusters(
184     const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
185     BlockFrequencyInfo *BFI) const {
186   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
187 }
188 
189 int TargetTransformInfo::getUserCost(const User *U,
190     ArrayRef<const Value *> Operands) const {
191   int Cost = TTIImpl->getUserCost(U, Operands);
192   assert(Cost >= 0 && "TTI should not produce negative costs!");
193   return Cost;
194 }
195 
196 bool TargetTransformInfo::hasBranchDivergence() const {
197   return TTIImpl->hasBranchDivergence();
198 }
199 
200 bool TargetTransformInfo::useGPUDivergenceAnalysis() const {
201   return TTIImpl->useGPUDivergenceAnalysis();
202 }
203 
204 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
205   return TTIImpl->isSourceOfDivergence(V);
206 }
207 
208 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
209   return TTIImpl->isAlwaysUniform(V);
210 }
211 
212 unsigned TargetTransformInfo::getFlatAddressSpace() const {
213   return TTIImpl->getFlatAddressSpace();
214 }
215 
216 bool TargetTransformInfo::collectFlatAddressOperands(
217   SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const  {
218   return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
219 }
220 
221 bool TargetTransformInfo::rewriteIntrinsicWithAddressSpace(
222   IntrinsicInst *II, Value *OldV, Value *NewV) const {
223   return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
224 }
225 
226 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
227   return TTIImpl->isLoweredToCall(F);
228 }
229 
230 bool TargetTransformInfo::isHardwareLoopProfitable(
231   Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
232   TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
233   return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
234 }
235 
236 bool TargetTransformInfo::preferPredicateOverEpilogue(Loop *L, LoopInfo *LI,
237     ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI,
238     DominatorTree *DT, const LoopAccessInfo *LAI) const {
239   return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LAI);
240 }
241 
242 void TargetTransformInfo::getUnrollingPreferences(
243     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
244   return TTIImpl->getUnrollingPreferences(L, SE, UP);
245 }
246 
247 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
248   return TTIImpl->isLegalAddImmediate(Imm);
249 }
250 
251 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
252   return TTIImpl->isLegalICmpImmediate(Imm);
253 }
254 
255 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
256                                                 int64_t BaseOffset,
257                                                 bool HasBaseReg,
258                                                 int64_t Scale,
259                                                 unsigned AddrSpace,
260                                                 Instruction *I) const {
261   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
262                                         Scale, AddrSpace, I);
263 }
264 
265 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
266   return TTIImpl->isLSRCostLess(C1, C2);
267 }
268 
269 bool TargetTransformInfo::canMacroFuseCmp() const {
270   return TTIImpl->canMacroFuseCmp();
271 }
272 
273 bool TargetTransformInfo::canSaveCmp(Loop *L, BranchInst **BI,
274                                      ScalarEvolution *SE, LoopInfo *LI,
275                                      DominatorTree *DT, AssumptionCache *AC,
276                                      TargetLibraryInfo *LibInfo) const {
277   return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
278 }
279 
280 bool TargetTransformInfo::shouldFavorPostInc() const {
281   return TTIImpl->shouldFavorPostInc();
282 }
283 
284 bool TargetTransformInfo::shouldFavorBackedgeIndex(const Loop *L) const {
285   return TTIImpl->shouldFavorBackedgeIndex(L);
286 }
287 
288 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType,
289                                              MaybeAlign Alignment) const {
290   return TTIImpl->isLegalMaskedStore(DataType, Alignment);
291 }
292 
293 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType,
294                                             MaybeAlign Alignment) const {
295   return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
296 }
297 
298 bool TargetTransformInfo::isLegalNTStore(Type *DataType,
299                                          Align Alignment) const {
300   return TTIImpl->isLegalNTStore(DataType, Alignment);
301 }
302 
303 bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
304   return TTIImpl->isLegalNTLoad(DataType, Alignment);
305 }
306 
307 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType,
308                                               MaybeAlign Alignment) const {
309   return TTIImpl->isLegalMaskedGather(DataType, Alignment);
310 }
311 
312 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType,
313                                                MaybeAlign Alignment) const {
314   return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
315 }
316 
317 bool TargetTransformInfo::isLegalMaskedCompressStore(Type *DataType) const {
318   return TTIImpl->isLegalMaskedCompressStore(DataType);
319 }
320 
321 bool TargetTransformInfo::isLegalMaskedExpandLoad(Type *DataType) const {
322   return TTIImpl->isLegalMaskedExpandLoad(DataType);
323 }
324 
325 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
326   return TTIImpl->hasDivRemOp(DataType, IsSigned);
327 }
328 
329 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
330                                              unsigned AddrSpace) const {
331   return TTIImpl->hasVolatileVariant(I, AddrSpace);
332 }
333 
334 bool TargetTransformInfo::prefersVectorizedAddressing() const {
335   return TTIImpl->prefersVectorizedAddressing();
336 }
337 
338 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
339                                               int64_t BaseOffset,
340                                               bool HasBaseReg,
341                                               int64_t Scale,
342                                               unsigned AddrSpace) const {
343   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
344                                            Scale, AddrSpace);
345   assert(Cost >= 0 && "TTI should not produce negative costs!");
346   return Cost;
347 }
348 
349 bool TargetTransformInfo::LSRWithInstrQueries() const {
350   return TTIImpl->LSRWithInstrQueries();
351 }
352 
353 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
354   return TTIImpl->isTruncateFree(Ty1, Ty2);
355 }
356 
357 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
358   return TTIImpl->isProfitableToHoist(I);
359 }
360 
361 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
362 
363 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
364   return TTIImpl->isTypeLegal(Ty);
365 }
366 
367 bool TargetTransformInfo::shouldBuildLookupTables() const {
368   return TTIImpl->shouldBuildLookupTables();
369 }
370 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(Constant *C) const {
371   return TTIImpl->shouldBuildLookupTablesForConstant(C);
372 }
373 
374 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
375   return TTIImpl->useColdCCForColdCall(F);
376 }
377 
378 unsigned TargetTransformInfo::
379 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
380   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
381 }
382 
383 unsigned TargetTransformInfo::
384 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
385                                  unsigned VF) const {
386   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
387 }
388 
389 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
390   return TTIImpl->supportsEfficientVectorElementLoadStore();
391 }
392 
393 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
394   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
395 }
396 
397 TargetTransformInfo::MemCmpExpansionOptions
398 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
399   return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
400 }
401 
402 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
403   return TTIImpl->enableInterleavedAccessVectorization();
404 }
405 
406 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const {
407   return TTIImpl->enableMaskedInterleavedAccessVectorization();
408 }
409 
410 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
411   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
412 }
413 
414 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
415                                                          unsigned BitWidth,
416                                                          unsigned AddressSpace,
417                                                          unsigned Alignment,
418                                                          bool *Fast) const {
419   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
420                                                  Alignment, Fast);
421 }
422 
423 TargetTransformInfo::PopcntSupportKind
424 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
425   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
426 }
427 
428 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
429   return TTIImpl->haveFastSqrt(Ty);
430 }
431 
432 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
433   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
434 }
435 
436 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
437   int Cost = TTIImpl->getFPOpCost(Ty);
438   assert(Cost >= 0 && "TTI should not produce negative costs!");
439   return Cost;
440 }
441 
442 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
443                                                const APInt &Imm,
444                                                Type *Ty) const {
445   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
446   assert(Cost >= 0 && "TTI should not produce negative costs!");
447   return Cost;
448 }
449 
450 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
451   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
452   assert(Cost >= 0 && "TTI should not produce negative costs!");
453   return Cost;
454 }
455 
456 int TargetTransformInfo::getIntImmCostInst(unsigned Opcode, unsigned Idx,
457                                            const APInt &Imm, Type *Ty) const {
458   int Cost = TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty);
459   assert(Cost >= 0 && "TTI should not produce negative costs!");
460   return Cost;
461 }
462 
463 int TargetTransformInfo::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
464                                              const APInt &Imm, Type *Ty) const {
465   int Cost = TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty);
466   assert(Cost >= 0 && "TTI should not produce negative costs!");
467   return Cost;
468 }
469 
470 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
471   return TTIImpl->getNumberOfRegisters(ClassID);
472 }
473 
474 unsigned TargetTransformInfo::getRegisterClassForType(bool Vector, Type *Ty) const {
475   return TTIImpl->getRegisterClassForType(Vector, Ty);
476 }
477 
478 const char* TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
479   return TTIImpl->getRegisterClassName(ClassID);
480 }
481 
482 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
483   return TTIImpl->getRegisterBitWidth(Vector);
484 }
485 
486 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
487   return TTIImpl->getMinVectorRegisterBitWidth();
488 }
489 
490 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
491   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
492 }
493 
494 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
495   return TTIImpl->getMinimumVF(ElemWidth);
496 }
497 
498 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
499     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
500   return TTIImpl->shouldConsiderAddressTypePromotion(
501       I, AllowPromotionWithoutCommonHeader);
502 }
503 
504 unsigned TargetTransformInfo::getCacheLineSize() const {
505   return TTIImpl->getCacheLineSize();
506 }
507 
508 llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
509   const {
510   return TTIImpl->getCacheSize(Level);
511 }
512 
513 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
514   CacheLevel Level) const {
515   return TTIImpl->getCacheAssociativity(Level);
516 }
517 
518 unsigned TargetTransformInfo::getPrefetchDistance() const {
519   return TTIImpl->getPrefetchDistance();
520 }
521 
522 unsigned TargetTransformInfo::getMinPrefetchStride(unsigned NumMemAccesses,
523                                                   unsigned NumStridedMemAccesses,
524                                                    unsigned NumPrefetches,
525                                                    bool HasCall) const {
526   return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
527                                        NumPrefetches, HasCall);
528 }
529 
530 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
531   return TTIImpl->getMaxPrefetchIterationsAhead();
532 }
533 
534 bool TargetTransformInfo::enableWritePrefetching() const {
535   return TTIImpl->enableWritePrefetching();
536 }
537 
538 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
539   return TTIImpl->getMaxInterleaveFactor(VF);
540 }
541 
542 TargetTransformInfo::OperandValueKind
543 TargetTransformInfo::getOperandInfo(Value *V, OperandValueProperties &OpProps) {
544   OperandValueKind OpInfo = OK_AnyValue;
545   OpProps = OP_None;
546 
547   if (auto *CI = dyn_cast<ConstantInt>(V)) {
548     if (CI->getValue().isPowerOf2())
549       OpProps = OP_PowerOf2;
550     return OK_UniformConstantValue;
551   }
552 
553   // A broadcast shuffle creates a uniform value.
554   // TODO: Add support for non-zero index broadcasts.
555   // TODO: Add support for different source vector width.
556   if (auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
557     if (ShuffleInst->isZeroEltSplat())
558       OpInfo = OK_UniformValue;
559 
560   const Value *Splat = getSplatValue(V);
561 
562   // Check for a splat of a constant or for a non uniform vector of constants
563   // and check if the constant(s) are all powers of two.
564   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
565     OpInfo = OK_NonUniformConstantValue;
566     if (Splat) {
567       OpInfo = OK_UniformConstantValue;
568       if (auto *CI = dyn_cast<ConstantInt>(Splat))
569         if (CI->getValue().isPowerOf2())
570           OpProps = OP_PowerOf2;
571     } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
572       OpProps = OP_PowerOf2;
573       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
574         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
575           if (CI->getValue().isPowerOf2())
576             continue;
577         OpProps = OP_None;
578         break;
579       }
580     }
581   }
582 
583   // Check for a splat of a uniform value. This is not loop aware, so return
584   // true only for the obviously uniform cases (argument, globalvalue)
585   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
586     OpInfo = OK_UniformValue;
587 
588   return OpInfo;
589 }
590 
591 int TargetTransformInfo::getArithmeticInstrCost(
592     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
593     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
594     OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
595     const Instruction *CxtI) const {
596   int Cost = TTIImpl->getArithmeticInstrCost(
597       Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo, Args, CxtI);
598   assert(Cost >= 0 && "TTI should not produce negative costs!");
599   return Cost;
600 }
601 
602 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
603                                         Type *SubTp) const {
604   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
605   assert(Cost >= 0 && "TTI should not produce negative costs!");
606   return Cost;
607 }
608 
609 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
610                                  Type *Src, const Instruction *I) const {
611   assert ((I == nullptr || I->getOpcode() == Opcode) &&
612           "Opcode should reflect passed instruction.");
613   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
614   assert(Cost >= 0 && "TTI should not produce negative costs!");
615   return Cost;
616 }
617 
618 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
619                                                   VectorType *VecTy,
620                                                   unsigned Index) const {
621   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
622   assert(Cost >= 0 && "TTI should not produce negative costs!");
623   return Cost;
624 }
625 
626 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
627   int Cost = TTIImpl->getCFInstrCost(Opcode);
628   assert(Cost >= 0 && "TTI should not produce negative costs!");
629   return Cost;
630 }
631 
632 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
633                                  Type *CondTy, const Instruction *I) const {
634   assert ((I == nullptr || I->getOpcode() == Opcode) &&
635           "Opcode should reflect passed instruction.");
636   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
637   assert(Cost >= 0 && "TTI should not produce negative costs!");
638   return Cost;
639 }
640 
641 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
642                                             unsigned Index) const {
643   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
644   assert(Cost >= 0 && "TTI should not produce negative costs!");
645   return Cost;
646 }
647 
648 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
649                                          MaybeAlign Alignment,
650                                          unsigned AddressSpace,
651                                          const Instruction *I) const {
652   assert ((I == nullptr || I->getOpcode() == Opcode) &&
653           "Opcode should reflect passed instruction.");
654   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
655   assert(Cost >= 0 && "TTI should not produce negative costs!");
656   return Cost;
657 }
658 
659 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
660                                                unsigned Alignment,
661                                                unsigned AddressSpace) const {
662   int Cost =
663       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
664   assert(Cost >= 0 && "TTI should not produce negative costs!");
665   return Cost;
666 }
667 
668 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
669                                                 Value *Ptr, bool VariableMask,
670                                                 unsigned Alignment,
671                                                 const Instruction *I) const {
672   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
673                                              Alignment, I);
674   assert(Cost >= 0 && "TTI should not produce negative costs!");
675   return Cost;
676 }
677 
678 int TargetTransformInfo::getInterleavedMemoryOpCost(
679     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
680     unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond,
681     bool UseMaskForGaps) const {
682   int Cost = TTIImpl->getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
683                                                  Alignment, AddressSpace,
684                                                  UseMaskForCond,
685                                                  UseMaskForGaps);
686   assert(Cost >= 0 && "TTI should not produce negative costs!");
687   return Cost;
688 }
689 
690 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
691                                                ArrayRef<Type *> Tys,
692                                                FastMathFlags FMF,
693                                                unsigned ScalarizationCostPassed,
694                                                const Instruction *I) const {
695   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
696                                             ScalarizationCostPassed, I);
697   assert(Cost >= 0 && "TTI should not produce negative costs!");
698   return Cost;
699 }
700 
701 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
702                                                ArrayRef<Value *> Args,
703                                                FastMathFlags FMF, unsigned VF,
704                                                const Instruction *I) const {
705   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF, I);
706   assert(Cost >= 0 && "TTI should not produce negative costs!");
707   return Cost;
708 }
709 
710 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
711                                           ArrayRef<Type *> Tys) const {
712   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
713   assert(Cost >= 0 && "TTI should not produce negative costs!");
714   return Cost;
715 }
716 
717 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
718   return TTIImpl->getNumberOfParts(Tp);
719 }
720 
721 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
722                                                    ScalarEvolution *SE,
723                                                    const SCEV *Ptr) const {
724   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
725   assert(Cost >= 0 && "TTI should not produce negative costs!");
726   return Cost;
727 }
728 
729 int TargetTransformInfo::getMemcpyCost(const Instruction *I) const {
730   int Cost = TTIImpl->getMemcpyCost(I);
731   assert(Cost >= 0 && "TTI should not produce negative costs!");
732   return Cost;
733 }
734 
735 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
736                                                     bool IsPairwiseForm) const {
737   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
738   assert(Cost >= 0 && "TTI should not produce negative costs!");
739   return Cost;
740 }
741 
742 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
743                                                 bool IsPairwiseForm,
744                                                 bool IsUnsigned) const {
745   int Cost =
746       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
747   assert(Cost >= 0 && "TTI should not produce negative costs!");
748   return Cost;
749 }
750 
751 unsigned
752 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
753   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
754 }
755 
756 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
757                                              MemIntrinsicInfo &Info) const {
758   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
759 }
760 
761 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
762   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
763 }
764 
765 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
766     IntrinsicInst *Inst, Type *ExpectedType) const {
767   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
768 }
769 
770 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
771                                                      Value *Length,
772                                                      unsigned SrcAddrSpace,
773                                                      unsigned DestAddrSpace,
774                                                      unsigned SrcAlign,
775                                                      unsigned DestAlign) const {
776   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
777                                             DestAddrSpace, SrcAlign,
778                                             DestAlign);
779 }
780 
781 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
782     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
783     unsigned RemainingBytes,
784     unsigned SrcAddrSpace,
785     unsigned DestAddrSpace,
786     unsigned SrcAlign, unsigned DestAlign) const {
787   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
788                                              SrcAddrSpace, DestAddrSpace,
789                                              SrcAlign, DestAlign);
790 }
791 
792 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
793                                               const Function *Callee) const {
794   return TTIImpl->areInlineCompatible(Caller, Callee);
795 }
796 
797 bool TargetTransformInfo::areFunctionArgsABICompatible(
798     const Function *Caller, const Function *Callee,
799     SmallPtrSetImpl<Argument *> &Args) const {
800   return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
801 }
802 
803 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
804                                              Type *Ty) const {
805   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
806 }
807 
808 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
809                                               Type *Ty) const {
810   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
811 }
812 
813 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
814   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
815 }
816 
817 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
818   return TTIImpl->isLegalToVectorizeLoad(LI);
819 }
820 
821 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
822   return TTIImpl->isLegalToVectorizeStore(SI);
823 }
824 
825 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
826     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
827   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
828                                               AddrSpace);
829 }
830 
831 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
832     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
833   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
834                                                AddrSpace);
835 }
836 
837 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
838                                                   unsigned LoadSize,
839                                                   unsigned ChainSizeInBytes,
840                                                   VectorType *VecTy) const {
841   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
842 }
843 
844 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
845                                                    unsigned StoreSize,
846                                                    unsigned ChainSizeInBytes,
847                                                    VectorType *VecTy) const {
848   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
849 }
850 
851 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode,
852                                                 Type *Ty, ReductionFlags Flags) const {
853   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
854 }
855 
856 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
857   return TTIImpl->shouldExpandReduction(II);
858 }
859 
860 unsigned TargetTransformInfo::getGISelRematGlobalCost() const {
861   return TTIImpl->getGISelRematGlobalCost();
862 }
863 
864 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
865   return TTIImpl->getInstructionLatency(I);
866 }
867 
868 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
869                                      unsigned Level) {
870   // We don't need a shuffle if we just want to have element 0 in position 0 of
871   // the vector.
872   if (!SI && Level == 0 && IsLeft)
873     return true;
874   else if (!SI)
875     return false;
876 
877   SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
878 
879   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
880   // we look at the left or right side.
881   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
882     Mask[i] = val;
883 
884   ArrayRef<int> ActualMask = SI->getShuffleMask();
885   return Mask == ActualMask;
886 }
887 
888 namespace {
889 /// Kind of the reduction data.
890 enum ReductionKind {
891   RK_None,           /// Not a reduction.
892   RK_Arithmetic,     /// Binary reduction data.
893   RK_MinMax,         /// Min/max reduction data.
894   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
895 };
896 /// Contains opcode + LHS/RHS parts of the reduction operations.
897 struct ReductionData {
898   ReductionData() = delete;
899   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
900       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
901     assert(Kind != RK_None && "expected binary or min/max reduction only.");
902   }
903   unsigned Opcode = 0;
904   Value *LHS = nullptr;
905   Value *RHS = nullptr;
906   ReductionKind Kind = RK_None;
907   bool hasSameData(ReductionData &RD) const {
908     return Kind == RD.Kind && Opcode == RD.Opcode;
909   }
910 };
911 } // namespace
912 
913 static Optional<ReductionData> getReductionData(Instruction *I) {
914   Value *L, *R;
915   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
916     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
917   if (auto *SI = dyn_cast<SelectInst>(I)) {
918     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
919         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
920         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
921         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
922         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
923         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
924       auto *CI = cast<CmpInst>(SI->getCondition());
925       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
926     }
927     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
928         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
929       auto *CI = cast<CmpInst>(SI->getCondition());
930       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
931     }
932   }
933   return llvm::None;
934 }
935 
936 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
937                                                    unsigned Level,
938                                                    unsigned NumLevels) {
939   // Match one level of pairwise operations.
940   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
941   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
942   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
943   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
944   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
945   if (!I)
946     return RK_None;
947 
948   assert(I->getType()->isVectorTy() && "Expecting a vector type");
949 
950   Optional<ReductionData> RD = getReductionData(I);
951   if (!RD)
952     return RK_None;
953 
954   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
955   if (!LS && Level)
956     return RK_None;
957   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
958   if (!RS && Level)
959     return RK_None;
960 
961   // On level 0 we can omit one shufflevector instruction.
962   if (!Level && !RS && !LS)
963     return RK_None;
964 
965   // Shuffle inputs must match.
966   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
967   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
968   Value *NextLevelOp = nullptr;
969   if (NextLevelOpR && NextLevelOpL) {
970     // If we have two shuffles their operands must match.
971     if (NextLevelOpL != NextLevelOpR)
972       return RK_None;
973 
974     NextLevelOp = NextLevelOpL;
975   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
976     // On the first level we can omit the shufflevector <0, undef,...>. So the
977     // input to the other shufflevector <1, undef> must match with one of the
978     // inputs to the current binary operation.
979     // Example:
980     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
981     //  %BinOp        = fadd          %NextLevelOpL, %R
982     if (NextLevelOpL && NextLevelOpL != RD->RHS)
983       return RK_None;
984     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
985       return RK_None;
986 
987     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
988   } else
989     return RK_None;
990 
991   // Check that the next levels binary operation exists and matches with the
992   // current one.
993   if (Level + 1 != NumLevels) {
994     Optional<ReductionData> NextLevelRD =
995         getReductionData(cast<Instruction>(NextLevelOp));
996     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
997       return RK_None;
998   }
999 
1000   // Shuffle mask for pairwise operation must match.
1001   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
1002     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
1003       return RK_None;
1004   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
1005     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
1006       return RK_None;
1007   } else {
1008     return RK_None;
1009   }
1010 
1011   if (++Level == NumLevels)
1012     return RD->Kind;
1013 
1014   // Match next level.
1015   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
1016                                        NumLevels);
1017 }
1018 
1019 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
1020                                             unsigned &Opcode, Type *&Ty) {
1021   if (!EnableReduxCost)
1022     return RK_None;
1023 
1024   // Need to extract the first element.
1025   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1026   unsigned Idx = ~0u;
1027   if (CI)
1028     Idx = CI->getZExtValue();
1029   if (Idx != 0)
1030     return RK_None;
1031 
1032   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1033   if (!RdxStart)
1034     return RK_None;
1035   Optional<ReductionData> RD = getReductionData(RdxStart);
1036   if (!RD)
1037     return RK_None;
1038 
1039   Type *VecTy = RdxStart->getType();
1040   unsigned NumVecElems = VecTy->getVectorNumElements();
1041   if (!isPowerOf2_32(NumVecElems))
1042     return RK_None;
1043 
1044   // We look for a sequence of shuffle,shuffle,add triples like the following
1045   // that builds a pairwise reduction tree.
1046   //
1047   //  (X0, X1, X2, X3)
1048   //   (X0 + X1, X2 + X3, undef, undef)
1049   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
1050   //
1051   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
1052   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
1053   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
1054   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
1055   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
1056   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1057   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
1058   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1059   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1060   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
1061   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1062   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
1063       RK_None)
1064     return RK_None;
1065 
1066   Opcode = RD->Opcode;
1067   Ty = VecTy;
1068 
1069   return RD->Kind;
1070 }
1071 
1072 static std::pair<Value *, ShuffleVectorInst *>
1073 getShuffleAndOtherOprd(Value *L, Value *R) {
1074   ShuffleVectorInst *S = nullptr;
1075 
1076   if ((S = dyn_cast<ShuffleVectorInst>(L)))
1077     return std::make_pair(R, S);
1078 
1079   S = dyn_cast<ShuffleVectorInst>(R);
1080   return std::make_pair(L, S);
1081 }
1082 
1083 static ReductionKind
1084 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
1085                               unsigned &Opcode, Type *&Ty) {
1086   if (!EnableReduxCost)
1087     return RK_None;
1088 
1089   // Need to extract the first element.
1090   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1091   unsigned Idx = ~0u;
1092   if (CI)
1093     Idx = CI->getZExtValue();
1094   if (Idx != 0)
1095     return RK_None;
1096 
1097   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1098   if (!RdxStart)
1099     return RK_None;
1100   Optional<ReductionData> RD = getReductionData(RdxStart);
1101   if (!RD)
1102     return RK_None;
1103 
1104   Type *VecTy = ReduxRoot->getOperand(0)->getType();
1105   unsigned NumVecElems = VecTy->getVectorNumElements();
1106   if (!isPowerOf2_32(NumVecElems))
1107     return RK_None;
1108 
1109   // We look for a sequence of shuffles and adds like the following matching one
1110   // fadd, shuffle vector pair at a time.
1111   //
1112   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
1113   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
1114   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
1115   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
1116   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1117   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
1118   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1119 
1120   unsigned MaskStart = 1;
1121   Instruction *RdxOp = RdxStart;
1122   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
1123   unsigned NumVecElemsRemain = NumVecElems;
1124   while (NumVecElemsRemain - 1) {
1125     // Check for the right reduction operation.
1126     if (!RdxOp)
1127       return RK_None;
1128     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
1129     if (!RDLevel || !RDLevel->hasSameData(*RD))
1130       return RK_None;
1131 
1132     Value *NextRdxOp;
1133     ShuffleVectorInst *Shuffle;
1134     std::tie(NextRdxOp, Shuffle) =
1135         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
1136 
1137     // Check the current reduction operation and the shuffle use the same value.
1138     if (Shuffle == nullptr)
1139       return RK_None;
1140     if (Shuffle->getOperand(0) != NextRdxOp)
1141       return RK_None;
1142 
1143     // Check that shuffle masks matches.
1144     for (unsigned j = 0; j != MaskStart; ++j)
1145       ShuffleMask[j] = MaskStart + j;
1146     // Fill the rest of the mask with -1 for undef.
1147     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
1148 
1149     ArrayRef<int> Mask = Shuffle->getShuffleMask();
1150     if (ShuffleMask != Mask)
1151       return RK_None;
1152 
1153     RdxOp = dyn_cast<Instruction>(NextRdxOp);
1154     NumVecElemsRemain /= 2;
1155     MaskStart *= 2;
1156   }
1157 
1158   Opcode = RD->Opcode;
1159   Ty = VecTy;
1160   return RD->Kind;
1161 }
1162 
1163 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1164   switch (I->getOpcode()) {
1165   case Instruction::GetElementPtr:
1166     return getUserCost(I);
1167 
1168   case Instruction::Ret:
1169   case Instruction::PHI:
1170   case Instruction::Br: {
1171     return getCFInstrCost(I->getOpcode());
1172   }
1173   case Instruction::Add:
1174   case Instruction::FAdd:
1175   case Instruction::Sub:
1176   case Instruction::FSub:
1177   case Instruction::Mul:
1178   case Instruction::FMul:
1179   case Instruction::UDiv:
1180   case Instruction::SDiv:
1181   case Instruction::FDiv:
1182   case Instruction::URem:
1183   case Instruction::SRem:
1184   case Instruction::FRem:
1185   case Instruction::Shl:
1186   case Instruction::LShr:
1187   case Instruction::AShr:
1188   case Instruction::And:
1189   case Instruction::Or:
1190   case Instruction::Xor: {
1191     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1192     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1193     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1194     Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1195     SmallVector<const Value *, 2> Operands(I->operand_values());
1196     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1197                                   Op1VP, Op2VP, Operands, I);
1198   }
1199   case Instruction::FNeg: {
1200     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1201     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1202     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1203     Op2VK = OK_AnyValue;
1204     Op2VP = OP_None;
1205     SmallVector<const Value *, 2> Operands(I->operand_values());
1206     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1207                                   Op1VP, Op2VP, Operands, I);
1208   }
1209   case Instruction::Select: {
1210     const SelectInst *SI = cast<SelectInst>(I);
1211     Type *CondTy = SI->getCondition()->getType();
1212     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1213   }
1214   case Instruction::ICmp:
1215   case Instruction::FCmp: {
1216     Type *ValTy = I->getOperand(0)->getType();
1217     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1218   }
1219   case Instruction::Store: {
1220     const StoreInst *SI = cast<StoreInst>(I);
1221     Type *ValTy = SI->getValueOperand()->getType();
1222     return getMemoryOpCost(I->getOpcode(), ValTy,
1223                            MaybeAlign(SI->getAlignment()),
1224                            SI->getPointerAddressSpace(), I);
1225   }
1226   case Instruction::Load: {
1227     const LoadInst *LI = cast<LoadInst>(I);
1228     return getMemoryOpCost(I->getOpcode(), I->getType(),
1229                            MaybeAlign(LI->getAlignment()),
1230                            LI->getPointerAddressSpace(), I);
1231   }
1232   case Instruction::ZExt:
1233   case Instruction::SExt:
1234   case Instruction::FPToUI:
1235   case Instruction::FPToSI:
1236   case Instruction::FPExt:
1237   case Instruction::PtrToInt:
1238   case Instruction::IntToPtr:
1239   case Instruction::SIToFP:
1240   case Instruction::UIToFP:
1241   case Instruction::Trunc:
1242   case Instruction::FPTrunc:
1243   case Instruction::BitCast:
1244   case Instruction::AddrSpaceCast: {
1245     Type *SrcTy = I->getOperand(0)->getType();
1246     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1247   }
1248   case Instruction::ExtractElement: {
1249     const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1250     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1251     unsigned Idx = -1;
1252     if (CI)
1253       Idx = CI->getZExtValue();
1254 
1255     // Try to match a reduction sequence (series of shufflevector and vector
1256     // adds followed by a extractelement).
1257     unsigned ReduxOpCode;
1258     Type *ReduxType;
1259 
1260     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1261     case RK_Arithmetic:
1262       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1263                                              /*IsPairwiseForm=*/false);
1264     case RK_MinMax:
1265       return getMinMaxReductionCost(
1266           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1267           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1268     case RK_UnsignedMinMax:
1269       return getMinMaxReductionCost(
1270           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1271           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1272     case RK_None:
1273       break;
1274     }
1275 
1276     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1277     case RK_Arithmetic:
1278       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1279                                              /*IsPairwiseForm=*/true);
1280     case RK_MinMax:
1281       return getMinMaxReductionCost(
1282           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1283           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1284     case RK_UnsignedMinMax:
1285       return getMinMaxReductionCost(
1286           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1287           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1288     case RK_None:
1289       break;
1290     }
1291 
1292     return getVectorInstrCost(I->getOpcode(),
1293                                    EEI->getOperand(0)->getType(), Idx);
1294   }
1295   case Instruction::InsertElement: {
1296     const InsertElementInst * IE = cast<InsertElementInst>(I);
1297     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1298     unsigned Idx = -1;
1299     if (CI)
1300       Idx = CI->getZExtValue();
1301     return getVectorInstrCost(I->getOpcode(),
1302                                    IE->getType(), Idx);
1303   }
1304   case Instruction::ExtractValue:
1305     return 0; // Model all ExtractValue nodes as free.
1306   case Instruction::ShuffleVector: {
1307     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1308     Type *Ty = Shuffle->getType();
1309     Type *SrcTy = Shuffle->getOperand(0)->getType();
1310 
1311     // TODO: Identify and add costs for insert subvector, etc.
1312     int SubIndex;
1313     if (Shuffle->isExtractSubvectorMask(SubIndex))
1314       return TTIImpl->getShuffleCost(SK_ExtractSubvector, SrcTy, SubIndex, Ty);
1315 
1316     if (Shuffle->changesLength())
1317       return -1;
1318 
1319     if (Shuffle->isIdentity())
1320       return 0;
1321 
1322     if (Shuffle->isReverse())
1323       return TTIImpl->getShuffleCost(SK_Reverse, Ty, 0, nullptr);
1324 
1325     if (Shuffle->isSelect())
1326       return TTIImpl->getShuffleCost(SK_Select, Ty, 0, nullptr);
1327 
1328     if (Shuffle->isTranspose())
1329       return TTIImpl->getShuffleCost(SK_Transpose, Ty, 0, nullptr);
1330 
1331     if (Shuffle->isZeroEltSplat())
1332       return TTIImpl->getShuffleCost(SK_Broadcast, Ty, 0, nullptr);
1333 
1334     if (Shuffle->isSingleSource())
1335       return TTIImpl->getShuffleCost(SK_PermuteSingleSrc, Ty, 0, nullptr);
1336 
1337     return TTIImpl->getShuffleCost(SK_PermuteTwoSrc, Ty, 0, nullptr);
1338   }
1339   case Instruction::Call:
1340     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1341       SmallVector<Value *, 4> Args(II->arg_operands());
1342 
1343       FastMathFlags FMF;
1344       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1345         FMF = FPMO->getFastMathFlags();
1346 
1347       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(), Args,
1348                                    FMF, 1, II);
1349     }
1350     return -1;
1351   default:
1352     // We don't have any information on this instruction.
1353     return -1;
1354   }
1355 }
1356 
1357 TargetTransformInfo::Concept::~Concept() {}
1358 
1359 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1360 
1361 TargetIRAnalysis::TargetIRAnalysis(
1362     std::function<Result(const Function &)> TTICallback)
1363     : TTICallback(std::move(TTICallback)) {}
1364 
1365 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1366                                                FunctionAnalysisManager &) {
1367   return TTICallback(F);
1368 }
1369 
1370 AnalysisKey TargetIRAnalysis::Key;
1371 
1372 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1373   return Result(F.getParent()->getDataLayout());
1374 }
1375 
1376 // Register the basic pass.
1377 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1378                 "Target Transform Information", false, true)
1379 char TargetTransformInfoWrapperPass::ID = 0;
1380 
1381 void TargetTransformInfoWrapperPass::anchor() {}
1382 
1383 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1384     : ImmutablePass(ID) {
1385   initializeTargetTransformInfoWrapperPassPass(
1386       *PassRegistry::getPassRegistry());
1387 }
1388 
1389 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1390     TargetIRAnalysis TIRA)
1391     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1392   initializeTargetTransformInfoWrapperPassPass(
1393       *PassRegistry::getPassRegistry());
1394 }
1395 
1396 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1397   FunctionAnalysisManager DummyFAM;
1398   TTI = TIRA.run(F, DummyFAM);
1399   return *TTI;
1400 }
1401 
1402 ImmutablePass *
1403 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1404   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1405 }
1406