1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/Analysis/TargetTransformInfo.h"
11 #include "llvm/Analysis/TargetTransformInfoImpl.h"
12 #include "llvm/IR/CallSite.h"
13 #include "llvm/IR/DataLayout.h"
14 #include "llvm/IR/Instruction.h"
15 #include "llvm/IR/Instructions.h"
16 #include "llvm/IR/IntrinsicInst.h"
17 #include "llvm/IR/Module.h"
18 #include "llvm/IR/Operator.h"
19 #include "llvm/IR/PatternMatch.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include <utility>
23 
24 using namespace llvm;
25 using namespace PatternMatch;
26 
27 #define DEBUG_TYPE "tti"
28 
29 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
30                                      cl::Hidden,
31                                      cl::desc("Recognize reduction patterns."));
32 
33 namespace {
34 /// No-op implementation of the TTI interface using the utility base
35 /// classes.
36 ///
37 /// This is used when no target specific information is available.
38 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
39   explicit NoTTIImpl(const DataLayout &DL)
40       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
41 };
42 }
43 
44 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
45     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
46 
47 TargetTransformInfo::~TargetTransformInfo() {}
48 
49 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
50     : TTIImpl(std::move(Arg.TTIImpl)) {}
51 
52 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
53   TTIImpl = std::move(RHS.TTIImpl);
54   return *this;
55 }
56 
57 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
58                                           Type *OpTy) const {
59   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
60   assert(Cost >= 0 && "TTI should not produce negative costs!");
61   return Cost;
62 }
63 
64 int TargetTransformInfo::getCallCost(FunctionType *FTy, int NumArgs) const {
65   int Cost = TTIImpl->getCallCost(FTy, NumArgs);
66   assert(Cost >= 0 && "TTI should not produce negative costs!");
67   return Cost;
68 }
69 
70 int TargetTransformInfo::getCallCost(const Function *F,
71                                      ArrayRef<const Value *> Arguments) const {
72   int Cost = TTIImpl->getCallCost(F, Arguments);
73   assert(Cost >= 0 && "TTI should not produce negative costs!");
74   return Cost;
75 }
76 
77 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
78   return TTIImpl->getInliningThresholdMultiplier();
79 }
80 
81 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
82                                     ArrayRef<const Value *> Operands) const {
83   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
84 }
85 
86 int TargetTransformInfo::getExtCost(const Instruction *I,
87                                     const Value *Src) const {
88   return TTIImpl->getExtCost(I, Src);
89 }
90 
91 int TargetTransformInfo::getIntrinsicCost(
92     Intrinsic::ID IID, Type *RetTy, ArrayRef<const Value *> Arguments) const {
93   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments);
94   assert(Cost >= 0 && "TTI should not produce negative costs!");
95   return Cost;
96 }
97 
98 unsigned
99 TargetTransformInfo::getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
100                                                       unsigned &JTSize) const {
101   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize);
102 }
103 
104 int TargetTransformInfo::getUserCost(const User *U,
105     ArrayRef<const Value *> Operands) const {
106   int Cost = TTIImpl->getUserCost(U, Operands);
107   assert(Cost >= 0 && "TTI should not produce negative costs!");
108   return Cost;
109 }
110 
111 bool TargetTransformInfo::hasBranchDivergence() const {
112   return TTIImpl->hasBranchDivergence();
113 }
114 
115 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
116   return TTIImpl->isSourceOfDivergence(V);
117 }
118 
119 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
120   return TTIImpl->isAlwaysUniform(V);
121 }
122 
123 unsigned TargetTransformInfo::getFlatAddressSpace() const {
124   return TTIImpl->getFlatAddressSpace();
125 }
126 
127 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
128   return TTIImpl->isLoweredToCall(F);
129 }
130 
131 void TargetTransformInfo::getUnrollingPreferences(
132     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
133   return TTIImpl->getUnrollingPreferences(L, SE, UP);
134 }
135 
136 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
137   return TTIImpl->isLegalAddImmediate(Imm);
138 }
139 
140 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
141   return TTIImpl->isLegalICmpImmediate(Imm);
142 }
143 
144 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
145                                                 int64_t BaseOffset,
146                                                 bool HasBaseReg,
147                                                 int64_t Scale,
148                                                 unsigned AddrSpace,
149                                                 Instruction *I) const {
150   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
151                                         Scale, AddrSpace, I);
152 }
153 
154 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
155   return TTIImpl->isLSRCostLess(C1, C2);
156 }
157 
158 bool TargetTransformInfo::canMacroFuseCmp() const {
159   return TTIImpl->canMacroFuseCmp();
160 }
161 
162 bool TargetTransformInfo::shouldFavorPostInc() const {
163   return TTIImpl->shouldFavorPostInc();
164 }
165 
166 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType) const {
167   return TTIImpl->isLegalMaskedStore(DataType);
168 }
169 
170 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType) const {
171   return TTIImpl->isLegalMaskedLoad(DataType);
172 }
173 
174 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
175   return TTIImpl->isLegalMaskedGather(DataType);
176 }
177 
178 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
179   return TTIImpl->isLegalMaskedScatter(DataType);
180 }
181 
182 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
183   return TTIImpl->hasDivRemOp(DataType, IsSigned);
184 }
185 
186 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
187                                              unsigned AddrSpace) const {
188   return TTIImpl->hasVolatileVariant(I, AddrSpace);
189 }
190 
191 bool TargetTransformInfo::prefersVectorizedAddressing() const {
192   return TTIImpl->prefersVectorizedAddressing();
193 }
194 
195 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
196                                               int64_t BaseOffset,
197                                               bool HasBaseReg,
198                                               int64_t Scale,
199                                               unsigned AddrSpace) const {
200   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
201                                            Scale, AddrSpace);
202   assert(Cost >= 0 && "TTI should not produce negative costs!");
203   return Cost;
204 }
205 
206 bool TargetTransformInfo::LSRWithInstrQueries() const {
207   return TTIImpl->LSRWithInstrQueries();
208 }
209 
210 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
211   return TTIImpl->isTruncateFree(Ty1, Ty2);
212 }
213 
214 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
215   return TTIImpl->isProfitableToHoist(I);
216 }
217 
218 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
219 
220 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
221   return TTIImpl->isTypeLegal(Ty);
222 }
223 
224 unsigned TargetTransformInfo::getJumpBufAlignment() const {
225   return TTIImpl->getJumpBufAlignment();
226 }
227 
228 unsigned TargetTransformInfo::getJumpBufSize() const {
229   return TTIImpl->getJumpBufSize();
230 }
231 
232 bool TargetTransformInfo::shouldBuildLookupTables() const {
233   return TTIImpl->shouldBuildLookupTables();
234 }
235 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(Constant *C) const {
236   return TTIImpl->shouldBuildLookupTablesForConstant(C);
237 }
238 
239 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
240   return TTIImpl->useColdCCForColdCall(F);
241 }
242 
243 unsigned TargetTransformInfo::
244 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
245   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
246 }
247 
248 unsigned TargetTransformInfo::
249 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
250                                  unsigned VF) const {
251   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
252 }
253 
254 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
255   return TTIImpl->supportsEfficientVectorElementLoadStore();
256 }
257 
258 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
259   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
260 }
261 
262 const TargetTransformInfo::MemCmpExpansionOptions *
263 TargetTransformInfo::enableMemCmpExpansion(bool IsZeroCmp) const {
264   return TTIImpl->enableMemCmpExpansion(IsZeroCmp);
265 }
266 
267 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
268   return TTIImpl->enableInterleavedAccessVectorization();
269 }
270 
271 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
272   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
273 }
274 
275 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
276                                                          unsigned BitWidth,
277                                                          unsigned AddressSpace,
278                                                          unsigned Alignment,
279                                                          bool *Fast) const {
280   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
281                                                  Alignment, Fast);
282 }
283 
284 TargetTransformInfo::PopcntSupportKind
285 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
286   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
287 }
288 
289 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
290   return TTIImpl->haveFastSqrt(Ty);
291 }
292 
293 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
294   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
295 }
296 
297 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
298   int Cost = TTIImpl->getFPOpCost(Ty);
299   assert(Cost >= 0 && "TTI should not produce negative costs!");
300   return Cost;
301 }
302 
303 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
304                                                const APInt &Imm,
305                                                Type *Ty) const {
306   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
307   assert(Cost >= 0 && "TTI should not produce negative costs!");
308   return Cost;
309 }
310 
311 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
312   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
313   assert(Cost >= 0 && "TTI should not produce negative costs!");
314   return Cost;
315 }
316 
317 int TargetTransformInfo::getIntImmCost(unsigned Opcode, unsigned Idx,
318                                        const APInt &Imm, Type *Ty) const {
319   int Cost = TTIImpl->getIntImmCost(Opcode, Idx, Imm, Ty);
320   assert(Cost >= 0 && "TTI should not produce negative costs!");
321   return Cost;
322 }
323 
324 int TargetTransformInfo::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
325                                        const APInt &Imm, Type *Ty) const {
326   int Cost = TTIImpl->getIntImmCost(IID, Idx, Imm, Ty);
327   assert(Cost >= 0 && "TTI should not produce negative costs!");
328   return Cost;
329 }
330 
331 unsigned TargetTransformInfo::getNumberOfRegisters(bool Vector) const {
332   return TTIImpl->getNumberOfRegisters(Vector);
333 }
334 
335 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
336   return TTIImpl->getRegisterBitWidth(Vector);
337 }
338 
339 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
340   return TTIImpl->getMinVectorRegisterBitWidth();
341 }
342 
343 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
344   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
345 }
346 
347 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
348   return TTIImpl->getMinimumVF(ElemWidth);
349 }
350 
351 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
352     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
353   return TTIImpl->shouldConsiderAddressTypePromotion(
354       I, AllowPromotionWithoutCommonHeader);
355 }
356 
357 unsigned TargetTransformInfo::getCacheLineSize() const {
358   return TTIImpl->getCacheLineSize();
359 }
360 
361 llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
362   const {
363   return TTIImpl->getCacheSize(Level);
364 }
365 
366 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
367   CacheLevel Level) const {
368   return TTIImpl->getCacheAssociativity(Level);
369 }
370 
371 unsigned TargetTransformInfo::getPrefetchDistance() const {
372   return TTIImpl->getPrefetchDistance();
373 }
374 
375 unsigned TargetTransformInfo::getMinPrefetchStride() const {
376   return TTIImpl->getMinPrefetchStride();
377 }
378 
379 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
380   return TTIImpl->getMaxPrefetchIterationsAhead();
381 }
382 
383 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
384   return TTIImpl->getMaxInterleaveFactor(VF);
385 }
386 
387 int TargetTransformInfo::getArithmeticInstrCost(
388     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
389     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
390     OperandValueProperties Opd2PropInfo,
391     ArrayRef<const Value *> Args) const {
392   int Cost = TTIImpl->getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
393                                              Opd1PropInfo, Opd2PropInfo, Args);
394   assert(Cost >= 0 && "TTI should not produce negative costs!");
395   return Cost;
396 }
397 
398 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
399                                         Type *SubTp) const {
400   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
401   assert(Cost >= 0 && "TTI should not produce negative costs!");
402   return Cost;
403 }
404 
405 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
406                                  Type *Src, const Instruction *I) const {
407   assert ((I == nullptr || I->getOpcode() == Opcode) &&
408           "Opcode should reflect passed instruction.");
409   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
410   assert(Cost >= 0 && "TTI should not produce negative costs!");
411   return Cost;
412 }
413 
414 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
415                                                   VectorType *VecTy,
416                                                   unsigned Index) const {
417   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
418   assert(Cost >= 0 && "TTI should not produce negative costs!");
419   return Cost;
420 }
421 
422 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
423   int Cost = TTIImpl->getCFInstrCost(Opcode);
424   assert(Cost >= 0 && "TTI should not produce negative costs!");
425   return Cost;
426 }
427 
428 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
429                                  Type *CondTy, const Instruction *I) const {
430   assert ((I == nullptr || I->getOpcode() == Opcode) &&
431           "Opcode should reflect passed instruction.");
432   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
433   assert(Cost >= 0 && "TTI should not produce negative costs!");
434   return Cost;
435 }
436 
437 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
438                                             unsigned Index) const {
439   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
440   assert(Cost >= 0 && "TTI should not produce negative costs!");
441   return Cost;
442 }
443 
444 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
445                                          unsigned Alignment,
446                                          unsigned AddressSpace,
447                                          const Instruction *I) const {
448   assert ((I == nullptr || I->getOpcode() == Opcode) &&
449           "Opcode should reflect passed instruction.");
450   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
451   assert(Cost >= 0 && "TTI should not produce negative costs!");
452   return Cost;
453 }
454 
455 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
456                                                unsigned Alignment,
457                                                unsigned AddressSpace) const {
458   int Cost =
459       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
460   assert(Cost >= 0 && "TTI should not produce negative costs!");
461   return Cost;
462 }
463 
464 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
465                                                 Value *Ptr, bool VariableMask,
466                                                 unsigned Alignment) const {
467   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
468                                              Alignment);
469   assert(Cost >= 0 && "TTI should not produce negative costs!");
470   return Cost;
471 }
472 
473 int TargetTransformInfo::getInterleavedMemoryOpCost(
474     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
475     unsigned Alignment, unsigned AddressSpace) const {
476   int Cost = TTIImpl->getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
477                                                  Alignment, AddressSpace);
478   assert(Cost >= 0 && "TTI should not produce negative costs!");
479   return Cost;
480 }
481 
482 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
483                                     ArrayRef<Type *> Tys, FastMathFlags FMF,
484                                     unsigned ScalarizationCostPassed) const {
485   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
486                                             ScalarizationCostPassed);
487   assert(Cost >= 0 && "TTI should not produce negative costs!");
488   return Cost;
489 }
490 
491 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
492            ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) const {
493   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
494   assert(Cost >= 0 && "TTI should not produce negative costs!");
495   return Cost;
496 }
497 
498 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
499                                           ArrayRef<Type *> Tys) const {
500   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
501   assert(Cost >= 0 && "TTI should not produce negative costs!");
502   return Cost;
503 }
504 
505 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
506   return TTIImpl->getNumberOfParts(Tp);
507 }
508 
509 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
510                                                    ScalarEvolution *SE,
511                                                    const SCEV *Ptr) const {
512   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
513   assert(Cost >= 0 && "TTI should not produce negative costs!");
514   return Cost;
515 }
516 
517 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
518                                                     bool IsPairwiseForm) const {
519   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
520   assert(Cost >= 0 && "TTI should not produce negative costs!");
521   return Cost;
522 }
523 
524 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
525                                                 bool IsPairwiseForm,
526                                                 bool IsUnsigned) const {
527   int Cost =
528       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
529   assert(Cost >= 0 && "TTI should not produce negative costs!");
530   return Cost;
531 }
532 
533 unsigned
534 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
535   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
536 }
537 
538 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
539                                              MemIntrinsicInfo &Info) const {
540   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
541 }
542 
543 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
544   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
545 }
546 
547 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
548     IntrinsicInst *Inst, Type *ExpectedType) const {
549   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
550 }
551 
552 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
553                                                      Value *Length,
554                                                      unsigned SrcAlign,
555                                                      unsigned DestAlign) const {
556   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
557                                             DestAlign);
558 }
559 
560 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
561     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
562     unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
563   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
564                                              SrcAlign, DestAlign);
565 }
566 
567 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
568                                               const Function *Callee) const {
569   return TTIImpl->areInlineCompatible(Caller, Callee);
570 }
571 
572 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
573                                              Type *Ty) const {
574   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
575 }
576 
577 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
578                                               Type *Ty) const {
579   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
580 }
581 
582 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
583   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
584 }
585 
586 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
587   return TTIImpl->isLegalToVectorizeLoad(LI);
588 }
589 
590 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
591   return TTIImpl->isLegalToVectorizeStore(SI);
592 }
593 
594 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
595     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
596   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
597                                               AddrSpace);
598 }
599 
600 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
601     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
602   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
603                                                AddrSpace);
604 }
605 
606 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
607                                                   unsigned LoadSize,
608                                                   unsigned ChainSizeInBytes,
609                                                   VectorType *VecTy) const {
610   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
611 }
612 
613 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
614                                                    unsigned StoreSize,
615                                                    unsigned ChainSizeInBytes,
616                                                    VectorType *VecTy) const {
617   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
618 }
619 
620 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode,
621                                                 Type *Ty, ReductionFlags Flags) const {
622   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
623 }
624 
625 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
626   return TTIImpl->shouldExpandReduction(II);
627 }
628 
629 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
630   return TTIImpl->getInstructionLatency(I);
631 }
632 
633 static bool isReverseVectorMask(ArrayRef<int> Mask) {
634   bool ReverseLHS = true;
635   bool ReverseRHS = true;
636   unsigned MaskSize = Mask.size();
637 
638   for (unsigned i = 0; i < MaskSize && (ReverseLHS || ReverseRHS); ++i) {
639     if (Mask[i] < 0)
640       continue;
641     ReverseLHS &= (Mask[i] == (int)(MaskSize - 1 - i));
642     ReverseRHS &= (Mask[i] == (int)(MaskSize + MaskSize - 1 - i));
643   }
644   return ReverseLHS || ReverseRHS;
645 }
646 
647 static bool isSingleSourceVectorMask(ArrayRef<int> Mask) {
648   bool ShuffleLHS = false;
649   bool ShuffleRHS = false;
650   unsigned MaskSize = Mask.size();
651 
652   for (unsigned i = 0; i < MaskSize && !(ShuffleLHS && ShuffleRHS); ++i) {
653     if (Mask[i] < 0)
654       continue;
655     if ((unsigned)Mask[i] >= MaskSize)
656       ShuffleRHS = true;
657     else
658       ShuffleLHS = true;
659   }
660   return !(ShuffleLHS && ShuffleRHS);
661 }
662 
663 static bool isZeroEltBroadcastVectorMask(ArrayRef<int> Mask) {
664   bool BroadcastLHS = true;
665   bool BroadcastRHS = true;
666   unsigned MaskSize = Mask.size();
667 
668   for (unsigned i = 0; i < MaskSize && (BroadcastLHS || BroadcastRHS); ++i) {
669     if (Mask[i] < 0)
670       continue;
671     BroadcastLHS &= (Mask[i] == 0);
672     BroadcastRHS &= (Mask[i] == (int)MaskSize);
673   }
674   return BroadcastLHS || BroadcastRHS;
675 }
676 
677 static bool isIdentityVectorMask(ArrayRef<int> Mask) {
678   bool IdentityLHS = true;
679   bool IdentityRHS = true;
680   unsigned MaskSize = Mask.size();
681 
682   // Example: shufflevector A, B, <0,1,u,3>
683   // Example: shufflevector A, B, <4,u,6,u>
684   for (unsigned i = 0; i < MaskSize && (IdentityLHS || IdentityRHS); ++i) {
685     if (Mask[i] < 0)
686       continue;
687     IdentityLHS &= (Mask[i] == (int)i);
688     IdentityRHS &= (Mask[i] == (int)(i + MaskSize));
689   }
690   return IdentityLHS || IdentityRHS;
691 }
692 
693 static bool isSelectVectorMask(ArrayRef<int> Mask) {
694   bool IsSelect = true;
695   bool FoundLHS = false;
696   bool FoundRHS = false;
697   unsigned MaskSize = Mask.size();
698 
699   // Example: shufflevector A, B, <0,1,6,3>
700   // Example: shufflevector A, B, <4,1,6,3>
701   for (unsigned i = 0; i < MaskSize && IsSelect; ++i) {
702     if (Mask[i] < 0)
703       continue;
704     bool IsLHS = (Mask[i] == (int)i);
705     bool IsRHS = (Mask[i] == (int)(i + MaskSize));
706     FoundLHS |= IsLHS;
707     FoundRHS |= IsRHS;
708     IsSelect = IsLHS || IsRHS;
709   }
710   // If we don't use both vectors this is really an Identity mask.
711   return IsSelect && FoundLHS && FoundRHS;
712 }
713 
714 static bool isTransposeVectorMask(ArrayRef<int> Mask) {
715   // Transpose vector masks transpose a 2xn matrix. They read corresponding
716   // even- or odd-numbered vector elements from two n-dimensional source
717   // vectors and write each result into consecutive elements of an
718   // n-dimensional destination vector. Two shuffles are necessary to complete
719   // the transpose, one for the even elements and another for the odd elements.
720   // This description closely follows how the TRN1 and TRN2 AArch64
721   // instructions operate.
722   //
723   // For example, a simple 2x2 matrix can be transposed with:
724   //
725   //   ; Original matrix
726   //   m0 = <a, b>
727   //   m1 = <c, d>
728   //
729   //   ; Transposed matrix
730   //   t0 = <a, c> = shufflevector m0, m1, <0, 2>
731   //   t1 = <b, d> = shufflevector m0, m1, <1, 3>
732   //
733   // For matrices having greater than n columns, the resulting nx2 transposed
734   // matrix is stored in two result vectors such that one vector contains
735   // interleaved elements from all the even-numbered rows and the other vector
736   // contains interleaved elements from all the odd-numbered rows. For example,
737   // a 2x4 matrix can be transposed with:
738   //
739   //   ; Original matrix
740   //   m0 = <a, b, c, d>
741   //   m1 = <e, f, g, h>
742   //
743   //   ; Transposed matrix
744   //   t0 = <a, e, c, g> = shufflevector m0, m1 <0, 4, 2, 6>
745   //   t1 = <b, f, d, h> = shufflevector m0, m1 <1, 5, 3, 7>
746   //
747   // The above explanation places limitations on what valid transpose masks can
748   // look like. These limitations are defined by the checks below.
749   //
750   // 1. The number of elements in the mask must be a power of two.
751   if (!isPowerOf2_32(Mask.size()))
752     return false;
753 
754   // 2. The first element of the mask must be either a zero (for the
755   // even-numbered vector elements) or a one (for the odd-numbered vector
756   // elements).
757   if (Mask[0] != 0 && Mask[0] != 1)
758     return false;
759 
760   // 3. The difference between the first two elements must be equal to the
761   // number of elements in the mask.
762   if (Mask[1] - Mask[0] != (int)Mask.size())
763     return false;
764 
765   // 4. The difference between consecutive even-numbered and odd-numbered
766   // elements must be equal to two.
767   for (int I = 2; I < (int)Mask.size(); ++I)
768     if (Mask[I] - Mask[I - 2] != 2)
769       return false;
770 
771   return true;
772 }
773 
774 static TargetTransformInfo::OperandValueKind
775 getOperandInfo(Value *V, TargetTransformInfo::OperandValueProperties &OpProps) {
776   TargetTransformInfo::OperandValueKind OpInfo =
777       TargetTransformInfo::OK_AnyValue;
778   OpProps = TargetTransformInfo::OP_None;
779 
780   const Value *Splat = getSplatValue(V);
781 
782   // Check for a splat of a constant or for a non uniform vector of constants
783   // and check if the constant(s) are all powers of two.
784   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
785     OpInfo = TargetTransformInfo::OK_NonUniformConstantValue;
786     if (Splat) {
787       OpInfo = TargetTransformInfo::OK_UniformConstantValue;
788       if (auto *CI = dyn_cast<ConstantInt>(Splat))
789         if (CI->getValue().isPowerOf2())
790           OpProps = TargetTransformInfo::OP_PowerOf2;
791     } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
792       OpProps = TargetTransformInfo::OP_PowerOf2;
793       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
794         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
795           if (CI->getValue().isPowerOf2())
796             continue;
797         OpProps = TargetTransformInfo::OP_None;
798         break;
799       }
800     }
801   }
802 
803   // Check for a splat of a uniform value. This is not loop aware, so return
804   // true only for the obviously uniform cases (argument, globalvalue)
805   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
806     OpInfo = TargetTransformInfo::OK_UniformValue;
807 
808   return OpInfo;
809 }
810 
811 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
812                                      unsigned Level) {
813   // We don't need a shuffle if we just want to have element 0 in position 0 of
814   // the vector.
815   if (!SI && Level == 0 && IsLeft)
816     return true;
817   else if (!SI)
818     return false;
819 
820   SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
821 
822   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
823   // we look at the left or right side.
824   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
825     Mask[i] = val;
826 
827   SmallVector<int, 16> ActualMask = SI->getShuffleMask();
828   return Mask == ActualMask;
829 }
830 
831 namespace {
832 /// Kind of the reduction data.
833 enum ReductionKind {
834   RK_None,           /// Not a reduction.
835   RK_Arithmetic,     /// Binary reduction data.
836   RK_MinMax,         /// Min/max reduction data.
837   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
838 };
839 /// Contains opcode + LHS/RHS parts of the reduction operations.
840 struct ReductionData {
841   ReductionData() = delete;
842   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
843       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
844     assert(Kind != RK_None && "expected binary or min/max reduction only.");
845   }
846   unsigned Opcode = 0;
847   Value *LHS = nullptr;
848   Value *RHS = nullptr;
849   ReductionKind Kind = RK_None;
850   bool hasSameData(ReductionData &RD) const {
851     return Kind == RD.Kind && Opcode == RD.Opcode;
852   }
853 };
854 } // namespace
855 
856 static Optional<ReductionData> getReductionData(Instruction *I) {
857   Value *L, *R;
858   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
859     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
860   if (auto *SI = dyn_cast<SelectInst>(I)) {
861     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
862         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
863         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
864         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
865         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
866         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
867       auto *CI = cast<CmpInst>(SI->getCondition());
868       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
869     }
870     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
871         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
872       auto *CI = cast<CmpInst>(SI->getCondition());
873       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
874     }
875   }
876   return llvm::None;
877 }
878 
879 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
880                                                    unsigned Level,
881                                                    unsigned NumLevels) {
882   // Match one level of pairwise operations.
883   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
884   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
885   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
886   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
887   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
888   if (!I)
889     return RK_None;
890 
891   assert(I->getType()->isVectorTy() && "Expecting a vector type");
892 
893   Optional<ReductionData> RD = getReductionData(I);
894   if (!RD)
895     return RK_None;
896 
897   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
898   if (!LS && Level)
899     return RK_None;
900   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
901   if (!RS && Level)
902     return RK_None;
903 
904   // On level 0 we can omit one shufflevector instruction.
905   if (!Level && !RS && !LS)
906     return RK_None;
907 
908   // Shuffle inputs must match.
909   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
910   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
911   Value *NextLevelOp = nullptr;
912   if (NextLevelOpR && NextLevelOpL) {
913     // If we have two shuffles their operands must match.
914     if (NextLevelOpL != NextLevelOpR)
915       return RK_None;
916 
917     NextLevelOp = NextLevelOpL;
918   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
919     // On the first level we can omit the shufflevector <0, undef,...>. So the
920     // input to the other shufflevector <1, undef> must match with one of the
921     // inputs to the current binary operation.
922     // Example:
923     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
924     //  %BinOp        = fadd          %NextLevelOpL, %R
925     if (NextLevelOpL && NextLevelOpL != RD->RHS)
926       return RK_None;
927     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
928       return RK_None;
929 
930     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
931   } else
932     return RK_None;
933 
934   // Check that the next levels binary operation exists and matches with the
935   // current one.
936   if (Level + 1 != NumLevels) {
937     Optional<ReductionData> NextLevelRD =
938         getReductionData(cast<Instruction>(NextLevelOp));
939     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
940       return RK_None;
941   }
942 
943   // Shuffle mask for pairwise operation must match.
944   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
945     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
946       return RK_None;
947   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
948     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
949       return RK_None;
950   } else {
951     return RK_None;
952   }
953 
954   if (++Level == NumLevels)
955     return RD->Kind;
956 
957   // Match next level.
958   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
959                                        NumLevels);
960 }
961 
962 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
963                                             unsigned &Opcode, Type *&Ty) {
964   if (!EnableReduxCost)
965     return RK_None;
966 
967   // Need to extract the first element.
968   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
969   unsigned Idx = ~0u;
970   if (CI)
971     Idx = CI->getZExtValue();
972   if (Idx != 0)
973     return RK_None;
974 
975   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
976   if (!RdxStart)
977     return RK_None;
978   Optional<ReductionData> RD = getReductionData(RdxStart);
979   if (!RD)
980     return RK_None;
981 
982   Type *VecTy = RdxStart->getType();
983   unsigned NumVecElems = VecTy->getVectorNumElements();
984   if (!isPowerOf2_32(NumVecElems))
985     return RK_None;
986 
987   // We look for a sequence of shuffle,shuffle,add triples like the following
988   // that builds a pairwise reduction tree.
989   //
990   //  (X0, X1, X2, X3)
991   //   (X0 + X1, X2 + X3, undef, undef)
992   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
993   //
994   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
995   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
996   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
997   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
998   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
999   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1000   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
1001   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1002   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1003   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
1004   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1005   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
1006       RK_None)
1007     return RK_None;
1008 
1009   Opcode = RD->Opcode;
1010   Ty = VecTy;
1011 
1012   return RD->Kind;
1013 }
1014 
1015 static std::pair<Value *, ShuffleVectorInst *>
1016 getShuffleAndOtherOprd(Value *L, Value *R) {
1017   ShuffleVectorInst *S = nullptr;
1018 
1019   if ((S = dyn_cast<ShuffleVectorInst>(L)))
1020     return std::make_pair(R, S);
1021 
1022   S = dyn_cast<ShuffleVectorInst>(R);
1023   return std::make_pair(L, S);
1024 }
1025 
1026 static ReductionKind
1027 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
1028                               unsigned &Opcode, Type *&Ty) {
1029   if (!EnableReduxCost)
1030     return RK_None;
1031 
1032   // Need to extract the first element.
1033   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1034   unsigned Idx = ~0u;
1035   if (CI)
1036     Idx = CI->getZExtValue();
1037   if (Idx != 0)
1038     return RK_None;
1039 
1040   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1041   if (!RdxStart)
1042     return RK_None;
1043   Optional<ReductionData> RD = getReductionData(RdxStart);
1044   if (!RD)
1045     return RK_None;
1046 
1047   Type *VecTy = ReduxRoot->getOperand(0)->getType();
1048   unsigned NumVecElems = VecTy->getVectorNumElements();
1049   if (!isPowerOf2_32(NumVecElems))
1050     return RK_None;
1051 
1052   // We look for a sequence of shuffles and adds like the following matching one
1053   // fadd, shuffle vector pair at a time.
1054   //
1055   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
1056   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
1057   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
1058   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
1059   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1060   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
1061   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1062 
1063   unsigned MaskStart = 1;
1064   Instruction *RdxOp = RdxStart;
1065   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
1066   unsigned NumVecElemsRemain = NumVecElems;
1067   while (NumVecElemsRemain - 1) {
1068     // Check for the right reduction operation.
1069     if (!RdxOp)
1070       return RK_None;
1071     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
1072     if (!RDLevel || !RDLevel->hasSameData(*RD))
1073       return RK_None;
1074 
1075     Value *NextRdxOp;
1076     ShuffleVectorInst *Shuffle;
1077     std::tie(NextRdxOp, Shuffle) =
1078         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
1079 
1080     // Check the current reduction operation and the shuffle use the same value.
1081     if (Shuffle == nullptr)
1082       return RK_None;
1083     if (Shuffle->getOperand(0) != NextRdxOp)
1084       return RK_None;
1085 
1086     // Check that shuffle masks matches.
1087     for (unsigned j = 0; j != MaskStart; ++j)
1088       ShuffleMask[j] = MaskStart + j;
1089     // Fill the rest of the mask with -1 for undef.
1090     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
1091 
1092     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
1093     if (ShuffleMask != Mask)
1094       return RK_None;
1095 
1096     RdxOp = dyn_cast<Instruction>(NextRdxOp);
1097     NumVecElemsRemain /= 2;
1098     MaskStart *= 2;
1099   }
1100 
1101   Opcode = RD->Opcode;
1102   Ty = VecTy;
1103   return RD->Kind;
1104 }
1105 
1106 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1107   switch (I->getOpcode()) {
1108   case Instruction::GetElementPtr:
1109     return getUserCost(I);
1110 
1111   case Instruction::Ret:
1112   case Instruction::PHI:
1113   case Instruction::Br: {
1114     return getCFInstrCost(I->getOpcode());
1115   }
1116   case Instruction::Add:
1117   case Instruction::FAdd:
1118   case Instruction::Sub:
1119   case Instruction::FSub:
1120   case Instruction::Mul:
1121   case Instruction::FMul:
1122   case Instruction::UDiv:
1123   case Instruction::SDiv:
1124   case Instruction::FDiv:
1125   case Instruction::URem:
1126   case Instruction::SRem:
1127   case Instruction::FRem:
1128   case Instruction::Shl:
1129   case Instruction::LShr:
1130   case Instruction::AShr:
1131   case Instruction::And:
1132   case Instruction::Or:
1133   case Instruction::Xor: {
1134     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1135     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1136     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1137     Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1138     SmallVector<const Value *, 2> Operands(I->operand_values());
1139     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1140                                   Op1VP, Op2VP, Operands);
1141   }
1142   case Instruction::Select: {
1143     const SelectInst *SI = cast<SelectInst>(I);
1144     Type *CondTy = SI->getCondition()->getType();
1145     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1146   }
1147   case Instruction::ICmp:
1148   case Instruction::FCmp: {
1149     Type *ValTy = I->getOperand(0)->getType();
1150     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1151   }
1152   case Instruction::Store: {
1153     const StoreInst *SI = cast<StoreInst>(I);
1154     Type *ValTy = SI->getValueOperand()->getType();
1155     return getMemoryOpCost(I->getOpcode(), ValTy,
1156                                 SI->getAlignment(),
1157                                 SI->getPointerAddressSpace(), I);
1158   }
1159   case Instruction::Load: {
1160     const LoadInst *LI = cast<LoadInst>(I);
1161     return getMemoryOpCost(I->getOpcode(), I->getType(),
1162                                 LI->getAlignment(),
1163                                 LI->getPointerAddressSpace(), I);
1164   }
1165   case Instruction::ZExt:
1166   case Instruction::SExt:
1167   case Instruction::FPToUI:
1168   case Instruction::FPToSI:
1169   case Instruction::FPExt:
1170   case Instruction::PtrToInt:
1171   case Instruction::IntToPtr:
1172   case Instruction::SIToFP:
1173   case Instruction::UIToFP:
1174   case Instruction::Trunc:
1175   case Instruction::FPTrunc:
1176   case Instruction::BitCast:
1177   case Instruction::AddrSpaceCast: {
1178     Type *SrcTy = I->getOperand(0)->getType();
1179     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1180   }
1181   case Instruction::ExtractElement: {
1182     const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1183     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1184     unsigned Idx = -1;
1185     if (CI)
1186       Idx = CI->getZExtValue();
1187 
1188     // Try to match a reduction sequence (series of shufflevector and vector
1189     // adds followed by a extractelement).
1190     unsigned ReduxOpCode;
1191     Type *ReduxType;
1192 
1193     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1194     case RK_Arithmetic:
1195       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1196                                              /*IsPairwiseForm=*/false);
1197     case RK_MinMax:
1198       return getMinMaxReductionCost(
1199           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1200           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1201     case RK_UnsignedMinMax:
1202       return getMinMaxReductionCost(
1203           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1204           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1205     case RK_None:
1206       break;
1207     }
1208 
1209     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1210     case RK_Arithmetic:
1211       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1212                                              /*IsPairwiseForm=*/true);
1213     case RK_MinMax:
1214       return getMinMaxReductionCost(
1215           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1216           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1217     case RK_UnsignedMinMax:
1218       return getMinMaxReductionCost(
1219           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1220           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1221     case RK_None:
1222       break;
1223     }
1224 
1225     return getVectorInstrCost(I->getOpcode(),
1226                                    EEI->getOperand(0)->getType(), Idx);
1227   }
1228   case Instruction::InsertElement: {
1229     const InsertElementInst * IE = cast<InsertElementInst>(I);
1230     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1231     unsigned Idx = -1;
1232     if (CI)
1233       Idx = CI->getZExtValue();
1234     return getVectorInstrCost(I->getOpcode(),
1235                                    IE->getType(), Idx);
1236   }
1237   case Instruction::ShuffleVector: {
1238     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1239     Type *VecTypOp0 = Shuffle->getOperand(0)->getType();
1240     unsigned NumVecElems = VecTypOp0->getVectorNumElements();
1241     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
1242 
1243     if (NumVecElems == Mask.size()) {
1244       if (isIdentityVectorMask(Mask))
1245         return 0;
1246 
1247       if (isReverseVectorMask(Mask))
1248         return TTIImpl->getShuffleCost(TargetTransformInfo::SK_Reverse,
1249                                        VecTypOp0, 0, nullptr);
1250 
1251       if (isSelectVectorMask(Mask))
1252         return TTIImpl->getShuffleCost(TargetTransformInfo::SK_Select,
1253                                        VecTypOp0, 0, nullptr);
1254 
1255       if (isTransposeVectorMask(Mask))
1256         return TTIImpl->getShuffleCost(TargetTransformInfo::SK_Transpose,
1257                                        VecTypOp0, 0, nullptr);
1258 
1259       if (isZeroEltBroadcastVectorMask(Mask))
1260         return TTIImpl->getShuffleCost(TargetTransformInfo::SK_Broadcast,
1261                                        VecTypOp0, 0, nullptr);
1262 
1263       if (isSingleSourceVectorMask(Mask))
1264         return TTIImpl->getShuffleCost(TargetTransformInfo::SK_PermuteSingleSrc,
1265                                        VecTypOp0, 0, nullptr);
1266 
1267       return TTIImpl->getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc,
1268                                      VecTypOp0, 0, nullptr);
1269     }
1270 
1271     return -1;
1272   }
1273   case Instruction::Call:
1274     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1275       SmallVector<Value *, 4> Args(II->arg_operands());
1276 
1277       FastMathFlags FMF;
1278       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1279         FMF = FPMO->getFastMathFlags();
1280 
1281       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
1282                                         Args, FMF);
1283     }
1284     return -1;
1285   default:
1286     // We don't have any information on this instruction.
1287     return -1;
1288   }
1289 }
1290 
1291 TargetTransformInfo::Concept::~Concept() {}
1292 
1293 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1294 
1295 TargetIRAnalysis::TargetIRAnalysis(
1296     std::function<Result(const Function &)> TTICallback)
1297     : TTICallback(std::move(TTICallback)) {}
1298 
1299 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1300                                                FunctionAnalysisManager &) {
1301   return TTICallback(F);
1302 }
1303 
1304 AnalysisKey TargetIRAnalysis::Key;
1305 
1306 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1307   return Result(F.getParent()->getDataLayout());
1308 }
1309 
1310 // Register the basic pass.
1311 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1312                 "Target Transform Information", false, true)
1313 char TargetTransformInfoWrapperPass::ID = 0;
1314 
1315 void TargetTransformInfoWrapperPass::anchor() {}
1316 
1317 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1318     : ImmutablePass(ID) {
1319   initializeTargetTransformInfoWrapperPassPass(
1320       *PassRegistry::getPassRegistry());
1321 }
1322 
1323 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1324     TargetIRAnalysis TIRA)
1325     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1326   initializeTargetTransformInfoWrapperPassPass(
1327       *PassRegistry::getPassRegistry());
1328 }
1329 
1330 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1331   FunctionAnalysisManager DummyFAM;
1332   TTI = TIRA.run(F, DummyFAM);
1333   return *TTI;
1334 }
1335 
1336 ImmutablePass *
1337 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1338   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1339 }
1340