1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/Analysis/TargetTransformInfo.h"
10 #include "llvm/Analysis/TargetTransformInfoImpl.h"
11 #include "llvm/IR/CallSite.h"
12 #include "llvm/IR/DataLayout.h"
13 #include "llvm/IR/Instruction.h"
14 #include "llvm/IR/Instructions.h"
15 #include "llvm/IR/IntrinsicInst.h"
16 #include "llvm/IR/Module.h"
17 #include "llvm/IR/Operator.h"
18 #include "llvm/IR/PatternMatch.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/LoopIterator.h"
23 #include <utility>
24 
25 using namespace llvm;
26 using namespace PatternMatch;
27 
28 #define DEBUG_TYPE "tti"
29 
30 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
31                                      cl::Hidden,
32                                      cl::desc("Recognize reduction patterns."));
33 
34 namespace {
35 /// No-op implementation of the TTI interface using the utility base
36 /// classes.
37 ///
38 /// This is used when no target specific information is available.
39 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
40   explicit NoTTIImpl(const DataLayout &DL)
41       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
42 };
43 }
44 
45 bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) {
46   // If the loop has irreducible control flow, it can not be converted to
47   // Hardware loop.
48   LoopBlocksRPO RPOT(L);
49   RPOT.perform(&LI);
50   if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
51     return false;
52   return true;
53 }
54 
55 bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
56                                                LoopInfo &LI, DominatorTree &DT,
57                                                bool ForceNestedLoop,
58                                                bool ForceHardwareLoopPHI) {
59   SmallVector<BasicBlock *, 4> ExitingBlocks;
60   L->getExitingBlocks(ExitingBlocks);
61 
62   for (SmallVectorImpl<BasicBlock *>::iterator I = ExitingBlocks.begin(),
63                                                IE = ExitingBlocks.end();
64        I != IE; ++I) {
65     BasicBlock *BB = *I;
66 
67     // If we pass the updated counter back through a phi, we need to know
68     // which latch the updated value will be coming from.
69     if (!L->isLoopLatch(BB)) {
70       if (ForceHardwareLoopPHI || CounterInReg)
71         continue;
72     }
73 
74     const SCEV *EC = SE.getExitCount(L, BB);
75     if (isa<SCEVCouldNotCompute>(EC))
76       continue;
77     if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
78       if (ConstEC->getValue()->isZero())
79         continue;
80     } else if (!SE.isLoopInvariant(EC, L))
81       continue;
82 
83     if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
84       continue;
85 
86     // If this exiting block is contained in a nested loop, it is not eligible
87     // for insertion of the branch-and-decrement since the inner loop would
88     // end up messing up the value in the CTR.
89     if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
90       continue;
91 
92     // We now have a loop-invariant count of loop iterations (which is not the
93     // constant zero) for which we know that this loop will not exit via this
94     // existing block.
95 
96     // We need to make sure that this block will run on every loop iteration.
97     // For this to be true, we must dominate all blocks with backedges. Such
98     // blocks are in-loop predecessors to the header block.
99     bool NotAlways = false;
100     for (pred_iterator PI = pred_begin(L->getHeader()),
101                        PIE = pred_end(L->getHeader());
102          PI != PIE; ++PI) {
103       if (!L->contains(*PI))
104         continue;
105 
106       if (!DT.dominates(*I, *PI)) {
107         NotAlways = true;
108         break;
109       }
110     }
111 
112     if (NotAlways)
113       continue;
114 
115     // Make sure this blocks ends with a conditional branch.
116     Instruction *TI = BB->getTerminator();
117     if (!TI)
118       continue;
119 
120     if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
121       if (!BI->isConditional())
122         continue;
123 
124       ExitBranch = BI;
125     } else
126       continue;
127 
128     // Note that this block may not be the loop latch block, even if the loop
129     // has a latch block.
130     ExitBlock = *I;
131     ExitCount = EC;
132     break;
133   }
134 
135   if (!ExitBlock)
136     return false;
137   return true;
138 }
139 
140 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
141     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
142 
143 TargetTransformInfo::~TargetTransformInfo() {}
144 
145 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
146     : TTIImpl(std::move(Arg.TTIImpl)) {}
147 
148 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
149   TTIImpl = std::move(RHS.TTIImpl);
150   return *this;
151 }
152 
153 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
154                                           Type *OpTy) const {
155   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
156   assert(Cost >= 0 && "TTI should not produce negative costs!");
157   return Cost;
158 }
159 
160 int TargetTransformInfo::getCallCost(FunctionType *FTy, int NumArgs,
161                                      const User *U) const {
162   int Cost = TTIImpl->getCallCost(FTy, NumArgs, U);
163   assert(Cost >= 0 && "TTI should not produce negative costs!");
164   return Cost;
165 }
166 
167 int TargetTransformInfo::getCallCost(const Function *F,
168                                      ArrayRef<const Value *> Arguments,
169                                      const User *U) const {
170   int Cost = TTIImpl->getCallCost(F, Arguments, U);
171   assert(Cost >= 0 && "TTI should not produce negative costs!");
172   return Cost;
173 }
174 
175 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
176   return TTIImpl->getInliningThresholdMultiplier();
177 }
178 
179 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
180                                     ArrayRef<const Value *> Operands) const {
181   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
182 }
183 
184 int TargetTransformInfo::getExtCost(const Instruction *I,
185                                     const Value *Src) const {
186   return TTIImpl->getExtCost(I, Src);
187 }
188 
189 int TargetTransformInfo::getIntrinsicCost(
190     Intrinsic::ID IID, Type *RetTy, ArrayRef<const Value *> Arguments,
191     const User *U) const {
192   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments, U);
193   assert(Cost >= 0 && "TTI should not produce negative costs!");
194   return Cost;
195 }
196 
197 unsigned
198 TargetTransformInfo::getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
199                                                       unsigned &JTSize) const {
200   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize);
201 }
202 
203 int TargetTransformInfo::getUserCost(const User *U,
204     ArrayRef<const Value *> Operands) const {
205   int Cost = TTIImpl->getUserCost(U, Operands);
206   assert(Cost >= 0 && "TTI should not produce negative costs!");
207   return Cost;
208 }
209 
210 bool TargetTransformInfo::hasBranchDivergence() const {
211   return TTIImpl->hasBranchDivergence();
212 }
213 
214 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
215   return TTIImpl->isSourceOfDivergence(V);
216 }
217 
218 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
219   return TTIImpl->isAlwaysUniform(V);
220 }
221 
222 unsigned TargetTransformInfo::getFlatAddressSpace() const {
223   return TTIImpl->getFlatAddressSpace();
224 }
225 
226 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
227   return TTIImpl->isLoweredToCall(F);
228 }
229 
230 bool TargetTransformInfo::isHardwareLoopProfitable(
231   Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
232   TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
233   return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
234 }
235 
236 void TargetTransformInfo::getUnrollingPreferences(
237     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
238   return TTIImpl->getUnrollingPreferences(L, SE, UP);
239 }
240 
241 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
242   return TTIImpl->isLegalAddImmediate(Imm);
243 }
244 
245 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
246   return TTIImpl->isLegalICmpImmediate(Imm);
247 }
248 
249 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
250                                                 int64_t BaseOffset,
251                                                 bool HasBaseReg,
252                                                 int64_t Scale,
253                                                 unsigned AddrSpace,
254                                                 Instruction *I) const {
255   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
256                                         Scale, AddrSpace, I);
257 }
258 
259 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
260   return TTIImpl->isLSRCostLess(C1, C2);
261 }
262 
263 bool TargetTransformInfo::canMacroFuseCmp() const {
264   return TTIImpl->canMacroFuseCmp();
265 }
266 
267 bool TargetTransformInfo::canSaveCmp(Loop *L, BranchInst **BI,
268                                      ScalarEvolution *SE, LoopInfo *LI,
269                                      DominatorTree *DT, AssumptionCache *AC,
270                                      TargetLibraryInfo *LibInfo) const {
271   return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
272 }
273 
274 bool TargetTransformInfo::shouldFavorPostInc() const {
275   return TTIImpl->shouldFavorPostInc();
276 }
277 
278 bool TargetTransformInfo::shouldFavorBackedgeIndex(const Loop *L) const {
279   return TTIImpl->shouldFavorBackedgeIndex(L);
280 }
281 
282 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType) const {
283   return TTIImpl->isLegalMaskedStore(DataType);
284 }
285 
286 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType) const {
287   return TTIImpl->isLegalMaskedLoad(DataType);
288 }
289 
290 bool TargetTransformInfo::isLegalNTStore(Type *DataType,
291                                          unsigned Alignment) const {
292   return TTIImpl->isLegalNTStore(DataType, Alignment);
293 }
294 
295 bool TargetTransformInfo::isLegalNTLoad(Type *DataType,
296                                         unsigned Alignment) const {
297   return TTIImpl->isLegalNTLoad(DataType, Alignment);
298 }
299 
300 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
301   return TTIImpl->isLegalMaskedGather(DataType);
302 }
303 
304 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
305   return TTIImpl->isLegalMaskedScatter(DataType);
306 }
307 
308 bool TargetTransformInfo::isLegalMaskedCompressStore(Type *DataType) const {
309   return TTIImpl->isLegalMaskedCompressStore(DataType);
310 }
311 
312 bool TargetTransformInfo::isLegalMaskedExpandLoad(Type *DataType) const {
313   return TTIImpl->isLegalMaskedExpandLoad(DataType);
314 }
315 
316 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
317   return TTIImpl->hasDivRemOp(DataType, IsSigned);
318 }
319 
320 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
321                                              unsigned AddrSpace) const {
322   return TTIImpl->hasVolatileVariant(I, AddrSpace);
323 }
324 
325 bool TargetTransformInfo::prefersVectorizedAddressing() const {
326   return TTIImpl->prefersVectorizedAddressing();
327 }
328 
329 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
330                                               int64_t BaseOffset,
331                                               bool HasBaseReg,
332                                               int64_t Scale,
333                                               unsigned AddrSpace) const {
334   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
335                                            Scale, AddrSpace);
336   assert(Cost >= 0 && "TTI should not produce negative costs!");
337   return Cost;
338 }
339 
340 bool TargetTransformInfo::LSRWithInstrQueries() const {
341   return TTIImpl->LSRWithInstrQueries();
342 }
343 
344 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
345   return TTIImpl->isTruncateFree(Ty1, Ty2);
346 }
347 
348 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
349   return TTIImpl->isProfitableToHoist(I);
350 }
351 
352 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
353 
354 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
355   return TTIImpl->isTypeLegal(Ty);
356 }
357 
358 unsigned TargetTransformInfo::getJumpBufAlignment() const {
359   return TTIImpl->getJumpBufAlignment();
360 }
361 
362 unsigned TargetTransformInfo::getJumpBufSize() const {
363   return TTIImpl->getJumpBufSize();
364 }
365 
366 bool TargetTransformInfo::shouldBuildLookupTables() const {
367   return TTIImpl->shouldBuildLookupTables();
368 }
369 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(Constant *C) const {
370   return TTIImpl->shouldBuildLookupTablesForConstant(C);
371 }
372 
373 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
374   return TTIImpl->useColdCCForColdCall(F);
375 }
376 
377 unsigned TargetTransformInfo::
378 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
379   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
380 }
381 
382 unsigned TargetTransformInfo::
383 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
384                                  unsigned VF) const {
385   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
386 }
387 
388 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
389   return TTIImpl->supportsEfficientVectorElementLoadStore();
390 }
391 
392 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
393   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
394 }
395 
396 TargetTransformInfo::MemCmpExpansionOptions
397 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
398   return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
399 }
400 
401 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
402   return TTIImpl->enableInterleavedAccessVectorization();
403 }
404 
405 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const {
406   return TTIImpl->enableMaskedInterleavedAccessVectorization();
407 }
408 
409 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
410   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
411 }
412 
413 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
414                                                          unsigned BitWidth,
415                                                          unsigned AddressSpace,
416                                                          unsigned Alignment,
417                                                          bool *Fast) const {
418   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
419                                                  Alignment, Fast);
420 }
421 
422 TargetTransformInfo::PopcntSupportKind
423 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
424   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
425 }
426 
427 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
428   return TTIImpl->haveFastSqrt(Ty);
429 }
430 
431 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
432   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
433 }
434 
435 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
436   int Cost = TTIImpl->getFPOpCost(Ty);
437   assert(Cost >= 0 && "TTI should not produce negative costs!");
438   return Cost;
439 }
440 
441 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
442                                                const APInt &Imm,
443                                                Type *Ty) const {
444   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
445   assert(Cost >= 0 && "TTI should not produce negative costs!");
446   return Cost;
447 }
448 
449 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
450   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
451   assert(Cost >= 0 && "TTI should not produce negative costs!");
452   return Cost;
453 }
454 
455 int TargetTransformInfo::getIntImmCost(unsigned Opcode, unsigned Idx,
456                                        const APInt &Imm, Type *Ty) const {
457   int Cost = TTIImpl->getIntImmCost(Opcode, Idx, Imm, Ty);
458   assert(Cost >= 0 && "TTI should not produce negative costs!");
459   return Cost;
460 }
461 
462 int TargetTransformInfo::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
463                                        const APInt &Imm, Type *Ty) const {
464   int Cost = TTIImpl->getIntImmCost(IID, Idx, Imm, Ty);
465   assert(Cost >= 0 && "TTI should not produce negative costs!");
466   return Cost;
467 }
468 
469 unsigned TargetTransformInfo::getNumberOfRegisters(bool Vector) const {
470   return TTIImpl->getNumberOfRegisters(Vector);
471 }
472 
473 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
474   return TTIImpl->getRegisterBitWidth(Vector);
475 }
476 
477 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
478   return TTIImpl->getMinVectorRegisterBitWidth();
479 }
480 
481 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
482   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
483 }
484 
485 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
486   return TTIImpl->getMinimumVF(ElemWidth);
487 }
488 
489 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
490     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
491   return TTIImpl->shouldConsiderAddressTypePromotion(
492       I, AllowPromotionWithoutCommonHeader);
493 }
494 
495 unsigned TargetTransformInfo::getCacheLineSize() const {
496   return TTIImpl->getCacheLineSize();
497 }
498 
499 llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
500   const {
501   return TTIImpl->getCacheSize(Level);
502 }
503 
504 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
505   CacheLevel Level) const {
506   return TTIImpl->getCacheAssociativity(Level);
507 }
508 
509 unsigned TargetTransformInfo::getPrefetchDistance() const {
510   return TTIImpl->getPrefetchDistance();
511 }
512 
513 unsigned TargetTransformInfo::getMinPrefetchStride() const {
514   return TTIImpl->getMinPrefetchStride();
515 }
516 
517 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
518   return TTIImpl->getMaxPrefetchIterationsAhead();
519 }
520 
521 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
522   return TTIImpl->getMaxInterleaveFactor(VF);
523 }
524 
525 TargetTransformInfo::OperandValueKind
526 TargetTransformInfo::getOperandInfo(Value *V, OperandValueProperties &OpProps) {
527   OperandValueKind OpInfo = OK_AnyValue;
528   OpProps = OP_None;
529 
530   if (auto *CI = dyn_cast<ConstantInt>(V)) {
531     if (CI->getValue().isPowerOf2())
532       OpProps = OP_PowerOf2;
533     return OK_UniformConstantValue;
534   }
535 
536   // A broadcast shuffle creates a uniform value.
537   // TODO: Add support for non-zero index broadcasts.
538   // TODO: Add support for different source vector width.
539   if (auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
540     if (ShuffleInst->isZeroEltSplat())
541       OpInfo = OK_UniformValue;
542 
543   const Value *Splat = getSplatValue(V);
544 
545   // Check for a splat of a constant or for a non uniform vector of constants
546   // and check if the constant(s) are all powers of two.
547   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
548     OpInfo = OK_NonUniformConstantValue;
549     if (Splat) {
550       OpInfo = OK_UniformConstantValue;
551       if (auto *CI = dyn_cast<ConstantInt>(Splat))
552         if (CI->getValue().isPowerOf2())
553           OpProps = OP_PowerOf2;
554     } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
555       OpProps = OP_PowerOf2;
556       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
557         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
558           if (CI->getValue().isPowerOf2())
559             continue;
560         OpProps = OP_None;
561         break;
562       }
563     }
564   }
565 
566   // Check for a splat of a uniform value. This is not loop aware, so return
567   // true only for the obviously uniform cases (argument, globalvalue)
568   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
569     OpInfo = OK_UniformValue;
570 
571   return OpInfo;
572 }
573 
574 int TargetTransformInfo::getArithmeticInstrCost(
575     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
576     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
577     OperandValueProperties Opd2PropInfo,
578     ArrayRef<const Value *> Args) const {
579   int Cost = TTIImpl->getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
580                                              Opd1PropInfo, Opd2PropInfo, Args);
581   assert(Cost >= 0 && "TTI should not produce negative costs!");
582   return Cost;
583 }
584 
585 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
586                                         Type *SubTp) const {
587   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
588   assert(Cost >= 0 && "TTI should not produce negative costs!");
589   return Cost;
590 }
591 
592 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
593                                  Type *Src, const Instruction *I) const {
594   assert ((I == nullptr || I->getOpcode() == Opcode) &&
595           "Opcode should reflect passed instruction.");
596   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
597   assert(Cost >= 0 && "TTI should not produce negative costs!");
598   return Cost;
599 }
600 
601 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
602                                                   VectorType *VecTy,
603                                                   unsigned Index) const {
604   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
605   assert(Cost >= 0 && "TTI should not produce negative costs!");
606   return Cost;
607 }
608 
609 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
610   int Cost = TTIImpl->getCFInstrCost(Opcode);
611   assert(Cost >= 0 && "TTI should not produce negative costs!");
612   return Cost;
613 }
614 
615 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
616                                  Type *CondTy, const Instruction *I) const {
617   assert ((I == nullptr || I->getOpcode() == Opcode) &&
618           "Opcode should reflect passed instruction.");
619   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
620   assert(Cost >= 0 && "TTI should not produce negative costs!");
621   return Cost;
622 }
623 
624 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
625                                             unsigned Index) const {
626   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
627   assert(Cost >= 0 && "TTI should not produce negative costs!");
628   return Cost;
629 }
630 
631 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
632                                          unsigned Alignment,
633                                          unsigned AddressSpace,
634                                          const Instruction *I) const {
635   assert ((I == nullptr || I->getOpcode() == Opcode) &&
636           "Opcode should reflect passed instruction.");
637   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
638   assert(Cost >= 0 && "TTI should not produce negative costs!");
639   return Cost;
640 }
641 
642 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
643                                                unsigned Alignment,
644                                                unsigned AddressSpace) const {
645   int Cost =
646       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
647   assert(Cost >= 0 && "TTI should not produce negative costs!");
648   return Cost;
649 }
650 
651 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
652                                                 Value *Ptr, bool VariableMask,
653                                                 unsigned Alignment) const {
654   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
655                                              Alignment);
656   assert(Cost >= 0 && "TTI should not produce negative costs!");
657   return Cost;
658 }
659 
660 int TargetTransformInfo::getInterleavedMemoryOpCost(
661     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
662     unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond,
663     bool UseMaskForGaps) const {
664   int Cost = TTIImpl->getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
665                                                  Alignment, AddressSpace,
666                                                  UseMaskForCond,
667                                                  UseMaskForGaps);
668   assert(Cost >= 0 && "TTI should not produce negative costs!");
669   return Cost;
670 }
671 
672 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
673                                     ArrayRef<Type *> Tys, FastMathFlags FMF,
674                                     unsigned ScalarizationCostPassed) const {
675   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
676                                             ScalarizationCostPassed);
677   assert(Cost >= 0 && "TTI should not produce negative costs!");
678   return Cost;
679 }
680 
681 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
682            ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) const {
683   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
684   assert(Cost >= 0 && "TTI should not produce negative costs!");
685   return Cost;
686 }
687 
688 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
689                                           ArrayRef<Type *> Tys) const {
690   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
691   assert(Cost >= 0 && "TTI should not produce negative costs!");
692   return Cost;
693 }
694 
695 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
696   return TTIImpl->getNumberOfParts(Tp);
697 }
698 
699 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
700                                                    ScalarEvolution *SE,
701                                                    const SCEV *Ptr) const {
702   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
703   assert(Cost >= 0 && "TTI should not produce negative costs!");
704   return Cost;
705 }
706 
707 int TargetTransformInfo::getMemcpyCost(const Instruction *I) const {
708   int Cost = TTIImpl->getMemcpyCost(I);
709   assert(Cost >= 0 && "TTI should not produce negative costs!");
710   return Cost;
711 }
712 
713 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
714                                                     bool IsPairwiseForm) const {
715   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
716   assert(Cost >= 0 && "TTI should not produce negative costs!");
717   return Cost;
718 }
719 
720 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
721                                                 bool IsPairwiseForm,
722                                                 bool IsUnsigned) const {
723   int Cost =
724       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
725   assert(Cost >= 0 && "TTI should not produce negative costs!");
726   return Cost;
727 }
728 
729 unsigned
730 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
731   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
732 }
733 
734 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
735                                              MemIntrinsicInfo &Info) const {
736   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
737 }
738 
739 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
740   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
741 }
742 
743 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
744     IntrinsicInst *Inst, Type *ExpectedType) const {
745   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
746 }
747 
748 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
749                                                      Value *Length,
750                                                      unsigned SrcAlign,
751                                                      unsigned DestAlign) const {
752   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
753                                             DestAlign);
754 }
755 
756 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
757     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
758     unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
759   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
760                                              SrcAlign, DestAlign);
761 }
762 
763 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
764                                               const Function *Callee) const {
765   return TTIImpl->areInlineCompatible(Caller, Callee);
766 }
767 
768 bool TargetTransformInfo::areFunctionArgsABICompatible(
769     const Function *Caller, const Function *Callee,
770     SmallPtrSetImpl<Argument *> &Args) const {
771   return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
772 }
773 
774 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
775                                              Type *Ty) const {
776   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
777 }
778 
779 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
780                                               Type *Ty) const {
781   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
782 }
783 
784 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
785   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
786 }
787 
788 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
789   return TTIImpl->isLegalToVectorizeLoad(LI);
790 }
791 
792 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
793   return TTIImpl->isLegalToVectorizeStore(SI);
794 }
795 
796 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
797     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
798   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
799                                               AddrSpace);
800 }
801 
802 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
803     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
804   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
805                                                AddrSpace);
806 }
807 
808 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
809                                                   unsigned LoadSize,
810                                                   unsigned ChainSizeInBytes,
811                                                   VectorType *VecTy) const {
812   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
813 }
814 
815 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
816                                                    unsigned StoreSize,
817                                                    unsigned ChainSizeInBytes,
818                                                    VectorType *VecTy) const {
819   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
820 }
821 
822 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode,
823                                                 Type *Ty, ReductionFlags Flags) const {
824   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
825 }
826 
827 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
828   return TTIImpl->shouldExpandReduction(II);
829 }
830 
831 unsigned TargetTransformInfo::getGISelRematGlobalCost() const {
832   return TTIImpl->getGISelRematGlobalCost();
833 }
834 
835 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
836   return TTIImpl->getInstructionLatency(I);
837 }
838 
839 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
840                                      unsigned Level) {
841   // We don't need a shuffle if we just want to have element 0 in position 0 of
842   // the vector.
843   if (!SI && Level == 0 && IsLeft)
844     return true;
845   else if (!SI)
846     return false;
847 
848   SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
849 
850   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
851   // we look at the left or right side.
852   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
853     Mask[i] = val;
854 
855   SmallVector<int, 16> ActualMask = SI->getShuffleMask();
856   return Mask == ActualMask;
857 }
858 
859 namespace {
860 /// Kind of the reduction data.
861 enum ReductionKind {
862   RK_None,           /// Not a reduction.
863   RK_Arithmetic,     /// Binary reduction data.
864   RK_MinMax,         /// Min/max reduction data.
865   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
866 };
867 /// Contains opcode + LHS/RHS parts of the reduction operations.
868 struct ReductionData {
869   ReductionData() = delete;
870   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
871       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
872     assert(Kind != RK_None && "expected binary or min/max reduction only.");
873   }
874   unsigned Opcode = 0;
875   Value *LHS = nullptr;
876   Value *RHS = nullptr;
877   ReductionKind Kind = RK_None;
878   bool hasSameData(ReductionData &RD) const {
879     return Kind == RD.Kind && Opcode == RD.Opcode;
880   }
881 };
882 } // namespace
883 
884 static Optional<ReductionData> getReductionData(Instruction *I) {
885   Value *L, *R;
886   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
887     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
888   if (auto *SI = dyn_cast<SelectInst>(I)) {
889     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
890         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
891         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
892         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
893         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
894         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
895       auto *CI = cast<CmpInst>(SI->getCondition());
896       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
897     }
898     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
899         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
900       auto *CI = cast<CmpInst>(SI->getCondition());
901       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
902     }
903   }
904   return llvm::None;
905 }
906 
907 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
908                                                    unsigned Level,
909                                                    unsigned NumLevels) {
910   // Match one level of pairwise operations.
911   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
912   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
913   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
914   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
915   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
916   if (!I)
917     return RK_None;
918 
919   assert(I->getType()->isVectorTy() && "Expecting a vector type");
920 
921   Optional<ReductionData> RD = getReductionData(I);
922   if (!RD)
923     return RK_None;
924 
925   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
926   if (!LS && Level)
927     return RK_None;
928   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
929   if (!RS && Level)
930     return RK_None;
931 
932   // On level 0 we can omit one shufflevector instruction.
933   if (!Level && !RS && !LS)
934     return RK_None;
935 
936   // Shuffle inputs must match.
937   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
938   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
939   Value *NextLevelOp = nullptr;
940   if (NextLevelOpR && NextLevelOpL) {
941     // If we have two shuffles their operands must match.
942     if (NextLevelOpL != NextLevelOpR)
943       return RK_None;
944 
945     NextLevelOp = NextLevelOpL;
946   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
947     // On the first level we can omit the shufflevector <0, undef,...>. So the
948     // input to the other shufflevector <1, undef> must match with one of the
949     // inputs to the current binary operation.
950     // Example:
951     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
952     //  %BinOp        = fadd          %NextLevelOpL, %R
953     if (NextLevelOpL && NextLevelOpL != RD->RHS)
954       return RK_None;
955     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
956       return RK_None;
957 
958     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
959   } else
960     return RK_None;
961 
962   // Check that the next levels binary operation exists and matches with the
963   // current one.
964   if (Level + 1 != NumLevels) {
965     Optional<ReductionData> NextLevelRD =
966         getReductionData(cast<Instruction>(NextLevelOp));
967     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
968       return RK_None;
969   }
970 
971   // Shuffle mask for pairwise operation must match.
972   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
973     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
974       return RK_None;
975   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
976     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
977       return RK_None;
978   } else {
979     return RK_None;
980   }
981 
982   if (++Level == NumLevels)
983     return RD->Kind;
984 
985   // Match next level.
986   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
987                                        NumLevels);
988 }
989 
990 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
991                                             unsigned &Opcode, Type *&Ty) {
992   if (!EnableReduxCost)
993     return RK_None;
994 
995   // Need to extract the first element.
996   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
997   unsigned Idx = ~0u;
998   if (CI)
999     Idx = CI->getZExtValue();
1000   if (Idx != 0)
1001     return RK_None;
1002 
1003   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1004   if (!RdxStart)
1005     return RK_None;
1006   Optional<ReductionData> RD = getReductionData(RdxStart);
1007   if (!RD)
1008     return RK_None;
1009 
1010   Type *VecTy = RdxStart->getType();
1011   unsigned NumVecElems = VecTy->getVectorNumElements();
1012   if (!isPowerOf2_32(NumVecElems))
1013     return RK_None;
1014 
1015   // We look for a sequence of shuffle,shuffle,add triples like the following
1016   // that builds a pairwise reduction tree.
1017   //
1018   //  (X0, X1, X2, X3)
1019   //   (X0 + X1, X2 + X3, undef, undef)
1020   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
1021   //
1022   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
1023   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
1024   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
1025   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
1026   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
1027   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1028   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
1029   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1030   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1031   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
1032   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1033   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
1034       RK_None)
1035     return RK_None;
1036 
1037   Opcode = RD->Opcode;
1038   Ty = VecTy;
1039 
1040   return RD->Kind;
1041 }
1042 
1043 static std::pair<Value *, ShuffleVectorInst *>
1044 getShuffleAndOtherOprd(Value *L, Value *R) {
1045   ShuffleVectorInst *S = nullptr;
1046 
1047   if ((S = dyn_cast<ShuffleVectorInst>(L)))
1048     return std::make_pair(R, S);
1049 
1050   S = dyn_cast<ShuffleVectorInst>(R);
1051   return std::make_pair(L, S);
1052 }
1053 
1054 static ReductionKind
1055 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
1056                               unsigned &Opcode, Type *&Ty) {
1057   if (!EnableReduxCost)
1058     return RK_None;
1059 
1060   // Need to extract the first element.
1061   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1062   unsigned Idx = ~0u;
1063   if (CI)
1064     Idx = CI->getZExtValue();
1065   if (Idx != 0)
1066     return RK_None;
1067 
1068   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1069   if (!RdxStart)
1070     return RK_None;
1071   Optional<ReductionData> RD = getReductionData(RdxStart);
1072   if (!RD)
1073     return RK_None;
1074 
1075   Type *VecTy = ReduxRoot->getOperand(0)->getType();
1076   unsigned NumVecElems = VecTy->getVectorNumElements();
1077   if (!isPowerOf2_32(NumVecElems))
1078     return RK_None;
1079 
1080   // We look for a sequence of shuffles and adds like the following matching one
1081   // fadd, shuffle vector pair at a time.
1082   //
1083   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
1084   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
1085   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
1086   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
1087   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1088   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
1089   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1090 
1091   unsigned MaskStart = 1;
1092   Instruction *RdxOp = RdxStart;
1093   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
1094   unsigned NumVecElemsRemain = NumVecElems;
1095   while (NumVecElemsRemain - 1) {
1096     // Check for the right reduction operation.
1097     if (!RdxOp)
1098       return RK_None;
1099     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
1100     if (!RDLevel || !RDLevel->hasSameData(*RD))
1101       return RK_None;
1102 
1103     Value *NextRdxOp;
1104     ShuffleVectorInst *Shuffle;
1105     std::tie(NextRdxOp, Shuffle) =
1106         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
1107 
1108     // Check the current reduction operation and the shuffle use the same value.
1109     if (Shuffle == nullptr)
1110       return RK_None;
1111     if (Shuffle->getOperand(0) != NextRdxOp)
1112       return RK_None;
1113 
1114     // Check that shuffle masks matches.
1115     for (unsigned j = 0; j != MaskStart; ++j)
1116       ShuffleMask[j] = MaskStart + j;
1117     // Fill the rest of the mask with -1 for undef.
1118     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
1119 
1120     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
1121     if (ShuffleMask != Mask)
1122       return RK_None;
1123 
1124     RdxOp = dyn_cast<Instruction>(NextRdxOp);
1125     NumVecElemsRemain /= 2;
1126     MaskStart *= 2;
1127   }
1128 
1129   Opcode = RD->Opcode;
1130   Ty = VecTy;
1131   return RD->Kind;
1132 }
1133 
1134 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1135   switch (I->getOpcode()) {
1136   case Instruction::GetElementPtr:
1137     return getUserCost(I);
1138 
1139   case Instruction::Ret:
1140   case Instruction::PHI:
1141   case Instruction::Br: {
1142     return getCFInstrCost(I->getOpcode());
1143   }
1144   case Instruction::Add:
1145   case Instruction::FAdd:
1146   case Instruction::Sub:
1147   case Instruction::FSub:
1148   case Instruction::Mul:
1149   case Instruction::FMul:
1150   case Instruction::UDiv:
1151   case Instruction::SDiv:
1152   case Instruction::FDiv:
1153   case Instruction::URem:
1154   case Instruction::SRem:
1155   case Instruction::FRem:
1156   case Instruction::Shl:
1157   case Instruction::LShr:
1158   case Instruction::AShr:
1159   case Instruction::And:
1160   case Instruction::Or:
1161   case Instruction::Xor: {
1162     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1163     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1164     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1165     Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1166     SmallVector<const Value *, 2> Operands(I->operand_values());
1167     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1168                                   Op1VP, Op2VP, Operands);
1169   }
1170   case Instruction::FNeg: {
1171     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1172     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1173     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1174     Op2VK = OK_AnyValue;
1175     Op2VP = OP_None;
1176     SmallVector<const Value *, 2> Operands(I->operand_values());
1177     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1178                                   Op1VP, Op2VP, Operands);
1179   }
1180   case Instruction::Select: {
1181     const SelectInst *SI = cast<SelectInst>(I);
1182     Type *CondTy = SI->getCondition()->getType();
1183     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1184   }
1185   case Instruction::ICmp:
1186   case Instruction::FCmp: {
1187     Type *ValTy = I->getOperand(0)->getType();
1188     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1189   }
1190   case Instruction::Store: {
1191     const StoreInst *SI = cast<StoreInst>(I);
1192     Type *ValTy = SI->getValueOperand()->getType();
1193     return getMemoryOpCost(I->getOpcode(), ValTy,
1194                                 SI->getAlignment(),
1195                                 SI->getPointerAddressSpace(), I);
1196   }
1197   case Instruction::Load: {
1198     const LoadInst *LI = cast<LoadInst>(I);
1199     return getMemoryOpCost(I->getOpcode(), I->getType(),
1200                                 LI->getAlignment(),
1201                                 LI->getPointerAddressSpace(), I);
1202   }
1203   case Instruction::ZExt:
1204   case Instruction::SExt:
1205   case Instruction::FPToUI:
1206   case Instruction::FPToSI:
1207   case Instruction::FPExt:
1208   case Instruction::PtrToInt:
1209   case Instruction::IntToPtr:
1210   case Instruction::SIToFP:
1211   case Instruction::UIToFP:
1212   case Instruction::Trunc:
1213   case Instruction::FPTrunc:
1214   case Instruction::BitCast:
1215   case Instruction::AddrSpaceCast: {
1216     Type *SrcTy = I->getOperand(0)->getType();
1217     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1218   }
1219   case Instruction::ExtractElement: {
1220     const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1221     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1222     unsigned Idx = -1;
1223     if (CI)
1224       Idx = CI->getZExtValue();
1225 
1226     // Try to match a reduction sequence (series of shufflevector and vector
1227     // adds followed by a extractelement).
1228     unsigned ReduxOpCode;
1229     Type *ReduxType;
1230 
1231     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1232     case RK_Arithmetic:
1233       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1234                                              /*IsPairwiseForm=*/false);
1235     case RK_MinMax:
1236       return getMinMaxReductionCost(
1237           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1238           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1239     case RK_UnsignedMinMax:
1240       return getMinMaxReductionCost(
1241           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1242           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1243     case RK_None:
1244       break;
1245     }
1246 
1247     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1248     case RK_Arithmetic:
1249       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1250                                              /*IsPairwiseForm=*/true);
1251     case RK_MinMax:
1252       return getMinMaxReductionCost(
1253           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1254           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1255     case RK_UnsignedMinMax:
1256       return getMinMaxReductionCost(
1257           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1258           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1259     case RK_None:
1260       break;
1261     }
1262 
1263     return getVectorInstrCost(I->getOpcode(),
1264                                    EEI->getOperand(0)->getType(), Idx);
1265   }
1266   case Instruction::InsertElement: {
1267     const InsertElementInst * IE = cast<InsertElementInst>(I);
1268     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1269     unsigned Idx = -1;
1270     if (CI)
1271       Idx = CI->getZExtValue();
1272     return getVectorInstrCost(I->getOpcode(),
1273                                    IE->getType(), Idx);
1274   }
1275   case Instruction::ShuffleVector: {
1276     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1277     Type *Ty = Shuffle->getType();
1278     Type *SrcTy = Shuffle->getOperand(0)->getType();
1279 
1280     // TODO: Identify and add costs for insert subvector, etc.
1281     int SubIndex;
1282     if (Shuffle->isExtractSubvectorMask(SubIndex))
1283       return TTIImpl->getShuffleCost(SK_ExtractSubvector, SrcTy, SubIndex, Ty);
1284 
1285     if (Shuffle->changesLength())
1286       return -1;
1287 
1288     if (Shuffle->isIdentity())
1289       return 0;
1290 
1291     if (Shuffle->isReverse())
1292       return TTIImpl->getShuffleCost(SK_Reverse, Ty, 0, nullptr);
1293 
1294     if (Shuffle->isSelect())
1295       return TTIImpl->getShuffleCost(SK_Select, Ty, 0, nullptr);
1296 
1297     if (Shuffle->isTranspose())
1298       return TTIImpl->getShuffleCost(SK_Transpose, Ty, 0, nullptr);
1299 
1300     if (Shuffle->isZeroEltSplat())
1301       return TTIImpl->getShuffleCost(SK_Broadcast, Ty, 0, nullptr);
1302 
1303     if (Shuffle->isSingleSource())
1304       return TTIImpl->getShuffleCost(SK_PermuteSingleSrc, Ty, 0, nullptr);
1305 
1306     return TTIImpl->getShuffleCost(SK_PermuteTwoSrc, Ty, 0, nullptr);
1307   }
1308   case Instruction::Call:
1309     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1310       SmallVector<Value *, 4> Args(II->arg_operands());
1311 
1312       FastMathFlags FMF;
1313       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1314         FMF = FPMO->getFastMathFlags();
1315 
1316       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
1317                                         Args, FMF);
1318     }
1319     return -1;
1320   default:
1321     // We don't have any information on this instruction.
1322     return -1;
1323   }
1324 }
1325 
1326 TargetTransformInfo::Concept::~Concept() {}
1327 
1328 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1329 
1330 TargetIRAnalysis::TargetIRAnalysis(
1331     std::function<Result(const Function &)> TTICallback)
1332     : TTICallback(std::move(TTICallback)) {}
1333 
1334 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1335                                                FunctionAnalysisManager &) {
1336   return TTICallback(F);
1337 }
1338 
1339 AnalysisKey TargetIRAnalysis::Key;
1340 
1341 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1342   return Result(F.getParent()->getDataLayout());
1343 }
1344 
1345 // Register the basic pass.
1346 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1347                 "Target Transform Information", false, true)
1348 char TargetTransformInfoWrapperPass::ID = 0;
1349 
1350 void TargetTransformInfoWrapperPass::anchor() {}
1351 
1352 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1353     : ImmutablePass(ID) {
1354   initializeTargetTransformInfoWrapperPassPass(
1355       *PassRegistry::getPassRegistry());
1356 }
1357 
1358 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1359     TargetIRAnalysis TIRA)
1360     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1361   initializeTargetTransformInfoWrapperPassPass(
1362       *PassRegistry::getPassRegistry());
1363 }
1364 
1365 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1366   FunctionAnalysisManager DummyFAM;
1367   TTI = TIRA.run(F, DummyFAM);
1368   return *TTI;
1369 }
1370 
1371 ImmutablePass *
1372 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1373   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1374 }
1375