1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/Analysis/TargetTransformInfo.h"
11 #include "llvm/Analysis/TargetTransformInfoImpl.h"
12 #include "llvm/IR/CallSite.h"
13 #include "llvm/IR/DataLayout.h"
14 #include "llvm/IR/Instruction.h"
15 #include "llvm/IR/Instructions.h"
16 #include "llvm/IR/IntrinsicInst.h"
17 #include "llvm/IR/Module.h"
18 #include "llvm/IR/Operator.h"
19 #include "llvm/IR/PatternMatch.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include <utility>
23 
24 using namespace llvm;
25 using namespace PatternMatch;
26 
27 #define DEBUG_TYPE "tti"
28 
29 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
30                                      cl::Hidden,
31                                      cl::desc("Recognize reduction patterns."));
32 
33 namespace {
34 /// \brief No-op implementation of the TTI interface using the utility base
35 /// classes.
36 ///
37 /// This is used when no target specific information is available.
38 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
39   explicit NoTTIImpl(const DataLayout &DL)
40       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
41 };
42 }
43 
44 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
45     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
46 
47 TargetTransformInfo::~TargetTransformInfo() {}
48 
49 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
50     : TTIImpl(std::move(Arg.TTIImpl)) {}
51 
52 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
53   TTIImpl = std::move(RHS.TTIImpl);
54   return *this;
55 }
56 
57 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
58                                           Type *OpTy) const {
59   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
60   assert(Cost >= 0 && "TTI should not produce negative costs!");
61   return Cost;
62 }
63 
64 int TargetTransformInfo::getCallCost(FunctionType *FTy, int NumArgs) const {
65   int Cost = TTIImpl->getCallCost(FTy, NumArgs);
66   assert(Cost >= 0 && "TTI should not produce negative costs!");
67   return Cost;
68 }
69 
70 int TargetTransformInfo::getCallCost(const Function *F,
71                                      ArrayRef<const Value *> Arguments) const {
72   int Cost = TTIImpl->getCallCost(F, Arguments);
73   assert(Cost >= 0 && "TTI should not produce negative costs!");
74   return Cost;
75 }
76 
77 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
78   return TTIImpl->getInliningThresholdMultiplier();
79 }
80 
81 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
82                                     ArrayRef<const Value *> Operands) const {
83   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
84 }
85 
86 int TargetTransformInfo::getExtCost(const Instruction *I,
87                                     const Value *Src) const {
88   return TTIImpl->getExtCost(I, Src);
89 }
90 
91 int TargetTransformInfo::getIntrinsicCost(
92     Intrinsic::ID IID, Type *RetTy, ArrayRef<const Value *> Arguments) const {
93   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments);
94   assert(Cost >= 0 && "TTI should not produce negative costs!");
95   return Cost;
96 }
97 
98 unsigned
99 TargetTransformInfo::getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
100                                                       unsigned &JTSize) const {
101   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize);
102 }
103 
104 int TargetTransformInfo::getUserCost(const User *U,
105     ArrayRef<const Value *> Operands) const {
106   int Cost = TTIImpl->getUserCost(U, Operands);
107   assert(Cost >= 0 && "TTI should not produce negative costs!");
108   return Cost;
109 }
110 
111 bool TargetTransformInfo::hasBranchDivergence() const {
112   return TTIImpl->hasBranchDivergence();
113 }
114 
115 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
116   return TTIImpl->isSourceOfDivergence(V);
117 }
118 
119 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
120   return TTIImpl->isAlwaysUniform(V);
121 }
122 
123 unsigned TargetTransformInfo::getFlatAddressSpace() const {
124   return TTIImpl->getFlatAddressSpace();
125 }
126 
127 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
128   return TTIImpl->isLoweredToCall(F);
129 }
130 
131 void TargetTransformInfo::getUnrollingPreferences(
132     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
133   return TTIImpl->getUnrollingPreferences(L, SE, UP);
134 }
135 
136 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
137   return TTIImpl->isLegalAddImmediate(Imm);
138 }
139 
140 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
141   return TTIImpl->isLegalICmpImmediate(Imm);
142 }
143 
144 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
145                                                 int64_t BaseOffset,
146                                                 bool HasBaseReg,
147                                                 int64_t Scale,
148                                                 unsigned AddrSpace,
149                                                 Instruction *I) const {
150   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
151                                         Scale, AddrSpace, I);
152 }
153 
154 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
155   return TTIImpl->isLSRCostLess(C1, C2);
156 }
157 
158 bool TargetTransformInfo::canMacroFuseCmp() const {
159   return TTIImpl->canMacroFuseCmp();
160 }
161 
162 bool TargetTransformInfo::shouldFavorPostInc() const {
163   return TTIImpl->shouldFavorPostInc();
164 }
165 
166 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType) const {
167   return TTIImpl->isLegalMaskedStore(DataType);
168 }
169 
170 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType) const {
171   return TTIImpl->isLegalMaskedLoad(DataType);
172 }
173 
174 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
175   return TTIImpl->isLegalMaskedGather(DataType);
176 }
177 
178 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
179   return TTIImpl->isLegalMaskedScatter(DataType);
180 }
181 
182 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
183   return TTIImpl->hasDivRemOp(DataType, IsSigned);
184 }
185 
186 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
187                                              unsigned AddrSpace) const {
188   return TTIImpl->hasVolatileVariant(I, AddrSpace);
189 }
190 
191 bool TargetTransformInfo::prefersVectorizedAddressing() const {
192   return TTIImpl->prefersVectorizedAddressing();
193 }
194 
195 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
196                                               int64_t BaseOffset,
197                                               bool HasBaseReg,
198                                               int64_t Scale,
199                                               unsigned AddrSpace) const {
200   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
201                                            Scale, AddrSpace);
202   assert(Cost >= 0 && "TTI should not produce negative costs!");
203   return Cost;
204 }
205 
206 bool TargetTransformInfo::LSRWithInstrQueries() const {
207   return TTIImpl->LSRWithInstrQueries();
208 }
209 
210 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
211   return TTIImpl->isTruncateFree(Ty1, Ty2);
212 }
213 
214 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
215   return TTIImpl->isProfitableToHoist(I);
216 }
217 
218 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
219 
220 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
221   return TTIImpl->isTypeLegal(Ty);
222 }
223 
224 unsigned TargetTransformInfo::getJumpBufAlignment() const {
225   return TTIImpl->getJumpBufAlignment();
226 }
227 
228 unsigned TargetTransformInfo::getJumpBufSize() const {
229   return TTIImpl->getJumpBufSize();
230 }
231 
232 bool TargetTransformInfo::shouldBuildLookupTables() const {
233   return TTIImpl->shouldBuildLookupTables();
234 }
235 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(Constant *C) const {
236   return TTIImpl->shouldBuildLookupTablesForConstant(C);
237 }
238 
239 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
240   return TTIImpl->useColdCCForColdCall(F);
241 }
242 
243 unsigned TargetTransformInfo::
244 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
245   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
246 }
247 
248 unsigned TargetTransformInfo::
249 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
250                                  unsigned VF) const {
251   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
252 }
253 
254 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
255   return TTIImpl->supportsEfficientVectorElementLoadStore();
256 }
257 
258 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
259   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
260 }
261 
262 const TargetTransformInfo::MemCmpExpansionOptions *
263 TargetTransformInfo::enableMemCmpExpansion(bool IsZeroCmp) const {
264   return TTIImpl->enableMemCmpExpansion(IsZeroCmp);
265 }
266 
267 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
268   return TTIImpl->enableInterleavedAccessVectorization();
269 }
270 
271 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
272   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
273 }
274 
275 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
276                                                          unsigned BitWidth,
277                                                          unsigned AddressSpace,
278                                                          unsigned Alignment,
279                                                          bool *Fast) const {
280   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
281                                                  Alignment, Fast);
282 }
283 
284 TargetTransformInfo::PopcntSupportKind
285 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
286   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
287 }
288 
289 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
290   return TTIImpl->haveFastSqrt(Ty);
291 }
292 
293 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
294   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
295 }
296 
297 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
298   int Cost = TTIImpl->getFPOpCost(Ty);
299   assert(Cost >= 0 && "TTI should not produce negative costs!");
300   return Cost;
301 }
302 
303 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
304                                                const APInt &Imm,
305                                                Type *Ty) const {
306   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
307   assert(Cost >= 0 && "TTI should not produce negative costs!");
308   return Cost;
309 }
310 
311 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
312   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
313   assert(Cost >= 0 && "TTI should not produce negative costs!");
314   return Cost;
315 }
316 
317 int TargetTransformInfo::getIntImmCost(unsigned Opcode, unsigned Idx,
318                                        const APInt &Imm, Type *Ty) const {
319   int Cost = TTIImpl->getIntImmCost(Opcode, Idx, Imm, Ty);
320   assert(Cost >= 0 && "TTI should not produce negative costs!");
321   return Cost;
322 }
323 
324 int TargetTransformInfo::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
325                                        const APInt &Imm, Type *Ty) const {
326   int Cost = TTIImpl->getIntImmCost(IID, Idx, Imm, Ty);
327   assert(Cost >= 0 && "TTI should not produce negative costs!");
328   return Cost;
329 }
330 
331 unsigned TargetTransformInfo::getNumberOfRegisters(bool Vector) const {
332   return TTIImpl->getNumberOfRegisters(Vector);
333 }
334 
335 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
336   return TTIImpl->getRegisterBitWidth(Vector);
337 }
338 
339 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
340   return TTIImpl->getMinVectorRegisterBitWidth();
341 }
342 
343 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
344   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
345 }
346 
347 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
348     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
349   return TTIImpl->shouldConsiderAddressTypePromotion(
350       I, AllowPromotionWithoutCommonHeader);
351 }
352 
353 unsigned TargetTransformInfo::getCacheLineSize() const {
354   return TTIImpl->getCacheLineSize();
355 }
356 
357 llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
358   const {
359   return TTIImpl->getCacheSize(Level);
360 }
361 
362 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
363   CacheLevel Level) const {
364   return TTIImpl->getCacheAssociativity(Level);
365 }
366 
367 unsigned TargetTransformInfo::getPrefetchDistance() const {
368   return TTIImpl->getPrefetchDistance();
369 }
370 
371 unsigned TargetTransformInfo::getMinPrefetchStride() const {
372   return TTIImpl->getMinPrefetchStride();
373 }
374 
375 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
376   return TTIImpl->getMaxPrefetchIterationsAhead();
377 }
378 
379 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
380   return TTIImpl->getMaxInterleaveFactor(VF);
381 }
382 
383 int TargetTransformInfo::getArithmeticInstrCost(
384     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
385     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
386     OperandValueProperties Opd2PropInfo,
387     ArrayRef<const Value *> Args) const {
388   int Cost = TTIImpl->getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
389                                              Opd1PropInfo, Opd2PropInfo, Args);
390   assert(Cost >= 0 && "TTI should not produce negative costs!");
391   return Cost;
392 }
393 
394 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
395                                         Type *SubTp) const {
396   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
397   assert(Cost >= 0 && "TTI should not produce negative costs!");
398   return Cost;
399 }
400 
401 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
402                                  Type *Src, const Instruction *I) const {
403   assert ((I == nullptr || I->getOpcode() == Opcode) &&
404           "Opcode should reflect passed instruction.");
405   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
406   assert(Cost >= 0 && "TTI should not produce negative costs!");
407   return Cost;
408 }
409 
410 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
411                                                   VectorType *VecTy,
412                                                   unsigned Index) const {
413   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
414   assert(Cost >= 0 && "TTI should not produce negative costs!");
415   return Cost;
416 }
417 
418 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
419   int Cost = TTIImpl->getCFInstrCost(Opcode);
420   assert(Cost >= 0 && "TTI should not produce negative costs!");
421   return Cost;
422 }
423 
424 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
425                                  Type *CondTy, const Instruction *I) const {
426   assert ((I == nullptr || I->getOpcode() == Opcode) &&
427           "Opcode should reflect passed instruction.");
428   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
429   assert(Cost >= 0 && "TTI should not produce negative costs!");
430   return Cost;
431 }
432 
433 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
434                                             unsigned Index) const {
435   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
436   assert(Cost >= 0 && "TTI should not produce negative costs!");
437   return Cost;
438 }
439 
440 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
441                                          unsigned Alignment,
442                                          unsigned AddressSpace,
443                                          const Instruction *I) const {
444   assert ((I == nullptr || I->getOpcode() == Opcode) &&
445           "Opcode should reflect passed instruction.");
446   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
447   assert(Cost >= 0 && "TTI should not produce negative costs!");
448   return Cost;
449 }
450 
451 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
452                                                unsigned Alignment,
453                                                unsigned AddressSpace) const {
454   int Cost =
455       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
456   assert(Cost >= 0 && "TTI should not produce negative costs!");
457   return Cost;
458 }
459 
460 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
461                                                 Value *Ptr, bool VariableMask,
462                                                 unsigned Alignment) const {
463   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
464                                              Alignment);
465   assert(Cost >= 0 && "TTI should not produce negative costs!");
466   return Cost;
467 }
468 
469 int TargetTransformInfo::getInterleavedMemoryOpCost(
470     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
471     unsigned Alignment, unsigned AddressSpace) const {
472   int Cost = TTIImpl->getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
473                                                  Alignment, AddressSpace);
474   assert(Cost >= 0 && "TTI should not produce negative costs!");
475   return Cost;
476 }
477 
478 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
479                                     ArrayRef<Type *> Tys, FastMathFlags FMF,
480                                     unsigned ScalarizationCostPassed) const {
481   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
482                                             ScalarizationCostPassed);
483   assert(Cost >= 0 && "TTI should not produce negative costs!");
484   return Cost;
485 }
486 
487 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
488            ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) const {
489   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
490   assert(Cost >= 0 && "TTI should not produce negative costs!");
491   return Cost;
492 }
493 
494 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
495                                           ArrayRef<Type *> Tys) const {
496   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
497   assert(Cost >= 0 && "TTI should not produce negative costs!");
498   return Cost;
499 }
500 
501 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
502   return TTIImpl->getNumberOfParts(Tp);
503 }
504 
505 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
506                                                    ScalarEvolution *SE,
507                                                    const SCEV *Ptr) const {
508   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
509   assert(Cost >= 0 && "TTI should not produce negative costs!");
510   return Cost;
511 }
512 
513 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
514                                                     bool IsPairwiseForm) const {
515   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
516   assert(Cost >= 0 && "TTI should not produce negative costs!");
517   return Cost;
518 }
519 
520 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
521                                                 bool IsPairwiseForm,
522                                                 bool IsUnsigned) const {
523   int Cost =
524       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
525   assert(Cost >= 0 && "TTI should not produce negative costs!");
526   return Cost;
527 }
528 
529 unsigned
530 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
531   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
532 }
533 
534 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
535                                              MemIntrinsicInfo &Info) const {
536   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
537 }
538 
539 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
540   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
541 }
542 
543 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
544     IntrinsicInst *Inst, Type *ExpectedType) const {
545   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
546 }
547 
548 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
549                                                      Value *Length,
550                                                      unsigned SrcAlign,
551                                                      unsigned DestAlign) const {
552   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
553                                             DestAlign);
554 }
555 
556 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
557     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
558     unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
559   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
560                                              SrcAlign, DestAlign);
561 }
562 
563 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
564                                               const Function *Callee) const {
565   return TTIImpl->areInlineCompatible(Caller, Callee);
566 }
567 
568 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
569                                              Type *Ty) const {
570   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
571 }
572 
573 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
574                                               Type *Ty) const {
575   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
576 }
577 
578 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
579   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
580 }
581 
582 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
583   return TTIImpl->isLegalToVectorizeLoad(LI);
584 }
585 
586 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
587   return TTIImpl->isLegalToVectorizeStore(SI);
588 }
589 
590 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
591     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
592   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
593                                               AddrSpace);
594 }
595 
596 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
597     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
598   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
599                                                AddrSpace);
600 }
601 
602 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
603                                                   unsigned LoadSize,
604                                                   unsigned ChainSizeInBytes,
605                                                   VectorType *VecTy) const {
606   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
607 }
608 
609 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
610                                                    unsigned StoreSize,
611                                                    unsigned ChainSizeInBytes,
612                                                    VectorType *VecTy) const {
613   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
614 }
615 
616 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode,
617                                                 Type *Ty, ReductionFlags Flags) const {
618   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
619 }
620 
621 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
622   return TTIImpl->shouldExpandReduction(II);
623 }
624 
625 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
626   return TTIImpl->getInstructionLatency(I);
627 }
628 
629 static bool isReverseVectorMask(ArrayRef<int> Mask) {
630   for (unsigned i = 0, MaskSize = Mask.size(); i < MaskSize; ++i)
631     if (Mask[i] >= 0 && Mask[i] != (int)(MaskSize - 1 - i))
632       return false;
633   return true;
634 }
635 
636 static bool isSingleSourceVectorMask(ArrayRef<int> Mask) {
637   bool Vec0 = false;
638   bool Vec1 = false;
639   for (unsigned i = 0, NumVecElts = Mask.size(); i < NumVecElts; ++i) {
640     if (Mask[i] >= 0) {
641       if ((unsigned)Mask[i] >= NumVecElts)
642         Vec1 = true;
643       else
644         Vec0 = true;
645     }
646   }
647   return !(Vec0 && Vec1);
648 }
649 
650 static bool isZeroEltBroadcastVectorMask(ArrayRef<int> Mask) {
651   for (unsigned i = 0; i < Mask.size(); ++i)
652     if (Mask[i] > 0)
653       return false;
654   return true;
655 }
656 
657 static bool isAlternateVectorMask(ArrayRef<int> Mask) {
658   bool isAlternate = true;
659   unsigned MaskSize = Mask.size();
660 
661   // Example: shufflevector A, B, <0,5,2,7>
662   for (unsigned i = 0; i < MaskSize && isAlternate; ++i) {
663     if (Mask[i] < 0)
664       continue;
665     isAlternate = Mask[i] == (int)((i & 1) ? MaskSize + i : i);
666   }
667 
668   if (isAlternate)
669     return true;
670 
671   isAlternate = true;
672   // Example: shufflevector A, B, <4,1,6,3>
673   for (unsigned i = 0; i < MaskSize && isAlternate; ++i) {
674     if (Mask[i] < 0)
675       continue;
676     isAlternate = Mask[i] == (int)((i & 1) ? i : MaskSize + i);
677   }
678 
679   return isAlternate;
680 }
681 
682 static TargetTransformInfo::OperandValueKind getOperandInfo(Value *V) {
683   TargetTransformInfo::OperandValueKind OpInfo =
684       TargetTransformInfo::OK_AnyValue;
685 
686   // Check for a splat of a constant or for a non uniform vector of constants.
687   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
688     OpInfo = TargetTransformInfo::OK_NonUniformConstantValue;
689     if (cast<Constant>(V)->getSplatValue() != nullptr)
690       OpInfo = TargetTransformInfo::OK_UniformConstantValue;
691   }
692 
693   // Check for a splat of a uniform value. This is not loop aware, so return
694   // true only for the obviously uniform cases (argument, globalvalue)
695   const Value *Splat = getSplatValue(V);
696   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
697     OpInfo = TargetTransformInfo::OK_UniformValue;
698 
699   return OpInfo;
700 }
701 
702 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
703                                      unsigned Level) {
704   // We don't need a shuffle if we just want to have element 0 in position 0 of
705   // the vector.
706   if (!SI && Level == 0 && IsLeft)
707     return true;
708   else if (!SI)
709     return false;
710 
711   SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
712 
713   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
714   // we look at the left or right side.
715   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
716     Mask[i] = val;
717 
718   SmallVector<int, 16> ActualMask = SI->getShuffleMask();
719   return Mask == ActualMask;
720 }
721 
722 namespace {
723 /// Kind of the reduction data.
724 enum ReductionKind {
725   RK_None,           /// Not a reduction.
726   RK_Arithmetic,     /// Binary reduction data.
727   RK_MinMax,         /// Min/max reduction data.
728   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
729 };
730 /// Contains opcode + LHS/RHS parts of the reduction operations.
731 struct ReductionData {
732   ReductionData() = delete;
733   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
734       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
735     assert(Kind != RK_None && "expected binary or min/max reduction only.");
736   }
737   unsigned Opcode = 0;
738   Value *LHS = nullptr;
739   Value *RHS = nullptr;
740   ReductionKind Kind = RK_None;
741   bool hasSameData(ReductionData &RD) const {
742     return Kind == RD.Kind && Opcode == RD.Opcode;
743   }
744 };
745 } // namespace
746 
747 static Optional<ReductionData> getReductionData(Instruction *I) {
748   Value *L, *R;
749   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
750     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
751   if (auto *SI = dyn_cast<SelectInst>(I)) {
752     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
753         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
754         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
755         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
756         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
757         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
758       auto *CI = cast<CmpInst>(SI->getCondition());
759       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
760     }
761     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
762         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
763       auto *CI = cast<CmpInst>(SI->getCondition());
764       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
765     }
766   }
767   return llvm::None;
768 }
769 
770 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
771                                                    unsigned Level,
772                                                    unsigned NumLevels) {
773   // Match one level of pairwise operations.
774   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
775   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
776   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
777   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
778   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
779   if (!I)
780     return RK_None;
781 
782   assert(I->getType()->isVectorTy() && "Expecting a vector type");
783 
784   Optional<ReductionData> RD = getReductionData(I);
785   if (!RD)
786     return RK_None;
787 
788   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
789   if (!LS && Level)
790     return RK_None;
791   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
792   if (!RS && Level)
793     return RK_None;
794 
795   // On level 0 we can omit one shufflevector instruction.
796   if (!Level && !RS && !LS)
797     return RK_None;
798 
799   // Shuffle inputs must match.
800   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
801   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
802   Value *NextLevelOp = nullptr;
803   if (NextLevelOpR && NextLevelOpL) {
804     // If we have two shuffles their operands must match.
805     if (NextLevelOpL != NextLevelOpR)
806       return RK_None;
807 
808     NextLevelOp = NextLevelOpL;
809   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
810     // On the first level we can omit the shufflevector <0, undef,...>. So the
811     // input to the other shufflevector <1, undef> must match with one of the
812     // inputs to the current binary operation.
813     // Example:
814     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
815     //  %BinOp        = fadd          %NextLevelOpL, %R
816     if (NextLevelOpL && NextLevelOpL != RD->RHS)
817       return RK_None;
818     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
819       return RK_None;
820 
821     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
822   } else
823     return RK_None;
824 
825   // Check that the next levels binary operation exists and matches with the
826   // current one.
827   if (Level + 1 != NumLevels) {
828     Optional<ReductionData> NextLevelRD =
829         getReductionData(cast<Instruction>(NextLevelOp));
830     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
831       return RK_None;
832   }
833 
834   // Shuffle mask for pairwise operation must match.
835   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
836     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
837       return RK_None;
838   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
839     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
840       return RK_None;
841   } else {
842     return RK_None;
843   }
844 
845   if (++Level == NumLevels)
846     return RD->Kind;
847 
848   // Match next level.
849   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
850                                        NumLevels);
851 }
852 
853 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
854                                             unsigned &Opcode, Type *&Ty) {
855   if (!EnableReduxCost)
856     return RK_None;
857 
858   // Need to extract the first element.
859   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
860   unsigned Idx = ~0u;
861   if (CI)
862     Idx = CI->getZExtValue();
863   if (Idx != 0)
864     return RK_None;
865 
866   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
867   if (!RdxStart)
868     return RK_None;
869   Optional<ReductionData> RD = getReductionData(RdxStart);
870   if (!RD)
871     return RK_None;
872 
873   Type *VecTy = RdxStart->getType();
874   unsigned NumVecElems = VecTy->getVectorNumElements();
875   if (!isPowerOf2_32(NumVecElems))
876     return RK_None;
877 
878   // We look for a sequence of shuffle,shuffle,add triples like the following
879   // that builds a pairwise reduction tree.
880   //
881   //  (X0, X1, X2, X3)
882   //   (X0 + X1, X2 + X3, undef, undef)
883   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
884   //
885   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
886   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
887   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
888   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
889   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
890   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
891   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
892   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
893   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
894   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
895   // %r = extractelement <4 x float> %bin.rdx8, i32 0
896   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
897       RK_None)
898     return RK_None;
899 
900   Opcode = RD->Opcode;
901   Ty = VecTy;
902 
903   return RD->Kind;
904 }
905 
906 static std::pair<Value *, ShuffleVectorInst *>
907 getShuffleAndOtherOprd(Value *L, Value *R) {
908   ShuffleVectorInst *S = nullptr;
909 
910   if ((S = dyn_cast<ShuffleVectorInst>(L)))
911     return std::make_pair(R, S);
912 
913   S = dyn_cast<ShuffleVectorInst>(R);
914   return std::make_pair(L, S);
915 }
916 
917 static ReductionKind
918 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
919                               unsigned &Opcode, Type *&Ty) {
920   if (!EnableReduxCost)
921     return RK_None;
922 
923   // Need to extract the first element.
924   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
925   unsigned Idx = ~0u;
926   if (CI)
927     Idx = CI->getZExtValue();
928   if (Idx != 0)
929     return RK_None;
930 
931   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
932   if (!RdxStart)
933     return RK_None;
934   Optional<ReductionData> RD = getReductionData(RdxStart);
935   if (!RD)
936     return RK_None;
937 
938   Type *VecTy = ReduxRoot->getOperand(0)->getType();
939   unsigned NumVecElems = VecTy->getVectorNumElements();
940   if (!isPowerOf2_32(NumVecElems))
941     return RK_None;
942 
943   // We look for a sequence of shuffles and adds like the following matching one
944   // fadd, shuffle vector pair at a time.
945   //
946   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
947   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
948   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
949   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
950   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
951   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
952   // %r = extractelement <4 x float> %bin.rdx8, i32 0
953 
954   unsigned MaskStart = 1;
955   Instruction *RdxOp = RdxStart;
956   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
957   unsigned NumVecElemsRemain = NumVecElems;
958   while (NumVecElemsRemain - 1) {
959     // Check for the right reduction operation.
960     if (!RdxOp)
961       return RK_None;
962     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
963     if (!RDLevel || !RDLevel->hasSameData(*RD))
964       return RK_None;
965 
966     Value *NextRdxOp;
967     ShuffleVectorInst *Shuffle;
968     std::tie(NextRdxOp, Shuffle) =
969         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
970 
971     // Check the current reduction operation and the shuffle use the same value.
972     if (Shuffle == nullptr)
973       return RK_None;
974     if (Shuffle->getOperand(0) != NextRdxOp)
975       return RK_None;
976 
977     // Check that shuffle masks matches.
978     for (unsigned j = 0; j != MaskStart; ++j)
979       ShuffleMask[j] = MaskStart + j;
980     // Fill the rest of the mask with -1 for undef.
981     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
982 
983     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
984     if (ShuffleMask != Mask)
985       return RK_None;
986 
987     RdxOp = dyn_cast<Instruction>(NextRdxOp);
988     NumVecElemsRemain /= 2;
989     MaskStart *= 2;
990   }
991 
992   Opcode = RD->Opcode;
993   Ty = VecTy;
994   return RD->Kind;
995 }
996 
997 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
998   switch (I->getOpcode()) {
999   case Instruction::GetElementPtr:
1000     return getUserCost(I);
1001 
1002   case Instruction::Ret:
1003   case Instruction::PHI:
1004   case Instruction::Br: {
1005     return getCFInstrCost(I->getOpcode());
1006   }
1007   case Instruction::Add:
1008   case Instruction::FAdd:
1009   case Instruction::Sub:
1010   case Instruction::FSub:
1011   case Instruction::Mul:
1012   case Instruction::FMul:
1013   case Instruction::UDiv:
1014   case Instruction::SDiv:
1015   case Instruction::FDiv:
1016   case Instruction::URem:
1017   case Instruction::SRem:
1018   case Instruction::FRem:
1019   case Instruction::Shl:
1020   case Instruction::LShr:
1021   case Instruction::AShr:
1022   case Instruction::And:
1023   case Instruction::Or:
1024   case Instruction::Xor: {
1025     TargetTransformInfo::OperandValueKind Op1VK =
1026       getOperandInfo(I->getOperand(0));
1027     TargetTransformInfo::OperandValueKind Op2VK =
1028       getOperandInfo(I->getOperand(1));
1029     SmallVector<const Value*, 2> Operands(I->operand_values());
1030     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK,
1031                                        Op2VK, TargetTransformInfo::OP_None,
1032                                        TargetTransformInfo::OP_None,
1033                                        Operands);
1034   }
1035   case Instruction::Select: {
1036     const SelectInst *SI = cast<SelectInst>(I);
1037     Type *CondTy = SI->getCondition()->getType();
1038     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1039   }
1040   case Instruction::ICmp:
1041   case Instruction::FCmp: {
1042     Type *ValTy = I->getOperand(0)->getType();
1043     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1044   }
1045   case Instruction::Store: {
1046     const StoreInst *SI = cast<StoreInst>(I);
1047     Type *ValTy = SI->getValueOperand()->getType();
1048     return getMemoryOpCost(I->getOpcode(), ValTy,
1049                                 SI->getAlignment(),
1050                                 SI->getPointerAddressSpace(), I);
1051   }
1052   case Instruction::Load: {
1053     const LoadInst *LI = cast<LoadInst>(I);
1054     return getMemoryOpCost(I->getOpcode(), I->getType(),
1055                                 LI->getAlignment(),
1056                                 LI->getPointerAddressSpace(), I);
1057   }
1058   case Instruction::ZExt:
1059   case Instruction::SExt:
1060   case Instruction::FPToUI:
1061   case Instruction::FPToSI:
1062   case Instruction::FPExt:
1063   case Instruction::PtrToInt:
1064   case Instruction::IntToPtr:
1065   case Instruction::SIToFP:
1066   case Instruction::UIToFP:
1067   case Instruction::Trunc:
1068   case Instruction::FPTrunc:
1069   case Instruction::BitCast:
1070   case Instruction::AddrSpaceCast: {
1071     Type *SrcTy = I->getOperand(0)->getType();
1072     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1073   }
1074   case Instruction::ExtractElement: {
1075     const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1076     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1077     unsigned Idx = -1;
1078     if (CI)
1079       Idx = CI->getZExtValue();
1080 
1081     // Try to match a reduction sequence (series of shufflevector and vector
1082     // adds followed by a extractelement).
1083     unsigned ReduxOpCode;
1084     Type *ReduxType;
1085 
1086     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1087     case RK_Arithmetic:
1088       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1089                                              /*IsPairwiseForm=*/false);
1090     case RK_MinMax:
1091       return getMinMaxReductionCost(
1092           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1093           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1094     case RK_UnsignedMinMax:
1095       return getMinMaxReductionCost(
1096           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1097           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1098     case RK_None:
1099       break;
1100     }
1101 
1102     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1103     case RK_Arithmetic:
1104       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1105                                              /*IsPairwiseForm=*/true);
1106     case RK_MinMax:
1107       return getMinMaxReductionCost(
1108           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1109           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1110     case RK_UnsignedMinMax:
1111       return getMinMaxReductionCost(
1112           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1113           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1114     case RK_None:
1115       break;
1116     }
1117 
1118     return getVectorInstrCost(I->getOpcode(),
1119                                    EEI->getOperand(0)->getType(), Idx);
1120   }
1121   case Instruction::InsertElement: {
1122     const InsertElementInst * IE = cast<InsertElementInst>(I);
1123     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1124     unsigned Idx = -1;
1125     if (CI)
1126       Idx = CI->getZExtValue();
1127     return getVectorInstrCost(I->getOpcode(),
1128                                    IE->getType(), Idx);
1129   }
1130   case Instruction::ShuffleVector: {
1131     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1132     Type *VecTypOp0 = Shuffle->getOperand(0)->getType();
1133     unsigned NumVecElems = VecTypOp0->getVectorNumElements();
1134     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
1135 
1136     if (NumVecElems == Mask.size()) {
1137       if (isReverseVectorMask(Mask))
1138         return getShuffleCost(TargetTransformInfo::SK_Reverse, VecTypOp0,
1139                                    0, nullptr);
1140       if (isAlternateVectorMask(Mask))
1141         return getShuffleCost(TargetTransformInfo::SK_Alternate,
1142                                    VecTypOp0, 0, nullptr);
1143 
1144       if (isZeroEltBroadcastVectorMask(Mask))
1145         return getShuffleCost(TargetTransformInfo::SK_Broadcast,
1146                                    VecTypOp0, 0, nullptr);
1147 
1148       if (isSingleSourceVectorMask(Mask))
1149         return getShuffleCost(TargetTransformInfo::SK_PermuteSingleSrc,
1150                                    VecTypOp0, 0, nullptr);
1151 
1152       return getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc,
1153                                  VecTypOp0, 0, nullptr);
1154     }
1155 
1156     return -1;
1157   }
1158   case Instruction::Call:
1159     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1160       SmallVector<Value *, 4> Args(II->arg_operands());
1161 
1162       FastMathFlags FMF;
1163       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1164         FMF = FPMO->getFastMathFlags();
1165 
1166       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
1167                                         Args, FMF);
1168     }
1169     return -1;
1170   default:
1171     // We don't have any information on this instruction.
1172     return -1;
1173   }
1174 }
1175 
1176 TargetTransformInfo::Concept::~Concept() {}
1177 
1178 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1179 
1180 TargetIRAnalysis::TargetIRAnalysis(
1181     std::function<Result(const Function &)> TTICallback)
1182     : TTICallback(std::move(TTICallback)) {}
1183 
1184 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1185                                                FunctionAnalysisManager &) {
1186   return TTICallback(F);
1187 }
1188 
1189 AnalysisKey TargetIRAnalysis::Key;
1190 
1191 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1192   return Result(F.getParent()->getDataLayout());
1193 }
1194 
1195 // Register the basic pass.
1196 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1197                 "Target Transform Information", false, true)
1198 char TargetTransformInfoWrapperPass::ID = 0;
1199 
1200 void TargetTransformInfoWrapperPass::anchor() {}
1201 
1202 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1203     : ImmutablePass(ID) {
1204   initializeTargetTransformInfoWrapperPassPass(
1205       *PassRegistry::getPassRegistry());
1206 }
1207 
1208 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1209     TargetIRAnalysis TIRA)
1210     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1211   initializeTargetTransformInfoWrapperPassPass(
1212       *PassRegistry::getPassRegistry());
1213 }
1214 
1215 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1216   FunctionAnalysisManager DummyFAM;
1217   TTI = TIRA.run(F, DummyFAM);
1218   return *TTI;
1219 }
1220 
1221 ImmutablePass *
1222 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1223   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1224 }
1225