1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/Analysis/TargetTransformInfo.h"
10 #include "llvm/Analysis/TargetTransformInfoImpl.h"
11 #include "llvm/IR/CallSite.h"
12 #include "llvm/IR/DataLayout.h"
13 #include "llvm/IR/Instruction.h"
14 #include "llvm/IR/Instructions.h"
15 #include "llvm/IR/IntrinsicInst.h"
16 #include "llvm/IR/Module.h"
17 #include "llvm/IR/Operator.h"
18 #include "llvm/IR/PatternMatch.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <utility>
22 
23 using namespace llvm;
24 using namespace PatternMatch;
25 
26 #define DEBUG_TYPE "tti"
27 
28 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
29                                      cl::Hidden,
30                                      cl::desc("Recognize reduction patterns."));
31 
32 namespace {
33 /// No-op implementation of the TTI interface using the utility base
34 /// classes.
35 ///
36 /// This is used when no target specific information is available.
37 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
38   explicit NoTTIImpl(const DataLayout &DL)
39       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
40 };
41 }
42 
43 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
44     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
45 
46 TargetTransformInfo::~TargetTransformInfo() {}
47 
48 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
49     : TTIImpl(std::move(Arg.TTIImpl)) {}
50 
51 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
52   TTIImpl = std::move(RHS.TTIImpl);
53   return *this;
54 }
55 
56 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
57                                           Type *OpTy) const {
58   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
59   assert(Cost >= 0 && "TTI should not produce negative costs!");
60   return Cost;
61 }
62 
63 int TargetTransformInfo::getCallCost(FunctionType *FTy, int NumArgs,
64                                      const User *U) const {
65   int Cost = TTIImpl->getCallCost(FTy, NumArgs, U);
66   assert(Cost >= 0 && "TTI should not produce negative costs!");
67   return Cost;
68 }
69 
70 int TargetTransformInfo::getCallCost(const Function *F,
71                                      ArrayRef<const Value *> Arguments,
72                                      const User *U) const {
73   int Cost = TTIImpl->getCallCost(F, Arguments, U);
74   assert(Cost >= 0 && "TTI should not produce negative costs!");
75   return Cost;
76 }
77 
78 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
79   return TTIImpl->getInliningThresholdMultiplier();
80 }
81 
82 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
83                                     ArrayRef<const Value *> Operands) const {
84   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
85 }
86 
87 int TargetTransformInfo::getExtCost(const Instruction *I,
88                                     const Value *Src) const {
89   return TTIImpl->getExtCost(I, Src);
90 }
91 
92 int TargetTransformInfo::getIntrinsicCost(
93     Intrinsic::ID IID, Type *RetTy, ArrayRef<const Value *> Arguments,
94     const User *U) const {
95   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments, U);
96   assert(Cost >= 0 && "TTI should not produce negative costs!");
97   return Cost;
98 }
99 
100 unsigned
101 TargetTransformInfo::getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
102                                                       unsigned &JTSize) const {
103   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize);
104 }
105 
106 int TargetTransformInfo::getUserCost(const User *U,
107     ArrayRef<const Value *> Operands) const {
108   int Cost = TTIImpl->getUserCost(U, Operands);
109   assert(Cost >= 0 && "TTI should not produce negative costs!");
110   return Cost;
111 }
112 
113 bool TargetTransformInfo::hasBranchDivergence() const {
114   return TTIImpl->hasBranchDivergence();
115 }
116 
117 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
118   return TTIImpl->isSourceOfDivergence(V);
119 }
120 
121 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
122   return TTIImpl->isAlwaysUniform(V);
123 }
124 
125 unsigned TargetTransformInfo::getFlatAddressSpace() const {
126   return TTIImpl->getFlatAddressSpace();
127 }
128 
129 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
130   return TTIImpl->isLoweredToCall(F);
131 }
132 
133 bool TargetTransformInfo::isHardwareLoopProfitable(
134   Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
135   TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
136   return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
137 }
138 
139 void TargetTransformInfo::getUnrollingPreferences(
140     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
141   return TTIImpl->getUnrollingPreferences(L, SE, UP);
142 }
143 
144 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
145   return TTIImpl->isLegalAddImmediate(Imm);
146 }
147 
148 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
149   return TTIImpl->isLegalICmpImmediate(Imm);
150 }
151 
152 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
153                                                 int64_t BaseOffset,
154                                                 bool HasBaseReg,
155                                                 int64_t Scale,
156                                                 unsigned AddrSpace,
157                                                 Instruction *I) const {
158   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
159                                         Scale, AddrSpace, I);
160 }
161 
162 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
163   return TTIImpl->isLSRCostLess(C1, C2);
164 }
165 
166 bool TargetTransformInfo::canMacroFuseCmp() const {
167   return TTIImpl->canMacroFuseCmp();
168 }
169 
170 bool TargetTransformInfo::shouldFavorPostInc() const {
171   return TTIImpl->shouldFavorPostInc();
172 }
173 
174 bool TargetTransformInfo::shouldFavorBackedgeIndex(const Loop *L) const {
175   return TTIImpl->shouldFavorBackedgeIndex(L);
176 }
177 
178 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType) const {
179   return TTIImpl->isLegalMaskedStore(DataType);
180 }
181 
182 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType) const {
183   return TTIImpl->isLegalMaskedLoad(DataType);
184 }
185 
186 bool TargetTransformInfo::isLegalNTStore(Type *DataType,
187                                          unsigned Alignment) const {
188   return TTIImpl->isLegalNTStore(DataType, Alignment);
189 }
190 
191 bool TargetTransformInfo::isLegalNTLoad(Type *DataType,
192                                         unsigned Alignment) const {
193   return TTIImpl->isLegalNTLoad(DataType, Alignment);
194 }
195 
196 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
197   return TTIImpl->isLegalMaskedGather(DataType);
198 }
199 
200 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
201   return TTIImpl->isLegalMaskedScatter(DataType);
202 }
203 
204 bool TargetTransformInfo::isLegalMaskedCompressStore(Type *DataType) const {
205   return TTIImpl->isLegalMaskedCompressStore(DataType);
206 }
207 
208 bool TargetTransformInfo::isLegalMaskedExpandLoad(Type *DataType) const {
209   return TTIImpl->isLegalMaskedExpandLoad(DataType);
210 }
211 
212 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
213   return TTIImpl->hasDivRemOp(DataType, IsSigned);
214 }
215 
216 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
217                                              unsigned AddrSpace) const {
218   return TTIImpl->hasVolatileVariant(I, AddrSpace);
219 }
220 
221 bool TargetTransformInfo::prefersVectorizedAddressing() const {
222   return TTIImpl->prefersVectorizedAddressing();
223 }
224 
225 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
226                                               int64_t BaseOffset,
227                                               bool HasBaseReg,
228                                               int64_t Scale,
229                                               unsigned AddrSpace) const {
230   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
231                                            Scale, AddrSpace);
232   assert(Cost >= 0 && "TTI should not produce negative costs!");
233   return Cost;
234 }
235 
236 bool TargetTransformInfo::LSRWithInstrQueries() const {
237   return TTIImpl->LSRWithInstrQueries();
238 }
239 
240 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
241   return TTIImpl->isTruncateFree(Ty1, Ty2);
242 }
243 
244 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
245   return TTIImpl->isProfitableToHoist(I);
246 }
247 
248 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
249 
250 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
251   return TTIImpl->isTypeLegal(Ty);
252 }
253 
254 unsigned TargetTransformInfo::getJumpBufAlignment() const {
255   return TTIImpl->getJumpBufAlignment();
256 }
257 
258 unsigned TargetTransformInfo::getJumpBufSize() const {
259   return TTIImpl->getJumpBufSize();
260 }
261 
262 bool TargetTransformInfo::shouldBuildLookupTables() const {
263   return TTIImpl->shouldBuildLookupTables();
264 }
265 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(Constant *C) const {
266   return TTIImpl->shouldBuildLookupTablesForConstant(C);
267 }
268 
269 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
270   return TTIImpl->useColdCCForColdCall(F);
271 }
272 
273 unsigned TargetTransformInfo::
274 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
275   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
276 }
277 
278 unsigned TargetTransformInfo::
279 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
280                                  unsigned VF) const {
281   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
282 }
283 
284 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
285   return TTIImpl->supportsEfficientVectorElementLoadStore();
286 }
287 
288 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
289   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
290 }
291 
292 const TargetTransformInfo::MemCmpExpansionOptions *
293 TargetTransformInfo::enableMemCmpExpansion(bool IsZeroCmp) const {
294   return TTIImpl->enableMemCmpExpansion(IsZeroCmp);
295 }
296 
297 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
298   return TTIImpl->enableInterleavedAccessVectorization();
299 }
300 
301 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const {
302   return TTIImpl->enableMaskedInterleavedAccessVectorization();
303 }
304 
305 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
306   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
307 }
308 
309 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
310                                                          unsigned BitWidth,
311                                                          unsigned AddressSpace,
312                                                          unsigned Alignment,
313                                                          bool *Fast) const {
314   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
315                                                  Alignment, Fast);
316 }
317 
318 TargetTransformInfo::PopcntSupportKind
319 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
320   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
321 }
322 
323 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
324   return TTIImpl->haveFastSqrt(Ty);
325 }
326 
327 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
328   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
329 }
330 
331 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
332   int Cost = TTIImpl->getFPOpCost(Ty);
333   assert(Cost >= 0 && "TTI should not produce negative costs!");
334   return Cost;
335 }
336 
337 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
338                                                const APInt &Imm,
339                                                Type *Ty) const {
340   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
341   assert(Cost >= 0 && "TTI should not produce negative costs!");
342   return Cost;
343 }
344 
345 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
346   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
347   assert(Cost >= 0 && "TTI should not produce negative costs!");
348   return Cost;
349 }
350 
351 int TargetTransformInfo::getIntImmCost(unsigned Opcode, unsigned Idx,
352                                        const APInt &Imm, Type *Ty) const {
353   int Cost = TTIImpl->getIntImmCost(Opcode, Idx, Imm, Ty);
354   assert(Cost >= 0 && "TTI should not produce negative costs!");
355   return Cost;
356 }
357 
358 int TargetTransformInfo::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
359                                        const APInt &Imm, Type *Ty) const {
360   int Cost = TTIImpl->getIntImmCost(IID, Idx, Imm, Ty);
361   assert(Cost >= 0 && "TTI should not produce negative costs!");
362   return Cost;
363 }
364 
365 unsigned TargetTransformInfo::getNumberOfRegisters(bool Vector) const {
366   return TTIImpl->getNumberOfRegisters(Vector);
367 }
368 
369 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
370   return TTIImpl->getRegisterBitWidth(Vector);
371 }
372 
373 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
374   return TTIImpl->getMinVectorRegisterBitWidth();
375 }
376 
377 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
378   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
379 }
380 
381 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
382   return TTIImpl->getMinimumVF(ElemWidth);
383 }
384 
385 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
386     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
387   return TTIImpl->shouldConsiderAddressTypePromotion(
388       I, AllowPromotionWithoutCommonHeader);
389 }
390 
391 unsigned TargetTransformInfo::getCacheLineSize() const {
392   return TTIImpl->getCacheLineSize();
393 }
394 
395 llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
396   const {
397   return TTIImpl->getCacheSize(Level);
398 }
399 
400 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
401   CacheLevel Level) const {
402   return TTIImpl->getCacheAssociativity(Level);
403 }
404 
405 unsigned TargetTransformInfo::getPrefetchDistance() const {
406   return TTIImpl->getPrefetchDistance();
407 }
408 
409 unsigned TargetTransformInfo::getMinPrefetchStride() const {
410   return TTIImpl->getMinPrefetchStride();
411 }
412 
413 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
414   return TTIImpl->getMaxPrefetchIterationsAhead();
415 }
416 
417 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
418   return TTIImpl->getMaxInterleaveFactor(VF);
419 }
420 
421 TargetTransformInfo::OperandValueKind
422 TargetTransformInfo::getOperandInfo(Value *V, OperandValueProperties &OpProps) {
423   OperandValueKind OpInfo = OK_AnyValue;
424   OpProps = OP_None;
425 
426   if (auto *CI = dyn_cast<ConstantInt>(V)) {
427     if (CI->getValue().isPowerOf2())
428       OpProps = OP_PowerOf2;
429     return OK_UniformConstantValue;
430   }
431 
432   // A broadcast shuffle creates a uniform value.
433   // TODO: Add support for non-zero index broadcasts.
434   // TODO: Add support for different source vector width.
435   if (auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
436     if (ShuffleInst->isZeroEltSplat())
437       OpInfo = OK_UniformValue;
438 
439   const Value *Splat = getSplatValue(V);
440 
441   // Check for a splat of a constant or for a non uniform vector of constants
442   // and check if the constant(s) are all powers of two.
443   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
444     OpInfo = OK_NonUniformConstantValue;
445     if (Splat) {
446       OpInfo = OK_UniformConstantValue;
447       if (auto *CI = dyn_cast<ConstantInt>(Splat))
448         if (CI->getValue().isPowerOf2())
449           OpProps = OP_PowerOf2;
450     } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
451       OpProps = OP_PowerOf2;
452       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
453         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
454           if (CI->getValue().isPowerOf2())
455             continue;
456         OpProps = OP_None;
457         break;
458       }
459     }
460   }
461 
462   // Check for a splat of a uniform value. This is not loop aware, so return
463   // true only for the obviously uniform cases (argument, globalvalue)
464   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
465     OpInfo = OK_UniformValue;
466 
467   return OpInfo;
468 }
469 
470 int TargetTransformInfo::getArithmeticInstrCost(
471     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
472     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
473     OperandValueProperties Opd2PropInfo,
474     ArrayRef<const Value *> Args) const {
475   int Cost = TTIImpl->getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
476                                              Opd1PropInfo, Opd2PropInfo, Args);
477   assert(Cost >= 0 && "TTI should not produce negative costs!");
478   return Cost;
479 }
480 
481 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
482                                         Type *SubTp) const {
483   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
484   assert(Cost >= 0 && "TTI should not produce negative costs!");
485   return Cost;
486 }
487 
488 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
489                                  Type *Src, const Instruction *I) const {
490   assert ((I == nullptr || I->getOpcode() == Opcode) &&
491           "Opcode should reflect passed instruction.");
492   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
493   assert(Cost >= 0 && "TTI should not produce negative costs!");
494   return Cost;
495 }
496 
497 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
498                                                   VectorType *VecTy,
499                                                   unsigned Index) const {
500   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
501   assert(Cost >= 0 && "TTI should not produce negative costs!");
502   return Cost;
503 }
504 
505 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
506   int Cost = TTIImpl->getCFInstrCost(Opcode);
507   assert(Cost >= 0 && "TTI should not produce negative costs!");
508   return Cost;
509 }
510 
511 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
512                                  Type *CondTy, const Instruction *I) const {
513   assert ((I == nullptr || I->getOpcode() == Opcode) &&
514           "Opcode should reflect passed instruction.");
515   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
516   assert(Cost >= 0 && "TTI should not produce negative costs!");
517   return Cost;
518 }
519 
520 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
521                                             unsigned Index) const {
522   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
523   assert(Cost >= 0 && "TTI should not produce negative costs!");
524   return Cost;
525 }
526 
527 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
528                                          unsigned Alignment,
529                                          unsigned AddressSpace,
530                                          const Instruction *I) const {
531   assert ((I == nullptr || I->getOpcode() == Opcode) &&
532           "Opcode should reflect passed instruction.");
533   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
534   assert(Cost >= 0 && "TTI should not produce negative costs!");
535   return Cost;
536 }
537 
538 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
539                                                unsigned Alignment,
540                                                unsigned AddressSpace) const {
541   int Cost =
542       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
543   assert(Cost >= 0 && "TTI should not produce negative costs!");
544   return Cost;
545 }
546 
547 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
548                                                 Value *Ptr, bool VariableMask,
549                                                 unsigned Alignment) const {
550   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
551                                              Alignment);
552   assert(Cost >= 0 && "TTI should not produce negative costs!");
553   return Cost;
554 }
555 
556 int TargetTransformInfo::getInterleavedMemoryOpCost(
557     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
558     unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond,
559     bool UseMaskForGaps) const {
560   int Cost = TTIImpl->getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
561                                                  Alignment, AddressSpace,
562                                                  UseMaskForCond,
563                                                  UseMaskForGaps);
564   assert(Cost >= 0 && "TTI should not produce negative costs!");
565   return Cost;
566 }
567 
568 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
569                                     ArrayRef<Type *> Tys, FastMathFlags FMF,
570                                     unsigned ScalarizationCostPassed) const {
571   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
572                                             ScalarizationCostPassed);
573   assert(Cost >= 0 && "TTI should not produce negative costs!");
574   return Cost;
575 }
576 
577 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
578            ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) const {
579   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
580   assert(Cost >= 0 && "TTI should not produce negative costs!");
581   return Cost;
582 }
583 
584 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
585                                           ArrayRef<Type *> Tys) const {
586   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
587   assert(Cost >= 0 && "TTI should not produce negative costs!");
588   return Cost;
589 }
590 
591 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
592   return TTIImpl->getNumberOfParts(Tp);
593 }
594 
595 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
596                                                    ScalarEvolution *SE,
597                                                    const SCEV *Ptr) const {
598   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
599   assert(Cost >= 0 && "TTI should not produce negative costs!");
600   return Cost;
601 }
602 
603 int TargetTransformInfo::getMemcpyCost(const Instruction *I) const {
604   int Cost = TTIImpl->getMemcpyCost(I);
605   assert(Cost >= 0 && "TTI should not produce negative costs!");
606   return Cost;
607 }
608 
609 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
610                                                     bool IsPairwiseForm) const {
611   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
612   assert(Cost >= 0 && "TTI should not produce negative costs!");
613   return Cost;
614 }
615 
616 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
617                                                 bool IsPairwiseForm,
618                                                 bool IsUnsigned) const {
619   int Cost =
620       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
621   assert(Cost >= 0 && "TTI should not produce negative costs!");
622   return Cost;
623 }
624 
625 unsigned
626 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
627   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
628 }
629 
630 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
631                                              MemIntrinsicInfo &Info) const {
632   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
633 }
634 
635 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
636   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
637 }
638 
639 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
640     IntrinsicInst *Inst, Type *ExpectedType) const {
641   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
642 }
643 
644 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
645                                                      Value *Length,
646                                                      unsigned SrcAlign,
647                                                      unsigned DestAlign) const {
648   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
649                                             DestAlign);
650 }
651 
652 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
653     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
654     unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
655   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
656                                              SrcAlign, DestAlign);
657 }
658 
659 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
660                                               const Function *Callee) const {
661   return TTIImpl->areInlineCompatible(Caller, Callee);
662 }
663 
664 bool TargetTransformInfo::areFunctionArgsABICompatible(
665     const Function *Caller, const Function *Callee,
666     SmallPtrSetImpl<Argument *> &Args) const {
667   return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
668 }
669 
670 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
671                                              Type *Ty) const {
672   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
673 }
674 
675 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
676                                               Type *Ty) const {
677   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
678 }
679 
680 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
681   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
682 }
683 
684 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
685   return TTIImpl->isLegalToVectorizeLoad(LI);
686 }
687 
688 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
689   return TTIImpl->isLegalToVectorizeStore(SI);
690 }
691 
692 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
693     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
694   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
695                                               AddrSpace);
696 }
697 
698 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
699     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
700   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
701                                                AddrSpace);
702 }
703 
704 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
705                                                   unsigned LoadSize,
706                                                   unsigned ChainSizeInBytes,
707                                                   VectorType *VecTy) const {
708   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
709 }
710 
711 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
712                                                    unsigned StoreSize,
713                                                    unsigned ChainSizeInBytes,
714                                                    VectorType *VecTy) const {
715   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
716 }
717 
718 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode,
719                                                 Type *Ty, ReductionFlags Flags) const {
720   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
721 }
722 
723 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
724   return TTIImpl->shouldExpandReduction(II);
725 }
726 
727 unsigned TargetTransformInfo::getGISelRematGlobalCost() const {
728   return TTIImpl->getGISelRematGlobalCost();
729 }
730 
731 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
732   return TTIImpl->getInstructionLatency(I);
733 }
734 
735 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
736                                      unsigned Level) {
737   // We don't need a shuffle if we just want to have element 0 in position 0 of
738   // the vector.
739   if (!SI && Level == 0 && IsLeft)
740     return true;
741   else if (!SI)
742     return false;
743 
744   SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
745 
746   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
747   // we look at the left or right side.
748   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
749     Mask[i] = val;
750 
751   SmallVector<int, 16> ActualMask = SI->getShuffleMask();
752   return Mask == ActualMask;
753 }
754 
755 namespace {
756 /// Kind of the reduction data.
757 enum ReductionKind {
758   RK_None,           /// Not a reduction.
759   RK_Arithmetic,     /// Binary reduction data.
760   RK_MinMax,         /// Min/max reduction data.
761   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
762 };
763 /// Contains opcode + LHS/RHS parts of the reduction operations.
764 struct ReductionData {
765   ReductionData() = delete;
766   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
767       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
768     assert(Kind != RK_None && "expected binary or min/max reduction only.");
769   }
770   unsigned Opcode = 0;
771   Value *LHS = nullptr;
772   Value *RHS = nullptr;
773   ReductionKind Kind = RK_None;
774   bool hasSameData(ReductionData &RD) const {
775     return Kind == RD.Kind && Opcode == RD.Opcode;
776   }
777 };
778 } // namespace
779 
780 static Optional<ReductionData> getReductionData(Instruction *I) {
781   Value *L, *R;
782   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
783     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
784   if (auto *SI = dyn_cast<SelectInst>(I)) {
785     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
786         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
787         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
788         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
789         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
790         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
791       auto *CI = cast<CmpInst>(SI->getCondition());
792       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
793     }
794     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
795         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
796       auto *CI = cast<CmpInst>(SI->getCondition());
797       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
798     }
799   }
800   return llvm::None;
801 }
802 
803 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
804                                                    unsigned Level,
805                                                    unsigned NumLevels) {
806   // Match one level of pairwise operations.
807   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
808   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
809   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
810   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
811   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
812   if (!I)
813     return RK_None;
814 
815   assert(I->getType()->isVectorTy() && "Expecting a vector type");
816 
817   Optional<ReductionData> RD = getReductionData(I);
818   if (!RD)
819     return RK_None;
820 
821   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
822   if (!LS && Level)
823     return RK_None;
824   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
825   if (!RS && Level)
826     return RK_None;
827 
828   // On level 0 we can omit one shufflevector instruction.
829   if (!Level && !RS && !LS)
830     return RK_None;
831 
832   // Shuffle inputs must match.
833   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
834   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
835   Value *NextLevelOp = nullptr;
836   if (NextLevelOpR && NextLevelOpL) {
837     // If we have two shuffles their operands must match.
838     if (NextLevelOpL != NextLevelOpR)
839       return RK_None;
840 
841     NextLevelOp = NextLevelOpL;
842   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
843     // On the first level we can omit the shufflevector <0, undef,...>. So the
844     // input to the other shufflevector <1, undef> must match with one of the
845     // inputs to the current binary operation.
846     // Example:
847     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
848     //  %BinOp        = fadd          %NextLevelOpL, %R
849     if (NextLevelOpL && NextLevelOpL != RD->RHS)
850       return RK_None;
851     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
852       return RK_None;
853 
854     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
855   } else
856     return RK_None;
857 
858   // Check that the next levels binary operation exists and matches with the
859   // current one.
860   if (Level + 1 != NumLevels) {
861     Optional<ReductionData> NextLevelRD =
862         getReductionData(cast<Instruction>(NextLevelOp));
863     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
864       return RK_None;
865   }
866 
867   // Shuffle mask for pairwise operation must match.
868   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
869     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
870       return RK_None;
871   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
872     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
873       return RK_None;
874   } else {
875     return RK_None;
876   }
877 
878   if (++Level == NumLevels)
879     return RD->Kind;
880 
881   // Match next level.
882   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
883                                        NumLevels);
884 }
885 
886 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
887                                             unsigned &Opcode, Type *&Ty) {
888   if (!EnableReduxCost)
889     return RK_None;
890 
891   // Need to extract the first element.
892   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
893   unsigned Idx = ~0u;
894   if (CI)
895     Idx = CI->getZExtValue();
896   if (Idx != 0)
897     return RK_None;
898 
899   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
900   if (!RdxStart)
901     return RK_None;
902   Optional<ReductionData> RD = getReductionData(RdxStart);
903   if (!RD)
904     return RK_None;
905 
906   Type *VecTy = RdxStart->getType();
907   unsigned NumVecElems = VecTy->getVectorNumElements();
908   if (!isPowerOf2_32(NumVecElems))
909     return RK_None;
910 
911   // We look for a sequence of shuffle,shuffle,add triples like the following
912   // that builds a pairwise reduction tree.
913   //
914   //  (X0, X1, X2, X3)
915   //   (X0 + X1, X2 + X3, undef, undef)
916   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
917   //
918   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
919   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
920   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
921   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
922   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
923   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
924   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
925   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
926   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
927   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
928   // %r = extractelement <4 x float> %bin.rdx8, i32 0
929   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
930       RK_None)
931     return RK_None;
932 
933   Opcode = RD->Opcode;
934   Ty = VecTy;
935 
936   return RD->Kind;
937 }
938 
939 static std::pair<Value *, ShuffleVectorInst *>
940 getShuffleAndOtherOprd(Value *L, Value *R) {
941   ShuffleVectorInst *S = nullptr;
942 
943   if ((S = dyn_cast<ShuffleVectorInst>(L)))
944     return std::make_pair(R, S);
945 
946   S = dyn_cast<ShuffleVectorInst>(R);
947   return std::make_pair(L, S);
948 }
949 
950 static ReductionKind
951 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
952                               unsigned &Opcode, Type *&Ty) {
953   if (!EnableReduxCost)
954     return RK_None;
955 
956   // Need to extract the first element.
957   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
958   unsigned Idx = ~0u;
959   if (CI)
960     Idx = CI->getZExtValue();
961   if (Idx != 0)
962     return RK_None;
963 
964   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
965   if (!RdxStart)
966     return RK_None;
967   Optional<ReductionData> RD = getReductionData(RdxStart);
968   if (!RD)
969     return RK_None;
970 
971   Type *VecTy = ReduxRoot->getOperand(0)->getType();
972   unsigned NumVecElems = VecTy->getVectorNumElements();
973   if (!isPowerOf2_32(NumVecElems))
974     return RK_None;
975 
976   // We look for a sequence of shuffles and adds like the following matching one
977   // fadd, shuffle vector pair at a time.
978   //
979   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
980   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
981   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
982   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
983   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
984   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
985   // %r = extractelement <4 x float> %bin.rdx8, i32 0
986 
987   unsigned MaskStart = 1;
988   Instruction *RdxOp = RdxStart;
989   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
990   unsigned NumVecElemsRemain = NumVecElems;
991   while (NumVecElemsRemain - 1) {
992     // Check for the right reduction operation.
993     if (!RdxOp)
994       return RK_None;
995     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
996     if (!RDLevel || !RDLevel->hasSameData(*RD))
997       return RK_None;
998 
999     Value *NextRdxOp;
1000     ShuffleVectorInst *Shuffle;
1001     std::tie(NextRdxOp, Shuffle) =
1002         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
1003 
1004     // Check the current reduction operation and the shuffle use the same value.
1005     if (Shuffle == nullptr)
1006       return RK_None;
1007     if (Shuffle->getOperand(0) != NextRdxOp)
1008       return RK_None;
1009 
1010     // Check that shuffle masks matches.
1011     for (unsigned j = 0; j != MaskStart; ++j)
1012       ShuffleMask[j] = MaskStart + j;
1013     // Fill the rest of the mask with -1 for undef.
1014     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
1015 
1016     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
1017     if (ShuffleMask != Mask)
1018       return RK_None;
1019 
1020     RdxOp = dyn_cast<Instruction>(NextRdxOp);
1021     NumVecElemsRemain /= 2;
1022     MaskStart *= 2;
1023   }
1024 
1025   Opcode = RD->Opcode;
1026   Ty = VecTy;
1027   return RD->Kind;
1028 }
1029 
1030 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1031   switch (I->getOpcode()) {
1032   case Instruction::GetElementPtr:
1033     return getUserCost(I);
1034 
1035   case Instruction::Ret:
1036   case Instruction::PHI:
1037   case Instruction::Br: {
1038     return getCFInstrCost(I->getOpcode());
1039   }
1040   case Instruction::Add:
1041   case Instruction::FAdd:
1042   case Instruction::Sub:
1043   case Instruction::FSub:
1044   case Instruction::Mul:
1045   case Instruction::FMul:
1046   case Instruction::UDiv:
1047   case Instruction::SDiv:
1048   case Instruction::FDiv:
1049   case Instruction::URem:
1050   case Instruction::SRem:
1051   case Instruction::FRem:
1052   case Instruction::Shl:
1053   case Instruction::LShr:
1054   case Instruction::AShr:
1055   case Instruction::And:
1056   case Instruction::Or:
1057   case Instruction::Xor: {
1058     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1059     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1060     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1061     Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1062     SmallVector<const Value *, 2> Operands(I->operand_values());
1063     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1064                                   Op1VP, Op2VP, Operands);
1065   }
1066   case Instruction::FNeg: {
1067     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1068     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1069     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1070     Op2VK = OK_AnyValue;
1071     Op2VP = OP_None;
1072     SmallVector<const Value *, 2> Operands(I->operand_values());
1073     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1074                                   Op1VP, Op2VP, Operands);
1075   }
1076   case Instruction::Select: {
1077     const SelectInst *SI = cast<SelectInst>(I);
1078     Type *CondTy = SI->getCondition()->getType();
1079     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1080   }
1081   case Instruction::ICmp:
1082   case Instruction::FCmp: {
1083     Type *ValTy = I->getOperand(0)->getType();
1084     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1085   }
1086   case Instruction::Store: {
1087     const StoreInst *SI = cast<StoreInst>(I);
1088     Type *ValTy = SI->getValueOperand()->getType();
1089     return getMemoryOpCost(I->getOpcode(), ValTy,
1090                                 SI->getAlignment(),
1091                                 SI->getPointerAddressSpace(), I);
1092   }
1093   case Instruction::Load: {
1094     const LoadInst *LI = cast<LoadInst>(I);
1095     return getMemoryOpCost(I->getOpcode(), I->getType(),
1096                                 LI->getAlignment(),
1097                                 LI->getPointerAddressSpace(), I);
1098   }
1099   case Instruction::ZExt:
1100   case Instruction::SExt:
1101   case Instruction::FPToUI:
1102   case Instruction::FPToSI:
1103   case Instruction::FPExt:
1104   case Instruction::PtrToInt:
1105   case Instruction::IntToPtr:
1106   case Instruction::SIToFP:
1107   case Instruction::UIToFP:
1108   case Instruction::Trunc:
1109   case Instruction::FPTrunc:
1110   case Instruction::BitCast:
1111   case Instruction::AddrSpaceCast: {
1112     Type *SrcTy = I->getOperand(0)->getType();
1113     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1114   }
1115   case Instruction::ExtractElement: {
1116     const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1117     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1118     unsigned Idx = -1;
1119     if (CI)
1120       Idx = CI->getZExtValue();
1121 
1122     // Try to match a reduction sequence (series of shufflevector and vector
1123     // adds followed by a extractelement).
1124     unsigned ReduxOpCode;
1125     Type *ReduxType;
1126 
1127     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1128     case RK_Arithmetic:
1129       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1130                                              /*IsPairwiseForm=*/false);
1131     case RK_MinMax:
1132       return getMinMaxReductionCost(
1133           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1134           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1135     case RK_UnsignedMinMax:
1136       return getMinMaxReductionCost(
1137           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1138           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1139     case RK_None:
1140       break;
1141     }
1142 
1143     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1144     case RK_Arithmetic:
1145       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1146                                              /*IsPairwiseForm=*/true);
1147     case RK_MinMax:
1148       return getMinMaxReductionCost(
1149           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1150           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1151     case RK_UnsignedMinMax:
1152       return getMinMaxReductionCost(
1153           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1154           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1155     case RK_None:
1156       break;
1157     }
1158 
1159     return getVectorInstrCost(I->getOpcode(),
1160                                    EEI->getOperand(0)->getType(), Idx);
1161   }
1162   case Instruction::InsertElement: {
1163     const InsertElementInst * IE = cast<InsertElementInst>(I);
1164     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1165     unsigned Idx = -1;
1166     if (CI)
1167       Idx = CI->getZExtValue();
1168     return getVectorInstrCost(I->getOpcode(),
1169                                    IE->getType(), Idx);
1170   }
1171   case Instruction::ShuffleVector: {
1172     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1173     Type *Ty = Shuffle->getType();
1174     Type *SrcTy = Shuffle->getOperand(0)->getType();
1175 
1176     // TODO: Identify and add costs for insert subvector, etc.
1177     int SubIndex;
1178     if (Shuffle->isExtractSubvectorMask(SubIndex))
1179       return TTIImpl->getShuffleCost(SK_ExtractSubvector, SrcTy, SubIndex, Ty);
1180 
1181     if (Shuffle->changesLength())
1182       return -1;
1183 
1184     if (Shuffle->isIdentity())
1185       return 0;
1186 
1187     if (Shuffle->isReverse())
1188       return TTIImpl->getShuffleCost(SK_Reverse, Ty, 0, nullptr);
1189 
1190     if (Shuffle->isSelect())
1191       return TTIImpl->getShuffleCost(SK_Select, Ty, 0, nullptr);
1192 
1193     if (Shuffle->isTranspose())
1194       return TTIImpl->getShuffleCost(SK_Transpose, Ty, 0, nullptr);
1195 
1196     if (Shuffle->isZeroEltSplat())
1197       return TTIImpl->getShuffleCost(SK_Broadcast, Ty, 0, nullptr);
1198 
1199     if (Shuffle->isSingleSource())
1200       return TTIImpl->getShuffleCost(SK_PermuteSingleSrc, Ty, 0, nullptr);
1201 
1202     return TTIImpl->getShuffleCost(SK_PermuteTwoSrc, Ty, 0, nullptr);
1203   }
1204   case Instruction::Call:
1205     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1206       SmallVector<Value *, 4> Args(II->arg_operands());
1207 
1208       FastMathFlags FMF;
1209       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1210         FMF = FPMO->getFastMathFlags();
1211 
1212       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
1213                                         Args, FMF);
1214     }
1215     return -1;
1216   default:
1217     // We don't have any information on this instruction.
1218     return -1;
1219   }
1220 }
1221 
1222 TargetTransformInfo::Concept::~Concept() {}
1223 
1224 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1225 
1226 TargetIRAnalysis::TargetIRAnalysis(
1227     std::function<Result(const Function &)> TTICallback)
1228     : TTICallback(std::move(TTICallback)) {}
1229 
1230 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1231                                                FunctionAnalysisManager &) {
1232   return TTICallback(F);
1233 }
1234 
1235 AnalysisKey TargetIRAnalysis::Key;
1236 
1237 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1238   return Result(F.getParent()->getDataLayout());
1239 }
1240 
1241 // Register the basic pass.
1242 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1243                 "Target Transform Information", false, true)
1244 char TargetTransformInfoWrapperPass::ID = 0;
1245 
1246 void TargetTransformInfoWrapperPass::anchor() {}
1247 
1248 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1249     : ImmutablePass(ID) {
1250   initializeTargetTransformInfoWrapperPassPass(
1251       *PassRegistry::getPassRegistry());
1252 }
1253 
1254 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1255     TargetIRAnalysis TIRA)
1256     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1257   initializeTargetTransformInfoWrapperPassPass(
1258       *PassRegistry::getPassRegistry());
1259 }
1260 
1261 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1262   FunctionAnalysisManager DummyFAM;
1263   TTI = TIRA.run(F, DummyFAM);
1264   return *TTI;
1265 }
1266 
1267 ImmutablePass *
1268 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1269   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1270 }
1271