1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/Analysis/TargetTransformInfo.h"
11 #include "llvm/Analysis/TargetTransformInfoImpl.h"
12 #include "llvm/IR/CallSite.h"
13 #include "llvm/IR/DataLayout.h"
14 #include "llvm/IR/Instruction.h"
15 #include "llvm/IR/Instructions.h"
16 #include "llvm/IR/IntrinsicInst.h"
17 #include "llvm/IR/Module.h"
18 #include "llvm/IR/Operator.h"
19 #include "llvm/IR/PatternMatch.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include <utility>
23 
24 using namespace llvm;
25 using namespace PatternMatch;
26 
27 #define DEBUG_TYPE "tti"
28 
29 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
30                                      cl::Hidden,
31                                      cl::desc("Recognize reduction patterns."));
32 
33 namespace {
34 /// No-op implementation of the TTI interface using the utility base
35 /// classes.
36 ///
37 /// This is used when no target specific information is available.
38 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
39   explicit NoTTIImpl(const DataLayout &DL)
40       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
41 };
42 }
43 
44 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
45     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
46 
47 TargetTransformInfo::~TargetTransformInfo() {}
48 
49 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
50     : TTIImpl(std::move(Arg.TTIImpl)) {}
51 
52 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
53   TTIImpl = std::move(RHS.TTIImpl);
54   return *this;
55 }
56 
57 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
58                                           Type *OpTy) const {
59   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
60   assert(Cost >= 0 && "TTI should not produce negative costs!");
61   return Cost;
62 }
63 
64 int TargetTransformInfo::getCallCost(FunctionType *FTy, int NumArgs) const {
65   int Cost = TTIImpl->getCallCost(FTy, NumArgs);
66   assert(Cost >= 0 && "TTI should not produce negative costs!");
67   return Cost;
68 }
69 
70 int TargetTransformInfo::getCallCost(const Function *F,
71                                      ArrayRef<const Value *> Arguments) const {
72   int Cost = TTIImpl->getCallCost(F, Arguments);
73   assert(Cost >= 0 && "TTI should not produce negative costs!");
74   return Cost;
75 }
76 
77 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
78   return TTIImpl->getInliningThresholdMultiplier();
79 }
80 
81 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
82                                     ArrayRef<const Value *> Operands) const {
83   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
84 }
85 
86 int TargetTransformInfo::getExtCost(const Instruction *I,
87                                     const Value *Src) const {
88   return TTIImpl->getExtCost(I, Src);
89 }
90 
91 int TargetTransformInfo::getIntrinsicCost(
92     Intrinsic::ID IID, Type *RetTy, ArrayRef<const Value *> Arguments) const {
93   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments);
94   assert(Cost >= 0 && "TTI should not produce negative costs!");
95   return Cost;
96 }
97 
98 unsigned
99 TargetTransformInfo::getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
100                                                       unsigned &JTSize) const {
101   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize);
102 }
103 
104 int TargetTransformInfo::getUserCost(const User *U,
105     ArrayRef<const Value *> Operands) const {
106   int Cost = TTIImpl->getUserCost(U, Operands);
107   assert(Cost >= 0 && "TTI should not produce negative costs!");
108   return Cost;
109 }
110 
111 bool TargetTransformInfo::hasBranchDivergence() const {
112   return TTIImpl->hasBranchDivergence();
113 }
114 
115 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
116   return TTIImpl->isSourceOfDivergence(V);
117 }
118 
119 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
120   return TTIImpl->isAlwaysUniform(V);
121 }
122 
123 unsigned TargetTransformInfo::getFlatAddressSpace() const {
124   return TTIImpl->getFlatAddressSpace();
125 }
126 
127 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
128   return TTIImpl->isLoweredToCall(F);
129 }
130 
131 void TargetTransformInfo::getUnrollingPreferences(
132     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
133   return TTIImpl->getUnrollingPreferences(L, SE, UP);
134 }
135 
136 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
137   return TTIImpl->isLegalAddImmediate(Imm);
138 }
139 
140 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
141   return TTIImpl->isLegalICmpImmediate(Imm);
142 }
143 
144 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
145                                                 int64_t BaseOffset,
146                                                 bool HasBaseReg,
147                                                 int64_t Scale,
148                                                 unsigned AddrSpace,
149                                                 Instruction *I) const {
150   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
151                                         Scale, AddrSpace, I);
152 }
153 
154 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
155   return TTIImpl->isLSRCostLess(C1, C2);
156 }
157 
158 bool TargetTransformInfo::canMacroFuseCmp() const {
159   return TTIImpl->canMacroFuseCmp();
160 }
161 
162 bool TargetTransformInfo::shouldFavorPostInc() const {
163   return TTIImpl->shouldFavorPostInc();
164 }
165 
166 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType) const {
167   return TTIImpl->isLegalMaskedStore(DataType);
168 }
169 
170 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType) const {
171   return TTIImpl->isLegalMaskedLoad(DataType);
172 }
173 
174 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
175   return TTIImpl->isLegalMaskedGather(DataType);
176 }
177 
178 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
179   return TTIImpl->isLegalMaskedScatter(DataType);
180 }
181 
182 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
183   return TTIImpl->hasDivRemOp(DataType, IsSigned);
184 }
185 
186 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
187                                              unsigned AddrSpace) const {
188   return TTIImpl->hasVolatileVariant(I, AddrSpace);
189 }
190 
191 bool TargetTransformInfo::prefersVectorizedAddressing() const {
192   return TTIImpl->prefersVectorizedAddressing();
193 }
194 
195 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
196                                               int64_t BaseOffset,
197                                               bool HasBaseReg,
198                                               int64_t Scale,
199                                               unsigned AddrSpace) const {
200   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
201                                            Scale, AddrSpace);
202   assert(Cost >= 0 && "TTI should not produce negative costs!");
203   return Cost;
204 }
205 
206 bool TargetTransformInfo::LSRWithInstrQueries() const {
207   return TTIImpl->LSRWithInstrQueries();
208 }
209 
210 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
211   return TTIImpl->isTruncateFree(Ty1, Ty2);
212 }
213 
214 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
215   return TTIImpl->isProfitableToHoist(I);
216 }
217 
218 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
219 
220 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
221   return TTIImpl->isTypeLegal(Ty);
222 }
223 
224 unsigned TargetTransformInfo::getJumpBufAlignment() const {
225   return TTIImpl->getJumpBufAlignment();
226 }
227 
228 unsigned TargetTransformInfo::getJumpBufSize() const {
229   return TTIImpl->getJumpBufSize();
230 }
231 
232 bool TargetTransformInfo::shouldBuildLookupTables() const {
233   return TTIImpl->shouldBuildLookupTables();
234 }
235 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(Constant *C) const {
236   return TTIImpl->shouldBuildLookupTablesForConstant(C);
237 }
238 
239 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
240   return TTIImpl->useColdCCForColdCall(F);
241 }
242 
243 unsigned TargetTransformInfo::
244 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
245   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
246 }
247 
248 unsigned TargetTransformInfo::
249 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
250                                  unsigned VF) const {
251   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
252 }
253 
254 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
255   return TTIImpl->supportsEfficientVectorElementLoadStore();
256 }
257 
258 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
259   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
260 }
261 
262 const TargetTransformInfo::MemCmpExpansionOptions *
263 TargetTransformInfo::enableMemCmpExpansion(bool IsZeroCmp) const {
264   return TTIImpl->enableMemCmpExpansion(IsZeroCmp);
265 }
266 
267 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
268   return TTIImpl->enableInterleavedAccessVectorization();
269 }
270 
271 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
272   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
273 }
274 
275 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
276                                                          unsigned BitWidth,
277                                                          unsigned AddressSpace,
278                                                          unsigned Alignment,
279                                                          bool *Fast) const {
280   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
281                                                  Alignment, Fast);
282 }
283 
284 TargetTransformInfo::PopcntSupportKind
285 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
286   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
287 }
288 
289 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
290   return TTIImpl->haveFastSqrt(Ty);
291 }
292 
293 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
294   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
295 }
296 
297 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
298   int Cost = TTIImpl->getFPOpCost(Ty);
299   assert(Cost >= 0 && "TTI should not produce negative costs!");
300   return Cost;
301 }
302 
303 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
304                                                const APInt &Imm,
305                                                Type *Ty) const {
306   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
307   assert(Cost >= 0 && "TTI should not produce negative costs!");
308   return Cost;
309 }
310 
311 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
312   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
313   assert(Cost >= 0 && "TTI should not produce negative costs!");
314   return Cost;
315 }
316 
317 int TargetTransformInfo::getIntImmCost(unsigned Opcode, unsigned Idx,
318                                        const APInt &Imm, Type *Ty) const {
319   int Cost = TTIImpl->getIntImmCost(Opcode, Idx, Imm, Ty);
320   assert(Cost >= 0 && "TTI should not produce negative costs!");
321   return Cost;
322 }
323 
324 int TargetTransformInfo::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
325                                        const APInt &Imm, Type *Ty) const {
326   int Cost = TTIImpl->getIntImmCost(IID, Idx, Imm, Ty);
327   assert(Cost >= 0 && "TTI should not produce negative costs!");
328   return Cost;
329 }
330 
331 unsigned TargetTransformInfo::getNumberOfRegisters(bool Vector) const {
332   return TTIImpl->getNumberOfRegisters(Vector);
333 }
334 
335 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
336   return TTIImpl->getRegisterBitWidth(Vector);
337 }
338 
339 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
340   return TTIImpl->getMinVectorRegisterBitWidth();
341 }
342 
343 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
344   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
345 }
346 
347 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
348   return TTIImpl->getMinimumVF(ElemWidth);
349 }
350 
351 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
352     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
353   return TTIImpl->shouldConsiderAddressTypePromotion(
354       I, AllowPromotionWithoutCommonHeader);
355 }
356 
357 unsigned TargetTransformInfo::getCacheLineSize() const {
358   return TTIImpl->getCacheLineSize();
359 }
360 
361 llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
362   const {
363   return TTIImpl->getCacheSize(Level);
364 }
365 
366 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
367   CacheLevel Level) const {
368   return TTIImpl->getCacheAssociativity(Level);
369 }
370 
371 unsigned TargetTransformInfo::getPrefetchDistance() const {
372   return TTIImpl->getPrefetchDistance();
373 }
374 
375 unsigned TargetTransformInfo::getMinPrefetchStride() const {
376   return TTIImpl->getMinPrefetchStride();
377 }
378 
379 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
380   return TTIImpl->getMaxPrefetchIterationsAhead();
381 }
382 
383 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
384   return TTIImpl->getMaxInterleaveFactor(VF);
385 }
386 
387 int TargetTransformInfo::getArithmeticInstrCost(
388     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
389     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
390     OperandValueProperties Opd2PropInfo,
391     ArrayRef<const Value *> Args) const {
392   int Cost = TTIImpl->getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
393                                              Opd1PropInfo, Opd2PropInfo, Args);
394   assert(Cost >= 0 && "TTI should not produce negative costs!");
395   return Cost;
396 }
397 
398 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
399                                         Type *SubTp) const {
400   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
401   assert(Cost >= 0 && "TTI should not produce negative costs!");
402   return Cost;
403 }
404 
405 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
406                                  Type *Src, const Instruction *I) const {
407   assert ((I == nullptr || I->getOpcode() == Opcode) &&
408           "Opcode should reflect passed instruction.");
409   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
410   assert(Cost >= 0 && "TTI should not produce negative costs!");
411   return Cost;
412 }
413 
414 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
415                                                   VectorType *VecTy,
416                                                   unsigned Index) const {
417   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
418   assert(Cost >= 0 && "TTI should not produce negative costs!");
419   return Cost;
420 }
421 
422 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
423   int Cost = TTIImpl->getCFInstrCost(Opcode);
424   assert(Cost >= 0 && "TTI should not produce negative costs!");
425   return Cost;
426 }
427 
428 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
429                                  Type *CondTy, const Instruction *I) const {
430   assert ((I == nullptr || I->getOpcode() == Opcode) &&
431           "Opcode should reflect passed instruction.");
432   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
433   assert(Cost >= 0 && "TTI should not produce negative costs!");
434   return Cost;
435 }
436 
437 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
438                                             unsigned Index) const {
439   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
440   assert(Cost >= 0 && "TTI should not produce negative costs!");
441   return Cost;
442 }
443 
444 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
445                                          unsigned Alignment,
446                                          unsigned AddressSpace,
447                                          const Instruction *I) const {
448   assert ((I == nullptr || I->getOpcode() == Opcode) &&
449           "Opcode should reflect passed instruction.");
450   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
451   assert(Cost >= 0 && "TTI should not produce negative costs!");
452   return Cost;
453 }
454 
455 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
456                                                unsigned Alignment,
457                                                unsigned AddressSpace) const {
458   int Cost =
459       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
460   assert(Cost >= 0 && "TTI should not produce negative costs!");
461   return Cost;
462 }
463 
464 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
465                                                 Value *Ptr, bool VariableMask,
466                                                 unsigned Alignment) const {
467   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
468                                              Alignment);
469   assert(Cost >= 0 && "TTI should not produce negative costs!");
470   return Cost;
471 }
472 
473 int TargetTransformInfo::getInterleavedMemoryOpCost(
474     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
475     unsigned Alignment, unsigned AddressSpace) const {
476   int Cost = TTIImpl->getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
477                                                  Alignment, AddressSpace);
478   assert(Cost >= 0 && "TTI should not produce negative costs!");
479   return Cost;
480 }
481 
482 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
483                                     ArrayRef<Type *> Tys, FastMathFlags FMF,
484                                     unsigned ScalarizationCostPassed) const {
485   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
486                                             ScalarizationCostPassed);
487   assert(Cost >= 0 && "TTI should not produce negative costs!");
488   return Cost;
489 }
490 
491 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
492            ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) const {
493   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
494   assert(Cost >= 0 && "TTI should not produce negative costs!");
495   return Cost;
496 }
497 
498 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
499                                           ArrayRef<Type *> Tys) const {
500   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
501   assert(Cost >= 0 && "TTI should not produce negative costs!");
502   return Cost;
503 }
504 
505 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
506   return TTIImpl->getNumberOfParts(Tp);
507 }
508 
509 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
510                                                    ScalarEvolution *SE,
511                                                    const SCEV *Ptr) const {
512   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
513   assert(Cost >= 0 && "TTI should not produce negative costs!");
514   return Cost;
515 }
516 
517 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
518                                                     bool IsPairwiseForm) const {
519   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
520   assert(Cost >= 0 && "TTI should not produce negative costs!");
521   return Cost;
522 }
523 
524 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
525                                                 bool IsPairwiseForm,
526                                                 bool IsUnsigned) const {
527   int Cost =
528       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
529   assert(Cost >= 0 && "TTI should not produce negative costs!");
530   return Cost;
531 }
532 
533 unsigned
534 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
535   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
536 }
537 
538 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
539                                              MemIntrinsicInfo &Info) const {
540   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
541 }
542 
543 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
544   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
545 }
546 
547 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
548     IntrinsicInst *Inst, Type *ExpectedType) const {
549   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
550 }
551 
552 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
553                                                      Value *Length,
554                                                      unsigned SrcAlign,
555                                                      unsigned DestAlign) const {
556   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
557                                             DestAlign);
558 }
559 
560 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
561     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
562     unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
563   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
564                                              SrcAlign, DestAlign);
565 }
566 
567 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
568                                               const Function *Callee) const {
569   return TTIImpl->areInlineCompatible(Caller, Callee);
570 }
571 
572 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
573                                              Type *Ty) const {
574   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
575 }
576 
577 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
578                                               Type *Ty) const {
579   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
580 }
581 
582 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
583   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
584 }
585 
586 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
587   return TTIImpl->isLegalToVectorizeLoad(LI);
588 }
589 
590 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
591   return TTIImpl->isLegalToVectorizeStore(SI);
592 }
593 
594 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
595     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
596   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
597                                               AddrSpace);
598 }
599 
600 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
601     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
602   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
603                                                AddrSpace);
604 }
605 
606 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
607                                                   unsigned LoadSize,
608                                                   unsigned ChainSizeInBytes,
609                                                   VectorType *VecTy) const {
610   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
611 }
612 
613 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
614                                                    unsigned StoreSize,
615                                                    unsigned ChainSizeInBytes,
616                                                    VectorType *VecTy) const {
617   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
618 }
619 
620 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode,
621                                                 Type *Ty, ReductionFlags Flags) const {
622   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
623 }
624 
625 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
626   return TTIImpl->shouldExpandReduction(II);
627 }
628 
629 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
630   return TTIImpl->getInstructionLatency(I);
631 }
632 
633 static bool isReverseVectorMask(ArrayRef<int> Mask) {
634   for (unsigned i = 0, MaskSize = Mask.size(); i < MaskSize; ++i)
635     if (Mask[i] >= 0 && Mask[i] != (int)(MaskSize - 1 - i))
636       return false;
637   return true;
638 }
639 
640 static bool isSingleSourceVectorMask(ArrayRef<int> Mask) {
641   bool Vec0 = false;
642   bool Vec1 = false;
643   for (unsigned i = 0, NumVecElts = Mask.size(); i < NumVecElts; ++i) {
644     if (Mask[i] >= 0) {
645       if ((unsigned)Mask[i] >= NumVecElts)
646         Vec1 = true;
647       else
648         Vec0 = true;
649     }
650   }
651   return !(Vec0 && Vec1);
652 }
653 
654 static bool isZeroEltBroadcastVectorMask(ArrayRef<int> Mask) {
655   for (unsigned i = 0; i < Mask.size(); ++i)
656     if (Mask[i] > 0)
657       return false;
658   return true;
659 }
660 
661 static bool isAlternateVectorMask(ArrayRef<int> Mask) {
662   bool isAlternate = true;
663   unsigned MaskSize = Mask.size();
664 
665   // Example: shufflevector A, B, <0,5,2,7>
666   for (unsigned i = 0; i < MaskSize && isAlternate; ++i) {
667     if (Mask[i] < 0)
668       continue;
669     isAlternate = Mask[i] == (int)((i & 1) ? MaskSize + i : i);
670   }
671 
672   if (isAlternate)
673     return true;
674 
675   isAlternate = true;
676   // Example: shufflevector A, B, <4,1,6,3>
677   for (unsigned i = 0; i < MaskSize && isAlternate; ++i) {
678     if (Mask[i] < 0)
679       continue;
680     isAlternate = Mask[i] == (int)((i & 1) ? i : MaskSize + i);
681   }
682 
683   return isAlternate;
684 }
685 
686 static bool isTransposeVectorMask(ArrayRef<int> Mask) {
687   // Transpose vector masks transpose a 2xn matrix. They read corresponding
688   // even- or odd-numbered vector elements from two n-dimensional source
689   // vectors and write each result into consecutive elements of an
690   // n-dimensional destination vector. Two shuffles are necessary to complete
691   // the transpose, one for the even elements and another for the odd elements.
692   // This description closely follows how the TRN1 and TRN2 AArch64
693   // instructions operate.
694   //
695   // For example, a simple 2x2 matrix can be transposed with:
696   //
697   //   ; Original matrix
698   //   m0 = <a, b>
699   //   m1 = <c, d>
700   //
701   //   ; Transposed matrix
702   //   t0 = <a, c> = shufflevector m0, m1, <0, 2>
703   //   t1 = <b, d> = shufflevector m0, m1, <1, 3>
704   //
705   // For matrices having greater than n columns, the resulting nx2 transposed
706   // matrix is stored in two result vectors such that one vector contains
707   // interleaved elements from all the even-numbered rows and the other vector
708   // contains interleaved elements from all the odd-numbered rows. For example,
709   // a 2x4 matrix can be transposed with:
710   //
711   //   ; Original matrix
712   //   m0 = <a, b, c, d>
713   //   m1 = <e, f, g, h>
714   //
715   //   ; Transposed matrix
716   //   t0 = <a, e, c, g> = shufflevector m0, m1 <0, 4, 2, 6>
717   //   t1 = <b, f, d, h> = shufflevector m0, m1 <1, 5, 3, 7>
718   //
719   // The above explanation places limitations on what valid transpose masks can
720   // look like. These limitations are defined by the checks below.
721   //
722   // 1. The number of elements in the mask must be a power of two.
723   if (!isPowerOf2_32(Mask.size()))
724     return false;
725 
726   // 2. The first element of the mask must be either a zero (for the
727   // even-numbered vector elements) or a one (for the odd-numbered vector
728   // elements).
729   if (Mask[0] != 0 && Mask[0] != 1)
730     return false;
731 
732   // 3. The difference between the first two elements must be equal to the
733   // number of elements in the mask.
734   if (Mask[1] - Mask[0] != (int)Mask.size())
735     return false;
736 
737   // 4. The difference between consecutive even-numbered and odd-numbered
738   // elements must be equal to two.
739   for (int I = 2; I < (int)Mask.size(); ++I)
740     if (Mask[I] - Mask[I - 2] != 2)
741       return false;
742 
743   return true;
744 }
745 
746 TargetTransformInfo::OperandValueKind
747 getOperandInfo(Value *V, TargetTransformInfo::OperandValueProperties &OpProps) {
748   TargetTransformInfo::OperandValueKind OpInfo =
749       TargetTransformInfo::OK_AnyValue;
750   OpProps = TargetTransformInfo::OP_None;
751 
752   const Value *Splat = getSplatValue(V);
753 
754   // Check for a splat of a constant or for a non uniform vector of constants
755   // and check if the constant(s) are all powers of two.
756   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
757     OpInfo = TargetTransformInfo::OK_NonUniformConstantValue;
758     if (Splat) {
759       OpInfo = TargetTransformInfo::OK_UniformConstantValue;
760       if (auto *CI = dyn_cast<ConstantInt>(Splat))
761         if (CI->getValue().isPowerOf2())
762           OpProps = TargetTransformInfo::OP_PowerOf2;
763     } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
764       OpProps = TargetTransformInfo::OP_PowerOf2;
765       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
766         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
767           if (CI->getValue().isPowerOf2())
768             continue;
769         OpProps = TargetTransformInfo::OP_None;
770         break;
771       }
772     }
773   }
774 
775   // Check for a splat of a uniform value. This is not loop aware, so return
776   // true only for the obviously uniform cases (argument, globalvalue)
777   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
778     OpInfo = TargetTransformInfo::OK_UniformValue;
779 
780   return OpInfo;
781 }
782 
783 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
784                                      unsigned Level) {
785   // We don't need a shuffle if we just want to have element 0 in position 0 of
786   // the vector.
787   if (!SI && Level == 0 && IsLeft)
788     return true;
789   else if (!SI)
790     return false;
791 
792   SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
793 
794   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
795   // we look at the left or right side.
796   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
797     Mask[i] = val;
798 
799   SmallVector<int, 16> ActualMask = SI->getShuffleMask();
800   return Mask == ActualMask;
801 }
802 
803 namespace {
804 /// Kind of the reduction data.
805 enum ReductionKind {
806   RK_None,           /// Not a reduction.
807   RK_Arithmetic,     /// Binary reduction data.
808   RK_MinMax,         /// Min/max reduction data.
809   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
810 };
811 /// Contains opcode + LHS/RHS parts of the reduction operations.
812 struct ReductionData {
813   ReductionData() = delete;
814   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
815       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
816     assert(Kind != RK_None && "expected binary or min/max reduction only.");
817   }
818   unsigned Opcode = 0;
819   Value *LHS = nullptr;
820   Value *RHS = nullptr;
821   ReductionKind Kind = RK_None;
822   bool hasSameData(ReductionData &RD) const {
823     return Kind == RD.Kind && Opcode == RD.Opcode;
824   }
825 };
826 } // namespace
827 
828 static Optional<ReductionData> getReductionData(Instruction *I) {
829   Value *L, *R;
830   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
831     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
832   if (auto *SI = dyn_cast<SelectInst>(I)) {
833     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
834         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
835         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
836         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
837         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
838         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
839       auto *CI = cast<CmpInst>(SI->getCondition());
840       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
841     }
842     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
843         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
844       auto *CI = cast<CmpInst>(SI->getCondition());
845       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
846     }
847   }
848   return llvm::None;
849 }
850 
851 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
852                                                    unsigned Level,
853                                                    unsigned NumLevels) {
854   // Match one level of pairwise operations.
855   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
856   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
857   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
858   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
859   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
860   if (!I)
861     return RK_None;
862 
863   assert(I->getType()->isVectorTy() && "Expecting a vector type");
864 
865   Optional<ReductionData> RD = getReductionData(I);
866   if (!RD)
867     return RK_None;
868 
869   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
870   if (!LS && Level)
871     return RK_None;
872   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
873   if (!RS && Level)
874     return RK_None;
875 
876   // On level 0 we can omit one shufflevector instruction.
877   if (!Level && !RS && !LS)
878     return RK_None;
879 
880   // Shuffle inputs must match.
881   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
882   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
883   Value *NextLevelOp = nullptr;
884   if (NextLevelOpR && NextLevelOpL) {
885     // If we have two shuffles their operands must match.
886     if (NextLevelOpL != NextLevelOpR)
887       return RK_None;
888 
889     NextLevelOp = NextLevelOpL;
890   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
891     // On the first level we can omit the shufflevector <0, undef,...>. So the
892     // input to the other shufflevector <1, undef> must match with one of the
893     // inputs to the current binary operation.
894     // Example:
895     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
896     //  %BinOp        = fadd          %NextLevelOpL, %R
897     if (NextLevelOpL && NextLevelOpL != RD->RHS)
898       return RK_None;
899     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
900       return RK_None;
901 
902     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
903   } else
904     return RK_None;
905 
906   // Check that the next levels binary operation exists and matches with the
907   // current one.
908   if (Level + 1 != NumLevels) {
909     Optional<ReductionData> NextLevelRD =
910         getReductionData(cast<Instruction>(NextLevelOp));
911     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
912       return RK_None;
913   }
914 
915   // Shuffle mask for pairwise operation must match.
916   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
917     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
918       return RK_None;
919   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
920     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
921       return RK_None;
922   } else {
923     return RK_None;
924   }
925 
926   if (++Level == NumLevels)
927     return RD->Kind;
928 
929   // Match next level.
930   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
931                                        NumLevels);
932 }
933 
934 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
935                                             unsigned &Opcode, Type *&Ty) {
936   if (!EnableReduxCost)
937     return RK_None;
938 
939   // Need to extract the first element.
940   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
941   unsigned Idx = ~0u;
942   if (CI)
943     Idx = CI->getZExtValue();
944   if (Idx != 0)
945     return RK_None;
946 
947   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
948   if (!RdxStart)
949     return RK_None;
950   Optional<ReductionData> RD = getReductionData(RdxStart);
951   if (!RD)
952     return RK_None;
953 
954   Type *VecTy = RdxStart->getType();
955   unsigned NumVecElems = VecTy->getVectorNumElements();
956   if (!isPowerOf2_32(NumVecElems))
957     return RK_None;
958 
959   // We look for a sequence of shuffle,shuffle,add triples like the following
960   // that builds a pairwise reduction tree.
961   //
962   //  (X0, X1, X2, X3)
963   //   (X0 + X1, X2 + X3, undef, undef)
964   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
965   //
966   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
967   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
968   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
969   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
970   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
971   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
972   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
973   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
974   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
975   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
976   // %r = extractelement <4 x float> %bin.rdx8, i32 0
977   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
978       RK_None)
979     return RK_None;
980 
981   Opcode = RD->Opcode;
982   Ty = VecTy;
983 
984   return RD->Kind;
985 }
986 
987 static std::pair<Value *, ShuffleVectorInst *>
988 getShuffleAndOtherOprd(Value *L, Value *R) {
989   ShuffleVectorInst *S = nullptr;
990 
991   if ((S = dyn_cast<ShuffleVectorInst>(L)))
992     return std::make_pair(R, S);
993 
994   S = dyn_cast<ShuffleVectorInst>(R);
995   return std::make_pair(L, S);
996 }
997 
998 static ReductionKind
999 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
1000                               unsigned &Opcode, Type *&Ty) {
1001   if (!EnableReduxCost)
1002     return RK_None;
1003 
1004   // Need to extract the first element.
1005   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1006   unsigned Idx = ~0u;
1007   if (CI)
1008     Idx = CI->getZExtValue();
1009   if (Idx != 0)
1010     return RK_None;
1011 
1012   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1013   if (!RdxStart)
1014     return RK_None;
1015   Optional<ReductionData> RD = getReductionData(RdxStart);
1016   if (!RD)
1017     return RK_None;
1018 
1019   Type *VecTy = ReduxRoot->getOperand(0)->getType();
1020   unsigned NumVecElems = VecTy->getVectorNumElements();
1021   if (!isPowerOf2_32(NumVecElems))
1022     return RK_None;
1023 
1024   // We look for a sequence of shuffles and adds like the following matching one
1025   // fadd, shuffle vector pair at a time.
1026   //
1027   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
1028   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
1029   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
1030   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
1031   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1032   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
1033   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1034 
1035   unsigned MaskStart = 1;
1036   Instruction *RdxOp = RdxStart;
1037   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
1038   unsigned NumVecElemsRemain = NumVecElems;
1039   while (NumVecElemsRemain - 1) {
1040     // Check for the right reduction operation.
1041     if (!RdxOp)
1042       return RK_None;
1043     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
1044     if (!RDLevel || !RDLevel->hasSameData(*RD))
1045       return RK_None;
1046 
1047     Value *NextRdxOp;
1048     ShuffleVectorInst *Shuffle;
1049     std::tie(NextRdxOp, Shuffle) =
1050         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
1051 
1052     // Check the current reduction operation and the shuffle use the same value.
1053     if (Shuffle == nullptr)
1054       return RK_None;
1055     if (Shuffle->getOperand(0) != NextRdxOp)
1056       return RK_None;
1057 
1058     // Check that shuffle masks matches.
1059     for (unsigned j = 0; j != MaskStart; ++j)
1060       ShuffleMask[j] = MaskStart + j;
1061     // Fill the rest of the mask with -1 for undef.
1062     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
1063 
1064     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
1065     if (ShuffleMask != Mask)
1066       return RK_None;
1067 
1068     RdxOp = dyn_cast<Instruction>(NextRdxOp);
1069     NumVecElemsRemain /= 2;
1070     MaskStart *= 2;
1071   }
1072 
1073   Opcode = RD->Opcode;
1074   Ty = VecTy;
1075   return RD->Kind;
1076 }
1077 
1078 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1079   switch (I->getOpcode()) {
1080   case Instruction::GetElementPtr:
1081     return getUserCost(I);
1082 
1083   case Instruction::Ret:
1084   case Instruction::PHI:
1085   case Instruction::Br: {
1086     return getCFInstrCost(I->getOpcode());
1087   }
1088   case Instruction::Add:
1089   case Instruction::FAdd:
1090   case Instruction::Sub:
1091   case Instruction::FSub:
1092   case Instruction::Mul:
1093   case Instruction::FMul:
1094   case Instruction::UDiv:
1095   case Instruction::SDiv:
1096   case Instruction::FDiv:
1097   case Instruction::URem:
1098   case Instruction::SRem:
1099   case Instruction::FRem:
1100   case Instruction::Shl:
1101   case Instruction::LShr:
1102   case Instruction::AShr:
1103   case Instruction::And:
1104   case Instruction::Or:
1105   case Instruction::Xor: {
1106     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1107     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1108     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1109     Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1110     SmallVector<const Value *, 2> Operands(I->operand_values());
1111     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1112                                   Op1VP, Op2VP, Operands);
1113   }
1114   case Instruction::Select: {
1115     const SelectInst *SI = cast<SelectInst>(I);
1116     Type *CondTy = SI->getCondition()->getType();
1117     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1118   }
1119   case Instruction::ICmp:
1120   case Instruction::FCmp: {
1121     Type *ValTy = I->getOperand(0)->getType();
1122     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1123   }
1124   case Instruction::Store: {
1125     const StoreInst *SI = cast<StoreInst>(I);
1126     Type *ValTy = SI->getValueOperand()->getType();
1127     return getMemoryOpCost(I->getOpcode(), ValTy,
1128                                 SI->getAlignment(),
1129                                 SI->getPointerAddressSpace(), I);
1130   }
1131   case Instruction::Load: {
1132     const LoadInst *LI = cast<LoadInst>(I);
1133     return getMemoryOpCost(I->getOpcode(), I->getType(),
1134                                 LI->getAlignment(),
1135                                 LI->getPointerAddressSpace(), I);
1136   }
1137   case Instruction::ZExt:
1138   case Instruction::SExt:
1139   case Instruction::FPToUI:
1140   case Instruction::FPToSI:
1141   case Instruction::FPExt:
1142   case Instruction::PtrToInt:
1143   case Instruction::IntToPtr:
1144   case Instruction::SIToFP:
1145   case Instruction::UIToFP:
1146   case Instruction::Trunc:
1147   case Instruction::FPTrunc:
1148   case Instruction::BitCast:
1149   case Instruction::AddrSpaceCast: {
1150     Type *SrcTy = I->getOperand(0)->getType();
1151     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1152   }
1153   case Instruction::ExtractElement: {
1154     const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1155     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1156     unsigned Idx = -1;
1157     if (CI)
1158       Idx = CI->getZExtValue();
1159 
1160     // Try to match a reduction sequence (series of shufflevector and vector
1161     // adds followed by a extractelement).
1162     unsigned ReduxOpCode;
1163     Type *ReduxType;
1164 
1165     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1166     case RK_Arithmetic:
1167       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1168                                              /*IsPairwiseForm=*/false);
1169     case RK_MinMax:
1170       return getMinMaxReductionCost(
1171           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1172           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1173     case RK_UnsignedMinMax:
1174       return getMinMaxReductionCost(
1175           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1176           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1177     case RK_None:
1178       break;
1179     }
1180 
1181     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1182     case RK_Arithmetic:
1183       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1184                                              /*IsPairwiseForm=*/true);
1185     case RK_MinMax:
1186       return getMinMaxReductionCost(
1187           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1188           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1189     case RK_UnsignedMinMax:
1190       return getMinMaxReductionCost(
1191           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1192           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1193     case RK_None:
1194       break;
1195     }
1196 
1197     return getVectorInstrCost(I->getOpcode(),
1198                                    EEI->getOperand(0)->getType(), Idx);
1199   }
1200   case Instruction::InsertElement: {
1201     const InsertElementInst * IE = cast<InsertElementInst>(I);
1202     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1203     unsigned Idx = -1;
1204     if (CI)
1205       Idx = CI->getZExtValue();
1206     return getVectorInstrCost(I->getOpcode(),
1207                                    IE->getType(), Idx);
1208   }
1209   case Instruction::ShuffleVector: {
1210     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1211     Type *VecTypOp0 = Shuffle->getOperand(0)->getType();
1212     unsigned NumVecElems = VecTypOp0->getVectorNumElements();
1213     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
1214 
1215     if (NumVecElems == Mask.size()) {
1216       if (isReverseVectorMask(Mask))
1217         return TTIImpl->getShuffleCost(TargetTransformInfo::SK_Reverse,
1218                                        VecTypOp0, 0, nullptr);
1219       if (isAlternateVectorMask(Mask))
1220         return TTIImpl->getShuffleCost(TargetTransformInfo::SK_Alternate,
1221                                        VecTypOp0, 0, nullptr);
1222 
1223       if (isTransposeVectorMask(Mask))
1224         return TTIImpl->getShuffleCost(TargetTransformInfo::SK_Transpose,
1225                                        VecTypOp0, 0, nullptr);
1226 
1227       if (isZeroEltBroadcastVectorMask(Mask))
1228         return TTIImpl->getShuffleCost(TargetTransformInfo::SK_Broadcast,
1229                                        VecTypOp0, 0, nullptr);
1230 
1231       if (isSingleSourceVectorMask(Mask))
1232         return TTIImpl->getShuffleCost(TargetTransformInfo::SK_PermuteSingleSrc,
1233                                        VecTypOp0, 0, nullptr);
1234 
1235       return TTIImpl->getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc,
1236                                      VecTypOp0, 0, nullptr);
1237     }
1238 
1239     return -1;
1240   }
1241   case Instruction::Call:
1242     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1243       SmallVector<Value *, 4> Args(II->arg_operands());
1244 
1245       FastMathFlags FMF;
1246       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1247         FMF = FPMO->getFastMathFlags();
1248 
1249       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
1250                                         Args, FMF);
1251     }
1252     return -1;
1253   default:
1254     // We don't have any information on this instruction.
1255     return -1;
1256   }
1257 }
1258 
1259 TargetTransformInfo::Concept::~Concept() {}
1260 
1261 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1262 
1263 TargetIRAnalysis::TargetIRAnalysis(
1264     std::function<Result(const Function &)> TTICallback)
1265     : TTICallback(std::move(TTICallback)) {}
1266 
1267 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1268                                                FunctionAnalysisManager &) {
1269   return TTICallback(F);
1270 }
1271 
1272 AnalysisKey TargetIRAnalysis::Key;
1273 
1274 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1275   return Result(F.getParent()->getDataLayout());
1276 }
1277 
1278 // Register the basic pass.
1279 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1280                 "Target Transform Information", false, true)
1281 char TargetTransformInfoWrapperPass::ID = 0;
1282 
1283 void TargetTransformInfoWrapperPass::anchor() {}
1284 
1285 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1286     : ImmutablePass(ID) {
1287   initializeTargetTransformInfoWrapperPassPass(
1288       *PassRegistry::getPassRegistry());
1289 }
1290 
1291 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1292     TargetIRAnalysis TIRA)
1293     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1294   initializeTargetTransformInfoWrapperPassPass(
1295       *PassRegistry::getPassRegistry());
1296 }
1297 
1298 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1299   FunctionAnalysisManager DummyFAM;
1300   TTI = TIRA.run(F, DummyFAM);
1301   return *TTI;
1302 }
1303 
1304 ImmutablePass *
1305 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1306   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1307 }
1308