1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/Analysis/TargetTransformInfo.h"
10 #include "llvm/Analysis/TargetTransformInfoImpl.h"
11 #include "llvm/IR/CallSite.h"
12 #include "llvm/IR/CFG.h"
13 #include "llvm/IR/DataLayout.h"
14 #include "llvm/IR/Instruction.h"
15 #include "llvm/IR/Instructions.h"
16 #include "llvm/IR/IntrinsicInst.h"
17 #include "llvm/IR/Module.h"
18 #include "llvm/IR/Operator.h"
19 #include "llvm/IR/PatternMatch.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Analysis/CFG.h"
23 #include "llvm/Analysis/LoopIterator.h"
24 #include <utility>
25 
26 using namespace llvm;
27 using namespace PatternMatch;
28 
29 #define DEBUG_TYPE "tti"
30 
31 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
32                                      cl::Hidden,
33                                      cl::desc("Recognize reduction patterns."));
34 
35 namespace {
36 /// No-op implementation of the TTI interface using the utility base
37 /// classes.
38 ///
39 /// This is used when no target specific information is available.
40 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
41   explicit NoTTIImpl(const DataLayout &DL)
42       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
43 
44   unsigned getCacheLineSize() const { return 0; }
45 
46   llvm::Optional<unsigned> getCacheSize(TargetTransformInfo::CacheLevel Level) const {
47     switch (Level) {
48     case TargetTransformInfo::CacheLevel::L1D:
49       LLVM_FALLTHROUGH;
50     case TargetTransformInfo::CacheLevel::L2D:
51       return llvm::Optional<unsigned>();
52     }
53     llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
54   }
55 
56   llvm::Optional<unsigned> getCacheAssociativity(
57     TargetTransformInfo::CacheLevel Level) const {
58     switch (Level) {
59     case TargetTransformInfo::CacheLevel::L1D:
60       LLVM_FALLTHROUGH;
61     case TargetTransformInfo::CacheLevel::L2D:
62       return llvm::Optional<unsigned>();
63     }
64 
65     llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
66   }
67 
68   unsigned getPrefetchDistance() const { return 0; }
69   unsigned getMinPrefetchStride() const { return 1; }
70   unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
71 };
72 }
73 
74 bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) {
75   // If the loop has irreducible control flow, it can not be converted to
76   // Hardware loop.
77   LoopBlocksRPO RPOT(L);
78   RPOT.perform(&LI);
79   if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
80     return false;
81   return true;
82 }
83 
84 bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
85                                                LoopInfo &LI, DominatorTree &DT,
86                                                bool ForceNestedLoop,
87                                                bool ForceHardwareLoopPHI) {
88   SmallVector<BasicBlock *, 4> ExitingBlocks;
89   L->getExitingBlocks(ExitingBlocks);
90 
91   for (BasicBlock *BB : ExitingBlocks) {
92     // If we pass the updated counter back through a phi, we need to know
93     // which latch the updated value will be coming from.
94     if (!L->isLoopLatch(BB)) {
95       if (ForceHardwareLoopPHI || CounterInReg)
96         continue;
97     }
98 
99     const SCEV *EC = SE.getExitCount(L, BB);
100     if (isa<SCEVCouldNotCompute>(EC))
101       continue;
102     if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
103       if (ConstEC->getValue()->isZero())
104         continue;
105     } else if (!SE.isLoopInvariant(EC, L))
106       continue;
107 
108     if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
109       continue;
110 
111     // If this exiting block is contained in a nested loop, it is not eligible
112     // for insertion of the branch-and-decrement since the inner loop would
113     // end up messing up the value in the CTR.
114     if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
115       continue;
116 
117     // We now have a loop-invariant count of loop iterations (which is not the
118     // constant zero) for which we know that this loop will not exit via this
119     // existing block.
120 
121     // We need to make sure that this block will run on every loop iteration.
122     // For this to be true, we must dominate all blocks with backedges. Such
123     // blocks are in-loop predecessors to the header block.
124     bool NotAlways = false;
125     for (BasicBlock *Pred : predecessors(L->getHeader())) {
126       if (!L->contains(Pred))
127         continue;
128 
129       if (!DT.dominates(BB, Pred)) {
130         NotAlways = true;
131         break;
132       }
133     }
134 
135     if (NotAlways)
136       continue;
137 
138     // Make sure this blocks ends with a conditional branch.
139     Instruction *TI = BB->getTerminator();
140     if (!TI)
141       continue;
142 
143     if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
144       if (!BI->isConditional())
145         continue;
146 
147       ExitBranch = BI;
148     } else
149       continue;
150 
151     // Note that this block may not be the loop latch block, even if the loop
152     // has a latch block.
153     ExitBlock = BB;
154     ExitCount = EC;
155     break;
156   }
157 
158   if (!ExitBlock)
159     return false;
160   return true;
161 }
162 
163 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
164     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
165 
166 TargetTransformInfo::~TargetTransformInfo() {}
167 
168 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
169     : TTIImpl(std::move(Arg.TTIImpl)) {}
170 
171 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
172   TTIImpl = std::move(RHS.TTIImpl);
173   return *this;
174 }
175 
176 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
177                                           Type *OpTy) const {
178   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
179   assert(Cost >= 0 && "TTI should not produce negative costs!");
180   return Cost;
181 }
182 
183 int TargetTransformInfo::getCallCost(FunctionType *FTy, int NumArgs,
184                                      const User *U) const {
185   int Cost = TTIImpl->getCallCost(FTy, NumArgs, U);
186   assert(Cost >= 0 && "TTI should not produce negative costs!");
187   return Cost;
188 }
189 
190 int TargetTransformInfo::getCallCost(const Function *F,
191                                      ArrayRef<const Value *> Arguments,
192                                      const User *U) const {
193   int Cost = TTIImpl->getCallCost(F, Arguments, U);
194   assert(Cost >= 0 && "TTI should not produce negative costs!");
195   return Cost;
196 }
197 
198 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
199   return TTIImpl->getInliningThresholdMultiplier();
200 }
201 
202 int TargetTransformInfo::getInlinerVectorBonusPercent() const {
203   return TTIImpl->getInlinerVectorBonusPercent();
204 }
205 
206 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
207                                     ArrayRef<const Value *> Operands) const {
208   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
209 }
210 
211 int TargetTransformInfo::getExtCost(const Instruction *I,
212                                     const Value *Src) const {
213   return TTIImpl->getExtCost(I, Src);
214 }
215 
216 int TargetTransformInfo::getIntrinsicCost(
217     Intrinsic::ID IID, Type *RetTy, ArrayRef<const Value *> Arguments,
218     const User *U) const {
219   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments, U);
220   assert(Cost >= 0 && "TTI should not produce negative costs!");
221   return Cost;
222 }
223 
224 unsigned
225 TargetTransformInfo::getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
226                                                       unsigned &JTSize) const {
227   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize);
228 }
229 
230 int TargetTransformInfo::getUserCost(const User *U,
231     ArrayRef<const Value *> Operands) const {
232   int Cost = TTIImpl->getUserCost(U, Operands);
233   assert(Cost >= 0 && "TTI should not produce negative costs!");
234   return Cost;
235 }
236 
237 bool TargetTransformInfo::hasBranchDivergence() const {
238   return TTIImpl->hasBranchDivergence();
239 }
240 
241 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
242   return TTIImpl->isSourceOfDivergence(V);
243 }
244 
245 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
246   return TTIImpl->isAlwaysUniform(V);
247 }
248 
249 unsigned TargetTransformInfo::getFlatAddressSpace() const {
250   return TTIImpl->getFlatAddressSpace();
251 }
252 
253 bool TargetTransformInfo::collectFlatAddressOperands(
254   SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const  {
255   return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
256 }
257 
258 bool TargetTransformInfo::rewriteIntrinsicWithAddressSpace(
259   IntrinsicInst *II, Value *OldV, Value *NewV) const {
260   return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
261 }
262 
263 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
264   return TTIImpl->isLoweredToCall(F);
265 }
266 
267 bool TargetTransformInfo::isHardwareLoopProfitable(
268   Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
269   TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
270   return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
271 }
272 
273 void TargetTransformInfo::getUnrollingPreferences(
274     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
275   return TTIImpl->getUnrollingPreferences(L, SE, UP);
276 }
277 
278 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
279   return TTIImpl->isLegalAddImmediate(Imm);
280 }
281 
282 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
283   return TTIImpl->isLegalICmpImmediate(Imm);
284 }
285 
286 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
287                                                 int64_t BaseOffset,
288                                                 bool HasBaseReg,
289                                                 int64_t Scale,
290                                                 unsigned AddrSpace,
291                                                 Instruction *I) const {
292   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
293                                         Scale, AddrSpace, I);
294 }
295 
296 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
297   return TTIImpl->isLSRCostLess(C1, C2);
298 }
299 
300 bool TargetTransformInfo::canMacroFuseCmp() const {
301   return TTIImpl->canMacroFuseCmp();
302 }
303 
304 bool TargetTransformInfo::canSaveCmp(Loop *L, BranchInst **BI,
305                                      ScalarEvolution *SE, LoopInfo *LI,
306                                      DominatorTree *DT, AssumptionCache *AC,
307                                      TargetLibraryInfo *LibInfo) const {
308   return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
309 }
310 
311 bool TargetTransformInfo::shouldFavorPostInc() const {
312   return TTIImpl->shouldFavorPostInc();
313 }
314 
315 bool TargetTransformInfo::shouldFavorBackedgeIndex(const Loop *L) const {
316   return TTIImpl->shouldFavorBackedgeIndex(L);
317 }
318 
319 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType) const {
320   return TTIImpl->isLegalMaskedStore(DataType);
321 }
322 
323 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType) const {
324   return TTIImpl->isLegalMaskedLoad(DataType);
325 }
326 
327 bool TargetTransformInfo::isLegalNTStore(Type *DataType,
328                                          Align Alignment) const {
329   return TTIImpl->isLegalNTStore(DataType, Alignment);
330 }
331 
332 bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
333   return TTIImpl->isLegalNTLoad(DataType, Alignment);
334 }
335 
336 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
337   return TTIImpl->isLegalMaskedGather(DataType);
338 }
339 
340 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
341   return TTIImpl->isLegalMaskedScatter(DataType);
342 }
343 
344 bool TargetTransformInfo::isLegalMaskedCompressStore(Type *DataType) const {
345   return TTIImpl->isLegalMaskedCompressStore(DataType);
346 }
347 
348 bool TargetTransformInfo::isLegalMaskedExpandLoad(Type *DataType) const {
349   return TTIImpl->isLegalMaskedExpandLoad(DataType);
350 }
351 
352 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
353   return TTIImpl->hasDivRemOp(DataType, IsSigned);
354 }
355 
356 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
357                                              unsigned AddrSpace) const {
358   return TTIImpl->hasVolatileVariant(I, AddrSpace);
359 }
360 
361 bool TargetTransformInfo::prefersVectorizedAddressing() const {
362   return TTIImpl->prefersVectorizedAddressing();
363 }
364 
365 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
366                                               int64_t BaseOffset,
367                                               bool HasBaseReg,
368                                               int64_t Scale,
369                                               unsigned AddrSpace) const {
370   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
371                                            Scale, AddrSpace);
372   assert(Cost >= 0 && "TTI should not produce negative costs!");
373   return Cost;
374 }
375 
376 bool TargetTransformInfo::LSRWithInstrQueries() const {
377   return TTIImpl->LSRWithInstrQueries();
378 }
379 
380 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
381   return TTIImpl->isTruncateFree(Ty1, Ty2);
382 }
383 
384 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
385   return TTIImpl->isProfitableToHoist(I);
386 }
387 
388 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
389 
390 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
391   return TTIImpl->isTypeLegal(Ty);
392 }
393 
394 bool TargetTransformInfo::shouldBuildLookupTables() const {
395   return TTIImpl->shouldBuildLookupTables();
396 }
397 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(Constant *C) const {
398   return TTIImpl->shouldBuildLookupTablesForConstant(C);
399 }
400 
401 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
402   return TTIImpl->useColdCCForColdCall(F);
403 }
404 
405 unsigned TargetTransformInfo::
406 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
407   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
408 }
409 
410 unsigned TargetTransformInfo::
411 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
412                                  unsigned VF) const {
413   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
414 }
415 
416 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
417   return TTIImpl->supportsEfficientVectorElementLoadStore();
418 }
419 
420 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
421   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
422 }
423 
424 TargetTransformInfo::MemCmpExpansionOptions
425 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
426   return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
427 }
428 
429 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
430   return TTIImpl->enableInterleavedAccessVectorization();
431 }
432 
433 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const {
434   return TTIImpl->enableMaskedInterleavedAccessVectorization();
435 }
436 
437 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
438   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
439 }
440 
441 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
442                                                          unsigned BitWidth,
443                                                          unsigned AddressSpace,
444                                                          unsigned Alignment,
445                                                          bool *Fast) const {
446   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
447                                                  Alignment, Fast);
448 }
449 
450 TargetTransformInfo::PopcntSupportKind
451 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
452   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
453 }
454 
455 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
456   return TTIImpl->haveFastSqrt(Ty);
457 }
458 
459 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
460   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
461 }
462 
463 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
464   int Cost = TTIImpl->getFPOpCost(Ty);
465   assert(Cost >= 0 && "TTI should not produce negative costs!");
466   return Cost;
467 }
468 
469 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
470                                                const APInt &Imm,
471                                                Type *Ty) const {
472   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
473   assert(Cost >= 0 && "TTI should not produce negative costs!");
474   return Cost;
475 }
476 
477 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
478   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
479   assert(Cost >= 0 && "TTI should not produce negative costs!");
480   return Cost;
481 }
482 
483 int TargetTransformInfo::getIntImmCost(unsigned Opcode, unsigned Idx,
484                                        const APInt &Imm, Type *Ty) const {
485   int Cost = TTIImpl->getIntImmCost(Opcode, Idx, Imm, Ty);
486   assert(Cost >= 0 && "TTI should not produce negative costs!");
487   return Cost;
488 }
489 
490 int TargetTransformInfo::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
491                                        const APInt &Imm, Type *Ty) const {
492   int Cost = TTIImpl->getIntImmCost(IID, Idx, Imm, Ty);
493   assert(Cost >= 0 && "TTI should not produce negative costs!");
494   return Cost;
495 }
496 
497 unsigned TargetTransformInfo::getNumberOfRegisters(bool Vector) const {
498   return TTIImpl->getNumberOfRegisters(Vector);
499 }
500 
501 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
502   return TTIImpl->getRegisterBitWidth(Vector);
503 }
504 
505 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
506   return TTIImpl->getMinVectorRegisterBitWidth();
507 }
508 
509 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
510   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
511 }
512 
513 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
514   return TTIImpl->getMinimumVF(ElemWidth);
515 }
516 
517 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
518     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
519   return TTIImpl->shouldConsiderAddressTypePromotion(
520       I, AllowPromotionWithoutCommonHeader);
521 }
522 
523 unsigned TargetTransformInfo::getCacheLineSize() const {
524   return TTIImpl->getCacheLineSize();
525 }
526 
527 llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
528   const {
529   return TTIImpl->getCacheSize(Level);
530 }
531 
532 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
533   CacheLevel Level) const {
534   return TTIImpl->getCacheAssociativity(Level);
535 }
536 
537 unsigned TargetTransformInfo::getPrefetchDistance() const {
538   return TTIImpl->getPrefetchDistance();
539 }
540 
541 unsigned TargetTransformInfo::getMinPrefetchStride() const {
542   return TTIImpl->getMinPrefetchStride();
543 }
544 
545 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
546   return TTIImpl->getMaxPrefetchIterationsAhead();
547 }
548 
549 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
550   return TTIImpl->getMaxInterleaveFactor(VF);
551 }
552 
553 TargetTransformInfo::OperandValueKind
554 TargetTransformInfo::getOperandInfo(Value *V, OperandValueProperties &OpProps) {
555   OperandValueKind OpInfo = OK_AnyValue;
556   OpProps = OP_None;
557 
558   if (auto *CI = dyn_cast<ConstantInt>(V)) {
559     if (CI->getValue().isPowerOf2())
560       OpProps = OP_PowerOf2;
561     return OK_UniformConstantValue;
562   }
563 
564   // A broadcast shuffle creates a uniform value.
565   // TODO: Add support for non-zero index broadcasts.
566   // TODO: Add support for different source vector width.
567   if (auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
568     if (ShuffleInst->isZeroEltSplat())
569       OpInfo = OK_UniformValue;
570 
571   const Value *Splat = getSplatValue(V);
572 
573   // Check for a splat of a constant or for a non uniform vector of constants
574   // and check if the constant(s) are all powers of two.
575   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
576     OpInfo = OK_NonUniformConstantValue;
577     if (Splat) {
578       OpInfo = OK_UniformConstantValue;
579       if (auto *CI = dyn_cast<ConstantInt>(Splat))
580         if (CI->getValue().isPowerOf2())
581           OpProps = OP_PowerOf2;
582     } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
583       OpProps = OP_PowerOf2;
584       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
585         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
586           if (CI->getValue().isPowerOf2())
587             continue;
588         OpProps = OP_None;
589         break;
590       }
591     }
592   }
593 
594   // Check for a splat of a uniform value. This is not loop aware, so return
595   // true only for the obviously uniform cases (argument, globalvalue)
596   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
597     OpInfo = OK_UniformValue;
598 
599   return OpInfo;
600 }
601 
602 int TargetTransformInfo::getArithmeticInstrCost(
603     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
604     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
605     OperandValueProperties Opd2PropInfo,
606     ArrayRef<const Value *> Args) const {
607   int Cost = TTIImpl->getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
608                                              Opd1PropInfo, Opd2PropInfo, Args);
609   assert(Cost >= 0 && "TTI should not produce negative costs!");
610   return Cost;
611 }
612 
613 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
614                                         Type *SubTp) const {
615   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
616   assert(Cost >= 0 && "TTI should not produce negative costs!");
617   return Cost;
618 }
619 
620 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
621                                  Type *Src, const Instruction *I) const {
622   assert ((I == nullptr || I->getOpcode() == Opcode) &&
623           "Opcode should reflect passed instruction.");
624   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
625   assert(Cost >= 0 && "TTI should not produce negative costs!");
626   return Cost;
627 }
628 
629 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
630                                                   VectorType *VecTy,
631                                                   unsigned Index) const {
632   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
633   assert(Cost >= 0 && "TTI should not produce negative costs!");
634   return Cost;
635 }
636 
637 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
638   int Cost = TTIImpl->getCFInstrCost(Opcode);
639   assert(Cost >= 0 && "TTI should not produce negative costs!");
640   return Cost;
641 }
642 
643 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
644                                  Type *CondTy, const Instruction *I) const {
645   assert ((I == nullptr || I->getOpcode() == Opcode) &&
646           "Opcode should reflect passed instruction.");
647   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
648   assert(Cost >= 0 && "TTI should not produce negative costs!");
649   return Cost;
650 }
651 
652 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
653                                             unsigned Index) const {
654   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
655   assert(Cost >= 0 && "TTI should not produce negative costs!");
656   return Cost;
657 }
658 
659 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
660                                          unsigned Alignment,
661                                          unsigned AddressSpace,
662                                          const Instruction *I) const {
663   assert ((I == nullptr || I->getOpcode() == Opcode) &&
664           "Opcode should reflect passed instruction.");
665   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
666   assert(Cost >= 0 && "TTI should not produce negative costs!");
667   return Cost;
668 }
669 
670 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
671                                                unsigned Alignment,
672                                                unsigned AddressSpace) const {
673   int Cost =
674       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
675   assert(Cost >= 0 && "TTI should not produce negative costs!");
676   return Cost;
677 }
678 
679 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
680                                                 Value *Ptr, bool VariableMask,
681                                                 unsigned Alignment) const {
682   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
683                                              Alignment);
684   assert(Cost >= 0 && "TTI should not produce negative costs!");
685   return Cost;
686 }
687 
688 int TargetTransformInfo::getInterleavedMemoryOpCost(
689     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
690     unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond,
691     bool UseMaskForGaps) const {
692   int Cost = TTIImpl->getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
693                                                  Alignment, AddressSpace,
694                                                  UseMaskForCond,
695                                                  UseMaskForGaps);
696   assert(Cost >= 0 && "TTI should not produce negative costs!");
697   return Cost;
698 }
699 
700 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
701                                     ArrayRef<Type *> Tys, FastMathFlags FMF,
702                                     unsigned ScalarizationCostPassed) const {
703   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
704                                             ScalarizationCostPassed);
705   assert(Cost >= 0 && "TTI should not produce negative costs!");
706   return Cost;
707 }
708 
709 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
710            ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) const {
711   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
712   assert(Cost >= 0 && "TTI should not produce negative costs!");
713   return Cost;
714 }
715 
716 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
717                                           ArrayRef<Type *> Tys) const {
718   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
719   assert(Cost >= 0 && "TTI should not produce negative costs!");
720   return Cost;
721 }
722 
723 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
724   return TTIImpl->getNumberOfParts(Tp);
725 }
726 
727 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
728                                                    ScalarEvolution *SE,
729                                                    const SCEV *Ptr) const {
730   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
731   assert(Cost >= 0 && "TTI should not produce negative costs!");
732   return Cost;
733 }
734 
735 int TargetTransformInfo::getMemcpyCost(const Instruction *I) const {
736   int Cost = TTIImpl->getMemcpyCost(I);
737   assert(Cost >= 0 && "TTI should not produce negative costs!");
738   return Cost;
739 }
740 
741 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
742                                                     bool IsPairwiseForm) const {
743   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
744   assert(Cost >= 0 && "TTI should not produce negative costs!");
745   return Cost;
746 }
747 
748 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
749                                                 bool IsPairwiseForm,
750                                                 bool IsUnsigned) const {
751   int Cost =
752       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
753   assert(Cost >= 0 && "TTI should not produce negative costs!");
754   return Cost;
755 }
756 
757 unsigned
758 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
759   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
760 }
761 
762 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
763                                              MemIntrinsicInfo &Info) const {
764   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
765 }
766 
767 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
768   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
769 }
770 
771 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
772     IntrinsicInst *Inst, Type *ExpectedType) const {
773   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
774 }
775 
776 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
777                                                      Value *Length,
778                                                      unsigned SrcAlign,
779                                                      unsigned DestAlign) const {
780   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
781                                             DestAlign);
782 }
783 
784 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
785     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
786     unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
787   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
788                                              SrcAlign, DestAlign);
789 }
790 
791 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
792                                               const Function *Callee) const {
793   return TTIImpl->areInlineCompatible(Caller, Callee);
794 }
795 
796 bool TargetTransformInfo::areFunctionArgsABICompatible(
797     const Function *Caller, const Function *Callee,
798     SmallPtrSetImpl<Argument *> &Args) const {
799   return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
800 }
801 
802 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
803                                              Type *Ty) const {
804   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
805 }
806 
807 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
808                                               Type *Ty) const {
809   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
810 }
811 
812 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
813   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
814 }
815 
816 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
817   return TTIImpl->isLegalToVectorizeLoad(LI);
818 }
819 
820 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
821   return TTIImpl->isLegalToVectorizeStore(SI);
822 }
823 
824 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
825     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
826   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
827                                               AddrSpace);
828 }
829 
830 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
831     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
832   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
833                                                AddrSpace);
834 }
835 
836 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
837                                                   unsigned LoadSize,
838                                                   unsigned ChainSizeInBytes,
839                                                   VectorType *VecTy) const {
840   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
841 }
842 
843 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
844                                                    unsigned StoreSize,
845                                                    unsigned ChainSizeInBytes,
846                                                    VectorType *VecTy) const {
847   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
848 }
849 
850 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode,
851                                                 Type *Ty, ReductionFlags Flags) const {
852   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
853 }
854 
855 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
856   return TTIImpl->shouldExpandReduction(II);
857 }
858 
859 unsigned TargetTransformInfo::getGISelRematGlobalCost() const {
860   return TTIImpl->getGISelRematGlobalCost();
861 }
862 
863 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
864   return TTIImpl->getInstructionLatency(I);
865 }
866 
867 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
868                                      unsigned Level) {
869   // We don't need a shuffle if we just want to have element 0 in position 0 of
870   // the vector.
871   if (!SI && Level == 0 && IsLeft)
872     return true;
873   else if (!SI)
874     return false;
875 
876   SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
877 
878   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
879   // we look at the left or right side.
880   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
881     Mask[i] = val;
882 
883   SmallVector<int, 16> ActualMask = SI->getShuffleMask();
884   return Mask == ActualMask;
885 }
886 
887 namespace {
888 /// Kind of the reduction data.
889 enum ReductionKind {
890   RK_None,           /// Not a reduction.
891   RK_Arithmetic,     /// Binary reduction data.
892   RK_MinMax,         /// Min/max reduction data.
893   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
894 };
895 /// Contains opcode + LHS/RHS parts of the reduction operations.
896 struct ReductionData {
897   ReductionData() = delete;
898   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
899       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
900     assert(Kind != RK_None && "expected binary or min/max reduction only.");
901   }
902   unsigned Opcode = 0;
903   Value *LHS = nullptr;
904   Value *RHS = nullptr;
905   ReductionKind Kind = RK_None;
906   bool hasSameData(ReductionData &RD) const {
907     return Kind == RD.Kind && Opcode == RD.Opcode;
908   }
909 };
910 } // namespace
911 
912 static Optional<ReductionData> getReductionData(Instruction *I) {
913   Value *L, *R;
914   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
915     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
916   if (auto *SI = dyn_cast<SelectInst>(I)) {
917     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
918         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
919         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
920         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
921         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
922         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
923       auto *CI = cast<CmpInst>(SI->getCondition());
924       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
925     }
926     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
927         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
928       auto *CI = cast<CmpInst>(SI->getCondition());
929       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
930     }
931   }
932   return llvm::None;
933 }
934 
935 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
936                                                    unsigned Level,
937                                                    unsigned NumLevels) {
938   // Match one level of pairwise operations.
939   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
940   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
941   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
942   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
943   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
944   if (!I)
945     return RK_None;
946 
947   assert(I->getType()->isVectorTy() && "Expecting a vector type");
948 
949   Optional<ReductionData> RD = getReductionData(I);
950   if (!RD)
951     return RK_None;
952 
953   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
954   if (!LS && Level)
955     return RK_None;
956   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
957   if (!RS && Level)
958     return RK_None;
959 
960   // On level 0 we can omit one shufflevector instruction.
961   if (!Level && !RS && !LS)
962     return RK_None;
963 
964   // Shuffle inputs must match.
965   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
966   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
967   Value *NextLevelOp = nullptr;
968   if (NextLevelOpR && NextLevelOpL) {
969     // If we have two shuffles their operands must match.
970     if (NextLevelOpL != NextLevelOpR)
971       return RK_None;
972 
973     NextLevelOp = NextLevelOpL;
974   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
975     // On the first level we can omit the shufflevector <0, undef,...>. So the
976     // input to the other shufflevector <1, undef> must match with one of the
977     // inputs to the current binary operation.
978     // Example:
979     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
980     //  %BinOp        = fadd          %NextLevelOpL, %R
981     if (NextLevelOpL && NextLevelOpL != RD->RHS)
982       return RK_None;
983     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
984       return RK_None;
985 
986     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
987   } else
988     return RK_None;
989 
990   // Check that the next levels binary operation exists and matches with the
991   // current one.
992   if (Level + 1 != NumLevels) {
993     Optional<ReductionData> NextLevelRD =
994         getReductionData(cast<Instruction>(NextLevelOp));
995     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
996       return RK_None;
997   }
998 
999   // Shuffle mask for pairwise operation must match.
1000   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
1001     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
1002       return RK_None;
1003   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
1004     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
1005       return RK_None;
1006   } else {
1007     return RK_None;
1008   }
1009 
1010   if (++Level == NumLevels)
1011     return RD->Kind;
1012 
1013   // Match next level.
1014   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
1015                                        NumLevels);
1016 }
1017 
1018 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
1019                                             unsigned &Opcode, Type *&Ty) {
1020   if (!EnableReduxCost)
1021     return RK_None;
1022 
1023   // Need to extract the first element.
1024   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1025   unsigned Idx = ~0u;
1026   if (CI)
1027     Idx = CI->getZExtValue();
1028   if (Idx != 0)
1029     return RK_None;
1030 
1031   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1032   if (!RdxStart)
1033     return RK_None;
1034   Optional<ReductionData> RD = getReductionData(RdxStart);
1035   if (!RD)
1036     return RK_None;
1037 
1038   Type *VecTy = RdxStart->getType();
1039   unsigned NumVecElems = VecTy->getVectorNumElements();
1040   if (!isPowerOf2_32(NumVecElems))
1041     return RK_None;
1042 
1043   // We look for a sequence of shuffle,shuffle,add triples like the following
1044   // that builds a pairwise reduction tree.
1045   //
1046   //  (X0, X1, X2, X3)
1047   //   (X0 + X1, X2 + X3, undef, undef)
1048   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
1049   //
1050   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
1051   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
1052   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
1053   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
1054   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
1055   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1056   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
1057   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1058   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1059   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
1060   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1061   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
1062       RK_None)
1063     return RK_None;
1064 
1065   Opcode = RD->Opcode;
1066   Ty = VecTy;
1067 
1068   return RD->Kind;
1069 }
1070 
1071 static std::pair<Value *, ShuffleVectorInst *>
1072 getShuffleAndOtherOprd(Value *L, Value *R) {
1073   ShuffleVectorInst *S = nullptr;
1074 
1075   if ((S = dyn_cast<ShuffleVectorInst>(L)))
1076     return std::make_pair(R, S);
1077 
1078   S = dyn_cast<ShuffleVectorInst>(R);
1079   return std::make_pair(L, S);
1080 }
1081 
1082 static ReductionKind
1083 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
1084                               unsigned &Opcode, Type *&Ty) {
1085   if (!EnableReduxCost)
1086     return RK_None;
1087 
1088   // Need to extract the first element.
1089   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1090   unsigned Idx = ~0u;
1091   if (CI)
1092     Idx = CI->getZExtValue();
1093   if (Idx != 0)
1094     return RK_None;
1095 
1096   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1097   if (!RdxStart)
1098     return RK_None;
1099   Optional<ReductionData> RD = getReductionData(RdxStart);
1100   if (!RD)
1101     return RK_None;
1102 
1103   Type *VecTy = ReduxRoot->getOperand(0)->getType();
1104   unsigned NumVecElems = VecTy->getVectorNumElements();
1105   if (!isPowerOf2_32(NumVecElems))
1106     return RK_None;
1107 
1108   // We look for a sequence of shuffles and adds like the following matching one
1109   // fadd, shuffle vector pair at a time.
1110   //
1111   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
1112   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
1113   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
1114   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
1115   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1116   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
1117   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1118 
1119   unsigned MaskStart = 1;
1120   Instruction *RdxOp = RdxStart;
1121   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
1122   unsigned NumVecElemsRemain = NumVecElems;
1123   while (NumVecElemsRemain - 1) {
1124     // Check for the right reduction operation.
1125     if (!RdxOp)
1126       return RK_None;
1127     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
1128     if (!RDLevel || !RDLevel->hasSameData(*RD))
1129       return RK_None;
1130 
1131     Value *NextRdxOp;
1132     ShuffleVectorInst *Shuffle;
1133     std::tie(NextRdxOp, Shuffle) =
1134         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
1135 
1136     // Check the current reduction operation and the shuffle use the same value.
1137     if (Shuffle == nullptr)
1138       return RK_None;
1139     if (Shuffle->getOperand(0) != NextRdxOp)
1140       return RK_None;
1141 
1142     // Check that shuffle masks matches.
1143     for (unsigned j = 0; j != MaskStart; ++j)
1144       ShuffleMask[j] = MaskStart + j;
1145     // Fill the rest of the mask with -1 for undef.
1146     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
1147 
1148     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
1149     if (ShuffleMask != Mask)
1150       return RK_None;
1151 
1152     RdxOp = dyn_cast<Instruction>(NextRdxOp);
1153     NumVecElemsRemain /= 2;
1154     MaskStart *= 2;
1155   }
1156 
1157   Opcode = RD->Opcode;
1158   Ty = VecTy;
1159   return RD->Kind;
1160 }
1161 
1162 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1163   switch (I->getOpcode()) {
1164   case Instruction::GetElementPtr:
1165     return getUserCost(I);
1166 
1167   case Instruction::Ret:
1168   case Instruction::PHI:
1169   case Instruction::Br: {
1170     return getCFInstrCost(I->getOpcode());
1171   }
1172   case Instruction::Add:
1173   case Instruction::FAdd:
1174   case Instruction::Sub:
1175   case Instruction::FSub:
1176   case Instruction::Mul:
1177   case Instruction::FMul:
1178   case Instruction::UDiv:
1179   case Instruction::SDiv:
1180   case Instruction::FDiv:
1181   case Instruction::URem:
1182   case Instruction::SRem:
1183   case Instruction::FRem:
1184   case Instruction::Shl:
1185   case Instruction::LShr:
1186   case Instruction::AShr:
1187   case Instruction::And:
1188   case Instruction::Or:
1189   case Instruction::Xor: {
1190     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1191     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1192     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1193     Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1194     SmallVector<const Value *, 2> Operands(I->operand_values());
1195     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1196                                   Op1VP, Op2VP, Operands);
1197   }
1198   case Instruction::FNeg: {
1199     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1200     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1201     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1202     Op2VK = OK_AnyValue;
1203     Op2VP = OP_None;
1204     SmallVector<const Value *, 2> Operands(I->operand_values());
1205     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1206                                   Op1VP, Op2VP, Operands);
1207   }
1208   case Instruction::Select: {
1209     const SelectInst *SI = cast<SelectInst>(I);
1210     Type *CondTy = SI->getCondition()->getType();
1211     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1212   }
1213   case Instruction::ICmp:
1214   case Instruction::FCmp: {
1215     Type *ValTy = I->getOperand(0)->getType();
1216     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1217   }
1218   case Instruction::Store: {
1219     const StoreInst *SI = cast<StoreInst>(I);
1220     Type *ValTy = SI->getValueOperand()->getType();
1221     return getMemoryOpCost(I->getOpcode(), ValTy,
1222                                 SI->getAlignment(),
1223                                 SI->getPointerAddressSpace(), I);
1224   }
1225   case Instruction::Load: {
1226     const LoadInst *LI = cast<LoadInst>(I);
1227     return getMemoryOpCost(I->getOpcode(), I->getType(),
1228                                 LI->getAlignment(),
1229                                 LI->getPointerAddressSpace(), I);
1230   }
1231   case Instruction::ZExt:
1232   case Instruction::SExt:
1233   case Instruction::FPToUI:
1234   case Instruction::FPToSI:
1235   case Instruction::FPExt:
1236   case Instruction::PtrToInt:
1237   case Instruction::IntToPtr:
1238   case Instruction::SIToFP:
1239   case Instruction::UIToFP:
1240   case Instruction::Trunc:
1241   case Instruction::FPTrunc:
1242   case Instruction::BitCast:
1243   case Instruction::AddrSpaceCast: {
1244     Type *SrcTy = I->getOperand(0)->getType();
1245     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1246   }
1247   case Instruction::ExtractElement: {
1248     const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1249     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1250     unsigned Idx = -1;
1251     if (CI)
1252       Idx = CI->getZExtValue();
1253 
1254     // Try to match a reduction sequence (series of shufflevector and vector
1255     // adds followed by a extractelement).
1256     unsigned ReduxOpCode;
1257     Type *ReduxType;
1258 
1259     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1260     case RK_Arithmetic:
1261       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1262                                              /*IsPairwiseForm=*/false);
1263     case RK_MinMax:
1264       return getMinMaxReductionCost(
1265           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1266           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1267     case RK_UnsignedMinMax:
1268       return getMinMaxReductionCost(
1269           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1270           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1271     case RK_None:
1272       break;
1273     }
1274 
1275     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1276     case RK_Arithmetic:
1277       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1278                                              /*IsPairwiseForm=*/true);
1279     case RK_MinMax:
1280       return getMinMaxReductionCost(
1281           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1282           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1283     case RK_UnsignedMinMax:
1284       return getMinMaxReductionCost(
1285           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1286           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1287     case RK_None:
1288       break;
1289     }
1290 
1291     return getVectorInstrCost(I->getOpcode(),
1292                                    EEI->getOperand(0)->getType(), Idx);
1293   }
1294   case Instruction::InsertElement: {
1295     const InsertElementInst * IE = cast<InsertElementInst>(I);
1296     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1297     unsigned Idx = -1;
1298     if (CI)
1299       Idx = CI->getZExtValue();
1300     return getVectorInstrCost(I->getOpcode(),
1301                                    IE->getType(), Idx);
1302   }
1303   case Instruction::ExtractValue:
1304     return 0; // Model all ExtractValue nodes as free.
1305   case Instruction::ShuffleVector: {
1306     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1307     Type *Ty = Shuffle->getType();
1308     Type *SrcTy = Shuffle->getOperand(0)->getType();
1309 
1310     // TODO: Identify and add costs for insert subvector, etc.
1311     int SubIndex;
1312     if (Shuffle->isExtractSubvectorMask(SubIndex))
1313       return TTIImpl->getShuffleCost(SK_ExtractSubvector, SrcTy, SubIndex, Ty);
1314 
1315     if (Shuffle->changesLength())
1316       return -1;
1317 
1318     if (Shuffle->isIdentity())
1319       return 0;
1320 
1321     if (Shuffle->isReverse())
1322       return TTIImpl->getShuffleCost(SK_Reverse, Ty, 0, nullptr);
1323 
1324     if (Shuffle->isSelect())
1325       return TTIImpl->getShuffleCost(SK_Select, Ty, 0, nullptr);
1326 
1327     if (Shuffle->isTranspose())
1328       return TTIImpl->getShuffleCost(SK_Transpose, Ty, 0, nullptr);
1329 
1330     if (Shuffle->isZeroEltSplat())
1331       return TTIImpl->getShuffleCost(SK_Broadcast, Ty, 0, nullptr);
1332 
1333     if (Shuffle->isSingleSource())
1334       return TTIImpl->getShuffleCost(SK_PermuteSingleSrc, Ty, 0, nullptr);
1335 
1336     return TTIImpl->getShuffleCost(SK_PermuteTwoSrc, Ty, 0, nullptr);
1337   }
1338   case Instruction::Call:
1339     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1340       SmallVector<Value *, 4> Args(II->arg_operands());
1341 
1342       FastMathFlags FMF;
1343       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1344         FMF = FPMO->getFastMathFlags();
1345 
1346       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
1347                                         Args, FMF);
1348     }
1349     return -1;
1350   default:
1351     // We don't have any information on this instruction.
1352     return -1;
1353   }
1354 }
1355 
1356 TargetTransformInfo::Concept::~Concept() {}
1357 
1358 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1359 
1360 TargetIRAnalysis::TargetIRAnalysis(
1361     std::function<Result(const Function &)> TTICallback)
1362     : TTICallback(std::move(TTICallback)) {}
1363 
1364 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1365                                                FunctionAnalysisManager &) {
1366   return TTICallback(F);
1367 }
1368 
1369 AnalysisKey TargetIRAnalysis::Key;
1370 
1371 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1372   return Result(F.getParent()->getDataLayout());
1373 }
1374 
1375 // Register the basic pass.
1376 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1377                 "Target Transform Information", false, true)
1378 char TargetTransformInfoWrapperPass::ID = 0;
1379 
1380 void TargetTransformInfoWrapperPass::anchor() {}
1381 
1382 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1383     : ImmutablePass(ID) {
1384   initializeTargetTransformInfoWrapperPassPass(
1385       *PassRegistry::getPassRegistry());
1386 }
1387 
1388 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1389     TargetIRAnalysis TIRA)
1390     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1391   initializeTargetTransformInfoWrapperPassPass(
1392       *PassRegistry::getPassRegistry());
1393 }
1394 
1395 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1396   FunctionAnalysisManager DummyFAM;
1397   TTI = TIRA.run(F, DummyFAM);
1398   return *TTI;
1399 }
1400 
1401 ImmutablePass *
1402 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1403   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1404 }
1405