1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/Analysis/TargetTransformInfo.h"
10 #include "llvm/Analysis/CFG.h"
11 #include "llvm/Analysis/LoopIterator.h"
12 #include "llvm/Analysis/TargetTransformInfoImpl.h"
13 #include "llvm/IR/CFG.h"
14 #include "llvm/IR/DataLayout.h"
15 #include "llvm/IR/Dominators.h"
16 #include "llvm/IR/Instruction.h"
17 #include "llvm/IR/Instructions.h"
18 #include "llvm/IR/IntrinsicInst.h"
19 #include "llvm/IR/Module.h"
20 #include "llvm/IR/Operator.h"
21 #include "llvm/IR/PatternMatch.h"
22 #include "llvm/InitializePasses.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include <utility>
26 
27 using namespace llvm;
28 using namespace PatternMatch;
29 
30 #define DEBUG_TYPE "tti"
31 
32 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
33                                      cl::Hidden,
34                                      cl::desc("Recognize reduction patterns."));
35 
36 namespace {
37 /// No-op implementation of the TTI interface using the utility base
38 /// classes.
39 ///
40 /// This is used when no target specific information is available.
41 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
42   explicit NoTTIImpl(const DataLayout &DL)
43       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
44 };
45 } // namespace
46 
47 bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) {
48   // If the loop has irreducible control flow, it can not be converted to
49   // Hardware loop.
50   LoopBlocksRPO RPOT(L);
51   RPOT.perform(&LI);
52   if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
53     return false;
54   return true;
55 }
56 
57 IntrinsicCostAttributes::IntrinsicCostAttributes(Intrinsic::ID Id,
58                                                  const CallBase &CI,
59                                                  unsigned ScalarizationCost)
60     : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
61       ScalarizationCost(ScalarizationCost) {
62 
63   if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
64     FMF = FPMO->getFastMathFlags();
65 
66   Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
67   FunctionType *FTy = CI.getCalledFunction()->getFunctionType();
68   ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
69 }
70 
71 IntrinsicCostAttributes::IntrinsicCostAttributes(Intrinsic::ID Id, Type *RTy,
72                                                  ArrayRef<Type *> Tys,
73                                                  FastMathFlags Flags,
74                                                  const IntrinsicInst *I,
75                                                  unsigned ScalarCost)
76     : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
77   ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
78 }
79 
80 IntrinsicCostAttributes::IntrinsicCostAttributes(Intrinsic::ID Id, Type *Ty,
81                                                  ArrayRef<const Value *> Args)
82     : RetTy(Ty), IID(Id) {
83 
84   Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
85   ParamTys.reserve(Arguments.size());
86   for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
87     ParamTys.push_back(Arguments[Idx]->getType());
88 }
89 
90 IntrinsicCostAttributes::IntrinsicCostAttributes(Intrinsic::ID Id, Type *RTy,
91                                                  ArrayRef<const Value *> Args,
92                                                  ArrayRef<Type *> Tys,
93                                                  FastMathFlags Flags,
94                                                  const IntrinsicInst *I,
95                                                  unsigned ScalarCost)
96     : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
97   ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
98   Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
99 }
100 
101 bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
102                                                LoopInfo &LI, DominatorTree &DT,
103                                                bool ForceNestedLoop,
104                                                bool ForceHardwareLoopPHI) {
105   SmallVector<BasicBlock *, 4> ExitingBlocks;
106   L->getExitingBlocks(ExitingBlocks);
107 
108   for (BasicBlock *BB : ExitingBlocks) {
109     // If we pass the updated counter back through a phi, we need to know
110     // which latch the updated value will be coming from.
111     if (!L->isLoopLatch(BB)) {
112       if (ForceHardwareLoopPHI || CounterInReg)
113         continue;
114     }
115 
116     const SCEV *EC = SE.getExitCount(L, BB);
117     if (isa<SCEVCouldNotCompute>(EC))
118       continue;
119     if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
120       if (ConstEC->getValue()->isZero())
121         continue;
122     } else if (!SE.isLoopInvariant(EC, L))
123       continue;
124 
125     if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
126       continue;
127 
128     // If this exiting block is contained in a nested loop, it is not eligible
129     // for insertion of the branch-and-decrement since the inner loop would
130     // end up messing up the value in the CTR.
131     if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
132       continue;
133 
134     // We now have a loop-invariant count of loop iterations (which is not the
135     // constant zero) for which we know that this loop will not exit via this
136     // existing block.
137 
138     // We need to make sure that this block will run on every loop iteration.
139     // For this to be true, we must dominate all blocks with backedges. Such
140     // blocks are in-loop predecessors to the header block.
141     bool NotAlways = false;
142     for (BasicBlock *Pred : predecessors(L->getHeader())) {
143       if (!L->contains(Pred))
144         continue;
145 
146       if (!DT.dominates(BB, Pred)) {
147         NotAlways = true;
148         break;
149       }
150     }
151 
152     if (NotAlways)
153       continue;
154 
155     // Make sure this blocks ends with a conditional branch.
156     Instruction *TI = BB->getTerminator();
157     if (!TI)
158       continue;
159 
160     if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
161       if (!BI->isConditional())
162         continue;
163 
164       ExitBranch = BI;
165     } else
166       continue;
167 
168     // Note that this block may not be the loop latch block, even if the loop
169     // has a latch block.
170     ExitBlock = BB;
171     TripCount = SE.getAddExpr(EC, SE.getOne(EC->getType()));
172 
173     if (!EC->getType()->isPointerTy() && EC->getType() != CountType)
174       TripCount = SE.getZeroExtendExpr(TripCount, CountType);
175 
176     break;
177   }
178 
179   if (!ExitBlock)
180     return false;
181   return true;
182 }
183 
184 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
185     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
186 
187 TargetTransformInfo::~TargetTransformInfo() {}
188 
189 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
190     : TTIImpl(std::move(Arg.TTIImpl)) {}
191 
192 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
193   TTIImpl = std::move(RHS.TTIImpl);
194   return *this;
195 }
196 
197 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
198   return TTIImpl->getInliningThresholdMultiplier();
199 }
200 
201 unsigned
202 TargetTransformInfo::adjustInliningThreshold(const CallBase *CB) const {
203   return TTIImpl->adjustInliningThreshold(CB);
204 }
205 
206 int TargetTransformInfo::getInlinerVectorBonusPercent() const {
207   return TTIImpl->getInlinerVectorBonusPercent();
208 }
209 
210 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
211                                     ArrayRef<const Value *> Operands,
212                                     TTI::TargetCostKind CostKind) const {
213   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind);
214 }
215 
216 unsigned TargetTransformInfo::getEstimatedNumberOfCaseClusters(
217     const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
218     BlockFrequencyInfo *BFI) const {
219   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
220 }
221 
222 InstructionCost
223 TargetTransformInfo::getUserCost(const User *U,
224                                  ArrayRef<const Value *> Operands,
225                                  enum TargetCostKind CostKind) const {
226   InstructionCost Cost = TTIImpl->getUserCost(U, Operands, CostKind);
227   assert((CostKind == TTI::TCK_RecipThroughput || Cost >= 0) &&
228          "TTI should not produce negative costs!");
229   return Cost;
230 }
231 
232 BranchProbability TargetTransformInfo::getPredictableBranchThreshold() const {
233   return TTIImpl->getPredictableBranchThreshold();
234 }
235 
236 bool TargetTransformInfo::hasBranchDivergence() const {
237   return TTIImpl->hasBranchDivergence();
238 }
239 
240 bool TargetTransformInfo::useGPUDivergenceAnalysis() const {
241   return TTIImpl->useGPUDivergenceAnalysis();
242 }
243 
244 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
245   return TTIImpl->isSourceOfDivergence(V);
246 }
247 
248 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
249   return TTIImpl->isAlwaysUniform(V);
250 }
251 
252 unsigned TargetTransformInfo::getFlatAddressSpace() const {
253   return TTIImpl->getFlatAddressSpace();
254 }
255 
256 bool TargetTransformInfo::collectFlatAddressOperands(
257     SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
258   return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
259 }
260 
261 bool TargetTransformInfo::isNoopAddrSpaceCast(unsigned FromAS,
262                                               unsigned ToAS) const {
263   return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
264 }
265 
266 unsigned TargetTransformInfo::getAssumedAddrSpace(const Value *V) const {
267   return TTIImpl->getAssumedAddrSpace(V);
268 }
269 
270 Value *TargetTransformInfo::rewriteIntrinsicWithAddressSpace(
271     IntrinsicInst *II, Value *OldV, Value *NewV) const {
272   return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
273 }
274 
275 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
276   return TTIImpl->isLoweredToCall(F);
277 }
278 
279 bool TargetTransformInfo::isHardwareLoopProfitable(
280     Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
281     TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
282   return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
283 }
284 
285 bool TargetTransformInfo::preferPredicateOverEpilogue(
286     Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC,
287     TargetLibraryInfo *TLI, DominatorTree *DT,
288     const LoopAccessInfo *LAI) const {
289   return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LAI);
290 }
291 
292 bool TargetTransformInfo::emitGetActiveLaneMask() const {
293   return TTIImpl->emitGetActiveLaneMask();
294 }
295 
296 Optional<Instruction *>
297 TargetTransformInfo::instCombineIntrinsic(InstCombiner &IC,
298                                           IntrinsicInst &II) const {
299   return TTIImpl->instCombineIntrinsic(IC, II);
300 }
301 
302 Optional<Value *> TargetTransformInfo::simplifyDemandedUseBitsIntrinsic(
303     InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
304     bool &KnownBitsComputed) const {
305   return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
306                                                    KnownBitsComputed);
307 }
308 
309 Optional<Value *> TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic(
310     InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
311     APInt &UndefElts2, APInt &UndefElts3,
312     std::function<void(Instruction *, unsigned, APInt, APInt &)>
313         SimplifyAndSetOp) const {
314   return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
315       IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
316       SimplifyAndSetOp);
317 }
318 
319 void TargetTransformInfo::getUnrollingPreferences(
320     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
321   return TTIImpl->getUnrollingPreferences(L, SE, UP);
322 }
323 
324 void TargetTransformInfo::getPeelingPreferences(Loop *L, ScalarEvolution &SE,
325                                                 PeelingPreferences &PP) const {
326   return TTIImpl->getPeelingPreferences(L, SE, PP);
327 }
328 
329 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
330   return TTIImpl->isLegalAddImmediate(Imm);
331 }
332 
333 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
334   return TTIImpl->isLegalICmpImmediate(Imm);
335 }
336 
337 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
338                                                 int64_t BaseOffset,
339                                                 bool HasBaseReg, int64_t Scale,
340                                                 unsigned AddrSpace,
341                                                 Instruction *I) const {
342   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
343                                         Scale, AddrSpace, I);
344 }
345 
346 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
347   return TTIImpl->isLSRCostLess(C1, C2);
348 }
349 
350 bool TargetTransformInfo::isNumRegsMajorCostOfLSR() const {
351   return TTIImpl->isNumRegsMajorCostOfLSR();
352 }
353 
354 bool TargetTransformInfo::isProfitableLSRChainElement(Instruction *I) const {
355   return TTIImpl->isProfitableLSRChainElement(I);
356 }
357 
358 bool TargetTransformInfo::canMacroFuseCmp() const {
359   return TTIImpl->canMacroFuseCmp();
360 }
361 
362 bool TargetTransformInfo::canSaveCmp(Loop *L, BranchInst **BI,
363                                      ScalarEvolution *SE, LoopInfo *LI,
364                                      DominatorTree *DT, AssumptionCache *AC,
365                                      TargetLibraryInfo *LibInfo) const {
366   return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
367 }
368 
369 TTI::AddressingModeKind
370 TargetTransformInfo::getPreferredAddressingMode(const Loop *L,
371                                                 ScalarEvolution *SE) const {
372   return TTIImpl->getPreferredAddressingMode(L, SE);
373 }
374 
375 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType,
376                                              Align Alignment) const {
377   return TTIImpl->isLegalMaskedStore(DataType, Alignment);
378 }
379 
380 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType,
381                                             Align Alignment) const {
382   return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
383 }
384 
385 bool TargetTransformInfo::isLegalNTStore(Type *DataType,
386                                          Align Alignment) const {
387   return TTIImpl->isLegalNTStore(DataType, Alignment);
388 }
389 
390 bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
391   return TTIImpl->isLegalNTLoad(DataType, Alignment);
392 }
393 
394 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType,
395                                               Align Alignment) const {
396   return TTIImpl->isLegalMaskedGather(DataType, Alignment);
397 }
398 
399 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType,
400                                                Align Alignment) const {
401   return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
402 }
403 
404 bool TargetTransformInfo::isLegalMaskedCompressStore(Type *DataType) const {
405   return TTIImpl->isLegalMaskedCompressStore(DataType);
406 }
407 
408 bool TargetTransformInfo::isLegalMaskedExpandLoad(Type *DataType) const {
409   return TTIImpl->isLegalMaskedExpandLoad(DataType);
410 }
411 
412 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
413   return TTIImpl->hasDivRemOp(DataType, IsSigned);
414 }
415 
416 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
417                                              unsigned AddrSpace) const {
418   return TTIImpl->hasVolatileVariant(I, AddrSpace);
419 }
420 
421 bool TargetTransformInfo::prefersVectorizedAddressing() const {
422   return TTIImpl->prefersVectorizedAddressing();
423 }
424 
425 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
426                                               int64_t BaseOffset,
427                                               bool HasBaseReg, int64_t Scale,
428                                               unsigned AddrSpace) const {
429   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
430                                            Scale, AddrSpace);
431   assert(Cost >= 0 && "TTI should not produce negative costs!");
432   return Cost;
433 }
434 
435 bool TargetTransformInfo::LSRWithInstrQueries() const {
436   return TTIImpl->LSRWithInstrQueries();
437 }
438 
439 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
440   return TTIImpl->isTruncateFree(Ty1, Ty2);
441 }
442 
443 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
444   return TTIImpl->isProfitableToHoist(I);
445 }
446 
447 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
448 
449 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
450   return TTIImpl->isTypeLegal(Ty);
451 }
452 
453 unsigned TargetTransformInfo::getRegUsageForType(Type *Ty) const {
454   return TTIImpl->getRegUsageForType(Ty);
455 }
456 
457 bool TargetTransformInfo::shouldBuildLookupTables() const {
458   return TTIImpl->shouldBuildLookupTables();
459 }
460 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(
461     Constant *C) const {
462   return TTIImpl->shouldBuildLookupTablesForConstant(C);
463 }
464 
465 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
466   return TTIImpl->useColdCCForColdCall(F);
467 }
468 
469 unsigned
470 TargetTransformInfo::getScalarizationOverhead(VectorType *Ty,
471                                               const APInt &DemandedElts,
472                                               bool Insert, bool Extract) const {
473   return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
474 }
475 
476 unsigned TargetTransformInfo::getOperandsScalarizationOverhead(
477     ArrayRef<const Value *> Args, ArrayRef<Type *> Tys) const {
478   return TTIImpl->getOperandsScalarizationOverhead(Args, Tys);
479 }
480 
481 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
482   return TTIImpl->supportsEfficientVectorElementLoadStore();
483 }
484 
485 bool TargetTransformInfo::enableAggressiveInterleaving(
486     bool LoopHasReductions) const {
487   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
488 }
489 
490 TargetTransformInfo::MemCmpExpansionOptions
491 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
492   return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
493 }
494 
495 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
496   return TTIImpl->enableInterleavedAccessVectorization();
497 }
498 
499 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const {
500   return TTIImpl->enableMaskedInterleavedAccessVectorization();
501 }
502 
503 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
504   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
505 }
506 
507 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
508                                                          unsigned BitWidth,
509                                                          unsigned AddressSpace,
510                                                          Align Alignment,
511                                                          bool *Fast) const {
512   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
513                                                  AddressSpace, Alignment, Fast);
514 }
515 
516 TargetTransformInfo::PopcntSupportKind
517 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
518   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
519 }
520 
521 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
522   return TTIImpl->haveFastSqrt(Ty);
523 }
524 
525 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
526   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
527 }
528 
529 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
530   int Cost = TTIImpl->getFPOpCost(Ty);
531   assert(Cost >= 0 && "TTI should not produce negative costs!");
532   return Cost;
533 }
534 
535 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
536                                                const APInt &Imm,
537                                                Type *Ty) const {
538   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
539   assert(Cost >= 0 && "TTI should not produce negative costs!");
540   return Cost;
541 }
542 
543 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty,
544                                        TTI::TargetCostKind CostKind) const {
545   int Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
546   assert(Cost >= 0 && "TTI should not produce negative costs!");
547   return Cost;
548 }
549 
550 int TargetTransformInfo::getIntImmCostInst(unsigned Opcode, unsigned Idx,
551                                            const APInt &Imm, Type *Ty,
552                                            TTI::TargetCostKind CostKind,
553                                            Instruction *Inst) const {
554   int Cost = TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
555   assert(Cost >= 0 && "TTI should not produce negative costs!");
556   return Cost;
557 }
558 
559 int
560 TargetTransformInfo::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
561                                          const APInt &Imm, Type *Ty,
562                                          TTI::TargetCostKind CostKind) const {
563   int Cost = TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
564   assert(Cost >= 0 && "TTI should not produce negative costs!");
565   return Cost;
566 }
567 
568 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
569   return TTIImpl->getNumberOfRegisters(ClassID);
570 }
571 
572 unsigned TargetTransformInfo::getRegisterClassForType(bool Vector,
573                                                       Type *Ty) const {
574   return TTIImpl->getRegisterClassForType(Vector, Ty);
575 }
576 
577 const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
578   return TTIImpl->getRegisterClassName(ClassID);
579 }
580 
581 TypeSize TargetTransformInfo::getRegisterBitWidth(
582     TargetTransformInfo::RegisterKind K) const {
583   return TTIImpl->getRegisterBitWidth(K);
584 }
585 
586 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
587   return TTIImpl->getMinVectorRegisterBitWidth();
588 }
589 
590 Optional<unsigned> TargetTransformInfo::getMaxVScale() const {
591   return TTIImpl->getMaxVScale();
592 }
593 
594 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
595   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
596 }
597 
598 ElementCount TargetTransformInfo::getMinimumVF(unsigned ElemWidth,
599                                                bool IsScalable) const {
600   return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
601 }
602 
603 unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
604                                            unsigned Opcode) const {
605   return TTIImpl->getMaximumVF(ElemWidth, Opcode);
606 }
607 
608 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
609     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
610   return TTIImpl->shouldConsiderAddressTypePromotion(
611       I, AllowPromotionWithoutCommonHeader);
612 }
613 
614 unsigned TargetTransformInfo::getCacheLineSize() const {
615   return TTIImpl->getCacheLineSize();
616 }
617 
618 llvm::Optional<unsigned>
619 TargetTransformInfo::getCacheSize(CacheLevel Level) const {
620   return TTIImpl->getCacheSize(Level);
621 }
622 
623 llvm::Optional<unsigned>
624 TargetTransformInfo::getCacheAssociativity(CacheLevel Level) const {
625   return TTIImpl->getCacheAssociativity(Level);
626 }
627 
628 unsigned TargetTransformInfo::getPrefetchDistance() const {
629   return TTIImpl->getPrefetchDistance();
630 }
631 
632 unsigned TargetTransformInfo::getMinPrefetchStride(
633     unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
634     unsigned NumPrefetches, bool HasCall) const {
635   return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
636                                        NumPrefetches, HasCall);
637 }
638 
639 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
640   return TTIImpl->getMaxPrefetchIterationsAhead();
641 }
642 
643 bool TargetTransformInfo::enableWritePrefetching() const {
644   return TTIImpl->enableWritePrefetching();
645 }
646 
647 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
648   return TTIImpl->getMaxInterleaveFactor(VF);
649 }
650 
651 TargetTransformInfo::OperandValueKind
652 TargetTransformInfo::getOperandInfo(const Value *V,
653                                     OperandValueProperties &OpProps) {
654   OperandValueKind OpInfo = OK_AnyValue;
655   OpProps = OP_None;
656 
657   if (const auto *CI = dyn_cast<ConstantInt>(V)) {
658     if (CI->getValue().isPowerOf2())
659       OpProps = OP_PowerOf2;
660     return OK_UniformConstantValue;
661   }
662 
663   // A broadcast shuffle creates a uniform value.
664   // TODO: Add support for non-zero index broadcasts.
665   // TODO: Add support for different source vector width.
666   if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
667     if (ShuffleInst->isZeroEltSplat())
668       OpInfo = OK_UniformValue;
669 
670   const Value *Splat = getSplatValue(V);
671 
672   // Check for a splat of a constant or for a non uniform vector of constants
673   // and check if the constant(s) are all powers of two.
674   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
675     OpInfo = OK_NonUniformConstantValue;
676     if (Splat) {
677       OpInfo = OK_UniformConstantValue;
678       if (auto *CI = dyn_cast<ConstantInt>(Splat))
679         if (CI->getValue().isPowerOf2())
680           OpProps = OP_PowerOf2;
681     } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
682       OpProps = OP_PowerOf2;
683       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
684         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
685           if (CI->getValue().isPowerOf2())
686             continue;
687         OpProps = OP_None;
688         break;
689       }
690     }
691   }
692 
693   // Check for a splat of a uniform value. This is not loop aware, so return
694   // true only for the obviously uniform cases (argument, globalvalue)
695   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
696     OpInfo = OK_UniformValue;
697 
698   return OpInfo;
699 }
700 
701 int TargetTransformInfo::getArithmeticInstrCost(
702     unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
703     OperandValueKind Opd1Info,
704     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
705     OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
706     const Instruction *CxtI) const {
707   int Cost = TTIImpl->getArithmeticInstrCost(
708       Opcode, Ty, CostKind, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo,
709       Args, CxtI);
710   assert(Cost >= 0 && "TTI should not produce negative costs!");
711   return Cost;
712 }
713 
714 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, VectorType *Ty,
715                                         ArrayRef<int> Mask, int Index,
716                                         VectorType *SubTp) const {
717   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Mask, Index, SubTp);
718   assert(Cost >= 0 && "TTI should not produce negative costs!");
719   return Cost;
720 }
721 
722 TTI::CastContextHint
723 TargetTransformInfo::getCastContextHint(const Instruction *I) {
724   if (!I)
725     return CastContextHint::None;
726 
727   auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
728                              unsigned GatScatOp) {
729     const Instruction *I = dyn_cast<Instruction>(V);
730     if (!I)
731       return CastContextHint::None;
732 
733     if (I->getOpcode() == LdStOp)
734       return CastContextHint::Normal;
735 
736     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
737       if (II->getIntrinsicID() == MaskedOp)
738         return TTI::CastContextHint::Masked;
739       if (II->getIntrinsicID() == GatScatOp)
740         return TTI::CastContextHint::GatherScatter;
741     }
742 
743     return TTI::CastContextHint::None;
744   };
745 
746   switch (I->getOpcode()) {
747   case Instruction::ZExt:
748   case Instruction::SExt:
749   case Instruction::FPExt:
750     return getLoadStoreKind(I->getOperand(0), Instruction::Load,
751                             Intrinsic::masked_load, Intrinsic::masked_gather);
752   case Instruction::Trunc:
753   case Instruction::FPTrunc:
754     if (I->hasOneUse())
755       return getLoadStoreKind(*I->user_begin(), Instruction::Store,
756                               Intrinsic::masked_store,
757                               Intrinsic::masked_scatter);
758     break;
759   default:
760     return CastContextHint::None;
761   }
762 
763   return TTI::CastContextHint::None;
764 }
765 
766 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
767                                           CastContextHint CCH,
768                                           TTI::TargetCostKind CostKind,
769                                           const Instruction *I) const {
770   assert((I == nullptr || I->getOpcode() == Opcode) &&
771          "Opcode should reflect passed instruction.");
772   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
773   assert(Cost >= 0 && "TTI should not produce negative costs!");
774   return Cost;
775 }
776 
777 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
778                                                   VectorType *VecTy,
779                                                   unsigned Index) const {
780   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
781   assert(Cost >= 0 && "TTI should not produce negative costs!");
782   return Cost;
783 }
784 
785 int TargetTransformInfo::getCFInstrCost(unsigned Opcode,
786                                         TTI::TargetCostKind CostKind,
787                                         const Instruction *I) const {
788   assert((I == nullptr || I->getOpcode() == Opcode) &&
789          "Opcode should reflect passed instruction.");
790   int Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
791   assert(Cost >= 0 && "TTI should not produce negative costs!");
792   return Cost;
793 }
794 
795 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
796                                             Type *CondTy,
797                                             CmpInst::Predicate VecPred,
798                                             TTI::TargetCostKind CostKind,
799                                             const Instruction *I) const {
800   assert((I == nullptr || I->getOpcode() == Opcode) &&
801          "Opcode should reflect passed instruction.");
802   int Cost =
803       TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
804   assert(Cost >= 0 && "TTI should not produce negative costs!");
805   return Cost;
806 }
807 
808 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
809                                             unsigned Index) const {
810   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
811   assert(Cost >= 0 && "TTI should not produce negative costs!");
812   return Cost;
813 }
814 
815 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
816                                          Align Alignment, unsigned AddressSpace,
817                                          TTI::TargetCostKind CostKind,
818                                          const Instruction *I) const {
819   assert((I == nullptr || I->getOpcode() == Opcode) &&
820          "Opcode should reflect passed instruction.");
821   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
822                                       CostKind, I);
823   assert(Cost >= 0 && "TTI should not produce negative costs!");
824   return Cost;
825 }
826 
827 int TargetTransformInfo::getMaskedMemoryOpCost(
828     unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
829     TTI::TargetCostKind CostKind) const {
830   int Cost =
831       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
832                                      CostKind);
833   assert(Cost >= 0 && "TTI should not produce negative costs!");
834   return Cost;
835 }
836 
837 int TargetTransformInfo::getGatherScatterOpCost(
838     unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
839     Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
840   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
841                                              Alignment, CostKind, I);
842   assert(Cost >= 0 && "TTI should not produce negative costs!");
843   return Cost;
844 }
845 
846 int TargetTransformInfo::getInterleavedMemoryOpCost(
847     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
848     Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
849     bool UseMaskForCond, bool UseMaskForGaps) const {
850   int Cost = TTIImpl->getInterleavedMemoryOpCost(
851       Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
852       UseMaskForCond, UseMaskForGaps);
853   assert(Cost >= 0 && "TTI should not produce negative costs!");
854   return Cost;
855 }
856 
857 InstructionCost
858 TargetTransformInfo::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
859                                            TTI::TargetCostKind CostKind) const {
860   InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
861   assert(Cost >= 0 && "TTI should not produce negative costs!");
862   return Cost;
863 }
864 
865 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
866                                           ArrayRef<Type *> Tys,
867                                           TTI::TargetCostKind CostKind) const {
868   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
869   assert(Cost >= 0 && "TTI should not produce negative costs!");
870   return Cost;
871 }
872 
873 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
874   return TTIImpl->getNumberOfParts(Tp);
875 }
876 
877 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
878                                                    ScalarEvolution *SE,
879                                                    const SCEV *Ptr) const {
880   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
881   assert(Cost >= 0 && "TTI should not produce negative costs!");
882   return Cost;
883 }
884 
885 int TargetTransformInfo::getMemcpyCost(const Instruction *I) const {
886   int Cost = TTIImpl->getMemcpyCost(I);
887   assert(Cost >= 0 && "TTI should not produce negative costs!");
888   return Cost;
889 }
890 
891 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode,
892                                                     VectorType *Ty,
893                                                     bool IsPairwiseForm,
894                                                     TTI::TargetCostKind CostKind) const {
895   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm,
896                                                  CostKind);
897   assert(Cost >= 0 && "TTI should not produce negative costs!");
898   return Cost;
899 }
900 
901 int TargetTransformInfo::getMinMaxReductionCost(
902     VectorType *Ty, VectorType *CondTy, bool IsPairwiseForm, bool IsUnsigned,
903     TTI::TargetCostKind CostKind) const {
904   int Cost =
905       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned,
906                                       CostKind);
907   assert(Cost >= 0 && "TTI should not produce negative costs!");
908   return Cost;
909 }
910 
911 InstructionCost TargetTransformInfo::getExtendedAddReductionCost(
912     bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty,
913     TTI::TargetCostKind CostKind) const {
914   return TTIImpl->getExtendedAddReductionCost(IsMLA, IsUnsigned, ResTy, Ty,
915                                               CostKind);
916 }
917 
918 unsigned
919 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
920   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
921 }
922 
923 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
924                                              MemIntrinsicInfo &Info) const {
925   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
926 }
927 
928 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
929   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
930 }
931 
932 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
933     IntrinsicInst *Inst, Type *ExpectedType) const {
934   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
935 }
936 
937 Type *TargetTransformInfo::getMemcpyLoopLoweringType(
938     LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
939     unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const {
940   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
941                                             DestAddrSpace, SrcAlign, DestAlign);
942 }
943 
944 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
945     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
946     unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
947     unsigned SrcAlign, unsigned DestAlign) const {
948   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
949                                              SrcAddrSpace, DestAddrSpace,
950                                              SrcAlign, DestAlign);
951 }
952 
953 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
954                                               const Function *Callee) const {
955   return TTIImpl->areInlineCompatible(Caller, Callee);
956 }
957 
958 bool TargetTransformInfo::areFunctionArgsABICompatible(
959     const Function *Caller, const Function *Callee,
960     SmallPtrSetImpl<Argument *> &Args) const {
961   return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
962 }
963 
964 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
965                                              Type *Ty) const {
966   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
967 }
968 
969 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
970                                               Type *Ty) const {
971   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
972 }
973 
974 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
975   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
976 }
977 
978 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
979   return TTIImpl->isLegalToVectorizeLoad(LI);
980 }
981 
982 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
983   return TTIImpl->isLegalToVectorizeStore(SI);
984 }
985 
986 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
987     unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
988   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
989                                               AddrSpace);
990 }
991 
992 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
993     unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
994   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
995                                                AddrSpace);
996 }
997 
998 bool TargetTransformInfo::isLegalToVectorizeReduction(
999     RecurrenceDescriptor RdxDesc, ElementCount VF) const {
1000   return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1001 }
1002 
1003 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
1004                                                   unsigned LoadSize,
1005                                                   unsigned ChainSizeInBytes,
1006                                                   VectorType *VecTy) const {
1007   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1008 }
1009 
1010 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
1011                                                    unsigned StoreSize,
1012                                                    unsigned ChainSizeInBytes,
1013                                                    VectorType *VecTy) const {
1014   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1015 }
1016 
1017 bool TargetTransformInfo::preferInLoopReduction(unsigned Opcode, Type *Ty,
1018                                                 ReductionFlags Flags) const {
1019   return TTIImpl->preferInLoopReduction(Opcode, Ty, Flags);
1020 }
1021 
1022 bool TargetTransformInfo::preferPredicatedReductionSelect(
1023     unsigned Opcode, Type *Ty, ReductionFlags Flags) const {
1024   return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags);
1025 }
1026 
1027 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
1028   return TTIImpl->shouldExpandReduction(II);
1029 }
1030 
1031 unsigned TargetTransformInfo::getGISelRematGlobalCost() const {
1032   return TTIImpl->getGISelRematGlobalCost();
1033 }
1034 
1035 bool TargetTransformInfo::supportsScalableVectors() const {
1036   return TTIImpl->supportsScalableVectors();
1037 }
1038 
1039 InstructionCost
1040 TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
1041   return TTIImpl->getInstructionLatency(I);
1042 }
1043 
1044 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
1045                                      unsigned Level) {
1046   // We don't need a shuffle if we just want to have element 0 in position 0 of
1047   // the vector.
1048   if (!SI && Level == 0 && IsLeft)
1049     return true;
1050   else if (!SI)
1051     return false;
1052 
1053   SmallVector<int, 32> Mask(
1054       cast<FixedVectorType>(SI->getType())->getNumElements(), -1);
1055 
1056   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
1057   // we look at the left or right side.
1058   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
1059     Mask[i] = val;
1060 
1061   ArrayRef<int> ActualMask = SI->getShuffleMask();
1062   return Mask == ActualMask;
1063 }
1064 
1065 static Optional<TTI::ReductionData> getReductionData(Instruction *I) {
1066   Value *L, *R;
1067   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
1068     return TTI::ReductionData(TTI::RK_Arithmetic, I->getOpcode(), L, R);
1069   if (auto *SI = dyn_cast<SelectInst>(I)) {
1070     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
1071         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
1072         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
1073         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
1074         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
1075         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
1076       auto *CI = cast<CmpInst>(SI->getCondition());
1077       return TTI::ReductionData(TTI::RK_MinMax, CI->getOpcode(), L, R);
1078     }
1079     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
1080         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
1081       auto *CI = cast<CmpInst>(SI->getCondition());
1082       return TTI::ReductionData(TTI::RK_UnsignedMinMax, CI->getOpcode(), L, R);
1083     }
1084   }
1085   return llvm::None;
1086 }
1087 
1088 static TTI::ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
1089                                                         unsigned Level,
1090                                                         unsigned NumLevels) {
1091   // Match one level of pairwise operations.
1092   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
1093   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
1094   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
1095   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
1096   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
1097   if (!I)
1098     return TTI::RK_None;
1099 
1100   assert(I->getType()->isVectorTy() && "Expecting a vector type");
1101 
1102   Optional<TTI::ReductionData> RD = getReductionData(I);
1103   if (!RD)
1104     return TTI::RK_None;
1105 
1106   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
1107   if (!LS && Level)
1108     return TTI::RK_None;
1109   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
1110   if (!RS && Level)
1111     return TTI::RK_None;
1112 
1113   // On level 0 we can omit one shufflevector instruction.
1114   if (!Level && !RS && !LS)
1115     return TTI::RK_None;
1116 
1117   // Shuffle inputs must match.
1118   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
1119   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
1120   Value *NextLevelOp = nullptr;
1121   if (NextLevelOpR && NextLevelOpL) {
1122     // If we have two shuffles their operands must match.
1123     if (NextLevelOpL != NextLevelOpR)
1124       return TTI::RK_None;
1125 
1126     NextLevelOp = NextLevelOpL;
1127   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
1128     // On the first level we can omit the shufflevector <0, undef,...>. So the
1129     // input to the other shufflevector <1, undef> must match with one of the
1130     // inputs to the current binary operation.
1131     // Example:
1132     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
1133     //  %BinOp        = fadd          %NextLevelOpL, %R
1134     if (NextLevelOpL && NextLevelOpL != RD->RHS)
1135       return TTI::RK_None;
1136     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
1137       return TTI::RK_None;
1138 
1139     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
1140   } else
1141     return TTI::RK_None;
1142 
1143   // Check that the next levels binary operation exists and matches with the
1144   // current one.
1145   if (Level + 1 != NumLevels) {
1146     if (!isa<Instruction>(NextLevelOp))
1147       return TTI::RK_None;
1148     Optional<TTI::ReductionData> NextLevelRD =
1149         getReductionData(cast<Instruction>(NextLevelOp));
1150     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
1151       return TTI::RK_None;
1152   }
1153 
1154   // Shuffle mask for pairwise operation must match.
1155   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
1156     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
1157       return TTI::RK_None;
1158   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
1159     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
1160       return TTI::RK_None;
1161   } else {
1162     return TTI::RK_None;
1163   }
1164 
1165   if (++Level == NumLevels)
1166     return RD->Kind;
1167 
1168   // Match next level.
1169   return matchPairwiseReductionAtLevel(dyn_cast<Instruction>(NextLevelOp), Level,
1170                                        NumLevels);
1171 }
1172 
1173 TTI::ReductionKind TTI::matchPairwiseReduction(
1174   const ExtractElementInst *ReduxRoot, unsigned &Opcode, VectorType *&Ty) {
1175   if (!EnableReduxCost)
1176     return TTI::RK_None;
1177 
1178   // Need to extract the first element.
1179   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1180   unsigned Idx = ~0u;
1181   if (CI)
1182     Idx = CI->getZExtValue();
1183   if (Idx != 0)
1184     return TTI::RK_None;
1185 
1186   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1187   if (!RdxStart)
1188     return TTI::RK_None;
1189   Optional<TTI::ReductionData> RD = getReductionData(RdxStart);
1190   if (!RD)
1191     return TTI::RK_None;
1192 
1193   auto *VecTy = cast<FixedVectorType>(RdxStart->getType());
1194   unsigned NumVecElems = VecTy->getNumElements();
1195   if (!isPowerOf2_32(NumVecElems))
1196     return TTI::RK_None;
1197 
1198   // We look for a sequence of shuffle,shuffle,add triples like the following
1199   // that builds a pairwise reduction tree.
1200   //
1201   //  (X0, X1, X2, X3)
1202   //   (X0 + X1, X2 + X3, undef, undef)
1203   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
1204   //
1205   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
1206   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
1207   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
1208   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
1209   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
1210   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1211   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
1212   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1213   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1214   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
1215   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1216   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
1217       TTI::RK_None)
1218     return TTI::RK_None;
1219 
1220   Opcode = RD->Opcode;
1221   Ty = VecTy;
1222 
1223   return RD->Kind;
1224 }
1225 
1226 static std::pair<Value *, ShuffleVectorInst *>
1227 getShuffleAndOtherOprd(Value *L, Value *R) {
1228   ShuffleVectorInst *S = nullptr;
1229 
1230   if ((S = dyn_cast<ShuffleVectorInst>(L)))
1231     return std::make_pair(R, S);
1232 
1233   S = dyn_cast<ShuffleVectorInst>(R);
1234   return std::make_pair(L, S);
1235 }
1236 
1237 TTI::ReductionKind TTI::matchVectorSplittingReduction(
1238   const ExtractElementInst *ReduxRoot, unsigned &Opcode, VectorType *&Ty) {
1239 
1240   if (!EnableReduxCost)
1241     return TTI::RK_None;
1242 
1243   // Need to extract the first element.
1244   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1245   unsigned Idx = ~0u;
1246   if (CI)
1247     Idx = CI->getZExtValue();
1248   if (Idx != 0)
1249     return TTI::RK_None;
1250 
1251   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1252   if (!RdxStart)
1253     return TTI::RK_None;
1254   Optional<TTI::ReductionData> RD = getReductionData(RdxStart);
1255   if (!RD)
1256     return TTI::RK_None;
1257 
1258   auto *VecTy = cast<FixedVectorType>(ReduxRoot->getOperand(0)->getType());
1259   unsigned NumVecElems = VecTy->getNumElements();
1260   if (!isPowerOf2_32(NumVecElems))
1261     return TTI::RK_None;
1262 
1263   // We look for a sequence of shuffles and adds like the following matching one
1264   // fadd, shuffle vector pair at a time.
1265   //
1266   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
1267   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
1268   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
1269   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
1270   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1271   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
1272   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1273 
1274   unsigned MaskStart = 1;
1275   Instruction *RdxOp = RdxStart;
1276   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
1277   unsigned NumVecElemsRemain = NumVecElems;
1278   while (NumVecElemsRemain - 1) {
1279     // Check for the right reduction operation.
1280     if (!RdxOp)
1281       return TTI::RK_None;
1282     Optional<TTI::ReductionData> RDLevel = getReductionData(RdxOp);
1283     if (!RDLevel || !RDLevel->hasSameData(*RD))
1284       return TTI::RK_None;
1285 
1286     Value *NextRdxOp;
1287     ShuffleVectorInst *Shuffle;
1288     std::tie(NextRdxOp, Shuffle) =
1289         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
1290 
1291     // Check the current reduction operation and the shuffle use the same value.
1292     if (Shuffle == nullptr)
1293       return TTI::RK_None;
1294     if (Shuffle->getOperand(0) != NextRdxOp)
1295       return TTI::RK_None;
1296 
1297     // Check that shuffle masks matches.
1298     for (unsigned j = 0; j != MaskStart; ++j)
1299       ShuffleMask[j] = MaskStart + j;
1300     // Fill the rest of the mask with -1 for undef.
1301     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
1302 
1303     ArrayRef<int> Mask = Shuffle->getShuffleMask();
1304     if (ShuffleMask != Mask)
1305       return TTI::RK_None;
1306 
1307     RdxOp = dyn_cast<Instruction>(NextRdxOp);
1308     NumVecElemsRemain /= 2;
1309     MaskStart *= 2;
1310   }
1311 
1312   Opcode = RD->Opcode;
1313   Ty = VecTy;
1314   return RD->Kind;
1315 }
1316 
1317 TTI::ReductionKind
1318 TTI::matchVectorReduction(const ExtractElementInst *Root, unsigned &Opcode,
1319                           VectorType *&Ty, bool &IsPairwise) {
1320   TTI::ReductionKind RdxKind = matchVectorSplittingReduction(Root, Opcode, Ty);
1321   if (RdxKind != TTI::ReductionKind::RK_None) {
1322     IsPairwise = false;
1323     return RdxKind;
1324   }
1325   IsPairwise = true;
1326   return matchPairwiseReduction(Root, Opcode, Ty);
1327 }
1328 
1329 InstructionCost
1330 TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1331   TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput;
1332 
1333   switch (I->getOpcode()) {
1334   case Instruction::GetElementPtr:
1335   case Instruction::Ret:
1336   case Instruction::PHI:
1337   case Instruction::Br:
1338   case Instruction::Add:
1339   case Instruction::FAdd:
1340   case Instruction::Sub:
1341   case Instruction::FSub:
1342   case Instruction::Mul:
1343   case Instruction::FMul:
1344   case Instruction::UDiv:
1345   case Instruction::SDiv:
1346   case Instruction::FDiv:
1347   case Instruction::URem:
1348   case Instruction::SRem:
1349   case Instruction::FRem:
1350   case Instruction::Shl:
1351   case Instruction::LShr:
1352   case Instruction::AShr:
1353   case Instruction::And:
1354   case Instruction::Or:
1355   case Instruction::Xor:
1356   case Instruction::FNeg:
1357   case Instruction::Select:
1358   case Instruction::ICmp:
1359   case Instruction::FCmp:
1360   case Instruction::Store:
1361   case Instruction::Load:
1362   case Instruction::ZExt:
1363   case Instruction::SExt:
1364   case Instruction::FPToUI:
1365   case Instruction::FPToSI:
1366   case Instruction::FPExt:
1367   case Instruction::PtrToInt:
1368   case Instruction::IntToPtr:
1369   case Instruction::SIToFP:
1370   case Instruction::UIToFP:
1371   case Instruction::Trunc:
1372   case Instruction::FPTrunc:
1373   case Instruction::BitCast:
1374   case Instruction::AddrSpaceCast:
1375   case Instruction::ExtractElement:
1376   case Instruction::InsertElement:
1377   case Instruction::ExtractValue:
1378   case Instruction::ShuffleVector:
1379   case Instruction::Call:
1380   case Instruction::Switch:
1381     return getUserCost(I, CostKind);
1382   default:
1383     // We don't have any information on this instruction.
1384     return -1;
1385   }
1386 }
1387 
1388 TargetTransformInfo::Concept::~Concept() {}
1389 
1390 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1391 
1392 TargetIRAnalysis::TargetIRAnalysis(
1393     std::function<Result(const Function &)> TTICallback)
1394     : TTICallback(std::move(TTICallback)) {}
1395 
1396 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1397                                                FunctionAnalysisManager &) {
1398   return TTICallback(F);
1399 }
1400 
1401 AnalysisKey TargetIRAnalysis::Key;
1402 
1403 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1404   return Result(F.getParent()->getDataLayout());
1405 }
1406 
1407 // Register the basic pass.
1408 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1409                 "Target Transform Information", false, true)
1410 char TargetTransformInfoWrapperPass::ID = 0;
1411 
1412 void TargetTransformInfoWrapperPass::anchor() {}
1413 
1414 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1415     : ImmutablePass(ID) {
1416   initializeTargetTransformInfoWrapperPassPass(
1417       *PassRegistry::getPassRegistry());
1418 }
1419 
1420 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1421     TargetIRAnalysis TIRA)
1422     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1423   initializeTargetTransformInfoWrapperPassPass(
1424       *PassRegistry::getPassRegistry());
1425 }
1426 
1427 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1428   FunctionAnalysisManager DummyFAM;
1429   TTI = TIRA.run(F, DummyFAM);
1430   return *TTI;
1431 }
1432 
1433 ImmutablePass *
1434 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1435   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1436 }
1437