1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/Analysis/TargetTransformInfo.h"
10 #include "llvm/Analysis/CFG.h"
11 #include "llvm/Analysis/LoopIterator.h"
12 #include "llvm/Analysis/TargetTransformInfoImpl.h"
13 #include "llvm/IR/CFG.h"
14 #include "llvm/IR/CallSite.h"
15 #include "llvm/IR/DataLayout.h"
16 #include "llvm/IR/Instruction.h"
17 #include "llvm/IR/Instructions.h"
18 #include "llvm/IR/IntrinsicInst.h"
19 #include "llvm/IR/Module.h"
20 #include "llvm/IR/Operator.h"
21 #include "llvm/IR/PatternMatch.h"
22 #include "llvm/InitializePasses.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include <utility>
26 
27 using namespace llvm;
28 using namespace PatternMatch;
29 
30 #define DEBUG_TYPE "tti"
31 
32 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
33                                      cl::Hidden,
34                                      cl::desc("Recognize reduction patterns."));
35 
36 namespace {
37 /// No-op implementation of the TTI interface using the utility base
38 /// classes.
39 ///
40 /// This is used when no target specific information is available.
41 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
42   explicit NoTTIImpl(const DataLayout &DL)
43       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
44 };
45 } // namespace
46 
47 bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) {
48   // If the loop has irreducible control flow, it can not be converted to
49   // Hardware loop.
50   LoopBlocksRPO RPOT(L);
51   RPOT.perform(&LI);
52   if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
53     return false;
54   return true;
55 }
56 
57 bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
58                                                LoopInfo &LI, DominatorTree &DT,
59                                                bool ForceNestedLoop,
60                                                bool ForceHardwareLoopPHI) {
61   SmallVector<BasicBlock *, 4> ExitingBlocks;
62   L->getExitingBlocks(ExitingBlocks);
63 
64   for (BasicBlock *BB : ExitingBlocks) {
65     // If we pass the updated counter back through a phi, we need to know
66     // which latch the updated value will be coming from.
67     if (!L->isLoopLatch(BB)) {
68       if (ForceHardwareLoopPHI || CounterInReg)
69         continue;
70     }
71 
72     const SCEV *EC = SE.getExitCount(L, BB);
73     if (isa<SCEVCouldNotCompute>(EC))
74       continue;
75     if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
76       if (ConstEC->getValue()->isZero())
77         continue;
78     } else if (!SE.isLoopInvariant(EC, L))
79       continue;
80 
81     if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
82       continue;
83 
84     // If this exiting block is contained in a nested loop, it is not eligible
85     // for insertion of the branch-and-decrement since the inner loop would
86     // end up messing up the value in the CTR.
87     if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
88       continue;
89 
90     // We now have a loop-invariant count of loop iterations (which is not the
91     // constant zero) for which we know that this loop will not exit via this
92     // existing block.
93 
94     // We need to make sure that this block will run on every loop iteration.
95     // For this to be true, we must dominate all blocks with backedges. Such
96     // blocks are in-loop predecessors to the header block.
97     bool NotAlways = false;
98     for (BasicBlock *Pred : predecessors(L->getHeader())) {
99       if (!L->contains(Pred))
100         continue;
101 
102       if (!DT.dominates(BB, Pred)) {
103         NotAlways = true;
104         break;
105       }
106     }
107 
108     if (NotAlways)
109       continue;
110 
111     // Make sure this blocks ends with a conditional branch.
112     Instruction *TI = BB->getTerminator();
113     if (!TI)
114       continue;
115 
116     if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
117       if (!BI->isConditional())
118         continue;
119 
120       ExitBranch = BI;
121     } else
122       continue;
123 
124     // Note that this block may not be the loop latch block, even if the loop
125     // has a latch block.
126     ExitBlock = BB;
127     ExitCount = EC;
128     break;
129   }
130 
131   if (!ExitBlock)
132     return false;
133   return true;
134 }
135 
136 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
137     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
138 
139 TargetTransformInfo::~TargetTransformInfo() {}
140 
141 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
142     : TTIImpl(std::move(Arg.TTIImpl)) {}
143 
144 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
145   TTIImpl = std::move(RHS.TTIImpl);
146   return *this;
147 }
148 
149 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
150                                           Type *OpTy) const {
151   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
152   assert(Cost >= 0 && "TTI should not produce negative costs!");
153   return Cost;
154 }
155 
156 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
157   return TTIImpl->getInliningThresholdMultiplier();
158 }
159 
160 int TargetTransformInfo::getInlinerVectorBonusPercent() const {
161   return TTIImpl->getInlinerVectorBonusPercent();
162 }
163 
164 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
165                                     ArrayRef<const Value *> Operands) const {
166   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
167 }
168 
169 int TargetTransformInfo::getExtCost(const Instruction *I,
170                                     const Value *Src) const {
171   return TTIImpl->getExtCost(I, Src);
172 }
173 
174 int TargetTransformInfo::getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
175                                           ArrayRef<const Value *> Arguments,
176                                           const User *U) const {
177   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments, U);
178   assert(Cost >= 0 && "TTI should not produce negative costs!");
179   return Cost;
180 }
181 
182 unsigned TargetTransformInfo::getEstimatedNumberOfCaseClusters(
183     const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
184     BlockFrequencyInfo *BFI) const {
185   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
186 }
187 
188 int TargetTransformInfo::getUserCost(const User *U,
189                                      ArrayRef<const Value *> Operands) const {
190   int Cost = TTIImpl->getUserCost(U, Operands);
191   assert(Cost >= 0 && "TTI should not produce negative costs!");
192   return Cost;
193 }
194 
195 bool TargetTransformInfo::hasBranchDivergence() const {
196   return TTIImpl->hasBranchDivergence();
197 }
198 
199 bool TargetTransformInfo::useGPUDivergenceAnalysis() const {
200   return TTIImpl->useGPUDivergenceAnalysis();
201 }
202 
203 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
204   return TTIImpl->isSourceOfDivergence(V);
205 }
206 
207 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
208   return TTIImpl->isAlwaysUniform(V);
209 }
210 
211 unsigned TargetTransformInfo::getFlatAddressSpace() const {
212   return TTIImpl->getFlatAddressSpace();
213 }
214 
215 bool TargetTransformInfo::collectFlatAddressOperands(
216     SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
217   return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
218 }
219 
220 bool TargetTransformInfo::rewriteIntrinsicWithAddressSpace(IntrinsicInst *II,
221                                                            Value *OldV,
222                                                            Value *NewV) const {
223   return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
224 }
225 
226 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
227   return TTIImpl->isLoweredToCall(F);
228 }
229 
230 bool TargetTransformInfo::isHardwareLoopProfitable(
231     Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
232     TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
233   return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
234 }
235 
236 bool TargetTransformInfo::preferPredicateOverEpilogue(
237     Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC,
238     TargetLibraryInfo *TLI, DominatorTree *DT,
239     const LoopAccessInfo *LAI) const {
240   return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LAI);
241 }
242 
243 void TargetTransformInfo::getUnrollingPreferences(
244     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
245   return TTIImpl->getUnrollingPreferences(L, SE, UP);
246 }
247 
248 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
249   return TTIImpl->isLegalAddImmediate(Imm);
250 }
251 
252 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
253   return TTIImpl->isLegalICmpImmediate(Imm);
254 }
255 
256 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
257                                                 int64_t BaseOffset,
258                                                 bool HasBaseReg, int64_t Scale,
259                                                 unsigned AddrSpace,
260                                                 Instruction *I) const {
261   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
262                                         Scale, AddrSpace, I);
263 }
264 
265 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
266   return TTIImpl->isLSRCostLess(C1, C2);
267 }
268 
269 bool TargetTransformInfo::canMacroFuseCmp() const {
270   return TTIImpl->canMacroFuseCmp();
271 }
272 
273 bool TargetTransformInfo::canSaveCmp(Loop *L, BranchInst **BI,
274                                      ScalarEvolution *SE, LoopInfo *LI,
275                                      DominatorTree *DT, AssumptionCache *AC,
276                                      TargetLibraryInfo *LibInfo) const {
277   return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
278 }
279 
280 bool TargetTransformInfo::shouldFavorPostInc() const {
281   return TTIImpl->shouldFavorPostInc();
282 }
283 
284 bool TargetTransformInfo::shouldFavorBackedgeIndex(const Loop *L) const {
285   return TTIImpl->shouldFavorBackedgeIndex(L);
286 }
287 
288 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType,
289                                              MaybeAlign Alignment) const {
290   return TTIImpl->isLegalMaskedStore(DataType, Alignment);
291 }
292 
293 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType,
294                                             MaybeAlign Alignment) const {
295   return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
296 }
297 
298 bool TargetTransformInfo::isLegalNTStore(Type *DataType,
299                                          Align Alignment) const {
300   return TTIImpl->isLegalNTStore(DataType, Alignment);
301 }
302 
303 bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
304   return TTIImpl->isLegalNTLoad(DataType, Alignment);
305 }
306 
307 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType,
308                                               MaybeAlign Alignment) const {
309   return TTIImpl->isLegalMaskedGather(DataType, Alignment);
310 }
311 
312 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType,
313                                                MaybeAlign Alignment) const {
314   return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
315 }
316 
317 bool TargetTransformInfo::isLegalMaskedCompressStore(Type *DataType) const {
318   return TTIImpl->isLegalMaskedCompressStore(DataType);
319 }
320 
321 bool TargetTransformInfo::isLegalMaskedExpandLoad(Type *DataType) const {
322   return TTIImpl->isLegalMaskedExpandLoad(DataType);
323 }
324 
325 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
326   return TTIImpl->hasDivRemOp(DataType, IsSigned);
327 }
328 
329 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
330                                              unsigned AddrSpace) const {
331   return TTIImpl->hasVolatileVariant(I, AddrSpace);
332 }
333 
334 bool TargetTransformInfo::prefersVectorizedAddressing() const {
335   return TTIImpl->prefersVectorizedAddressing();
336 }
337 
338 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
339                                               int64_t BaseOffset,
340                                               bool HasBaseReg, int64_t Scale,
341                                               unsigned AddrSpace) const {
342   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
343                                            Scale, AddrSpace);
344   assert(Cost >= 0 && "TTI should not produce negative costs!");
345   return Cost;
346 }
347 
348 bool TargetTransformInfo::LSRWithInstrQueries() const {
349   return TTIImpl->LSRWithInstrQueries();
350 }
351 
352 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
353   return TTIImpl->isTruncateFree(Ty1, Ty2);
354 }
355 
356 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
357   return TTIImpl->isProfitableToHoist(I);
358 }
359 
360 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
361 
362 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
363   return TTIImpl->isTypeLegal(Ty);
364 }
365 
366 bool TargetTransformInfo::shouldBuildLookupTables() const {
367   return TTIImpl->shouldBuildLookupTables();
368 }
369 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(
370     Constant *C) const {
371   return TTIImpl->shouldBuildLookupTablesForConstant(C);
372 }
373 
374 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
375   return TTIImpl->useColdCCForColdCall(F);
376 }
377 
378 unsigned TargetTransformInfo::getScalarizationOverhead(Type *Ty, bool Insert,
379                                                        bool Extract) const {
380   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
381 }
382 
383 unsigned TargetTransformInfo::getOperandsScalarizationOverhead(
384     ArrayRef<const Value *> Args, unsigned VF) const {
385   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
386 }
387 
388 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
389   return TTIImpl->supportsEfficientVectorElementLoadStore();
390 }
391 
392 bool TargetTransformInfo::enableAggressiveInterleaving(
393     bool LoopHasReductions) const {
394   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
395 }
396 
397 TargetTransformInfo::MemCmpExpansionOptions
398 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
399   return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
400 }
401 
402 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
403   return TTIImpl->enableInterleavedAccessVectorization();
404 }
405 
406 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const {
407   return TTIImpl->enableMaskedInterleavedAccessVectorization();
408 }
409 
410 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
411   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
412 }
413 
414 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
415                                                          unsigned BitWidth,
416                                                          unsigned AddressSpace,
417                                                          unsigned Alignment,
418                                                          bool *Fast) const {
419   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
420                                                  AddressSpace, Alignment, Fast);
421 }
422 
423 TargetTransformInfo::PopcntSupportKind
424 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
425   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
426 }
427 
428 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
429   return TTIImpl->haveFastSqrt(Ty);
430 }
431 
432 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
433   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
434 }
435 
436 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
437   int Cost = TTIImpl->getFPOpCost(Ty);
438   assert(Cost >= 0 && "TTI should not produce negative costs!");
439   return Cost;
440 }
441 
442 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
443                                                const APInt &Imm,
444                                                Type *Ty) const {
445   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
446   assert(Cost >= 0 && "TTI should not produce negative costs!");
447   return Cost;
448 }
449 
450 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
451   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
452   assert(Cost >= 0 && "TTI should not produce negative costs!");
453   return Cost;
454 }
455 
456 int TargetTransformInfo::getIntImmCostInst(unsigned Opcode, unsigned Idx,
457                                            const APInt &Imm, Type *Ty) const {
458   int Cost = TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty);
459   assert(Cost >= 0 && "TTI should not produce negative costs!");
460   return Cost;
461 }
462 
463 int TargetTransformInfo::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
464                                              const APInt &Imm, Type *Ty) const {
465   int Cost = TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty);
466   assert(Cost >= 0 && "TTI should not produce negative costs!");
467   return Cost;
468 }
469 
470 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
471   return TTIImpl->getNumberOfRegisters(ClassID);
472 }
473 
474 unsigned TargetTransformInfo::getRegisterClassForType(bool Vector,
475                                                       Type *Ty) const {
476   return TTIImpl->getRegisterClassForType(Vector, Ty);
477 }
478 
479 const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
480   return TTIImpl->getRegisterClassName(ClassID);
481 }
482 
483 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
484   return TTIImpl->getRegisterBitWidth(Vector);
485 }
486 
487 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
488   return TTIImpl->getMinVectorRegisterBitWidth();
489 }
490 
491 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
492   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
493 }
494 
495 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
496   return TTIImpl->getMinimumVF(ElemWidth);
497 }
498 
499 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
500     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
501   return TTIImpl->shouldConsiderAddressTypePromotion(
502       I, AllowPromotionWithoutCommonHeader);
503 }
504 
505 unsigned TargetTransformInfo::getCacheLineSize() const {
506   return TTIImpl->getCacheLineSize();
507 }
508 
509 llvm::Optional<unsigned>
510 TargetTransformInfo::getCacheSize(CacheLevel Level) const {
511   return TTIImpl->getCacheSize(Level);
512 }
513 
514 llvm::Optional<unsigned>
515 TargetTransformInfo::getCacheAssociativity(CacheLevel Level) const {
516   return TTIImpl->getCacheAssociativity(Level);
517 }
518 
519 unsigned TargetTransformInfo::getPrefetchDistance() const {
520   return TTIImpl->getPrefetchDistance();
521 }
522 
523 unsigned TargetTransformInfo::getMinPrefetchStride(
524     unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
525     unsigned NumPrefetches, bool HasCall) const {
526   return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
527                                        NumPrefetches, HasCall);
528 }
529 
530 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
531   return TTIImpl->getMaxPrefetchIterationsAhead();
532 }
533 
534 bool TargetTransformInfo::enableWritePrefetching() const {
535   return TTIImpl->enableWritePrefetching();
536 }
537 
538 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
539   return TTIImpl->getMaxInterleaveFactor(VF);
540 }
541 
542 TargetTransformInfo::OperandValueKind
543 TargetTransformInfo::getOperandInfo(Value *V, OperandValueProperties &OpProps) {
544   OperandValueKind OpInfo = OK_AnyValue;
545   OpProps = OP_None;
546 
547   if (auto *CI = dyn_cast<ConstantInt>(V)) {
548     if (CI->getValue().isPowerOf2())
549       OpProps = OP_PowerOf2;
550     return OK_UniformConstantValue;
551   }
552 
553   // A broadcast shuffle creates a uniform value.
554   // TODO: Add support for non-zero index broadcasts.
555   // TODO: Add support for different source vector width.
556   if (auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
557     if (ShuffleInst->isZeroEltSplat())
558       OpInfo = OK_UniformValue;
559 
560   const Value *Splat = getSplatValue(V);
561 
562   // Check for a splat of a constant or for a non uniform vector of constants
563   // and check if the constant(s) are all powers of two.
564   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
565     OpInfo = OK_NonUniformConstantValue;
566     if (Splat) {
567       OpInfo = OK_UniformConstantValue;
568       if (auto *CI = dyn_cast<ConstantInt>(Splat))
569         if (CI->getValue().isPowerOf2())
570           OpProps = OP_PowerOf2;
571     } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
572       OpProps = OP_PowerOf2;
573       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
574         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
575           if (CI->getValue().isPowerOf2())
576             continue;
577         OpProps = OP_None;
578         break;
579       }
580     }
581   }
582 
583   // Check for a splat of a uniform value. This is not loop aware, so return
584   // true only for the obviously uniform cases (argument, globalvalue)
585   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
586     OpInfo = OK_UniformValue;
587 
588   return OpInfo;
589 }
590 
591 int TargetTransformInfo::getArithmeticInstrCost(
592     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
593     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
594     OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
595     const Instruction *CxtI) const {
596   int Cost = TTIImpl->getArithmeticInstrCost(
597       Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo, Args, CxtI);
598   assert(Cost >= 0 && "TTI should not produce negative costs!");
599   return Cost;
600 }
601 
602 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
603                                         Type *SubTp) const {
604   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
605   assert(Cost >= 0 && "TTI should not produce negative costs!");
606   return Cost;
607 }
608 
609 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
610                                           const Instruction *I) const {
611   assert((I == nullptr || I->getOpcode() == Opcode) &&
612          "Opcode should reflect passed instruction.");
613   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
614   assert(Cost >= 0 && "TTI should not produce negative costs!");
615   return Cost;
616 }
617 
618 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
619                                                   VectorType *VecTy,
620                                                   unsigned Index) const {
621   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
622   assert(Cost >= 0 && "TTI should not produce negative costs!");
623   return Cost;
624 }
625 
626 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
627   int Cost = TTIImpl->getCFInstrCost(Opcode);
628   assert(Cost >= 0 && "TTI should not produce negative costs!");
629   return Cost;
630 }
631 
632 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
633                                             Type *CondTy,
634                                             const Instruction *I) const {
635   assert((I == nullptr || I->getOpcode() == Opcode) &&
636          "Opcode should reflect passed instruction.");
637   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
638   assert(Cost >= 0 && "TTI should not produce negative costs!");
639   return Cost;
640 }
641 
642 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
643                                             unsigned Index) const {
644   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
645   assert(Cost >= 0 && "TTI should not produce negative costs!");
646   return Cost;
647 }
648 
649 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
650                                          MaybeAlign Alignment,
651                                          unsigned AddressSpace,
652                                          const Instruction *I) const {
653   assert((I == nullptr || I->getOpcode() == Opcode) &&
654          "Opcode should reflect passed instruction.");
655   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
656   assert(Cost >= 0 && "TTI should not produce negative costs!");
657   return Cost;
658 }
659 
660 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
661                                                unsigned Alignment,
662                                                unsigned AddressSpace) const {
663   int Cost =
664       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
665   assert(Cost >= 0 && "TTI should not produce negative costs!");
666   return Cost;
667 }
668 
669 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
670                                                 Value *Ptr, bool VariableMask,
671                                                 unsigned Alignment,
672                                                 const Instruction *I) const {
673   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
674                                              Alignment, I);
675   assert(Cost >= 0 && "TTI should not produce negative costs!");
676   return Cost;
677 }
678 
679 int TargetTransformInfo::getInterleavedMemoryOpCost(
680     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
681     unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond,
682     bool UseMaskForGaps) const {
683   int Cost = TTIImpl->getInterleavedMemoryOpCost(
684       Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, UseMaskForCond,
685       UseMaskForGaps);
686   assert(Cost >= 0 && "TTI should not produce negative costs!");
687   return Cost;
688 }
689 
690 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
691                                                ArrayRef<Type *> Tys,
692                                                FastMathFlags FMF,
693                                                unsigned ScalarizationCostPassed,
694                                                const Instruction *I) const {
695   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
696                                             ScalarizationCostPassed, I);
697   assert(Cost >= 0 && "TTI should not produce negative costs!");
698   return Cost;
699 }
700 
701 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
702                                                ArrayRef<Value *> Args,
703                                                FastMathFlags FMF, unsigned VF,
704                                                const Instruction *I) const {
705   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF, I);
706   assert(Cost >= 0 && "TTI should not produce negative costs!");
707   return Cost;
708 }
709 
710 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
711                                           ArrayRef<Type *> Tys) const {
712   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
713   assert(Cost >= 0 && "TTI should not produce negative costs!");
714   return Cost;
715 }
716 
717 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
718   return TTIImpl->getNumberOfParts(Tp);
719 }
720 
721 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
722                                                    ScalarEvolution *SE,
723                                                    const SCEV *Ptr) const {
724   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
725   assert(Cost >= 0 && "TTI should not produce negative costs!");
726   return Cost;
727 }
728 
729 int TargetTransformInfo::getMemcpyCost(const Instruction *I) const {
730   int Cost = TTIImpl->getMemcpyCost(I);
731   assert(Cost >= 0 && "TTI should not produce negative costs!");
732   return Cost;
733 }
734 
735 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
736                                                     bool IsPairwiseForm) const {
737   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
738   assert(Cost >= 0 && "TTI should not produce negative costs!");
739   return Cost;
740 }
741 
742 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
743                                                 bool IsPairwiseForm,
744                                                 bool IsUnsigned) const {
745   int Cost =
746       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
747   assert(Cost >= 0 && "TTI should not produce negative costs!");
748   return Cost;
749 }
750 
751 unsigned
752 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
753   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
754 }
755 
756 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
757                                              MemIntrinsicInfo &Info) const {
758   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
759 }
760 
761 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
762   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
763 }
764 
765 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
766     IntrinsicInst *Inst, Type *ExpectedType) const {
767   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
768 }
769 
770 Type *TargetTransformInfo::getMemcpyLoopLoweringType(
771     LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
772     unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const {
773   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
774                                             DestAddrSpace, SrcAlign, DestAlign);
775 }
776 
777 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
778     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
779     unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
780     unsigned SrcAlign, unsigned DestAlign) const {
781   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
782                                              SrcAddrSpace, DestAddrSpace,
783                                              SrcAlign, DestAlign);
784 }
785 
786 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
787                                               const Function *Callee) const {
788   return TTIImpl->areInlineCompatible(Caller, Callee);
789 }
790 
791 bool TargetTransformInfo::areFunctionArgsABICompatible(
792     const Function *Caller, const Function *Callee,
793     SmallPtrSetImpl<Argument *> &Args) const {
794   return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
795 }
796 
797 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
798                                              Type *Ty) const {
799   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
800 }
801 
802 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
803                                               Type *Ty) const {
804   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
805 }
806 
807 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
808   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
809 }
810 
811 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
812   return TTIImpl->isLegalToVectorizeLoad(LI);
813 }
814 
815 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
816   return TTIImpl->isLegalToVectorizeStore(SI);
817 }
818 
819 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
820     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
821   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
822                                               AddrSpace);
823 }
824 
825 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
826     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
827   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
828                                                AddrSpace);
829 }
830 
831 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
832                                                   unsigned LoadSize,
833                                                   unsigned ChainSizeInBytes,
834                                                   VectorType *VecTy) const {
835   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
836 }
837 
838 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
839                                                    unsigned StoreSize,
840                                                    unsigned ChainSizeInBytes,
841                                                    VectorType *VecTy) const {
842   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
843 }
844 
845 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode, Type *Ty,
846                                                 ReductionFlags Flags) const {
847   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
848 }
849 
850 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
851   return TTIImpl->shouldExpandReduction(II);
852 }
853 
854 unsigned TargetTransformInfo::getGISelRematGlobalCost() const {
855   return TTIImpl->getGISelRematGlobalCost();
856 }
857 
858 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
859   return TTIImpl->getInstructionLatency(I);
860 }
861 
862 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
863                                      unsigned Level) {
864   // We don't need a shuffle if we just want to have element 0 in position 0 of
865   // the vector.
866   if (!SI && Level == 0 && IsLeft)
867     return true;
868   else if (!SI)
869     return false;
870 
871   SmallVector<int, 32> Mask(SI->getType()->getNumElements(), -1);
872 
873   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
874   // we look at the left or right side.
875   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
876     Mask[i] = val;
877 
878   ArrayRef<int> ActualMask = SI->getShuffleMask();
879   return Mask == ActualMask;
880 }
881 
882 namespace {
883 /// Kind of the reduction data.
884 enum ReductionKind {
885   RK_None,           /// Not a reduction.
886   RK_Arithmetic,     /// Binary reduction data.
887   RK_MinMax,         /// Min/max reduction data.
888   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
889 };
890 /// Contains opcode + LHS/RHS parts of the reduction operations.
891 struct ReductionData {
892   ReductionData() = delete;
893   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
894       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
895     assert(Kind != RK_None && "expected binary or min/max reduction only.");
896   }
897   unsigned Opcode = 0;
898   Value *LHS = nullptr;
899   Value *RHS = nullptr;
900   ReductionKind Kind = RK_None;
901   bool hasSameData(ReductionData &RD) const {
902     return Kind == RD.Kind && Opcode == RD.Opcode;
903   }
904 };
905 } // namespace
906 
907 static Optional<ReductionData> getReductionData(Instruction *I) {
908   Value *L, *R;
909   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
910     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
911   if (auto *SI = dyn_cast<SelectInst>(I)) {
912     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
913         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
914         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
915         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
916         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
917         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
918       auto *CI = cast<CmpInst>(SI->getCondition());
919       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
920     }
921     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
922         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
923       auto *CI = cast<CmpInst>(SI->getCondition());
924       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
925     }
926   }
927   return llvm::None;
928 }
929 
930 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
931                                                    unsigned Level,
932                                                    unsigned NumLevels) {
933   // Match one level of pairwise operations.
934   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
935   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
936   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
937   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
938   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
939   if (!I)
940     return RK_None;
941 
942   assert(I->getType()->isVectorTy() && "Expecting a vector type");
943 
944   Optional<ReductionData> RD = getReductionData(I);
945   if (!RD)
946     return RK_None;
947 
948   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
949   if (!LS && Level)
950     return RK_None;
951   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
952   if (!RS && Level)
953     return RK_None;
954 
955   // On level 0 we can omit one shufflevector instruction.
956   if (!Level && !RS && !LS)
957     return RK_None;
958 
959   // Shuffle inputs must match.
960   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
961   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
962   Value *NextLevelOp = nullptr;
963   if (NextLevelOpR && NextLevelOpL) {
964     // If we have two shuffles their operands must match.
965     if (NextLevelOpL != NextLevelOpR)
966       return RK_None;
967 
968     NextLevelOp = NextLevelOpL;
969   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
970     // On the first level we can omit the shufflevector <0, undef,...>. So the
971     // input to the other shufflevector <1, undef> must match with one of the
972     // inputs to the current binary operation.
973     // Example:
974     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
975     //  %BinOp        = fadd          %NextLevelOpL, %R
976     if (NextLevelOpL && NextLevelOpL != RD->RHS)
977       return RK_None;
978     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
979       return RK_None;
980 
981     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
982   } else
983     return RK_None;
984 
985   // Check that the next levels binary operation exists and matches with the
986   // current one.
987   if (Level + 1 != NumLevels) {
988     Optional<ReductionData> NextLevelRD =
989         getReductionData(cast<Instruction>(NextLevelOp));
990     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
991       return RK_None;
992   }
993 
994   // Shuffle mask for pairwise operation must match.
995   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
996     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
997       return RK_None;
998   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
999     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
1000       return RK_None;
1001   } else {
1002     return RK_None;
1003   }
1004 
1005   if (++Level == NumLevels)
1006     return RD->Kind;
1007 
1008   // Match next level.
1009   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
1010                                        NumLevels);
1011 }
1012 
1013 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
1014                                             unsigned &Opcode, Type *&Ty) {
1015   if (!EnableReduxCost)
1016     return RK_None;
1017 
1018   // Need to extract the first element.
1019   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1020   unsigned Idx = ~0u;
1021   if (CI)
1022     Idx = CI->getZExtValue();
1023   if (Idx != 0)
1024     return RK_None;
1025 
1026   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1027   if (!RdxStart)
1028     return RK_None;
1029   Optional<ReductionData> RD = getReductionData(RdxStart);
1030   if (!RD)
1031     return RK_None;
1032 
1033   auto *VecTy = cast<VectorType>(RdxStart->getType());
1034   unsigned NumVecElems = VecTy->getNumElements();
1035   if (!isPowerOf2_32(NumVecElems))
1036     return RK_None;
1037 
1038   // We look for a sequence of shuffle,shuffle,add triples like the following
1039   // that builds a pairwise reduction tree.
1040   //
1041   //  (X0, X1, X2, X3)
1042   //   (X0 + X1, X2 + X3, undef, undef)
1043   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
1044   //
1045   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
1046   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
1047   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
1048   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
1049   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
1050   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1051   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
1052   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1053   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1054   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
1055   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1056   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
1057       RK_None)
1058     return RK_None;
1059 
1060   Opcode = RD->Opcode;
1061   Ty = VecTy;
1062 
1063   return RD->Kind;
1064 }
1065 
1066 static std::pair<Value *, ShuffleVectorInst *>
1067 getShuffleAndOtherOprd(Value *L, Value *R) {
1068   ShuffleVectorInst *S = nullptr;
1069 
1070   if ((S = dyn_cast<ShuffleVectorInst>(L)))
1071     return std::make_pair(R, S);
1072 
1073   S = dyn_cast<ShuffleVectorInst>(R);
1074   return std::make_pair(L, S);
1075 }
1076 
1077 static ReductionKind
1078 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
1079                               unsigned &Opcode, Type *&Ty) {
1080   if (!EnableReduxCost)
1081     return RK_None;
1082 
1083   // Need to extract the first element.
1084   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1085   unsigned Idx = ~0u;
1086   if (CI)
1087     Idx = CI->getZExtValue();
1088   if (Idx != 0)
1089     return RK_None;
1090 
1091   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1092   if (!RdxStart)
1093     return RK_None;
1094   Optional<ReductionData> RD = getReductionData(RdxStart);
1095   if (!RD)
1096     return RK_None;
1097 
1098   auto *VecTy = cast<VectorType>(ReduxRoot->getOperand(0)->getType());
1099   unsigned NumVecElems = VecTy->getNumElements();
1100   if (!isPowerOf2_32(NumVecElems))
1101     return RK_None;
1102 
1103   // We look for a sequence of shuffles and adds like the following matching one
1104   // fadd, shuffle vector pair at a time.
1105   //
1106   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
1107   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
1108   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
1109   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
1110   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1111   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
1112   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1113 
1114   unsigned MaskStart = 1;
1115   Instruction *RdxOp = RdxStart;
1116   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
1117   unsigned NumVecElemsRemain = NumVecElems;
1118   while (NumVecElemsRemain - 1) {
1119     // Check for the right reduction operation.
1120     if (!RdxOp)
1121       return RK_None;
1122     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
1123     if (!RDLevel || !RDLevel->hasSameData(*RD))
1124       return RK_None;
1125 
1126     Value *NextRdxOp;
1127     ShuffleVectorInst *Shuffle;
1128     std::tie(NextRdxOp, Shuffle) =
1129         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
1130 
1131     // Check the current reduction operation and the shuffle use the same value.
1132     if (Shuffle == nullptr)
1133       return RK_None;
1134     if (Shuffle->getOperand(0) != NextRdxOp)
1135       return RK_None;
1136 
1137     // Check that shuffle masks matches.
1138     for (unsigned j = 0; j != MaskStart; ++j)
1139       ShuffleMask[j] = MaskStart + j;
1140     // Fill the rest of the mask with -1 for undef.
1141     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
1142 
1143     ArrayRef<int> Mask = Shuffle->getShuffleMask();
1144     if (ShuffleMask != Mask)
1145       return RK_None;
1146 
1147     RdxOp = dyn_cast<Instruction>(NextRdxOp);
1148     NumVecElemsRemain /= 2;
1149     MaskStart *= 2;
1150   }
1151 
1152   Opcode = RD->Opcode;
1153   Ty = VecTy;
1154   return RD->Kind;
1155 }
1156 
1157 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1158   switch (I->getOpcode()) {
1159   case Instruction::GetElementPtr:
1160     return getUserCost(I);
1161 
1162   case Instruction::Ret:
1163   case Instruction::PHI:
1164   case Instruction::Br: {
1165     return getCFInstrCost(I->getOpcode());
1166   }
1167   case Instruction::Add:
1168   case Instruction::FAdd:
1169   case Instruction::Sub:
1170   case Instruction::FSub:
1171   case Instruction::Mul:
1172   case Instruction::FMul:
1173   case Instruction::UDiv:
1174   case Instruction::SDiv:
1175   case Instruction::FDiv:
1176   case Instruction::URem:
1177   case Instruction::SRem:
1178   case Instruction::FRem:
1179   case Instruction::Shl:
1180   case Instruction::LShr:
1181   case Instruction::AShr:
1182   case Instruction::And:
1183   case Instruction::Or:
1184   case Instruction::Xor: {
1185     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1186     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1187     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1188     Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1189     SmallVector<const Value *, 2> Operands(I->operand_values());
1190     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1191                                   Op1VP, Op2VP, Operands, I);
1192   }
1193   case Instruction::FNeg: {
1194     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1195     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1196     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1197     Op2VK = OK_AnyValue;
1198     Op2VP = OP_None;
1199     SmallVector<const Value *, 2> Operands(I->operand_values());
1200     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1201                                   Op1VP, Op2VP, Operands, I);
1202   }
1203   case Instruction::Select: {
1204     const SelectInst *SI = cast<SelectInst>(I);
1205     Type *CondTy = SI->getCondition()->getType();
1206     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1207   }
1208   case Instruction::ICmp:
1209   case Instruction::FCmp: {
1210     Type *ValTy = I->getOperand(0)->getType();
1211     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1212   }
1213   case Instruction::Store: {
1214     const StoreInst *SI = cast<StoreInst>(I);
1215     Type *ValTy = SI->getValueOperand()->getType();
1216     return getMemoryOpCost(I->getOpcode(), ValTy,
1217                            MaybeAlign(SI->getAlignment()),
1218                            SI->getPointerAddressSpace(), I);
1219   }
1220   case Instruction::Load: {
1221     const LoadInst *LI = cast<LoadInst>(I);
1222     return getMemoryOpCost(I->getOpcode(), I->getType(),
1223                            MaybeAlign(LI->getAlignment()),
1224                            LI->getPointerAddressSpace(), I);
1225   }
1226   case Instruction::ZExt:
1227   case Instruction::SExt:
1228   case Instruction::FPToUI:
1229   case Instruction::FPToSI:
1230   case Instruction::FPExt:
1231   case Instruction::PtrToInt:
1232   case Instruction::IntToPtr:
1233   case Instruction::SIToFP:
1234   case Instruction::UIToFP:
1235   case Instruction::Trunc:
1236   case Instruction::FPTrunc:
1237   case Instruction::BitCast:
1238   case Instruction::AddrSpaceCast: {
1239     Type *SrcTy = I->getOperand(0)->getType();
1240     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1241   }
1242   case Instruction::ExtractElement: {
1243     const ExtractElementInst *EEI = cast<ExtractElementInst>(I);
1244     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1245     unsigned Idx = -1;
1246     if (CI)
1247       Idx = CI->getZExtValue();
1248 
1249     // Try to match a reduction sequence (series of shufflevector and vector
1250     // adds followed by a extractelement).
1251     unsigned ReduxOpCode;
1252     Type *ReduxType;
1253 
1254     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1255     case RK_Arithmetic:
1256       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1257                                         /*IsPairwiseForm=*/false);
1258     case RK_MinMax:
1259       return getMinMaxReductionCost(
1260           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1261           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1262     case RK_UnsignedMinMax:
1263       return getMinMaxReductionCost(
1264           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1265           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1266     case RK_None:
1267       break;
1268     }
1269 
1270     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1271     case RK_Arithmetic:
1272       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1273                                         /*IsPairwiseForm=*/true);
1274     case RK_MinMax:
1275       return getMinMaxReductionCost(
1276           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1277           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1278     case RK_UnsignedMinMax:
1279       return getMinMaxReductionCost(
1280           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1281           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1282     case RK_None:
1283       break;
1284     }
1285 
1286     return getVectorInstrCost(I->getOpcode(), EEI->getOperand(0)->getType(),
1287                               Idx);
1288   }
1289   case Instruction::InsertElement: {
1290     const InsertElementInst *IE = cast<InsertElementInst>(I);
1291     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1292     unsigned Idx = -1;
1293     if (CI)
1294       Idx = CI->getZExtValue();
1295     return getVectorInstrCost(I->getOpcode(), IE->getType(), Idx);
1296   }
1297   case Instruction::ExtractValue:
1298     return 0; // Model all ExtractValue nodes as free.
1299   case Instruction::ShuffleVector: {
1300     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1301     Type *Ty = Shuffle->getType();
1302     Type *SrcTy = Shuffle->getOperand(0)->getType();
1303 
1304     // TODO: Identify and add costs for insert subvector, etc.
1305     int SubIndex;
1306     if (Shuffle->isExtractSubvectorMask(SubIndex))
1307       return TTIImpl->getShuffleCost(SK_ExtractSubvector, SrcTy, SubIndex, Ty);
1308 
1309     if (Shuffle->changesLength())
1310       return -1;
1311 
1312     if (Shuffle->isIdentity())
1313       return 0;
1314 
1315     if (Shuffle->isReverse())
1316       return TTIImpl->getShuffleCost(SK_Reverse, Ty, 0, nullptr);
1317 
1318     if (Shuffle->isSelect())
1319       return TTIImpl->getShuffleCost(SK_Select, Ty, 0, nullptr);
1320 
1321     if (Shuffle->isTranspose())
1322       return TTIImpl->getShuffleCost(SK_Transpose, Ty, 0, nullptr);
1323 
1324     if (Shuffle->isZeroEltSplat())
1325       return TTIImpl->getShuffleCost(SK_Broadcast, Ty, 0, nullptr);
1326 
1327     if (Shuffle->isSingleSource())
1328       return TTIImpl->getShuffleCost(SK_PermuteSingleSrc, Ty, 0, nullptr);
1329 
1330     return TTIImpl->getShuffleCost(SK_PermuteTwoSrc, Ty, 0, nullptr);
1331   }
1332   case Instruction::Call:
1333     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1334       SmallVector<Value *, 4> Args(II->arg_operands());
1335 
1336       FastMathFlags FMF;
1337       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1338         FMF = FPMO->getFastMathFlags();
1339 
1340       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(), Args,
1341                                    FMF, 1, II);
1342     }
1343     return -1;
1344   default:
1345     // We don't have any information on this instruction.
1346     return -1;
1347   }
1348 }
1349 
1350 TargetTransformInfo::Concept::~Concept() {}
1351 
1352 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1353 
1354 TargetIRAnalysis::TargetIRAnalysis(
1355     std::function<Result(const Function &)> TTICallback)
1356     : TTICallback(std::move(TTICallback)) {}
1357 
1358 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1359                                                FunctionAnalysisManager &) {
1360   return TTICallback(F);
1361 }
1362 
1363 AnalysisKey TargetIRAnalysis::Key;
1364 
1365 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1366   return Result(F.getParent()->getDataLayout());
1367 }
1368 
1369 // Register the basic pass.
1370 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1371                 "Target Transform Information", false, true)
1372 char TargetTransformInfoWrapperPass::ID = 0;
1373 
1374 void TargetTransformInfoWrapperPass::anchor() {}
1375 
1376 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1377     : ImmutablePass(ID) {
1378   initializeTargetTransformInfoWrapperPassPass(
1379       *PassRegistry::getPassRegistry());
1380 }
1381 
1382 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1383     TargetIRAnalysis TIRA)
1384     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1385   initializeTargetTransformInfoWrapperPassPass(
1386       *PassRegistry::getPassRegistry());
1387 }
1388 
1389 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1390   FunctionAnalysisManager DummyFAM;
1391   TTI = TIRA.run(F, DummyFAM);
1392   return *TTI;
1393 }
1394 
1395 ImmutablePass *
1396 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1397   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1398 }
1399