1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/Analysis/TargetTransformInfo.h"
10 #include "llvm/Analysis/TargetTransformInfoImpl.h"
11 #include "llvm/IR/CallSite.h"
12 #include "llvm/IR/DataLayout.h"
13 #include "llvm/IR/Instruction.h"
14 #include "llvm/IR/Instructions.h"
15 #include "llvm/IR/IntrinsicInst.h"
16 #include "llvm/IR/Module.h"
17 #include "llvm/IR/Operator.h"
18 #include "llvm/IR/PatternMatch.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <utility>
22 
23 using namespace llvm;
24 using namespace PatternMatch;
25 
26 #define DEBUG_TYPE "tti"
27 
28 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
29                                      cl::Hidden,
30                                      cl::desc("Recognize reduction patterns."));
31 
32 namespace {
33 /// No-op implementation of the TTI interface using the utility base
34 /// classes.
35 ///
36 /// This is used when no target specific information is available.
37 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
38   explicit NoTTIImpl(const DataLayout &DL)
39       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
40 };
41 }
42 
43 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
44     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
45 
46 TargetTransformInfo::~TargetTransformInfo() {}
47 
48 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
49     : TTIImpl(std::move(Arg.TTIImpl)) {}
50 
51 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
52   TTIImpl = std::move(RHS.TTIImpl);
53   return *this;
54 }
55 
56 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
57                                           Type *OpTy) const {
58   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
59   assert(Cost >= 0 && "TTI should not produce negative costs!");
60   return Cost;
61 }
62 
63 int TargetTransformInfo::getCallCost(FunctionType *FTy, int NumArgs,
64                                      const User *U) const {
65   int Cost = TTIImpl->getCallCost(FTy, NumArgs, U);
66   assert(Cost >= 0 && "TTI should not produce negative costs!");
67   return Cost;
68 }
69 
70 int TargetTransformInfo::getCallCost(const Function *F,
71                                      ArrayRef<const Value *> Arguments,
72                                      const User *U) const {
73   int Cost = TTIImpl->getCallCost(F, Arguments, U);
74   assert(Cost >= 0 && "TTI should not produce negative costs!");
75   return Cost;
76 }
77 
78 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
79   return TTIImpl->getInliningThresholdMultiplier();
80 }
81 
82 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
83                                     ArrayRef<const Value *> Operands) const {
84   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
85 }
86 
87 int TargetTransformInfo::getExtCost(const Instruction *I,
88                                     const Value *Src) const {
89   return TTIImpl->getExtCost(I, Src);
90 }
91 
92 int TargetTransformInfo::getIntrinsicCost(
93     Intrinsic::ID IID, Type *RetTy, ArrayRef<const Value *> Arguments,
94     const User *U) const {
95   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments, U);
96   assert(Cost >= 0 && "TTI should not produce negative costs!");
97   return Cost;
98 }
99 
100 unsigned
101 TargetTransformInfo::getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
102                                                       unsigned &JTSize) const {
103   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize);
104 }
105 
106 int TargetTransformInfo::getUserCost(const User *U,
107     ArrayRef<const Value *> Operands) const {
108   int Cost = TTIImpl->getUserCost(U, Operands);
109   assert(Cost >= 0 && "TTI should not produce negative costs!");
110   return Cost;
111 }
112 
113 bool TargetTransformInfo::hasBranchDivergence() const {
114   return TTIImpl->hasBranchDivergence();
115 }
116 
117 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
118   return TTIImpl->isSourceOfDivergence(V);
119 }
120 
121 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
122   return TTIImpl->isAlwaysUniform(V);
123 }
124 
125 unsigned TargetTransformInfo::getFlatAddressSpace() const {
126   return TTIImpl->getFlatAddressSpace();
127 }
128 
129 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
130   return TTIImpl->isLoweredToCall(F);
131 }
132 
133 void TargetTransformInfo::getUnrollingPreferences(
134     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
135   return TTIImpl->getUnrollingPreferences(L, SE, UP);
136 }
137 
138 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
139   return TTIImpl->isLegalAddImmediate(Imm);
140 }
141 
142 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
143   return TTIImpl->isLegalICmpImmediate(Imm);
144 }
145 
146 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
147                                                 int64_t BaseOffset,
148                                                 bool HasBaseReg,
149                                                 int64_t Scale,
150                                                 unsigned AddrSpace,
151                                                 Instruction *I) const {
152   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
153                                         Scale, AddrSpace, I);
154 }
155 
156 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
157   return TTIImpl->isLSRCostLess(C1, C2);
158 }
159 
160 bool TargetTransformInfo::canMacroFuseCmp() const {
161   return TTIImpl->canMacroFuseCmp();
162 }
163 
164 bool TargetTransformInfo::shouldFavorPostInc() const {
165   return TTIImpl->shouldFavorPostInc();
166 }
167 
168 bool TargetTransformInfo::shouldFavorBackedgeIndex(const Loop *L) const {
169   return TTIImpl->shouldFavorBackedgeIndex(L);
170 }
171 
172 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType) const {
173   return TTIImpl->isLegalMaskedStore(DataType);
174 }
175 
176 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType) const {
177   return TTIImpl->isLegalMaskedLoad(DataType);
178 }
179 
180 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
181   return TTIImpl->isLegalMaskedGather(DataType);
182 }
183 
184 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
185   return TTIImpl->isLegalMaskedScatter(DataType);
186 }
187 
188 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
189   return TTIImpl->hasDivRemOp(DataType, IsSigned);
190 }
191 
192 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
193                                              unsigned AddrSpace) const {
194   return TTIImpl->hasVolatileVariant(I, AddrSpace);
195 }
196 
197 bool TargetTransformInfo::prefersVectorizedAddressing() const {
198   return TTIImpl->prefersVectorizedAddressing();
199 }
200 
201 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
202                                               int64_t BaseOffset,
203                                               bool HasBaseReg,
204                                               int64_t Scale,
205                                               unsigned AddrSpace) const {
206   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
207                                            Scale, AddrSpace);
208   assert(Cost >= 0 && "TTI should not produce negative costs!");
209   return Cost;
210 }
211 
212 bool TargetTransformInfo::LSRWithInstrQueries() const {
213   return TTIImpl->LSRWithInstrQueries();
214 }
215 
216 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
217   return TTIImpl->isTruncateFree(Ty1, Ty2);
218 }
219 
220 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
221   return TTIImpl->isProfitableToHoist(I);
222 }
223 
224 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
225 
226 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
227   return TTIImpl->isTypeLegal(Ty);
228 }
229 
230 unsigned TargetTransformInfo::getJumpBufAlignment() const {
231   return TTIImpl->getJumpBufAlignment();
232 }
233 
234 unsigned TargetTransformInfo::getJumpBufSize() const {
235   return TTIImpl->getJumpBufSize();
236 }
237 
238 bool TargetTransformInfo::shouldBuildLookupTables() const {
239   return TTIImpl->shouldBuildLookupTables();
240 }
241 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(Constant *C) const {
242   return TTIImpl->shouldBuildLookupTablesForConstant(C);
243 }
244 
245 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
246   return TTIImpl->useColdCCForColdCall(F);
247 }
248 
249 unsigned TargetTransformInfo::
250 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
251   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
252 }
253 
254 unsigned TargetTransformInfo::
255 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
256                                  unsigned VF) const {
257   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
258 }
259 
260 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
261   return TTIImpl->supportsEfficientVectorElementLoadStore();
262 }
263 
264 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
265   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
266 }
267 
268 const TargetTransformInfo::MemCmpExpansionOptions *
269 TargetTransformInfo::enableMemCmpExpansion(bool IsZeroCmp) const {
270   return TTIImpl->enableMemCmpExpansion(IsZeroCmp);
271 }
272 
273 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
274   return TTIImpl->enableInterleavedAccessVectorization();
275 }
276 
277 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const {
278   return TTIImpl->enableMaskedInterleavedAccessVectorization();
279 }
280 
281 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
282   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
283 }
284 
285 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
286                                                          unsigned BitWidth,
287                                                          unsigned AddressSpace,
288                                                          unsigned Alignment,
289                                                          bool *Fast) const {
290   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
291                                                  Alignment, Fast);
292 }
293 
294 TargetTransformInfo::PopcntSupportKind
295 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
296   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
297 }
298 
299 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
300   return TTIImpl->haveFastSqrt(Ty);
301 }
302 
303 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
304   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
305 }
306 
307 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
308   int Cost = TTIImpl->getFPOpCost(Ty);
309   assert(Cost >= 0 && "TTI should not produce negative costs!");
310   return Cost;
311 }
312 
313 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
314                                                const APInt &Imm,
315                                                Type *Ty) const {
316   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
317   assert(Cost >= 0 && "TTI should not produce negative costs!");
318   return Cost;
319 }
320 
321 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
322   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
323   assert(Cost >= 0 && "TTI should not produce negative costs!");
324   return Cost;
325 }
326 
327 int TargetTransformInfo::getIntImmCost(unsigned Opcode, unsigned Idx,
328                                        const APInt &Imm, Type *Ty) const {
329   int Cost = TTIImpl->getIntImmCost(Opcode, Idx, Imm, Ty);
330   assert(Cost >= 0 && "TTI should not produce negative costs!");
331   return Cost;
332 }
333 
334 int TargetTransformInfo::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
335                                        const APInt &Imm, Type *Ty) const {
336   int Cost = TTIImpl->getIntImmCost(IID, Idx, Imm, Ty);
337   assert(Cost >= 0 && "TTI should not produce negative costs!");
338   return Cost;
339 }
340 
341 unsigned TargetTransformInfo::getNumberOfRegisters(bool Vector) const {
342   return TTIImpl->getNumberOfRegisters(Vector);
343 }
344 
345 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
346   return TTIImpl->getRegisterBitWidth(Vector);
347 }
348 
349 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
350   return TTIImpl->getMinVectorRegisterBitWidth();
351 }
352 
353 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
354   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
355 }
356 
357 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
358   return TTIImpl->getMinimumVF(ElemWidth);
359 }
360 
361 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
362     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
363   return TTIImpl->shouldConsiderAddressTypePromotion(
364       I, AllowPromotionWithoutCommonHeader);
365 }
366 
367 unsigned TargetTransformInfo::getCacheLineSize() const {
368   return TTIImpl->getCacheLineSize();
369 }
370 
371 llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
372   const {
373   return TTIImpl->getCacheSize(Level);
374 }
375 
376 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
377   CacheLevel Level) const {
378   return TTIImpl->getCacheAssociativity(Level);
379 }
380 
381 unsigned TargetTransformInfo::getPrefetchDistance() const {
382   return TTIImpl->getPrefetchDistance();
383 }
384 
385 unsigned TargetTransformInfo::getMinPrefetchStride() const {
386   return TTIImpl->getMinPrefetchStride();
387 }
388 
389 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
390   return TTIImpl->getMaxPrefetchIterationsAhead();
391 }
392 
393 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
394   return TTIImpl->getMaxInterleaveFactor(VF);
395 }
396 
397 TargetTransformInfo::OperandValueKind
398 TargetTransformInfo::getOperandInfo(Value *V, OperandValueProperties &OpProps) {
399   OperandValueKind OpInfo = OK_AnyValue;
400   OpProps = OP_None;
401 
402   if (auto *CI = dyn_cast<ConstantInt>(V)) {
403     if (CI->getValue().isPowerOf2())
404       OpProps = OP_PowerOf2;
405     return OK_UniformConstantValue;
406   }
407 
408   // A broadcast shuffle creates a uniform value.
409   // TODO: Add support for non-zero index broadcasts.
410   // TODO: Add support for different source vector width.
411   if (auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
412     if (ShuffleInst->isZeroEltSplat())
413       OpInfo = OK_UniformValue;
414 
415   const Value *Splat = getSplatValue(V);
416 
417   // Check for a splat of a constant or for a non uniform vector of constants
418   // and check if the constant(s) are all powers of two.
419   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
420     OpInfo = OK_NonUniformConstantValue;
421     if (Splat) {
422       OpInfo = OK_UniformConstantValue;
423       if (auto *CI = dyn_cast<ConstantInt>(Splat))
424         if (CI->getValue().isPowerOf2())
425           OpProps = OP_PowerOf2;
426     } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
427       OpProps = OP_PowerOf2;
428       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
429         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
430           if (CI->getValue().isPowerOf2())
431             continue;
432         OpProps = OP_None;
433         break;
434       }
435     }
436   }
437 
438   // Check for a splat of a uniform value. This is not loop aware, so return
439   // true only for the obviously uniform cases (argument, globalvalue)
440   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
441     OpInfo = OK_UniformValue;
442 
443   return OpInfo;
444 }
445 
446 int TargetTransformInfo::getArithmeticInstrCost(
447     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
448     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
449     OperandValueProperties Opd2PropInfo,
450     ArrayRef<const Value *> Args) const {
451   int Cost = TTIImpl->getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
452                                              Opd1PropInfo, Opd2PropInfo, Args);
453   assert(Cost >= 0 && "TTI should not produce negative costs!");
454   return Cost;
455 }
456 
457 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
458                                         Type *SubTp) const {
459   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
460   assert(Cost >= 0 && "TTI should not produce negative costs!");
461   return Cost;
462 }
463 
464 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
465                                  Type *Src, const Instruction *I) const {
466   assert ((I == nullptr || I->getOpcode() == Opcode) &&
467           "Opcode should reflect passed instruction.");
468   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
469   assert(Cost >= 0 && "TTI should not produce negative costs!");
470   return Cost;
471 }
472 
473 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
474                                                   VectorType *VecTy,
475                                                   unsigned Index) const {
476   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
477   assert(Cost >= 0 && "TTI should not produce negative costs!");
478   return Cost;
479 }
480 
481 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
482   int Cost = TTIImpl->getCFInstrCost(Opcode);
483   assert(Cost >= 0 && "TTI should not produce negative costs!");
484   return Cost;
485 }
486 
487 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
488                                  Type *CondTy, const Instruction *I) const {
489   assert ((I == nullptr || I->getOpcode() == Opcode) &&
490           "Opcode should reflect passed instruction.");
491   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
492   assert(Cost >= 0 && "TTI should not produce negative costs!");
493   return Cost;
494 }
495 
496 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
497                                             unsigned Index) const {
498   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
499   assert(Cost >= 0 && "TTI should not produce negative costs!");
500   return Cost;
501 }
502 
503 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
504                                          unsigned Alignment,
505                                          unsigned AddressSpace,
506                                          const Instruction *I) const {
507   assert ((I == nullptr || I->getOpcode() == Opcode) &&
508           "Opcode should reflect passed instruction.");
509   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
510   assert(Cost >= 0 && "TTI should not produce negative costs!");
511   return Cost;
512 }
513 
514 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
515                                                unsigned Alignment,
516                                                unsigned AddressSpace) const {
517   int Cost =
518       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
519   assert(Cost >= 0 && "TTI should not produce negative costs!");
520   return Cost;
521 }
522 
523 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
524                                                 Value *Ptr, bool VariableMask,
525                                                 unsigned Alignment) const {
526   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
527                                              Alignment);
528   assert(Cost >= 0 && "TTI should not produce negative costs!");
529   return Cost;
530 }
531 
532 int TargetTransformInfo::getInterleavedMemoryOpCost(
533     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
534     unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond,
535     bool UseMaskForGaps) const {
536   int Cost = TTIImpl->getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
537                                                  Alignment, AddressSpace,
538                                                  UseMaskForCond,
539                                                  UseMaskForGaps);
540   assert(Cost >= 0 && "TTI should not produce negative costs!");
541   return Cost;
542 }
543 
544 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
545                                     ArrayRef<Type *> Tys, FastMathFlags FMF,
546                                     unsigned ScalarizationCostPassed) const {
547   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
548                                             ScalarizationCostPassed);
549   assert(Cost >= 0 && "TTI should not produce negative costs!");
550   return Cost;
551 }
552 
553 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
554            ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) const {
555   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
556   assert(Cost >= 0 && "TTI should not produce negative costs!");
557   return Cost;
558 }
559 
560 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
561                                           ArrayRef<Type *> Tys) const {
562   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
563   assert(Cost >= 0 && "TTI should not produce negative costs!");
564   return Cost;
565 }
566 
567 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
568   return TTIImpl->getNumberOfParts(Tp);
569 }
570 
571 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
572                                                    ScalarEvolution *SE,
573                                                    const SCEV *Ptr) const {
574   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
575   assert(Cost >= 0 && "TTI should not produce negative costs!");
576   return Cost;
577 }
578 
579 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
580                                                     bool IsPairwiseForm) const {
581   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
582   assert(Cost >= 0 && "TTI should not produce negative costs!");
583   return Cost;
584 }
585 
586 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
587                                                 bool IsPairwiseForm,
588                                                 bool IsUnsigned) const {
589   int Cost =
590       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
591   assert(Cost >= 0 && "TTI should not produce negative costs!");
592   return Cost;
593 }
594 
595 unsigned
596 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
597   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
598 }
599 
600 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
601                                              MemIntrinsicInfo &Info) const {
602   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
603 }
604 
605 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
606   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
607 }
608 
609 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
610     IntrinsicInst *Inst, Type *ExpectedType) const {
611   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
612 }
613 
614 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
615                                                      Value *Length,
616                                                      unsigned SrcAlign,
617                                                      unsigned DestAlign) const {
618   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
619                                             DestAlign);
620 }
621 
622 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
623     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
624     unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
625   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
626                                              SrcAlign, DestAlign);
627 }
628 
629 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
630                                               const Function *Callee) const {
631   return TTIImpl->areInlineCompatible(Caller, Callee);
632 }
633 
634 bool TargetTransformInfo::areFunctionArgsABICompatible(
635     const Function *Caller, const Function *Callee,
636     SmallPtrSetImpl<Argument *> &Args) const {
637   return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
638 }
639 
640 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
641                                              Type *Ty) const {
642   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
643 }
644 
645 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
646                                               Type *Ty) const {
647   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
648 }
649 
650 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
651   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
652 }
653 
654 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
655   return TTIImpl->isLegalToVectorizeLoad(LI);
656 }
657 
658 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
659   return TTIImpl->isLegalToVectorizeStore(SI);
660 }
661 
662 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
663     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
664   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
665                                               AddrSpace);
666 }
667 
668 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
669     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
670   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
671                                                AddrSpace);
672 }
673 
674 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
675                                                   unsigned LoadSize,
676                                                   unsigned ChainSizeInBytes,
677                                                   VectorType *VecTy) const {
678   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
679 }
680 
681 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
682                                                    unsigned StoreSize,
683                                                    unsigned ChainSizeInBytes,
684                                                    VectorType *VecTy) const {
685   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
686 }
687 
688 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode,
689                                                 Type *Ty, ReductionFlags Flags) const {
690   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
691 }
692 
693 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
694   return TTIImpl->shouldExpandReduction(II);
695 }
696 
697 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
698   return TTIImpl->getInstructionLatency(I);
699 }
700 
701 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
702                                      unsigned Level) {
703   // We don't need a shuffle if we just want to have element 0 in position 0 of
704   // the vector.
705   if (!SI && Level == 0 && IsLeft)
706     return true;
707   else if (!SI)
708     return false;
709 
710   SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
711 
712   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
713   // we look at the left or right side.
714   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
715     Mask[i] = val;
716 
717   SmallVector<int, 16> ActualMask = SI->getShuffleMask();
718   return Mask == ActualMask;
719 }
720 
721 namespace {
722 /// Kind of the reduction data.
723 enum ReductionKind {
724   RK_None,           /// Not a reduction.
725   RK_Arithmetic,     /// Binary reduction data.
726   RK_MinMax,         /// Min/max reduction data.
727   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
728 };
729 /// Contains opcode + LHS/RHS parts of the reduction operations.
730 struct ReductionData {
731   ReductionData() = delete;
732   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
733       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
734     assert(Kind != RK_None && "expected binary or min/max reduction only.");
735   }
736   unsigned Opcode = 0;
737   Value *LHS = nullptr;
738   Value *RHS = nullptr;
739   ReductionKind Kind = RK_None;
740   bool hasSameData(ReductionData &RD) const {
741     return Kind == RD.Kind && Opcode == RD.Opcode;
742   }
743 };
744 } // namespace
745 
746 static Optional<ReductionData> getReductionData(Instruction *I) {
747   Value *L, *R;
748   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
749     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
750   if (auto *SI = dyn_cast<SelectInst>(I)) {
751     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
752         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
753         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
754         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
755         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
756         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
757       auto *CI = cast<CmpInst>(SI->getCondition());
758       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
759     }
760     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
761         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
762       auto *CI = cast<CmpInst>(SI->getCondition());
763       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
764     }
765   }
766   return llvm::None;
767 }
768 
769 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
770                                                    unsigned Level,
771                                                    unsigned NumLevels) {
772   // Match one level of pairwise operations.
773   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
774   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
775   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
776   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
777   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
778   if (!I)
779     return RK_None;
780 
781   assert(I->getType()->isVectorTy() && "Expecting a vector type");
782 
783   Optional<ReductionData> RD = getReductionData(I);
784   if (!RD)
785     return RK_None;
786 
787   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
788   if (!LS && Level)
789     return RK_None;
790   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
791   if (!RS && Level)
792     return RK_None;
793 
794   // On level 0 we can omit one shufflevector instruction.
795   if (!Level && !RS && !LS)
796     return RK_None;
797 
798   // Shuffle inputs must match.
799   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
800   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
801   Value *NextLevelOp = nullptr;
802   if (NextLevelOpR && NextLevelOpL) {
803     // If we have two shuffles their operands must match.
804     if (NextLevelOpL != NextLevelOpR)
805       return RK_None;
806 
807     NextLevelOp = NextLevelOpL;
808   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
809     // On the first level we can omit the shufflevector <0, undef,...>. So the
810     // input to the other shufflevector <1, undef> must match with one of the
811     // inputs to the current binary operation.
812     // Example:
813     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
814     //  %BinOp        = fadd          %NextLevelOpL, %R
815     if (NextLevelOpL && NextLevelOpL != RD->RHS)
816       return RK_None;
817     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
818       return RK_None;
819 
820     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
821   } else
822     return RK_None;
823 
824   // Check that the next levels binary operation exists and matches with the
825   // current one.
826   if (Level + 1 != NumLevels) {
827     Optional<ReductionData> NextLevelRD =
828         getReductionData(cast<Instruction>(NextLevelOp));
829     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
830       return RK_None;
831   }
832 
833   // Shuffle mask for pairwise operation must match.
834   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
835     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
836       return RK_None;
837   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
838     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
839       return RK_None;
840   } else {
841     return RK_None;
842   }
843 
844   if (++Level == NumLevels)
845     return RD->Kind;
846 
847   // Match next level.
848   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
849                                        NumLevels);
850 }
851 
852 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
853                                             unsigned &Opcode, Type *&Ty) {
854   if (!EnableReduxCost)
855     return RK_None;
856 
857   // Need to extract the first element.
858   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
859   unsigned Idx = ~0u;
860   if (CI)
861     Idx = CI->getZExtValue();
862   if (Idx != 0)
863     return RK_None;
864 
865   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
866   if (!RdxStart)
867     return RK_None;
868   Optional<ReductionData> RD = getReductionData(RdxStart);
869   if (!RD)
870     return RK_None;
871 
872   Type *VecTy = RdxStart->getType();
873   unsigned NumVecElems = VecTy->getVectorNumElements();
874   if (!isPowerOf2_32(NumVecElems))
875     return RK_None;
876 
877   // We look for a sequence of shuffle,shuffle,add triples like the following
878   // that builds a pairwise reduction tree.
879   //
880   //  (X0, X1, X2, X3)
881   //   (X0 + X1, X2 + X3, undef, undef)
882   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
883   //
884   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
885   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
886   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
887   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
888   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
889   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
890   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
891   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
892   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
893   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
894   // %r = extractelement <4 x float> %bin.rdx8, i32 0
895   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
896       RK_None)
897     return RK_None;
898 
899   Opcode = RD->Opcode;
900   Ty = VecTy;
901 
902   return RD->Kind;
903 }
904 
905 static std::pair<Value *, ShuffleVectorInst *>
906 getShuffleAndOtherOprd(Value *L, Value *R) {
907   ShuffleVectorInst *S = nullptr;
908 
909   if ((S = dyn_cast<ShuffleVectorInst>(L)))
910     return std::make_pair(R, S);
911 
912   S = dyn_cast<ShuffleVectorInst>(R);
913   return std::make_pair(L, S);
914 }
915 
916 static ReductionKind
917 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
918                               unsigned &Opcode, Type *&Ty) {
919   if (!EnableReduxCost)
920     return RK_None;
921 
922   // Need to extract the first element.
923   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
924   unsigned Idx = ~0u;
925   if (CI)
926     Idx = CI->getZExtValue();
927   if (Idx != 0)
928     return RK_None;
929 
930   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
931   if (!RdxStart)
932     return RK_None;
933   Optional<ReductionData> RD = getReductionData(RdxStart);
934   if (!RD)
935     return RK_None;
936 
937   Type *VecTy = ReduxRoot->getOperand(0)->getType();
938   unsigned NumVecElems = VecTy->getVectorNumElements();
939   if (!isPowerOf2_32(NumVecElems))
940     return RK_None;
941 
942   // We look for a sequence of shuffles and adds like the following matching one
943   // fadd, shuffle vector pair at a time.
944   //
945   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
946   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
947   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
948   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
949   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
950   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
951   // %r = extractelement <4 x float> %bin.rdx8, i32 0
952 
953   unsigned MaskStart = 1;
954   Instruction *RdxOp = RdxStart;
955   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
956   unsigned NumVecElemsRemain = NumVecElems;
957   while (NumVecElemsRemain - 1) {
958     // Check for the right reduction operation.
959     if (!RdxOp)
960       return RK_None;
961     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
962     if (!RDLevel || !RDLevel->hasSameData(*RD))
963       return RK_None;
964 
965     Value *NextRdxOp;
966     ShuffleVectorInst *Shuffle;
967     std::tie(NextRdxOp, Shuffle) =
968         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
969 
970     // Check the current reduction operation and the shuffle use the same value.
971     if (Shuffle == nullptr)
972       return RK_None;
973     if (Shuffle->getOperand(0) != NextRdxOp)
974       return RK_None;
975 
976     // Check that shuffle masks matches.
977     for (unsigned j = 0; j != MaskStart; ++j)
978       ShuffleMask[j] = MaskStart + j;
979     // Fill the rest of the mask with -1 for undef.
980     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
981 
982     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
983     if (ShuffleMask != Mask)
984       return RK_None;
985 
986     RdxOp = dyn_cast<Instruction>(NextRdxOp);
987     NumVecElemsRemain /= 2;
988     MaskStart *= 2;
989   }
990 
991   Opcode = RD->Opcode;
992   Ty = VecTy;
993   return RD->Kind;
994 }
995 
996 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
997   switch (I->getOpcode()) {
998   case Instruction::GetElementPtr:
999     return getUserCost(I);
1000 
1001   case Instruction::Ret:
1002   case Instruction::PHI:
1003   case Instruction::Br: {
1004     return getCFInstrCost(I->getOpcode());
1005   }
1006   case Instruction::Add:
1007   case Instruction::FAdd:
1008   case Instruction::Sub:
1009   case Instruction::FSub:
1010   case Instruction::Mul:
1011   case Instruction::FMul:
1012   case Instruction::UDiv:
1013   case Instruction::SDiv:
1014   case Instruction::FDiv:
1015   case Instruction::URem:
1016   case Instruction::SRem:
1017   case Instruction::FRem:
1018   case Instruction::Shl:
1019   case Instruction::LShr:
1020   case Instruction::AShr:
1021   case Instruction::And:
1022   case Instruction::Or:
1023   case Instruction::Xor: {
1024     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1025     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1026     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1027     Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1028     SmallVector<const Value *, 2> Operands(I->operand_values());
1029     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1030                                   Op1VP, Op2VP, Operands);
1031   }
1032   case Instruction::Select: {
1033     const SelectInst *SI = cast<SelectInst>(I);
1034     Type *CondTy = SI->getCondition()->getType();
1035     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1036   }
1037   case Instruction::ICmp:
1038   case Instruction::FCmp: {
1039     Type *ValTy = I->getOperand(0)->getType();
1040     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1041   }
1042   case Instruction::Store: {
1043     const StoreInst *SI = cast<StoreInst>(I);
1044     Type *ValTy = SI->getValueOperand()->getType();
1045     return getMemoryOpCost(I->getOpcode(), ValTy,
1046                                 SI->getAlignment(),
1047                                 SI->getPointerAddressSpace(), I);
1048   }
1049   case Instruction::Load: {
1050     const LoadInst *LI = cast<LoadInst>(I);
1051     return getMemoryOpCost(I->getOpcode(), I->getType(),
1052                                 LI->getAlignment(),
1053                                 LI->getPointerAddressSpace(), I);
1054   }
1055   case Instruction::ZExt:
1056   case Instruction::SExt:
1057   case Instruction::FPToUI:
1058   case Instruction::FPToSI:
1059   case Instruction::FPExt:
1060   case Instruction::PtrToInt:
1061   case Instruction::IntToPtr:
1062   case Instruction::SIToFP:
1063   case Instruction::UIToFP:
1064   case Instruction::Trunc:
1065   case Instruction::FPTrunc:
1066   case Instruction::BitCast:
1067   case Instruction::AddrSpaceCast: {
1068     Type *SrcTy = I->getOperand(0)->getType();
1069     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1070   }
1071   case Instruction::ExtractElement: {
1072     const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1073     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1074     unsigned Idx = -1;
1075     if (CI)
1076       Idx = CI->getZExtValue();
1077 
1078     // Try to match a reduction sequence (series of shufflevector and vector
1079     // adds followed by a extractelement).
1080     unsigned ReduxOpCode;
1081     Type *ReduxType;
1082 
1083     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1084     case RK_Arithmetic:
1085       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1086                                              /*IsPairwiseForm=*/false);
1087     case RK_MinMax:
1088       return getMinMaxReductionCost(
1089           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1090           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1091     case RK_UnsignedMinMax:
1092       return getMinMaxReductionCost(
1093           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1094           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1095     case RK_None:
1096       break;
1097     }
1098 
1099     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1100     case RK_Arithmetic:
1101       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1102                                              /*IsPairwiseForm=*/true);
1103     case RK_MinMax:
1104       return getMinMaxReductionCost(
1105           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1106           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1107     case RK_UnsignedMinMax:
1108       return getMinMaxReductionCost(
1109           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1110           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1111     case RK_None:
1112       break;
1113     }
1114 
1115     return getVectorInstrCost(I->getOpcode(),
1116                                    EEI->getOperand(0)->getType(), Idx);
1117   }
1118   case Instruction::InsertElement: {
1119     const InsertElementInst * IE = cast<InsertElementInst>(I);
1120     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1121     unsigned Idx = -1;
1122     if (CI)
1123       Idx = CI->getZExtValue();
1124     return getVectorInstrCost(I->getOpcode(),
1125                                    IE->getType(), Idx);
1126   }
1127   case Instruction::ShuffleVector: {
1128     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1129     Type *Ty = Shuffle->getType();
1130     Type *SrcTy = Shuffle->getOperand(0)->getType();
1131 
1132     // TODO: Identify and add costs for insert subvector, etc.
1133     int SubIndex;
1134     if (Shuffle->isExtractSubvectorMask(SubIndex))
1135       return TTIImpl->getShuffleCost(SK_ExtractSubvector, SrcTy, SubIndex, Ty);
1136 
1137     if (Shuffle->changesLength())
1138       return -1;
1139 
1140     if (Shuffle->isIdentity())
1141       return 0;
1142 
1143     if (Shuffle->isReverse())
1144       return TTIImpl->getShuffleCost(SK_Reverse, Ty, 0, nullptr);
1145 
1146     if (Shuffle->isSelect())
1147       return TTIImpl->getShuffleCost(SK_Select, Ty, 0, nullptr);
1148 
1149     if (Shuffle->isTranspose())
1150       return TTIImpl->getShuffleCost(SK_Transpose, Ty, 0, nullptr);
1151 
1152     if (Shuffle->isZeroEltSplat())
1153       return TTIImpl->getShuffleCost(SK_Broadcast, Ty, 0, nullptr);
1154 
1155     if (Shuffle->isSingleSource())
1156       return TTIImpl->getShuffleCost(SK_PermuteSingleSrc, Ty, 0, nullptr);
1157 
1158     return TTIImpl->getShuffleCost(SK_PermuteTwoSrc, Ty, 0, nullptr);
1159   }
1160   case Instruction::Call:
1161     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1162       SmallVector<Value *, 4> Args(II->arg_operands());
1163 
1164       FastMathFlags FMF;
1165       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1166         FMF = FPMO->getFastMathFlags();
1167 
1168       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
1169                                         Args, FMF);
1170     }
1171     return -1;
1172   default:
1173     // We don't have any information on this instruction.
1174     return -1;
1175   }
1176 }
1177 
1178 TargetTransformInfo::Concept::~Concept() {}
1179 
1180 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1181 
1182 TargetIRAnalysis::TargetIRAnalysis(
1183     std::function<Result(const Function &)> TTICallback)
1184     : TTICallback(std::move(TTICallback)) {}
1185 
1186 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1187                                                FunctionAnalysisManager &) {
1188   return TTICallback(F);
1189 }
1190 
1191 AnalysisKey TargetIRAnalysis::Key;
1192 
1193 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1194   return Result(F.getParent()->getDataLayout());
1195 }
1196 
1197 // Register the basic pass.
1198 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1199                 "Target Transform Information", false, true)
1200 char TargetTransformInfoWrapperPass::ID = 0;
1201 
1202 void TargetTransformInfoWrapperPass::anchor() {}
1203 
1204 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1205     : ImmutablePass(ID) {
1206   initializeTargetTransformInfoWrapperPassPass(
1207       *PassRegistry::getPassRegistry());
1208 }
1209 
1210 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1211     TargetIRAnalysis TIRA)
1212     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1213   initializeTargetTransformInfoWrapperPassPass(
1214       *PassRegistry::getPassRegistry());
1215 }
1216 
1217 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1218   FunctionAnalysisManager DummyFAM;
1219   TTI = TIRA.run(F, DummyFAM);
1220   return *TTI;
1221 }
1222 
1223 ImmutablePass *
1224 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1225   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1226 }
1227