1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/Analysis/TargetTransformInfo.h"
11 #include "llvm/Analysis/TargetTransformInfoImpl.h"
12 #include "llvm/IR/CallSite.h"
13 #include "llvm/IR/DataLayout.h"
14 #include "llvm/IR/Instruction.h"
15 #include "llvm/IR/Instructions.h"
16 #include "llvm/IR/IntrinsicInst.h"
17 #include "llvm/IR/Module.h"
18 #include "llvm/IR/Operator.h"
19 #include "llvm/IR/PatternMatch.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include <utility>
23 
24 using namespace llvm;
25 using namespace PatternMatch;
26 
27 #define DEBUG_TYPE "tti"
28 
29 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
30                                      cl::Hidden,
31                                      cl::desc("Recognize reduction patterns."));
32 
33 namespace {
34 /// No-op implementation of the TTI interface using the utility base
35 /// classes.
36 ///
37 /// This is used when no target specific information is available.
38 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
39   explicit NoTTIImpl(const DataLayout &DL)
40       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
41 };
42 }
43 
44 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
45     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
46 
47 TargetTransformInfo::~TargetTransformInfo() {}
48 
49 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
50     : TTIImpl(std::move(Arg.TTIImpl)) {}
51 
52 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
53   TTIImpl = std::move(RHS.TTIImpl);
54   return *this;
55 }
56 
57 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
58                                           Type *OpTy) const {
59   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
60   assert(Cost >= 0 && "TTI should not produce negative costs!");
61   return Cost;
62 }
63 
64 int TargetTransformInfo::getCallCost(FunctionType *FTy, int NumArgs) const {
65   int Cost = TTIImpl->getCallCost(FTy, NumArgs);
66   assert(Cost >= 0 && "TTI should not produce negative costs!");
67   return Cost;
68 }
69 
70 int TargetTransformInfo::getCallCost(const Function *F,
71                                      ArrayRef<const Value *> Arguments) const {
72   int Cost = TTIImpl->getCallCost(F, Arguments);
73   assert(Cost >= 0 && "TTI should not produce negative costs!");
74   return Cost;
75 }
76 
77 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
78   return TTIImpl->getInliningThresholdMultiplier();
79 }
80 
81 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
82                                     ArrayRef<const Value *> Operands) const {
83   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
84 }
85 
86 int TargetTransformInfo::getExtCost(const Instruction *I,
87                                     const Value *Src) const {
88   return TTIImpl->getExtCost(I, Src);
89 }
90 
91 int TargetTransformInfo::getIntrinsicCost(
92     Intrinsic::ID IID, Type *RetTy, ArrayRef<const Value *> Arguments) const {
93   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments);
94   assert(Cost >= 0 && "TTI should not produce negative costs!");
95   return Cost;
96 }
97 
98 unsigned
99 TargetTransformInfo::getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
100                                                       unsigned &JTSize) const {
101   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize);
102 }
103 
104 int TargetTransformInfo::getUserCost(const User *U,
105     ArrayRef<const Value *> Operands) const {
106   int Cost = TTIImpl->getUserCost(U, Operands);
107   assert(Cost >= 0 && "TTI should not produce negative costs!");
108   return Cost;
109 }
110 
111 bool TargetTransformInfo::hasBranchDivergence() const {
112   return TTIImpl->hasBranchDivergence();
113 }
114 
115 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
116   return TTIImpl->isSourceOfDivergence(V);
117 }
118 
119 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
120   return TTIImpl->isAlwaysUniform(V);
121 }
122 
123 unsigned TargetTransformInfo::getFlatAddressSpace() const {
124   return TTIImpl->getFlatAddressSpace();
125 }
126 
127 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
128   return TTIImpl->isLoweredToCall(F);
129 }
130 
131 void TargetTransformInfo::getUnrollingPreferences(
132     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
133   return TTIImpl->getUnrollingPreferences(L, SE, UP);
134 }
135 
136 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
137   return TTIImpl->isLegalAddImmediate(Imm);
138 }
139 
140 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
141   return TTIImpl->isLegalICmpImmediate(Imm);
142 }
143 
144 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
145                                                 int64_t BaseOffset,
146                                                 bool HasBaseReg,
147                                                 int64_t Scale,
148                                                 unsigned AddrSpace,
149                                                 Instruction *I) const {
150   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
151                                         Scale, AddrSpace, I);
152 }
153 
154 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
155   return TTIImpl->isLSRCostLess(C1, C2);
156 }
157 
158 bool TargetTransformInfo::canMacroFuseCmp() const {
159   return TTIImpl->canMacroFuseCmp();
160 }
161 
162 bool TargetTransformInfo::shouldFavorPostInc() const {
163   return TTIImpl->shouldFavorPostInc();
164 }
165 
166 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType) const {
167   return TTIImpl->isLegalMaskedStore(DataType);
168 }
169 
170 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType) const {
171   return TTIImpl->isLegalMaskedLoad(DataType);
172 }
173 
174 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
175   return TTIImpl->isLegalMaskedGather(DataType);
176 }
177 
178 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
179   return TTIImpl->isLegalMaskedScatter(DataType);
180 }
181 
182 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
183   return TTIImpl->hasDivRemOp(DataType, IsSigned);
184 }
185 
186 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
187                                              unsigned AddrSpace) const {
188   return TTIImpl->hasVolatileVariant(I, AddrSpace);
189 }
190 
191 bool TargetTransformInfo::prefersVectorizedAddressing() const {
192   return TTIImpl->prefersVectorizedAddressing();
193 }
194 
195 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
196                                               int64_t BaseOffset,
197                                               bool HasBaseReg,
198                                               int64_t Scale,
199                                               unsigned AddrSpace) const {
200   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
201                                            Scale, AddrSpace);
202   assert(Cost >= 0 && "TTI should not produce negative costs!");
203   return Cost;
204 }
205 
206 bool TargetTransformInfo::LSRWithInstrQueries() const {
207   return TTIImpl->LSRWithInstrQueries();
208 }
209 
210 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
211   return TTIImpl->isTruncateFree(Ty1, Ty2);
212 }
213 
214 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
215   return TTIImpl->isProfitableToHoist(I);
216 }
217 
218 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
219 
220 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
221   return TTIImpl->isTypeLegal(Ty);
222 }
223 
224 unsigned TargetTransformInfo::getJumpBufAlignment() const {
225   return TTIImpl->getJumpBufAlignment();
226 }
227 
228 unsigned TargetTransformInfo::getJumpBufSize() const {
229   return TTIImpl->getJumpBufSize();
230 }
231 
232 bool TargetTransformInfo::shouldBuildLookupTables() const {
233   return TTIImpl->shouldBuildLookupTables();
234 }
235 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(Constant *C) const {
236   return TTIImpl->shouldBuildLookupTablesForConstant(C);
237 }
238 
239 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
240   return TTIImpl->useColdCCForColdCall(F);
241 }
242 
243 unsigned TargetTransformInfo::
244 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
245   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
246 }
247 
248 unsigned TargetTransformInfo::
249 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
250                                  unsigned VF) const {
251   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
252 }
253 
254 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
255   return TTIImpl->supportsEfficientVectorElementLoadStore();
256 }
257 
258 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
259   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
260 }
261 
262 const TargetTransformInfo::MemCmpExpansionOptions *
263 TargetTransformInfo::enableMemCmpExpansion(bool IsZeroCmp) const {
264   return TTIImpl->enableMemCmpExpansion(IsZeroCmp);
265 }
266 
267 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
268   return TTIImpl->enableInterleavedAccessVectorization();
269 }
270 
271 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const {
272   return TTIImpl->enableMaskedInterleavedAccessVectorization();
273 }
274 
275 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
276   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
277 }
278 
279 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
280                                                          unsigned BitWidth,
281                                                          unsigned AddressSpace,
282                                                          unsigned Alignment,
283                                                          bool *Fast) const {
284   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
285                                                  Alignment, Fast);
286 }
287 
288 TargetTransformInfo::PopcntSupportKind
289 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
290   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
291 }
292 
293 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
294   return TTIImpl->haveFastSqrt(Ty);
295 }
296 
297 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
298   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
299 }
300 
301 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
302   int Cost = TTIImpl->getFPOpCost(Ty);
303   assert(Cost >= 0 && "TTI should not produce negative costs!");
304   return Cost;
305 }
306 
307 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
308                                                const APInt &Imm,
309                                                Type *Ty) const {
310   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
311   assert(Cost >= 0 && "TTI should not produce negative costs!");
312   return Cost;
313 }
314 
315 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
316   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
317   assert(Cost >= 0 && "TTI should not produce negative costs!");
318   return Cost;
319 }
320 
321 int TargetTransformInfo::getIntImmCost(unsigned Opcode, unsigned Idx,
322                                        const APInt &Imm, Type *Ty) const {
323   int Cost = TTIImpl->getIntImmCost(Opcode, Idx, Imm, Ty);
324   assert(Cost >= 0 && "TTI should not produce negative costs!");
325   return Cost;
326 }
327 
328 int TargetTransformInfo::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
329                                        const APInt &Imm, Type *Ty) const {
330   int Cost = TTIImpl->getIntImmCost(IID, Idx, Imm, Ty);
331   assert(Cost >= 0 && "TTI should not produce negative costs!");
332   return Cost;
333 }
334 
335 unsigned TargetTransformInfo::getNumberOfRegisters(bool Vector) const {
336   return TTIImpl->getNumberOfRegisters(Vector);
337 }
338 
339 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
340   return TTIImpl->getRegisterBitWidth(Vector);
341 }
342 
343 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
344   return TTIImpl->getMinVectorRegisterBitWidth();
345 }
346 
347 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
348   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
349 }
350 
351 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
352   return TTIImpl->getMinimumVF(ElemWidth);
353 }
354 
355 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
356     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
357   return TTIImpl->shouldConsiderAddressTypePromotion(
358       I, AllowPromotionWithoutCommonHeader);
359 }
360 
361 unsigned TargetTransformInfo::getCacheLineSize() const {
362   return TTIImpl->getCacheLineSize();
363 }
364 
365 llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
366   const {
367   return TTIImpl->getCacheSize(Level);
368 }
369 
370 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
371   CacheLevel Level) const {
372   return TTIImpl->getCacheAssociativity(Level);
373 }
374 
375 unsigned TargetTransformInfo::getPrefetchDistance() const {
376   return TTIImpl->getPrefetchDistance();
377 }
378 
379 unsigned TargetTransformInfo::getMinPrefetchStride() const {
380   return TTIImpl->getMinPrefetchStride();
381 }
382 
383 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
384   return TTIImpl->getMaxPrefetchIterationsAhead();
385 }
386 
387 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
388   return TTIImpl->getMaxInterleaveFactor(VF);
389 }
390 
391 TargetTransformInfo::OperandValueKind
392 TargetTransformInfo::getOperandInfo(Value *V,
393                                     OperandValueProperties &OpProps) const {
394   OperandValueKind OpInfo = OK_AnyValue;
395   OpProps = OP_None;
396 
397   if (auto *CI = dyn_cast<ConstantInt>(V)) {
398     if (CI->getValue().isPowerOf2())
399       OpProps = OP_PowerOf2;
400     return OK_UniformConstantValue;
401   }
402 
403   const Value *Splat = getSplatValue(V);
404 
405   // Check for a splat of a constant or for a non uniform vector of constants
406   // and check if the constant(s) are all powers of two.
407   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
408     OpInfo = OK_NonUniformConstantValue;
409     if (Splat) {
410       OpInfo = OK_UniformConstantValue;
411       if (auto *CI = dyn_cast<ConstantInt>(Splat))
412         if (CI->getValue().isPowerOf2())
413           OpProps = OP_PowerOf2;
414     } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
415       OpProps = OP_PowerOf2;
416       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
417         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
418           if (CI->getValue().isPowerOf2())
419             continue;
420         OpProps = OP_None;
421         break;
422       }
423     }
424   }
425 
426   // Check for a splat of a uniform value. This is not loop aware, so return
427   // true only for the obviously uniform cases (argument, globalvalue)
428   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
429     OpInfo = OK_UniformValue;
430 
431   return OpInfo;
432 }
433 
434 int TargetTransformInfo::getArithmeticInstrCost(
435     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
436     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
437     OperandValueProperties Opd2PropInfo,
438     ArrayRef<const Value *> Args) const {
439   int Cost = TTIImpl->getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
440                                              Opd1PropInfo, Opd2PropInfo, Args);
441   assert(Cost >= 0 && "TTI should not produce negative costs!");
442   return Cost;
443 }
444 
445 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
446                                         Type *SubTp) const {
447   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
448   assert(Cost >= 0 && "TTI should not produce negative costs!");
449   return Cost;
450 }
451 
452 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
453                                  Type *Src, const Instruction *I) const {
454   assert ((I == nullptr || I->getOpcode() == Opcode) &&
455           "Opcode should reflect passed instruction.");
456   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
457   assert(Cost >= 0 && "TTI should not produce negative costs!");
458   return Cost;
459 }
460 
461 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
462                                                   VectorType *VecTy,
463                                                   unsigned Index) const {
464   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
465   assert(Cost >= 0 && "TTI should not produce negative costs!");
466   return Cost;
467 }
468 
469 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
470   int Cost = TTIImpl->getCFInstrCost(Opcode);
471   assert(Cost >= 0 && "TTI should not produce negative costs!");
472   return Cost;
473 }
474 
475 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
476                                  Type *CondTy, const Instruction *I) const {
477   assert ((I == nullptr || I->getOpcode() == Opcode) &&
478           "Opcode should reflect passed instruction.");
479   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
480   assert(Cost >= 0 && "TTI should not produce negative costs!");
481   return Cost;
482 }
483 
484 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
485                                             unsigned Index) const {
486   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
487   assert(Cost >= 0 && "TTI should not produce negative costs!");
488   return Cost;
489 }
490 
491 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
492                                          unsigned Alignment,
493                                          unsigned AddressSpace,
494                                          const Instruction *I) const {
495   assert ((I == nullptr || I->getOpcode() == Opcode) &&
496           "Opcode should reflect passed instruction.");
497   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
498   assert(Cost >= 0 && "TTI should not produce negative costs!");
499   return Cost;
500 }
501 
502 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
503                                                unsigned Alignment,
504                                                unsigned AddressSpace) const {
505   int Cost =
506       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
507   assert(Cost >= 0 && "TTI should not produce negative costs!");
508   return Cost;
509 }
510 
511 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
512                                                 Value *Ptr, bool VariableMask,
513                                                 unsigned Alignment) const {
514   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
515                                              Alignment);
516   assert(Cost >= 0 && "TTI should not produce negative costs!");
517   return Cost;
518 }
519 
520 int TargetTransformInfo::getInterleavedMemoryOpCost(
521     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
522     unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond,
523     bool UseMaskForGaps) const {
524   int Cost = TTIImpl->getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
525                                                  Alignment, AddressSpace,
526                                                  UseMaskForCond,
527                                                  UseMaskForGaps);
528   assert(Cost >= 0 && "TTI should not produce negative costs!");
529   return Cost;
530 }
531 
532 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
533                                     ArrayRef<Type *> Tys, FastMathFlags FMF,
534                                     unsigned ScalarizationCostPassed) const {
535   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
536                                             ScalarizationCostPassed);
537   assert(Cost >= 0 && "TTI should not produce negative costs!");
538   return Cost;
539 }
540 
541 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
542            ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) const {
543   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
544   assert(Cost >= 0 && "TTI should not produce negative costs!");
545   return Cost;
546 }
547 
548 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
549                                           ArrayRef<Type *> Tys) const {
550   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
551   assert(Cost >= 0 && "TTI should not produce negative costs!");
552   return Cost;
553 }
554 
555 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
556   return TTIImpl->getNumberOfParts(Tp);
557 }
558 
559 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
560                                                    ScalarEvolution *SE,
561                                                    const SCEV *Ptr) const {
562   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
563   assert(Cost >= 0 && "TTI should not produce negative costs!");
564   return Cost;
565 }
566 
567 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
568                                                     bool IsPairwiseForm) const {
569   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
570   assert(Cost >= 0 && "TTI should not produce negative costs!");
571   return Cost;
572 }
573 
574 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
575                                                 bool IsPairwiseForm,
576                                                 bool IsUnsigned) const {
577   int Cost =
578       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
579   assert(Cost >= 0 && "TTI should not produce negative costs!");
580   return Cost;
581 }
582 
583 unsigned
584 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
585   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
586 }
587 
588 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
589                                              MemIntrinsicInfo &Info) const {
590   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
591 }
592 
593 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
594   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
595 }
596 
597 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
598     IntrinsicInst *Inst, Type *ExpectedType) const {
599   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
600 }
601 
602 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
603                                                      Value *Length,
604                                                      unsigned SrcAlign,
605                                                      unsigned DestAlign) const {
606   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
607                                             DestAlign);
608 }
609 
610 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
611     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
612     unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
613   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
614                                              SrcAlign, DestAlign);
615 }
616 
617 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
618                                               const Function *Callee) const {
619   return TTIImpl->areInlineCompatible(Caller, Callee);
620 }
621 
622 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
623                                              Type *Ty) const {
624   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
625 }
626 
627 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
628                                               Type *Ty) const {
629   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
630 }
631 
632 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
633   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
634 }
635 
636 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
637   return TTIImpl->isLegalToVectorizeLoad(LI);
638 }
639 
640 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
641   return TTIImpl->isLegalToVectorizeStore(SI);
642 }
643 
644 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
645     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
646   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
647                                               AddrSpace);
648 }
649 
650 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
651     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
652   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
653                                                AddrSpace);
654 }
655 
656 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
657                                                   unsigned LoadSize,
658                                                   unsigned ChainSizeInBytes,
659                                                   VectorType *VecTy) const {
660   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
661 }
662 
663 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
664                                                    unsigned StoreSize,
665                                                    unsigned ChainSizeInBytes,
666                                                    VectorType *VecTy) const {
667   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
668 }
669 
670 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode,
671                                                 Type *Ty, ReductionFlags Flags) const {
672   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
673 }
674 
675 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
676   return TTIImpl->shouldExpandReduction(II);
677 }
678 
679 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
680   return TTIImpl->getInstructionLatency(I);
681 }
682 
683 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
684                                      unsigned Level) {
685   // We don't need a shuffle if we just want to have element 0 in position 0 of
686   // the vector.
687   if (!SI && Level == 0 && IsLeft)
688     return true;
689   else if (!SI)
690     return false;
691 
692   SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
693 
694   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
695   // we look at the left or right side.
696   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
697     Mask[i] = val;
698 
699   SmallVector<int, 16> ActualMask = SI->getShuffleMask();
700   return Mask == ActualMask;
701 }
702 
703 namespace {
704 /// Kind of the reduction data.
705 enum ReductionKind {
706   RK_None,           /// Not a reduction.
707   RK_Arithmetic,     /// Binary reduction data.
708   RK_MinMax,         /// Min/max reduction data.
709   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
710 };
711 /// Contains opcode + LHS/RHS parts of the reduction operations.
712 struct ReductionData {
713   ReductionData() = delete;
714   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
715       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
716     assert(Kind != RK_None && "expected binary or min/max reduction only.");
717   }
718   unsigned Opcode = 0;
719   Value *LHS = nullptr;
720   Value *RHS = nullptr;
721   ReductionKind Kind = RK_None;
722   bool hasSameData(ReductionData &RD) const {
723     return Kind == RD.Kind && Opcode == RD.Opcode;
724   }
725 };
726 } // namespace
727 
728 static Optional<ReductionData> getReductionData(Instruction *I) {
729   Value *L, *R;
730   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
731     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
732   if (auto *SI = dyn_cast<SelectInst>(I)) {
733     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
734         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
735         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
736         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
737         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
738         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
739       auto *CI = cast<CmpInst>(SI->getCondition());
740       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
741     }
742     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
743         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
744       auto *CI = cast<CmpInst>(SI->getCondition());
745       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
746     }
747   }
748   return llvm::None;
749 }
750 
751 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
752                                                    unsigned Level,
753                                                    unsigned NumLevels) {
754   // Match one level of pairwise operations.
755   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
756   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
757   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
758   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
759   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
760   if (!I)
761     return RK_None;
762 
763   assert(I->getType()->isVectorTy() && "Expecting a vector type");
764 
765   Optional<ReductionData> RD = getReductionData(I);
766   if (!RD)
767     return RK_None;
768 
769   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
770   if (!LS && Level)
771     return RK_None;
772   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
773   if (!RS && Level)
774     return RK_None;
775 
776   // On level 0 we can omit one shufflevector instruction.
777   if (!Level && !RS && !LS)
778     return RK_None;
779 
780   // Shuffle inputs must match.
781   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
782   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
783   Value *NextLevelOp = nullptr;
784   if (NextLevelOpR && NextLevelOpL) {
785     // If we have two shuffles their operands must match.
786     if (NextLevelOpL != NextLevelOpR)
787       return RK_None;
788 
789     NextLevelOp = NextLevelOpL;
790   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
791     // On the first level we can omit the shufflevector <0, undef,...>. So the
792     // input to the other shufflevector <1, undef> must match with one of the
793     // inputs to the current binary operation.
794     // Example:
795     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
796     //  %BinOp        = fadd          %NextLevelOpL, %R
797     if (NextLevelOpL && NextLevelOpL != RD->RHS)
798       return RK_None;
799     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
800       return RK_None;
801 
802     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
803   } else
804     return RK_None;
805 
806   // Check that the next levels binary operation exists and matches with the
807   // current one.
808   if (Level + 1 != NumLevels) {
809     Optional<ReductionData> NextLevelRD =
810         getReductionData(cast<Instruction>(NextLevelOp));
811     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
812       return RK_None;
813   }
814 
815   // Shuffle mask for pairwise operation must match.
816   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
817     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
818       return RK_None;
819   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
820     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
821       return RK_None;
822   } else {
823     return RK_None;
824   }
825 
826   if (++Level == NumLevels)
827     return RD->Kind;
828 
829   // Match next level.
830   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
831                                        NumLevels);
832 }
833 
834 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
835                                             unsigned &Opcode, Type *&Ty) {
836   if (!EnableReduxCost)
837     return RK_None;
838 
839   // Need to extract the first element.
840   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
841   unsigned Idx = ~0u;
842   if (CI)
843     Idx = CI->getZExtValue();
844   if (Idx != 0)
845     return RK_None;
846 
847   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
848   if (!RdxStart)
849     return RK_None;
850   Optional<ReductionData> RD = getReductionData(RdxStart);
851   if (!RD)
852     return RK_None;
853 
854   Type *VecTy = RdxStart->getType();
855   unsigned NumVecElems = VecTy->getVectorNumElements();
856   if (!isPowerOf2_32(NumVecElems))
857     return RK_None;
858 
859   // We look for a sequence of shuffle,shuffle,add triples like the following
860   // that builds a pairwise reduction tree.
861   //
862   //  (X0, X1, X2, X3)
863   //   (X0 + X1, X2 + X3, undef, undef)
864   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
865   //
866   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
867   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
868   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
869   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
870   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
871   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
872   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
873   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
874   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
875   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
876   // %r = extractelement <4 x float> %bin.rdx8, i32 0
877   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
878       RK_None)
879     return RK_None;
880 
881   Opcode = RD->Opcode;
882   Ty = VecTy;
883 
884   return RD->Kind;
885 }
886 
887 static std::pair<Value *, ShuffleVectorInst *>
888 getShuffleAndOtherOprd(Value *L, Value *R) {
889   ShuffleVectorInst *S = nullptr;
890 
891   if ((S = dyn_cast<ShuffleVectorInst>(L)))
892     return std::make_pair(R, S);
893 
894   S = dyn_cast<ShuffleVectorInst>(R);
895   return std::make_pair(L, S);
896 }
897 
898 static ReductionKind
899 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
900                               unsigned &Opcode, Type *&Ty) {
901   if (!EnableReduxCost)
902     return RK_None;
903 
904   // Need to extract the first element.
905   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
906   unsigned Idx = ~0u;
907   if (CI)
908     Idx = CI->getZExtValue();
909   if (Idx != 0)
910     return RK_None;
911 
912   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
913   if (!RdxStart)
914     return RK_None;
915   Optional<ReductionData> RD = getReductionData(RdxStart);
916   if (!RD)
917     return RK_None;
918 
919   Type *VecTy = ReduxRoot->getOperand(0)->getType();
920   unsigned NumVecElems = VecTy->getVectorNumElements();
921   if (!isPowerOf2_32(NumVecElems))
922     return RK_None;
923 
924   // We look for a sequence of shuffles and adds like the following matching one
925   // fadd, shuffle vector pair at a time.
926   //
927   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
928   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
929   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
930   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
931   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
932   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
933   // %r = extractelement <4 x float> %bin.rdx8, i32 0
934 
935   unsigned MaskStart = 1;
936   Instruction *RdxOp = RdxStart;
937   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
938   unsigned NumVecElemsRemain = NumVecElems;
939   while (NumVecElemsRemain - 1) {
940     // Check for the right reduction operation.
941     if (!RdxOp)
942       return RK_None;
943     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
944     if (!RDLevel || !RDLevel->hasSameData(*RD))
945       return RK_None;
946 
947     Value *NextRdxOp;
948     ShuffleVectorInst *Shuffle;
949     std::tie(NextRdxOp, Shuffle) =
950         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
951 
952     // Check the current reduction operation and the shuffle use the same value.
953     if (Shuffle == nullptr)
954       return RK_None;
955     if (Shuffle->getOperand(0) != NextRdxOp)
956       return RK_None;
957 
958     // Check that shuffle masks matches.
959     for (unsigned j = 0; j != MaskStart; ++j)
960       ShuffleMask[j] = MaskStart + j;
961     // Fill the rest of the mask with -1 for undef.
962     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
963 
964     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
965     if (ShuffleMask != Mask)
966       return RK_None;
967 
968     RdxOp = dyn_cast<Instruction>(NextRdxOp);
969     NumVecElemsRemain /= 2;
970     MaskStart *= 2;
971   }
972 
973   Opcode = RD->Opcode;
974   Ty = VecTy;
975   return RD->Kind;
976 }
977 
978 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
979   switch (I->getOpcode()) {
980   case Instruction::GetElementPtr:
981     return getUserCost(I);
982 
983   case Instruction::Ret:
984   case Instruction::PHI:
985   case Instruction::Br: {
986     return getCFInstrCost(I->getOpcode());
987   }
988   case Instruction::Add:
989   case Instruction::FAdd:
990   case Instruction::Sub:
991   case Instruction::FSub:
992   case Instruction::Mul:
993   case Instruction::FMul:
994   case Instruction::UDiv:
995   case Instruction::SDiv:
996   case Instruction::FDiv:
997   case Instruction::URem:
998   case Instruction::SRem:
999   case Instruction::FRem:
1000   case Instruction::Shl:
1001   case Instruction::LShr:
1002   case Instruction::AShr:
1003   case Instruction::And:
1004   case Instruction::Or:
1005   case Instruction::Xor: {
1006     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1007     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1008     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1009     Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1010     SmallVector<const Value *, 2> Operands(I->operand_values());
1011     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1012                                   Op1VP, Op2VP, Operands);
1013   }
1014   case Instruction::Select: {
1015     const SelectInst *SI = cast<SelectInst>(I);
1016     Type *CondTy = SI->getCondition()->getType();
1017     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1018   }
1019   case Instruction::ICmp:
1020   case Instruction::FCmp: {
1021     Type *ValTy = I->getOperand(0)->getType();
1022     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1023   }
1024   case Instruction::Store: {
1025     const StoreInst *SI = cast<StoreInst>(I);
1026     Type *ValTy = SI->getValueOperand()->getType();
1027     return getMemoryOpCost(I->getOpcode(), ValTy,
1028                                 SI->getAlignment(),
1029                                 SI->getPointerAddressSpace(), I);
1030   }
1031   case Instruction::Load: {
1032     const LoadInst *LI = cast<LoadInst>(I);
1033     return getMemoryOpCost(I->getOpcode(), I->getType(),
1034                                 LI->getAlignment(),
1035                                 LI->getPointerAddressSpace(), I);
1036   }
1037   case Instruction::ZExt:
1038   case Instruction::SExt:
1039   case Instruction::FPToUI:
1040   case Instruction::FPToSI:
1041   case Instruction::FPExt:
1042   case Instruction::PtrToInt:
1043   case Instruction::IntToPtr:
1044   case Instruction::SIToFP:
1045   case Instruction::UIToFP:
1046   case Instruction::Trunc:
1047   case Instruction::FPTrunc:
1048   case Instruction::BitCast:
1049   case Instruction::AddrSpaceCast: {
1050     Type *SrcTy = I->getOperand(0)->getType();
1051     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1052   }
1053   case Instruction::ExtractElement: {
1054     const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1055     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1056     unsigned Idx = -1;
1057     if (CI)
1058       Idx = CI->getZExtValue();
1059 
1060     // Try to match a reduction sequence (series of shufflevector and vector
1061     // adds followed by a extractelement).
1062     unsigned ReduxOpCode;
1063     Type *ReduxType;
1064 
1065     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1066     case RK_Arithmetic:
1067       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1068                                              /*IsPairwiseForm=*/false);
1069     case RK_MinMax:
1070       return getMinMaxReductionCost(
1071           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1072           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1073     case RK_UnsignedMinMax:
1074       return getMinMaxReductionCost(
1075           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1076           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1077     case RK_None:
1078       break;
1079     }
1080 
1081     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1082     case RK_Arithmetic:
1083       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1084                                              /*IsPairwiseForm=*/true);
1085     case RK_MinMax:
1086       return getMinMaxReductionCost(
1087           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1088           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1089     case RK_UnsignedMinMax:
1090       return getMinMaxReductionCost(
1091           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1092           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1093     case RK_None:
1094       break;
1095     }
1096 
1097     return getVectorInstrCost(I->getOpcode(),
1098                                    EEI->getOperand(0)->getType(), Idx);
1099   }
1100   case Instruction::InsertElement: {
1101     const InsertElementInst * IE = cast<InsertElementInst>(I);
1102     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1103     unsigned Idx = -1;
1104     if (CI)
1105       Idx = CI->getZExtValue();
1106     return getVectorInstrCost(I->getOpcode(),
1107                                    IE->getType(), Idx);
1108   }
1109   case Instruction::ShuffleVector: {
1110     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1111     // TODO: Identify and add costs for insert/extract subvector, etc.
1112     if (Shuffle->changesLength())
1113       return -1;
1114 
1115     if (Shuffle->isIdentity())
1116       return 0;
1117 
1118     Type *Ty = Shuffle->getType();
1119     if (Shuffle->isReverse())
1120       return TTIImpl->getShuffleCost(SK_Reverse, Ty, 0, nullptr);
1121 
1122     if (Shuffle->isSelect())
1123       return TTIImpl->getShuffleCost(SK_Select, Ty, 0, nullptr);
1124 
1125     if (Shuffle->isTranspose())
1126       return TTIImpl->getShuffleCost(SK_Transpose, Ty, 0, nullptr);
1127 
1128     if (Shuffle->isZeroEltSplat())
1129       return TTIImpl->getShuffleCost(SK_Broadcast, Ty, 0, nullptr);
1130 
1131     if (Shuffle->isSingleSource())
1132       return TTIImpl->getShuffleCost(SK_PermuteSingleSrc, Ty, 0, nullptr);
1133 
1134     return TTIImpl->getShuffleCost(SK_PermuteTwoSrc, Ty, 0, nullptr);
1135   }
1136   case Instruction::Call:
1137     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1138       SmallVector<Value *, 4> Args(II->arg_operands());
1139 
1140       FastMathFlags FMF;
1141       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1142         FMF = FPMO->getFastMathFlags();
1143 
1144       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
1145                                         Args, FMF);
1146     }
1147     return -1;
1148   default:
1149     // We don't have any information on this instruction.
1150     return -1;
1151   }
1152 }
1153 
1154 TargetTransformInfo::Concept::~Concept() {}
1155 
1156 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1157 
1158 TargetIRAnalysis::TargetIRAnalysis(
1159     std::function<Result(const Function &)> TTICallback)
1160     : TTICallback(std::move(TTICallback)) {}
1161 
1162 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1163                                                FunctionAnalysisManager &) {
1164   return TTICallback(F);
1165 }
1166 
1167 AnalysisKey TargetIRAnalysis::Key;
1168 
1169 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1170   return Result(F.getParent()->getDataLayout());
1171 }
1172 
1173 // Register the basic pass.
1174 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1175                 "Target Transform Information", false, true)
1176 char TargetTransformInfoWrapperPass::ID = 0;
1177 
1178 void TargetTransformInfoWrapperPass::anchor() {}
1179 
1180 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1181     : ImmutablePass(ID) {
1182   initializeTargetTransformInfoWrapperPassPass(
1183       *PassRegistry::getPassRegistry());
1184 }
1185 
1186 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1187     TargetIRAnalysis TIRA)
1188     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1189   initializeTargetTransformInfoWrapperPassPass(
1190       *PassRegistry::getPassRegistry());
1191 }
1192 
1193 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1194   FunctionAnalysisManager DummyFAM;
1195   TTI = TIRA.run(F, DummyFAM);
1196   return *TTI;
1197 }
1198 
1199 ImmutablePass *
1200 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1201   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1202 }
1203