1 2.. _gmir-opcodes: 3 4Generic Opcodes 5=============== 6 7.. contents:: 8 :local: 9 10.. note:: 11 12 This documentation does not yet fully account for vectors. Many of the 13 scalar/integer/floating-point operations can also take vectors. 14 15Constants 16--------- 17 18G_IMPLICIT_DEF 19^^^^^^^^^^^^^^ 20 21An undefined value. 22 23.. code-block:: none 24 25 %0:_(s32) = G_IMPLICIT_DEF 26 27G_CONSTANT 28^^^^^^^^^^ 29 30An integer constant. 31 32.. code-block:: none 33 34 %0:_(s32) = G_CONSTANT i32 1 35 36G_FCONSTANT 37^^^^^^^^^^^ 38 39A floating point constant. 40 41.. code-block:: none 42 43 %0:_(s32) = G_FCONSTANT float 1.0 44 45G_FRAME_INDEX 46^^^^^^^^^^^^^ 47 48The address of an object in the stack frame. 49 50.. code-block:: none 51 52 %1:_(p0) = G_FRAME_INDEX %stack.0.ptr0 53 54G_GLOBAL_VALUE 55^^^^^^^^^^^^^^ 56 57The address of a global value. 58 59.. code-block:: none 60 61 %0(p0) = G_GLOBAL_VALUE @var_local 62 63G_BLOCK_ADDR 64^^^^^^^^^^^^ 65 66The address of a basic block. 67 68.. code-block:: none 69 70 %0:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block) 71 72Integer Extension and Truncation 73-------------------------------- 74 75G_ANYEXT 76^^^^^^^^ 77 78Extend the underlying scalar type of an operation, leaving the high bits 79unspecified. 80 81.. code-block:: none 82 83 %1:_(s32) = G_ANYEXT %0:_(s16) 84 85G_SEXT 86^^^^^^ 87 88Sign extend the underlying scalar type of an operation, copying the sign bit 89into the newly-created space. 90 91.. code-block:: none 92 93 %1:_(s32) = G_SEXT %0:_(s16) 94 95G_SEXT_INREG 96^^^^^^^^^^^^ 97 98Sign extend the value from an arbitrary bit position, copying the sign bit 99into all bits above it. This is equivalent to a shl + ashr pair with an 100appropriate shift amount. $sz is an immediate (MachineOperand::isImm() 101returns true) to allow targets to have some bitwidths legal and others 102lowered. This opcode is particularly useful if the target has sign-extension 103instructions that are cheaper than the constituent shifts as the optimizer is 104able to make decisions on whether it's better to hang on to the G_SEXT_INREG 105or to lower it and optimize the individual shifts. 106 107.. code-block:: none 108 109 %1:_(s32) = G_SEXT_INREG %0:_(s32), 16 110 111G_ZEXT 112^^^^^^ 113 114Zero extend the underlying scalar type of an operation, putting zero bits 115into the newly-created space. 116 117.. code-block:: none 118 119 %1:_(s32) = G_ZEXT %0:_(s16) 120 121G_TRUNC 122^^^^^^^ 123 124Truncate the underlying scalar type of an operation. This is equivalent to 125G_EXTRACT for scalar types, but acts elementwise on vectors. 126 127.. code-block:: none 128 129 %1:_(s16) = G_TRUNC %0:_(s32) 130 131Type Conversions 132---------------- 133 134G_INTTOPTR 135^^^^^^^^^^ 136 137Convert an integer to a pointer. 138 139.. code-block:: none 140 141 %1:_(p0) = G_INTTOPTR %0:_(s32) 142 143G_PTRTOINT 144^^^^^^^^^^ 145 146Convert a pointer to an integer. 147 148.. code-block:: none 149 150 %1:_(s32) = G_PTRTOINT %0:_(p0) 151 152G_BITCAST 153^^^^^^^^^ 154 155Reinterpret a value as a new type. This is usually done without 156changing any bits but this is not always the case due a subtlety in the 157definition of the :ref:`LLVM-IR Bitcast Instruction <i_bitcast>`. It 158is allowed to bitcast between pointers with the same size, but 159different address spaces. 160 161.. code-block:: none 162 163 %1:_(s64) = G_BITCAST %0:_(<2 x s32>) 164 165G_ADDRSPACE_CAST 166^^^^^^^^^^^^^^^^ 167 168Convert a pointer to an address space to a pointer to another address space. 169 170.. code-block:: none 171 172 %1:_(p1) = G_ADDRSPACE_CAST %0:_(p0) 173 174.. caution:: 175 176 :ref:`i_addrspacecast` doesn't mention what happens if the cast is simply 177 invalid (i.e. if the address spaces are disjoint). 178 179Scalar Operations 180----------------- 181 182G_EXTRACT 183^^^^^^^^^ 184 185Extract a register of the specified size, starting from the block given by 186index. This will almost certainly be mapped to sub-register COPYs after 187register banks have been selected. 188 189G_INSERT 190^^^^^^^^ 191 192Insert a smaller register into a larger one at the specified bit-index. 193 194G_MERGE_VALUES 195^^^^^^^^^^^^^^ 196 197Concatenate multiple registers of the same size into a wider register. 198The input operands are always ordered from lowest bits to highest: 199 200.. code-block:: none 201 202 %0:(s32) = G_MERGE_VALUES %bits_0_7:(s8), %bits_8_15:(s8), 203 %bits_16_23:(s8), %bits_24_31:(s8) 204 205G_UNMERGE_VALUES 206^^^^^^^^^^^^^^^^ 207 208Extract multiple registers of the specified size, starting from blocks given by 209indexes. This will almost certainly be mapped to sub-register COPYs after 210register banks have been selected. 211The output operands are always ordered from lowest bits to highest: 212 213.. code-block:: none 214 215 %bits_0_7:(s8), %bits_8_15:(s8), 216 %bits_16_23:(s8), %bits_24_31:(s8) = G_UNMERGE_VALUES %0:(s32) 217 218G_BSWAP 219^^^^^^^ 220 221Reverse the order of the bytes in a scalar. 222 223.. code-block:: none 224 225 %1:_(s32) = G_BSWAP %0:_(s32) 226 227G_BITREVERSE 228^^^^^^^^^^^^ 229 230Reverse the order of the bits in a scalar. 231 232.. code-block:: none 233 234 %1:_(s32) = G_BITREVERSE %0:_(s32) 235 236G_SBFX, G_UBFX 237^^^^^^^^^^^^^^ 238 239Extract a range of bits from a register. 240 241The source operands are registers as follows: 242 243- Source 244- The least-significant bit for the extraction 245- The width of the extraction 246 247G_SBFX sign-extends the result, while G_UBFX zero-extends the result. 248 249.. code-block:: none 250 251 ; Extract 5 bits starting at bit 1 from %x and store them in %a. 252 ; Sign-extend the result. 253 ; 254 ; Example: 255 ; %x = 0...0000[10110]1 ---> %a = 1...111111[10110] 256 %lsb_one = G_CONSTANT i32 1 257 %width_five = G_CONSTANT i32 5 258 %a:_(s32) = G_SBFX %x, %lsb_one, %width_five 259 260 ; Extract 3 bits starting at bit 2 from %x and store them in %b. Zero-extend 261 ; the result. 262 ; 263 ; Example: 264 ; %x = 1...11111[100]11 ---> %b = 0...00000[100] 265 %lsb_two = G_CONSTANT i32 2 266 %width_three = G_CONSTANT i32 3 267 %b:_(s32) = G_UBFX %x, %lsb_two, %width_three 268 269Integer Operations 270------------------- 271 272G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, G_SDIV, G_UDIV, G_SREM, G_UREM 273^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 274 275These each perform their respective integer arithmetic on a scalar. 276 277.. code-block:: none 278 279 %2:_(s32) = G_ADD %0:_(s32), %1:_(s32) 280 281G_SDIVREM, G_UDIVREM 282^^^^^^^^^^^^^^^^^^^^ 283 284Perform integer division and remainder thereby producing two results. 285 286.. code-block:: none 287 288 %div:_(s32), %rem:_(s32) = G_SDIVREM %0:_(s32), %1:_(s32) 289 290G_SADDSAT, G_UADDSAT, G_SSUBSAT, G_USUBSAT, G_SSHLSAT, G_USHLSAT 291^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 292 293Signed and unsigned addition, subtraction and left shift with saturation. 294 295.. code-block:: none 296 297 %2:_(s32) = G_SADDSAT %0:_(s32), %1:_(s32) 298 299G_SHL, G_LSHR, G_ASHR 300^^^^^^^^^^^^^^^^^^^^^ 301 302Shift the bits of a scalar left or right inserting zeros (sign-bit for G_ASHR). 303 304G_ICMP 305^^^^^^ 306 307Perform integer comparison producing non-zero (true) or zero (false). It's 308target specific whether a true value is 1, ~0U, or some other non-zero value. 309 310G_SELECT 311^^^^^^^^ 312 313Select between two values depending on a zero/non-zero value. 314 315.. code-block:: none 316 317 %5:_(s32) = G_SELECT %4(s1), %6, %2 318 319G_PTR_ADD 320^^^^^^^^^ 321 322Add a scalar offset in addressible units to a pointer. Addressible units are 323typically bytes but this may vary between targets. 324 325.. code-block:: none 326 327 %1:_(p0) = G_PTR_ADD %0:_(p0), %1:_(s32) 328 329.. caution:: 330 331 There are currently no in-tree targets that use this with addressable units 332 not equal to 8 bit. 333 334G_PTRMASK 335^^^^^^^^^^ 336 337Zero out an arbitrary mask of bits of a pointer. The mask type must be 338an integer, and the number of vector elements must match for all 339operands. This corresponds to `i_intr_llvm_ptrmask`. 340 341.. code-block:: none 342 343 %2:_(p0) = G_PTRMASK %0, %1 344 345G_SMIN, G_SMAX, G_UMIN, G_UMAX 346^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 347 348Take the minimum/maximum of two values. 349 350.. code-block:: none 351 352 %5:_(s32) = G_SMIN %6, %2 353 354G_ABS 355^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 356 357Take the absolute value of a signed integer. The absolute value of the minimum 358negative value (e.g. the 8-bit value `0x80`) is defined to be itself. 359 360.. code-block:: none 361 362 %1:_(s32) = G_ABS %0 363 364G_UADDO, G_SADDO, G_USUBO, G_SSUBO, G_SMULO, G_UMULO 365^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 366 367Perform the requested arithmetic and produce a carry output in addition to the 368normal result. 369 370.. code-block:: none 371 372 %3:_(s32), %4:_(s1) = G_UADDO %0, %1 373 374G_UADDE, G_SADDE, G_USUBE, G_SSUBE 375^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 376 377Perform the requested arithmetic and consume a carry input in addition to the 378normal input. Also produce a carry output in addition to the normal result. 379 380.. code-block:: none 381 382 %4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3:_(s1) 383 384G_UMULH, G_SMULH 385^^^^^^^^^^^^^^^^ 386 387Multiply two numbers at twice the incoming bit width (signed) and return 388the high half of the result. 389 390.. code-block:: none 391 392 %3:_(s32) = G_UMULH %0, %1 393 394G_CTLZ, G_CTTZ, G_CTPOP 395^^^^^^^^^^^^^^^^^^^^^^^ 396 397Count leading zeros, trailing zeros, or number of set bits. 398 399.. code-block:: none 400 401 %2:_(s33) = G_CTLZ_ZERO_UNDEF %1 402 %2:_(s33) = G_CTTZ_ZERO_UNDEF %1 403 %2:_(s33) = G_CTPOP %1 404 405G_CTLZ_ZERO_UNDEF, G_CTTZ_ZERO_UNDEF 406^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 407 408Count leading zeros or trailing zeros. If the value is zero then the result is 409undefined. 410 411.. code-block:: none 412 413 %2:_(s33) = G_CTLZ_ZERO_UNDEF %1 414 %2:_(s33) = G_CTTZ_ZERO_UNDEF %1 415 416Floating Point Operations 417------------------------- 418 419G_FCMP 420^^^^^^ 421 422Perform floating point comparison producing non-zero (true) or zero 423(false). It's target specific whether a true value is 1, ~0U, or some other 424non-zero value. 425 426G_FNEG 427^^^^^^ 428 429Floating point negation. 430 431G_FPEXT 432^^^^^^^ 433 434Convert a floating point value to a larger type. 435 436G_FPTRUNC 437^^^^^^^^^ 438 439Convert a floating point value to a narrower type. 440 441G_FPTOSI, G_FPTOUI, G_SITOFP, G_UITOFP 442^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 443 444Convert between integer and floating point. 445 446G_FABS 447^^^^^^ 448 449Take the absolute value of a floating point value. 450 451G_FCOPYSIGN 452^^^^^^^^^^^ 453 454Copy the value of the first operand, replacing the sign bit with that of the 455second operand. 456 457G_FCANONICALIZE 458^^^^^^^^^^^^^^^ 459 460See :ref:`i_intr_llvm_canonicalize`. 461 462G_FMINNUM 463^^^^^^^^^ 464 465Perform floating-point minimum on two values. 466 467In the case where a single input is a NaN (either signaling or quiet), 468the non-NaN input is returned. 469 470The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0. 471 472G_FMAXNUM 473^^^^^^^^^ 474 475Perform floating-point maximum on two values. 476 477In the case where a single input is a NaN (either signaling or quiet), 478the non-NaN input is returned. 479 480The return value of (FMAXNUM 0.0, -0.0) could be either 0.0 or -0.0. 481 482G_FMINNUM_IEEE 483^^^^^^^^^^^^^^ 484 485Perform floating-point minimum on two values, following the IEEE-754 2008 486definition. This differs from FMINNUM in the handling of signaling NaNs. If one 487input is a signaling NaN, returns a quiet NaN. 488 489G_FMAXNUM_IEEE 490^^^^^^^^^^^^^^ 491 492Perform floating-point maximum on two values, following the IEEE-754 2008 493definition. This differs from FMAXNUM in the handling of signaling NaNs. If one 494input is a signaling NaN, returns a quiet NaN. 495 496G_FMINIMUM 497^^^^^^^^^^ 498 499NaN-propagating minimum that also treat -0.0 as less than 0.0. While 500FMINNUM_IEEE follow IEEE 754-2008 semantics, FMINIMUM follows IEEE 754-2018 501draft semantics. 502 503G_FMAXIMUM 504^^^^^^^^^^ 505 506NaN-propagating maximum that also treat -0.0 as less than 0.0. While 507FMAXNUM_IEEE follow IEEE 754-2008 semantics, FMAXIMUM follows IEEE 754-2018 508draft semantics. 509 510G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FREM 511^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 512 513Perform the specified floating point arithmetic. 514 515G_FMA 516^^^^^ 517 518Perform a fused multiply add (i.e. without the intermediate rounding step). 519 520G_FMAD 521^^^^^^ 522 523Perform a non-fused multiply add (i.e. with the intermediate rounding step). 524 525G_FPOW 526^^^^^^ 527 528Raise the first operand to the power of the second. 529 530G_FEXP, G_FEXP2 531^^^^^^^^^^^^^^^ 532 533Calculate the base-e or base-2 exponential of a value 534 535G_FLOG, G_FLOG2, G_FLOG10 536^^^^^^^^^^^^^^^^^^^^^^^^^ 537 538Calculate the base-e, base-2, or base-10 respectively. 539 540G_FCEIL, G_FCOS, G_FSIN, G_FSQRT, G_FFLOOR, G_FRINT, G_FNEARBYINT 541^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 542 543These correspond to the standard C functions of the same name. 544 545G_INTRINSIC_TRUNC 546^^^^^^^^^^^^^^^^^ 547 548Returns the operand rounded to the nearest integer not larger in magnitude than the operand. 549 550G_INTRINSIC_ROUND 551^^^^^^^^^^^^^^^^^ 552 553Returns the operand rounded to the nearest integer. 554 555Vector Specific Operations 556-------------------------- 557 558G_CONCAT_VECTORS 559^^^^^^^^^^^^^^^^ 560 561Concatenate two vectors to form a longer vector. 562 563G_BUILD_VECTOR, G_BUILD_VECTOR_TRUNC 564^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 565 566Create a vector from multiple scalar registers. No implicit 567conversion is performed (i.e. the result element type must be the 568same as all source operands) 569 570The _TRUNC version truncates the larger operand types to fit the 571destination vector elt type. 572 573G_INSERT_VECTOR_ELT 574^^^^^^^^^^^^^^^^^^^ 575 576Insert an element into a vector 577 578G_EXTRACT_VECTOR_ELT 579^^^^^^^^^^^^^^^^^^^^ 580 581Extract an element from a vector 582 583G_SHUFFLE_VECTOR 584^^^^^^^^^^^^^^^^ 585 586Concatenate two vectors and shuffle the elements according to the mask operand. 587The mask operand should be an IR Constant which exactly matches the 588corresponding mask for the IR shufflevector instruction. 589 590Vector Reduction Operations 591--------------------------- 592 593These operations represent horizontal vector reduction, producing a scalar result. 594 595G_VECREDUCE_SEQ_FADD, G_VECREDUCE_SEQ_FMUL 596^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 597 598The SEQ variants perform reductions in sequential order. The first operand is 599an initial scalar accumulator value, and the second operand is the vector to reduce. 600 601G_VECREDUCE_FADD, G_VECREDUCE_FMUL 602^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 603 604These reductions are relaxed variants which may reduce the elements in any order. 605 606G_VECREDUCE_FMAX, G_VECREDUCE_FMIN 607^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 608 609FMIN/FMAX nodes can have flags, for NaN/NoNaN variants. 610 611 612Integer/bitwise reductions 613^^^^^^^^^^^^^^^^^^^^^^^^^^ 614 615* G_VECREDUCE_ADD 616* G_VECREDUCE_MUL 617* G_VECREDUCE_AND 618* G_VECREDUCE_OR 619* G_VECREDUCE_XOR 620* G_VECREDUCE_SMAX 621* G_VECREDUCE_SMIN 622* G_VECREDUCE_UMAX 623* G_VECREDUCE_UMIN 624 625Integer reductions may have a result type larger than the vector element type. 626However, the reduction is performed using the vector element type and the value 627in the top bits is unspecified. 628 629Memory Operations 630----------------- 631 632G_LOAD, G_SEXTLOAD, G_ZEXTLOAD 633^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 634 635Generic load. Expects a MachineMemOperand in addition to explicit 636operands. If the result size is larger than the memory size, the 637high bits are undefined, sign-extended, or zero-extended respectively. 638 639Only G_LOAD is valid if the result is a vector type. If the result is larger 640than the memory size, the high elements are undefined (i.e. this is not a 641per-element, vector anyextload) 642 643G_INDEXED_LOAD 644^^^^^^^^^^^^^^ 645 646Generic indexed load. Combines a GEP with a load. $newaddr is set to $base + $offset. 647If $am is 0 (post-indexed), then the value is loaded from $base; if $am is 1 (pre-indexed) 648then the value is loaded from $newaddr. 649 650G_INDEXED_SEXTLOAD 651^^^^^^^^^^^^^^^^^^ 652 653Same as G_INDEXED_LOAD except that the load performed is sign-extending, as with G_SEXTLOAD. 654 655G_INDEXED_ZEXTLOAD 656^^^^^^^^^^^^^^^^^^ 657 658Same as G_INDEXED_LOAD except that the load performed is zero-extending, as with G_ZEXTLOAD. 659 660G_STORE 661^^^^^^^ 662 663Generic store. Expects a MachineMemOperand in addition to explicit 664operands. If the stored value size is greater than the memory size, 665the high bits are implicitly truncated. If this is a vector store, the 666high elements are discarded (i.e. this does not function as a per-lane 667vector, truncating store) 668 669G_INDEXED_STORE 670^^^^^^^^^^^^^^^ 671 672Combines a store with a GEP. See description of G_INDEXED_LOAD for indexing behaviour. 673 674G_ATOMIC_CMPXCHG_WITH_SUCCESS 675^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 676 677Generic atomic cmpxchg with internal success check. Expects a 678MachineMemOperand in addition to explicit operands. 679 680G_ATOMIC_CMPXCHG 681^^^^^^^^^^^^^^^^ 682 683Generic atomic cmpxchg. Expects a MachineMemOperand in addition to explicit 684operands. 685 686G_ATOMICRMW_XCHG, G_ATOMICRMW_ADD, G_ATOMICRMW_SUB, G_ATOMICRMW_AND, G_ATOMICRMW_NAND, G_ATOMICRMW_OR, G_ATOMICRMW_XOR, G_ATOMICRMW_MAX, G_ATOMICRMW_MIN, G_ATOMICRMW_UMAX, G_ATOMICRMW_UMIN, G_ATOMICRMW_FADD, G_ATOMICRMW_FSUB 687^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 688 689Generic atomicrmw. Expects a MachineMemOperand in addition to explicit 690operands. 691 692G_FENCE 693^^^^^^^ 694 695.. caution:: 696 697 I couldn't find any documentation on this at the time of writing. 698 699Control Flow 700------------ 701 702G_PHI 703^^^^^ 704 705Implement the φ node in the SSA graph representing the function. 706 707.. code-block:: none 708 709 %1(s8) = G_PHI %7(s8), %bb.0, %3(s8), %bb.1 710 711G_BR 712^^^^ 713 714Unconditional branch 715 716G_BRCOND 717^^^^^^^^ 718 719Conditional branch 720 721G_BRINDIRECT 722^^^^^^^^^^^^ 723 724Indirect branch 725 726G_BRJT 727^^^^^^ 728 729Indirect branch to jump table entry 730 731G_JUMP_TABLE 732^^^^^^^^^^^^ 733 734.. caution:: 735 736 I found no documentation for this instruction at the time of writing. 737 738G_INTRINSIC, G_INTRINSIC_W_SIDE_EFFECTS 739^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 740 741Call an intrinsic 742 743The _W_SIDE_EFFECTS version is considered to have unknown side-effects and 744as such cannot be reordered across other side-effecting instructions. 745 746.. note:: 747 748 Unlike SelectionDAG, there is no _VOID variant. Both of these are permitted 749 to have zero, one, or multiple results. 750 751Variadic Arguments 752------------------ 753 754G_VASTART 755^^^^^^^^^ 756 757.. caution:: 758 759 I found no documentation for this instruction at the time of writing. 760 761G_VAARG 762^^^^^^^ 763 764.. caution:: 765 766 I found no documentation for this instruction at the time of writing. 767 768Other Operations 769---------------- 770 771G_DYN_STACKALLOC 772^^^^^^^^^^^^^^^^ 773 774Dynamically realigns the stack pointer to the specified size and alignment. 775An alignment value of `0` or `1` mean no specific alignment. 776 777.. code-block:: none 778 779 %8:_(p0) = G_DYN_STACKALLOC %7(s64), 32 780 781Optimization Hints 782------------------ 783 784These instructions do not correspond to any target instructions. They act as 785hints for various combines. 786 787G_ASSERT_SEXT, G_ASSERT_ZEXT 788^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 789 790Signifies that the contents of a register were previously extended from a 791smaller type. 792 793The smaller type is denoted using an immediate operand. For scalars, this is the 794width of the entire smaller type. For vectors, this is the width of the smaller 795element type. 796 797.. code-block:: none 798 799 %x_was_zexted:_(s32) = G_ASSERT_ZEXT %x(s32), 16 800 %y_was_zexted:_(<2 x s32>) = G_ASSERT_ZEXT %y(<2 x s32>), 16 801 802 %z_was_sexted:_(s32) = G_ASSERT_SEXT %z(s32), 8 803 804G_ASSERT_SEXT and G_ASSERT_ZEXT act like copies, albeit with some restrictions. 805 806The source and destination registers must 807 808- Be virtual 809- Belong to the same register class 810- Belong to the same register bank 811 812It should always be safe to 813 814- Look through the source register 815- Replace the destination register with the source register 816