1
2.. _gmir-opcodes:
3
4Generic Opcodes
5===============
6
7.. contents::
8   :local:
9
10.. note::
11
12  This documentation does not yet fully account for vectors. Many of the
13  scalar/integer/floating-point operations can also take vectors.
14
15Constants
16---------
17
18G_IMPLICIT_DEF
19^^^^^^^^^^^^^^
20
21An undefined value.
22
23.. code-block:: none
24
25  %0:_(s32) = G_IMPLICIT_DEF
26
27G_CONSTANT
28^^^^^^^^^^
29
30An integer constant.
31
32.. code-block:: none
33
34  %0:_(s32) = G_CONSTANT i32 1
35
36G_FCONSTANT
37^^^^^^^^^^^
38
39A floating point constant.
40
41.. code-block:: none
42
43  %0:_(s32) = G_FCONSTANT float 1.0
44
45G_FRAME_INDEX
46^^^^^^^^^^^^^
47
48The address of an object in the stack frame.
49
50.. code-block:: none
51
52  %1:_(p0) = G_FRAME_INDEX %stack.0.ptr0
53
54G_GLOBAL_VALUE
55^^^^^^^^^^^^^^
56
57The address of a global value.
58
59.. code-block:: none
60
61  %0(p0) = G_GLOBAL_VALUE @var_local
62
63G_BLOCK_ADDR
64^^^^^^^^^^^^
65
66The address of a basic block.
67
68.. code-block:: none
69
70  %0:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
71
72Integer Extension and Truncation
73--------------------------------
74
75G_ANYEXT
76^^^^^^^^
77
78Extend the underlying scalar type of an operation, leaving the high bits
79unspecified.
80
81.. code-block:: none
82
83  %1:_(s32) = G_ANYEXT %0:_(s16)
84
85G_SEXT
86^^^^^^
87
88Sign extend the underlying scalar type of an operation, copying the sign bit
89into the newly-created space.
90
91.. code-block:: none
92
93  %1:_(s32) = G_SEXT %0:_(s16)
94
95G_SEXT_INREG
96^^^^^^^^^^^^
97
98Sign extend the value from an arbitrary bit position, copying the sign bit
99into all bits above it. This is equivalent to a shl + ashr pair with an
100appropriate shift amount. $sz is an immediate (MachineOperand::isImm()
101returns true) to allow targets to have some bitwidths legal and others
102lowered. This opcode is particularly useful if the target has sign-extension
103instructions that are cheaper than the constituent shifts as the optimizer is
104able to make decisions on whether it's better to hang on to the G_SEXT_INREG
105or to lower it and optimize the individual shifts.
106
107.. code-block:: none
108
109  %1:_(s32) = G_SEXT_INREG %0:_(s32), 16
110
111G_ZEXT
112^^^^^^
113
114Zero extend the underlying scalar type of an operation, putting zero bits
115into the newly-created space.
116
117.. code-block:: none
118
119  %1:_(s32) = G_ZEXT %0:_(s16)
120
121G_TRUNC
122^^^^^^^
123
124Truncate the underlying scalar type of an operation. This is equivalent to
125G_EXTRACT for scalar types, but acts elementwise on vectors.
126
127.. code-block:: none
128
129  %1:_(s16) = G_TRUNC %0:_(s32)
130
131Type Conversions
132----------------
133
134G_INTTOPTR
135^^^^^^^^^^
136
137Convert an integer to a pointer.
138
139.. code-block:: none
140
141  %1:_(p0) = G_INTTOPTR %0:_(s32)
142
143G_PTRTOINT
144^^^^^^^^^^
145
146Convert a pointer to an integer.
147
148.. code-block:: none
149
150  %1:_(s32) = G_PTRTOINT %0:_(p0)
151
152G_BITCAST
153^^^^^^^^^
154
155Reinterpret a value as a new type. This is usually done without changing any
156bits but this is not always the case due a sublety in the definition of the
157:ref:`LLVM-IR Bitcast Instruction <i_bitcast>`.
158
159.. code-block:: none
160
161  %1:_(s64) = G_BITCAST %0:_(<2 x s32>)
162
163G_ADDRSPACE_CAST
164^^^^^^^^^^^^^^^^
165
166Convert a pointer to an address space to a pointer to another address space.
167
168.. code-block:: none
169
170  %1:_(p1) = G_ADDRSPACE_CAST %0:_(p0)
171
172.. caution::
173
174  :ref:`i_addrspacecast` doesn't mention what happens if the cast is simply
175  invalid (i.e. if the address spaces are disjoint).
176
177Scalar Operations
178-----------------
179
180G_EXTRACT
181^^^^^^^^^
182
183Extract a register of the specified size, starting from the block given by
184index. This will almost certainly be mapped to sub-register COPYs after
185register banks have been selected.
186
187G_INSERT
188^^^^^^^^
189
190Insert a smaller register into a larger one at the specified bit-index.
191
192G_MERGE_VALUES
193^^^^^^^^^^^^^^
194
195Concatenate multiple registers of the same size into a wider register.
196The input operands are always ordered from lowest bits to highest:
197
198.. code-block:: none
199
200  %0:(s32) = G_MERGE_VALUES %bits_0_7:(s8), %bits_8_15:(s8),
201                            %bits_16_23:(s8), %bits_24_31:(s8)
202
203G_UNMERGE_VALUES
204^^^^^^^^^^^^^^^^
205
206Extract multiple registers of the specified size, starting from blocks given by
207indexes. This will almost certainly be mapped to sub-register COPYs after
208register banks have been selected.
209The output operands are always ordered from lowest bits to highest:
210
211.. code-block:: none
212
213  %bits_0_7:(s8), %bits_8_15:(s8),
214      %bits_16_23:(s8), %bits_24_31:(s8) = G_UNMERGE_VALUES %0:(s32)
215
216G_BSWAP
217^^^^^^^
218
219Reverse the order of the bytes in a scalar.
220
221.. code-block:: none
222
223  %1:_(s32) = G_BSWAP %0:_(s32)
224
225G_BITREVERSE
226^^^^^^^^^^^^
227
228Reverse the order of the bits in a scalar.
229
230.. code-block:: none
231
232  %1:_(s32) = G_BITREVERSE %0:_(s32)
233
234Integer Operations
235-------------------
236
237G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, G_SDIV, G_UDIV, G_SREM, G_UREM
238^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
239
240These each perform their respective integer arithmetic on a scalar.
241
242.. code-block:: none
243
244  %2:_(s32) = G_ADD %0:_(s32), %1:_(s32)
245
246G_SHL, G_LSHR, G_ASHR
247^^^^^^^^^^^^^^^^^^^^^
248
249Shift the bits of a scalar left or right inserting zeros (sign-bit for G_ASHR).
250
251G_ICMP
252^^^^^^
253
254Perform integer comparison producing non-zero (true) or zero (false). It's
255target specific whether a true value is 1, ~0U, or some other non-zero value.
256
257G_SELECT
258^^^^^^^^
259
260Select between two values depending on a zero/non-zero value.
261
262.. code-block:: none
263
264  %5:_(s32) = G_SELECT %4(s1), %6, %2
265
266G_PTR_ADD
267^^^^^^^^^
268
269Add a scalar offset in addressible units to a pointer. Addressible units are
270typically bytes but this may vary between targets.
271
272.. code-block:: none
273
274  %1:_(p0) = G_PTR_ADD %0:_(p0), %1:_(s32)
275
276.. caution::
277
278  There are currently no in-tree targets that use this with addressable units
279  not equal to 8 bit.
280
281G_PTR_MASK
282^^^^^^^^^^
283
284Zero the least significant N bits of a pointer.
285
286.. code-block:: none
287
288  %1:_(p0) = G_PTR_MASK %0, 3
289
290G_SMIN, G_SMAX, G_UMIN, G_UMAX
291^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
292
293Take the minimum/maximum of two values.
294
295.. code-block:: none
296
297  %5:_(s32) = G_SMIN %6, %2
298
299G_UADDO, G_SADDO, G_USUBO, G_SSUBO, G_SMULO, G_UMULO
300^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
301
302Perform the requested arithmetic and produce a carry output in addition to the
303normal result.
304
305.. code-block:: none
306
307  %3:_(s32), %4:_(s1) = G_UADDO %0, %1
308
309G_UADDE, G_SADDE, G_USUBE, G_SSUBE
310^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
311
312Perform the requested arithmetic and consume a carry input in addition to the
313normal input. Also produce a carry output in addition to the normal result.
314
315.. code-block:: none
316
317  %4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3:_(s1)
318
319G_UMULH, G_SMULH
320^^^^^^^^^^^^^^^^
321
322Multiply two numbers at twice the incoming bit width (signed) and return
323the high half of the result.
324
325.. code-block:: none
326
327  %3:_(s32) = G_UMULH %0, %1
328
329G_CTLZ, G_CTTZ, G_CTPOP
330^^^^^^^^^^^^^^^^^^^^^^^
331
332Count leading zeros, trailing zeros, or number of set bits.
333
334.. code-block:: none
335
336  %2:_(s33) = G_CTLZ_ZERO_UNDEF %1
337  %2:_(s33) = G_CTTZ_ZERO_UNDEF %1
338  %2:_(s33) = G_CTPOP %1
339
340G_CTLZ_ZERO_UNDEF, G_CTTZ_ZERO_UNDEF
341^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
342
343Count leading zeros or trailing zeros. If the value is zero then the result is
344undefined.
345
346.. code-block:: none
347
348  %2:_(s33) = G_CTLZ_ZERO_UNDEF %1
349  %2:_(s33) = G_CTTZ_ZERO_UNDEF %1
350
351Floating Point Operations
352-------------------------
353
354G_FCMP
355^^^^^^
356
357Perform floating point comparison producing non-zero (true) or zero
358(false). It's target specific whether a true value is 1, ~0U, or some other
359non-zero value.
360
361G_FNEG
362^^^^^^
363
364Floating point negation.
365
366G_FPEXT
367^^^^^^^
368
369Convert a floating point value to a larger type.
370
371G_FPTRUNC
372^^^^^^^^^
373
374Convert a floating point value to a narrower type.
375
376G_FPTOSI, G_FPTOUI, G_SITOFP, G_UITOFP
377^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
378
379Convert between integer and floating point.
380
381G_FABS
382^^^^^^
383
384Take the absolute value of a floating point value.
385
386G_FCOPYSIGN
387^^^^^^^^^^^
388
389Copy the value of the first operand, replacing the sign bit with that of the
390second operand.
391
392G_FCANONICALIZE
393^^^^^^^^^^^^^^^
394
395See :ref:`i_intr_llvm_canonicalize`.
396
397G_FMINNUM
398^^^^^^^^^
399
400Perform floating-point minimum on two values.
401
402In the case where a single input is a NaN (either signaling or quiet),
403the non-NaN input is returned.
404
405The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
406
407G_FMAXNUM
408^^^^^^^^^
409
410Perform floating-point maximum on two values.
411
412In the case where a single input is a NaN (either signaling or quiet),
413the non-NaN input is returned.
414
415The return value of (FMAXNUM 0.0, -0.0) could be either 0.0 or -0.0.
416
417G_FMINNUM_IEEE
418^^^^^^^^^^^^^^
419
420Perform floating-point minimum on two values, following the IEEE-754 2008
421definition. This differs from FMINNUM in the handling of signaling NaNs. If one
422input is a signaling NaN, returns a quiet NaN.
423
424G_FMAXNUM_IEEE
425^^^^^^^^^^^^^^
426
427Perform floating-point maximum on two values, following the IEEE-754 2008
428definition. This differs from FMAXNUM in the handling of signaling NaNs. If one
429input is a signaling NaN, returns a quiet NaN.
430
431G_FMINIMUM
432^^^^^^^^^^
433
434NaN-propagating minimum that also treat -0.0 as less than 0.0. While
435FMINNUM_IEEE follow IEEE 754-2008 semantics, FMINIMUM follows IEEE 754-2018
436draft semantics.
437
438G_FMAXIMUM
439^^^^^^^^^^
440
441NaN-propagating maximum that also treat -0.0 as less than 0.0. While
442FMAXNUM_IEEE follow IEEE 754-2008 semantics, FMAXIMUM follows IEEE 754-2018
443draft semantics.
444
445G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FREM
446^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
447
448Perform the specified floating point arithmetic.
449
450G_FMA
451^^^^^
452
453Perform a fused multiply add (i.e. without the intermediate rounding step).
454
455G_FMAD
456^^^^^^
457
458Perform a non-fused multiply add (i.e. with the intermediate rounding step).
459
460G_FPOW
461^^^^^^
462
463Raise the first operand to the power of the second.
464
465G_FEXP, G_FEXP2
466^^^^^^^^^^^^^^^
467
468Calculate the base-e or base-2 exponential of a value
469
470G_FLOG, G_FLOG2, G_FLOG10
471^^^^^^^^^^^^^^^^^^^^^^^^^
472
473Calculate the base-e, base-2, or base-10 respectively.
474
475G_FCEIL, G_FCOS, G_FSIN, G_FSQRT, G_FFLOOR, G_FRINT, G_FNEARBYINT
476^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
477
478These correspond to the standard C functions of the same name.
479
480G_INTRINSIC_TRUNC
481^^^^^^^^^^^^^^^^^
482
483Returns the operand rounded to the nearest integer not larger in magnitude than the operand.
484
485G_INTRINSIC_ROUND
486^^^^^^^^^^^^^^^^^
487
488Returns the operand rounded to the nearest integer.
489
490Vector Specific Operations
491--------------------------
492
493G_CONCAT_VECTORS
494^^^^^^^^^^^^^^^^
495
496Concatenate two vectors to form a longer vector.
497
498G_BUILD_VECTOR, G_BUILD_VECTOR_TRUNC
499^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
500
501Create a vector from multiple scalar registers. No implicit
502conversion is performed (i.e. the result element type must be the
503same as all source operands)
504
505The _TRUNC version truncates the larger operand types to fit the
506destination vector elt type.
507
508G_INSERT_VECTOR_ELT
509^^^^^^^^^^^^^^^^^^^
510
511Insert an element into a vector
512
513G_EXTRACT_VECTOR_ELT
514^^^^^^^^^^^^^^^^^^^^
515
516Extract an element from a vector
517
518G_SHUFFLE_VECTOR
519^^^^^^^^^^^^^^^^
520
521Concatenate two vectors and shuffle the elements according to the mask operand.
522The mask operand should be an IR Constant which exactly matches the
523corresponding mask for the IR shufflevector instruction.
524
525Memory Operations
526-----------------
527
528G_LOAD, G_SEXTLOAD, G_ZEXTLOAD
529^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
530
531Generic load. Expects a MachineMemOperand in addition to explicit
532operands. If the result size is larger than the memory size, the
533high bits are undefined, sign-extended, or zero-extended respectively.
534
535Only G_LOAD is valid if the result is a vector type. If the result is larger
536than the memory size, the high elements are undefined (i.e. this is not a
537per-element, vector anyextload)
538
539G_INDEXED_LOAD
540^^^^^^^^^^^^^^
541
542Generic indexed load. Combines a GEP with a load. $newaddr is set to $base + $offset.
543If $am is 0 (post-indexed), then the value is loaded from $base; if $am is 1 (pre-indexed)
544then the value is loaded from $newaddr.
545
546G_INDEXED_SEXTLOAD
547^^^^^^^^^^^^^^^^^^
548
549Same as G_INDEXED_LOAD except that the load performed is sign-extending, as with G_SEXTLOAD.
550
551G_INDEXED_ZEXTLOAD
552^^^^^^^^^^^^^^^^^^
553
554Same as G_INDEXED_LOAD except that the load performed is zero-extending, as with G_ZEXTLOAD.
555
556G_STORE
557^^^^^^^
558
559Generic store. Expects a MachineMemOperand in addition to explicit operands.
560
561G_INDEXED_STORE
562^^^^^^^^^^^^^^^
563
564Combines a store with a GEP. See description of G_INDEXED_LOAD for indexing behaviour.
565
566G_ATOMIC_CMPXCHG_WITH_SUCCESS
567^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
568
569Generic atomic cmpxchg with internal success check. Expects a
570MachineMemOperand in addition to explicit operands.
571
572G_ATOMIC_CMPXCHG
573^^^^^^^^^^^^^^^^
574
575Generic atomic cmpxchg. Expects a MachineMemOperand in addition to explicit
576operands.
577
578G_ATOMICRMW_XCHG, G_ATOMICRMW_ADD, G_ATOMICRMW_SUB, G_ATOMICRMW_AND, G_ATOMICRMW_NAND, G_ATOMICRMW_OR, G_ATOMICRMW_XOR, G_ATOMICRMW_MAX, G_ATOMICRMW_MIN, G_ATOMICRMW_UMAX, G_ATOMICRMW_UMIN, G_ATOMICRMW_FADD, G_ATOMICRMW_FSUB
579^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
580
581Generic atomicrmw. Expects a MachineMemOperand in addition to explicit
582operands.
583
584G_FENCE
585^^^^^^^
586
587.. caution::
588
589  I couldn't find any documentation on this at the time of writing.
590
591Control Flow
592------------
593
594G_PHI
595^^^^^
596
597Implement the φ node in the SSA graph representing the function.
598
599.. code-block:: none
600
601  %1(s8) = G_PHI %7(s8), %bb.0, %3(s8), %bb.1
602
603G_BR
604^^^^
605
606Unconditional branch
607
608G_BRCOND
609^^^^^^^^
610
611Conditional branch
612
613G_BRINDIRECT
614^^^^^^^^^^^^
615
616Indirect branch
617
618G_BRJT
619^^^^^^
620
621Indirect branch to jump table entry
622
623G_JUMP_TABLE
624^^^^^^^^^^^^
625
626.. caution::
627
628  I found no documentation for this instruction at the time of writing.
629
630G_INTRINSIC, G_INTRINSIC_W_SIDE_EFFECTS
631^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
632
633Call an intrinsic
634
635The _W_SIDE_EFFECTS version is considered to have unknown side-effects and
636as such cannot be reordered across other side-effecting instructions.
637
638.. note::
639
640  Unlike SelectionDAG, there is no _VOID variant. Both of these are permitted
641  to have zero, one, or multiple results.
642
643Variadic Arguments
644------------------
645
646G_VASTART
647^^^^^^^^^
648
649.. caution::
650
651  I found no documentation for this instruction at the time of writing.
652
653G_VAARG
654^^^^^^^
655
656.. caution::
657
658  I found no documentation for this instruction at the time of writing.
659
660Other Operations
661----------------
662
663G_DYN_STACKALLOC
664^^^^^^^^^^^^^^^^
665
666Dynamically realign the stack pointer to the specified alignment
667
668.. code-block:: none
669
670  %8:_(p0) = G_DYN_STACKALLOC %7(s64), 32
671
672.. caution::
673
674  What does it mean for the immediate to be 0? It happens in the tests
675