1====================================== 2Syntax of AMDGPU Instruction Modifiers 3====================================== 4 5.. contents:: 6 :local: 7 8Conventions 9=========== 10 11The following notation is used throughout this document: 12 13 =================== ============================================================= 14 Notation Description 15 =================== ============================================================= 16 {0..N} Any integer value in the range from 0 to N (inclusive). 17 <x> Syntax and meaning of *x* is explained elsewhere. 18 =================== ============================================================= 19 20.. _amdgpu_syn_modifiers: 21 22Modifiers 23========= 24 25DS Modifiers 26------------ 27 28.. _amdgpu_synid_ds_offset8: 29 30offset8 31~~~~~~~ 32 33Specifies an immediate unsigned 8-bit offset, in bytes. The default value is 0. 34 35Used with DS instructions which have 2 addresses. 36 37 =================== ==================================================================== 38 Syntax Description 39 =================== ==================================================================== 40 offset:{0..0xFF} Specifies an unsigned 8-bit offset as a positive 41 :ref:`integer number <amdgpu_synid_integer_number>` 42 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 43 =================== ==================================================================== 44 45Examples: 46 47.. parsed-literal:: 48 49 offset:0xff 50 offset:2-x 51 offset:-x-y 52 53.. _amdgpu_synid_ds_offset16: 54 55offset16 56~~~~~~~~ 57 58Specifies an immediate unsigned 16-bit offset, in bytes. The default value is 0. 59 60Used with DS instructions which have 1 address. 61 62 ==================== ==================================================================== 63 Syntax Description 64 ==================== ==================================================================== 65 offset:{0..0xFFFF} Specifies an unsigned 16-bit offset as a positive 66 :ref:`integer number <amdgpu_synid_integer_number>` 67 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 68 ==================== ==================================================================== 69 70Examples: 71 72.. parsed-literal:: 73 74 offset:65535 75 offset:0xffff 76 offset:-x-y 77 78.. _amdgpu_synid_sw_offset16: 79 80swizzle pattern 81~~~~~~~~~~~~~~~ 82 83This is a special modifier which may be used with *ds_swizzle_b32* instruction only. 84It specifies a swizzle pattern in numeric or symbolic form. The default value is 0. 85 86See AMD documentation for more information. 87 88 ======================================================= =========================================================== 89 Syntax Description 90 ======================================================= =========================================================== 91 offset:{0..0xFFFF} Specifies a 16-bit swizzle pattern. 92 offset:swizzle(QUAD_PERM,{0..3},{0..3},{0..3},{0..3}) Specifies a quad permute mode pattern 93 94 Each number is a lane *id*. 95 offset:swizzle(BITMASK_PERM, "<mask>") Specifies a bitmask permute mode pattern. 96 97 The pattern converts a 5-bit lane *id* to another 98 lane *id* with which the lane interacts. 99 100 *mask* is a 5 character sequence which 101 specifies how to transform the bits of the 102 lane *id*. 103 104 The following characters are allowed: 105 106 * "0" - set bit to 0. 107 108 * "1" - set bit to 1. 109 110 * "p" - preserve bit. 111 112 * "i" - inverse bit. 113 114 offset:swizzle(BROADCAST,{2..32},{0..N}) Specifies a broadcast mode. 115 116 Broadcasts the value of any particular lane to 117 all lanes in its group. 118 119 The first numeric parameter is a group 120 size and must be equal to 2, 4, 8, 16 or 32. 121 122 The second numeric parameter is an index of the 123 lane being broadcasted. 124 125 The index must not exceed group size. 126 offset:swizzle(SWAP,{1..16}) Specifies a swap mode. 127 128 Swaps the neighboring groups of 129 1, 2, 4, 8 or 16 lanes. 130 offset:swizzle(REVERSE,{2..32}) Specifies a reverse mode. 131 132 Reverses the lanes for groups of 2, 4, 8, 16 or 32 lanes. 133 ======================================================= =========================================================== 134 135Note: numeric values may be specified as either :ref:`integer numbers<amdgpu_synid_integer_number>` or 136:ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 137 138Examples: 139 140.. parsed-literal:: 141 142 offset:255 143 offset:0xffff 144 offset:swizzle(QUAD_PERM, 0, 1, 2, 3) 145 offset:swizzle(BITMASK_PERM, "01pi0") 146 offset:swizzle(BROADCAST, 2, 0) 147 offset:swizzle(SWAP, 8) 148 offset:swizzle(REVERSE, 30 + 2) 149 150.. _amdgpu_synid_gds: 151 152gds 153~~~ 154 155Specifies whether to use GDS or LDS memory (LDS is the default). 156 157 ======================================== ================================================ 158 Syntax Description 159 ======================================== ================================================ 160 gds Use GDS memory. 161 ======================================== ================================================ 162 163 164EXP Modifiers 165------------- 166 167.. _amdgpu_synid_done: 168 169done 170~~~~ 171 172Specifies if this is the last export from the shader to the target. By default, 173*exp* instruction does not finish an export sequence. 174 175 ======================================== ================================================ 176 Syntax Description 177 ======================================== ================================================ 178 done Indicates the last export operation. 179 ======================================== ================================================ 180 181.. _amdgpu_synid_compr: 182 183compr 184~~~~~ 185 186Indicates if the data are compressed (data are not compressed by default). 187 188 ======================================== ================================================ 189 Syntax Description 190 ======================================== ================================================ 191 compr Data are compressed. 192 ======================================== ================================================ 193 194.. _amdgpu_synid_vm: 195 196vm 197~~ 198 199Specifies valid mask flag state (off by default). 200 201 ======================================== ================================================ 202 Syntax Description 203 ======================================== ================================================ 204 vm Set valid mask flag. 205 ======================================== ================================================ 206 207FLAT Modifiers 208-------------- 209 210.. _amdgpu_synid_flat_offset12: 211 212offset12 213~~~~~~~~ 214 215Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0. 216 217Cannot be used with *global/scratch* opcodes. GFX9 only. 218 219 ================= ==================================================================== 220 Syntax Description 221 ================= ==================================================================== 222 offset:{0..4095} Specifies a 12-bit unsigned offset as a positive 223 :ref:`integer number <amdgpu_synid_integer_number>` 224 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 225 ================= ==================================================================== 226 227Examples: 228 229.. parsed-literal:: 230 231 offset:4095 232 offset:x-0xff 233 234.. _amdgpu_synid_flat_offset13s: 235 236offset13s 237~~~~~~~~~ 238 239Specifies an immediate signed 13-bit offset, in bytes. The default value is 0. 240 241Can be used with *global/scratch* opcodes only. GFX9 only. 242 243 ===================== ==================================================================== 244 Syntax Description 245 ===================== ==================================================================== 246 offset:{-4096..4095} Specifies a 13-bit signed offset as an 247 :ref:`integer number <amdgpu_synid_integer_number>` 248 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 249 ===================== ==================================================================== 250 251Examples: 252 253.. parsed-literal:: 254 255 offset:-4000 256 offset:0x10 257 offset:-x 258 259.. _amdgpu_synid_flat_offset12s: 260 261offset12s 262~~~~~~~~~ 263 264Specifies an immediate signed 12-bit offset, in bytes. The default value is 0. 265 266Can be used with *global/scratch* opcodes only. 267 268GFX10 only. 269 270 ===================== ==================================================================== 271 Syntax Description 272 ===================== ==================================================================== 273 offset:{-2048..2047} Specifies a 12-bit signed offset as an 274 :ref:`integer number <amdgpu_synid_integer_number>` 275 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 276 ===================== ==================================================================== 277 278Examples: 279 280.. parsed-literal:: 281 282 offset:-2000 283 offset:0x10 284 offset:-x+y 285 286.. _amdgpu_synid_flat_offset11: 287 288offset11 289~~~~~~~~ 290 291Specifies an immediate unsigned 11-bit offset, in bytes. The default value is 0. 292 293Cannot be used with *global/scratch* opcodes. 294 295GFX10 only. 296 297 ================= ==================================================================== 298 Syntax Description 299 ================= ==================================================================== 300 offset:{0..2047} Specifies an 11-bit unsigned offset as a positive 301 :ref:`integer number <amdgpu_synid_integer_number>` 302 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 303 ================= ==================================================================== 304 305Examples: 306 307.. parsed-literal:: 308 309 offset:2047 310 offset:x+0xff 311 312dlc 313~~~ 314 315See a description :ref:`here<amdgpu_synid_dlc>`. GFX10 only. 316 317glc 318~~~ 319 320See a description :ref:`here<amdgpu_synid_glc>`. 321 322lds 323~~~ 324 325See a description :ref:`here<amdgpu_synid_lds>`. GFX10 only. 326 327slc 328~~~ 329 330See a description :ref:`here<amdgpu_synid_slc>`. 331 332tfe 333~~~ 334 335See a description :ref:`here<amdgpu_synid_tfe>`. 336 337nv 338~~ 339 340See a description :ref:`here<amdgpu_synid_nv>`. 341 342MIMG Modifiers 343-------------- 344 345.. _amdgpu_synid_dmask: 346 347dmask 348~~~~~ 349 350Specifies which channels (image components) are used by the operation. By default, no channels 351are used. 352 353 =============== ==================================================================== 354 Syntax Description 355 =============== ==================================================================== 356 dmask:{0..15} Specifies image channels as a positive 357 :ref:`integer number <amdgpu_synid_integer_number>` 358 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 359 360 Each bit corresponds to one of 4 image components (RGBA). 361 362 If the specified bit value is 0, the component is not used, 363 value 1 means that the component is used. 364 =============== ==================================================================== 365 366This modifier has some limitations depending on instruction kind: 367 368 =================================================== ======================== 369 Instruction Kind Valid dmask Values 370 =================================================== ======================== 371 32-bit atomic *cmpswap* 0x3 372 32-bit atomic instructions except for *cmpswap* 0x1 373 64-bit atomic *cmpswap* 0xF 374 64-bit atomic instructions except for *cmpswap* 0x3 375 *gather4* 0x1, 0x2, 0x4, 0x8 376 Other instructions any value 377 =================================================== ======================== 378 379Examples: 380 381.. parsed-literal:: 382 383 dmask:0xf 384 dmask:0b1111 385 dmask:x|y|z 386 387.. _amdgpu_synid_unorm: 388 389unorm 390~~~~~ 391 392Specifies whether the address is normalized or not (the address is normalized by default). 393 394 ======================== ======================================== 395 Syntax Description 396 ======================== ======================================== 397 unorm Force the address to be unnormalized. 398 ======================== ======================================== 399 400glc 401~~~ 402 403See a description :ref:`here<amdgpu_synid_glc>`. 404 405slc 406~~~ 407 408See a description :ref:`here<amdgpu_synid_slc>`. 409 410.. _amdgpu_synid_r128: 411 412r128 413~~~~ 414 415Specifies texture resource size. The default size is 256 bits. 416 417GFX7, GFX8 and GFX10 only. 418 419 =================== ================================================ 420 Syntax Description 421 =================== ================================================ 422 r128 Specifies 128 bits texture resource size. 423 =================== ================================================ 424 425.. WARNING:: Using this modifier should descrease *rsrc* operand size from 8 to 4 dwords, but assembler does not currently support this feature. 426 427tfe 428~~~ 429 430See a description :ref:`here<amdgpu_synid_tfe>`. 431 432.. _amdgpu_synid_lwe: 433 434lwe 435~~~ 436 437Specifies LOD warning status (LOD warning is disabled by default). 438 439 ======================================== ================================================ 440 Syntax Description 441 ======================================== ================================================ 442 lwe Enables LOD warning. 443 ======================================== ================================================ 444 445.. _amdgpu_synid_da: 446 447da 448~~ 449 450Specifies if an array index must be sent to TA. By default, array index is not sent. 451 452 ======================================== ================================================ 453 Syntax Description 454 ======================================== ================================================ 455 da Send an array-index to TA. 456 ======================================== ================================================ 457 458.. _amdgpu_synid_d16: 459 460d16 461~~~ 462 463Specifies data size: 16 or 32 bits (32 bits by default). Not supported by GFX7. 464 465 ======================================== ================================================ 466 Syntax Description 467 ======================================== ================================================ 468 d16 Enables 16-bits data mode. 469 470 On loads, convert data in memory to 16-bit 471 format before storing it in VGPRs. 472 473 For stores, convert 16-bit data in VGPRs to 474 32 bits before going to memory. 475 476 Note that GFX8.0 does not support data packing. 477 Each 16-bit data element occupies 1 VGPR. 478 479 GFX8.1, GFX9 and GFX10 support data packing. 480 Each pair of 16-bit data elements 481 occupies 1 VGPR. 482 ======================================== ================================================ 483 484.. _amdgpu_synid_a16: 485 486a16 487~~~ 488 489Specifies size of image address components: 16 or 32 bits (32 bits by default). 490GFX9 and GFX10 only. 491 492 ======================================== ================================================ 493 Syntax Description 494 ======================================== ================================================ 495 a16 Enables 16-bits image address components. 496 ======================================== ================================================ 497 498.. _amdgpu_synid_dim: 499 500dim 501~~~ 502 503Specifies surface dimension. This is a mandatory modifier. There is no default value. 504 505GFX10 only. 506 507 =============================== ========================================================= 508 Syntax Description 509 =============================== ========================================================= 510 dim:1D One-dimensional image. 511 dim:2D Two-dimensional image. 512 dim:3D Three-dimensional image. 513 dim:CUBE Cubemap array. 514 dim:1D_ARRAY One-dimensional image array. 515 dim:2D_ARRAY Two-dimensional image array. 516 dim:2D_MSAA Two-dimensional multi-sample auto-aliasing image. 517 dim:2D_MSAA_ARRAY Two-dimensional multi-sample auto-aliasing image array. 518 =============================== ========================================================= 519 520The following table defines an alternative syntax which is supported 521for compatibility with SP3 assembler: 522 523 =============================== ========================================================= 524 Syntax Description 525 =============================== ========================================================= 526 dim:SQ_RSRC_IMG_1D One-dimensional image. 527 dim:SQ_RSRC_IMG_2D Two-dimensional image. 528 dim:SQ_RSRC_IMG_3D Three-dimensional image. 529 dim:SQ_RSRC_IMG_CUBE Cubemap array. 530 dim:SQ_RSRC_IMG_1D_ARRAY One-dimensional image array. 531 dim:SQ_RSRC_IMG_2D_ARRAY Two-dimensional image array. 532 dim:SQ_RSRC_IMG_2D_MSAA Two-dimensional multi-sample auto-aliasing image. 533 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY Two-dimensional multi-sample auto-aliasing image array. 534 =============================== ========================================================= 535 536dlc 537~~~ 538 539See a description :ref:`here<amdgpu_synid_dlc>`. GFX10 only. 540 541Miscellaneous Modifiers 542----------------------- 543 544.. _amdgpu_synid_dlc: 545 546dlc 547~~~ 548 549Controls device level cache policy for memory operations. Used for synchronization. 550When specified, forces operation to bypass device level cache making the operation device 551level coherent. By default, instructions use device level cache. 552 553GFX10 only. 554 555 ======================================== ================================================ 556 Syntax Description 557 ======================================== ================================================ 558 dlc Bypass device level cache. 559 ======================================== ================================================ 560 561.. _amdgpu_synid_glc: 562 563glc 564~~~ 565 566This modifier has different meaning for loads, stores, and atomic operations. 567The default value is off (0). 568 569See AMD documentation for details. 570 571 ======================================== ================================================ 572 Syntax Description 573 ======================================== ================================================ 574 glc Set glc bit to 1. 575 ======================================== ================================================ 576 577.. _amdgpu_synid_lds: 578 579lds 580~~~ 581 582Specifies where to store the result: VGPRs or LDS (VGPRs by default). 583 584 ======================================== =========================== 585 Syntax Description 586 ======================================== =========================== 587 lds Store result in LDS. 588 ======================================== =========================== 589 590.. _amdgpu_synid_nv: 591 592nv 593~~ 594 595Specifies if instruction is operating on non-volatile memory. By default, memory is volatile. 596 597GFX9 only. 598 599 ======================================== ================================================ 600 Syntax Description 601 ======================================== ================================================ 602 nv Indicates that instruction operates on 603 non-volatile memory. 604 ======================================== ================================================ 605 606.. _amdgpu_synid_slc: 607 608slc 609~~~ 610 611Specifies cache policy. The default value is off (0). 612 613See AMD documentation for details. 614 615 ======================================== ================================================ 616 Syntax Description 617 ======================================== ================================================ 618 slc Set slc bit to 1. 619 ======================================== ================================================ 620 621.. _amdgpu_synid_tfe: 622 623tfe 624~~~ 625 626Controls access to partially resident textures. The default value is off (0). 627 628See AMD documentation for details. 629 630 ======================================== ================================================ 631 Syntax Description 632 ======================================== ================================================ 633 tfe Set tfe bit to 1. 634 ======================================== ================================================ 635 636MUBUF/MTBUF Modifiers 637--------------------- 638 639.. _amdgpu_synid_idxen: 640 641idxen 642~~~~~ 643 644Specifies whether address components include an index. By default, no components are used. 645 646Can be used together with :ref:`offen<amdgpu_synid_offen>`. 647 648Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`. 649 650 ======================================== ================================================ 651 Syntax Description 652 ======================================== ================================================ 653 idxen Address components include an index. 654 ======================================== ================================================ 655 656.. _amdgpu_synid_offen: 657 658offen 659~~~~~ 660 661Specifies whether address components include an offset. By default, no components are used. 662 663Can be used together with :ref:`idxen<amdgpu_synid_idxen>`. 664 665Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`. 666 667 ======================================== ================================================ 668 Syntax Description 669 ======================================== ================================================ 670 offen Address components include an offset. 671 ======================================== ================================================ 672 673.. _amdgpu_synid_addr64: 674 675addr64 676~~~~~~ 677 678Specifies whether a 64-bit address is used. By default, no address is used. 679 680GFX7 only. Cannot be used with :ref:`offen<amdgpu_synid_offen>` and 681:ref:`idxen<amdgpu_synid_idxen>` modifiers. 682 683 ======================================== ================================================ 684 Syntax Description 685 ======================================== ================================================ 686 addr64 A 64-bit address is used. 687 ======================================== ================================================ 688 689.. _amdgpu_synid_buf_offset12: 690 691offset12 692~~~~~~~~ 693 694Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0. 695 696 ================== ==================================================================== 697 Syntax Description 698 ================== ==================================================================== 699 offset:{0..0xFFF} Specifies a 12-bit unsigned offset as a positive 700 :ref:`integer number <amdgpu_synid_integer_number>` 701 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 702 ================== ==================================================================== 703 704Examples: 705 706.. parsed-literal:: 707 708 offset:x+y 709 offset:0x10 710 711glc 712~~~ 713 714See a description :ref:`here<amdgpu_synid_glc>`. 715 716slc 717~~~ 718 719See a description :ref:`here<amdgpu_synid_slc>`. 720 721lds 722~~~ 723 724See a description :ref:`here<amdgpu_synid_lds>`. 725 726dlc 727~~~ 728 729See a description :ref:`here<amdgpu_synid_dlc>`. GFX10 only. 730 731tfe 732~~~ 733 734See a description :ref:`here<amdgpu_synid_tfe>`. 735 736.. _amdgpu_synid_dfmt: 737 738dfmt 739~~~~ 740 741TBD 742 743.. _amdgpu_synid_nfmt: 744 745nfmt 746~~~~ 747 748TBD 749 750SMRD/SMEM Modifiers 751------------------- 752 753glc 754~~~ 755 756See a description :ref:`here<amdgpu_synid_glc>`. 757 758nv 759~~ 760 761See a description :ref:`here<amdgpu_synid_nv>`. GFX9 only. 762 763dlc 764~~~ 765 766See a description :ref:`here<amdgpu_synid_dlc>`. GFX10 only. 767 768VINTRP Modifiers 769---------------- 770 771.. _amdgpu_synid_high: 772 773high 774~~~~ 775 776Specifies which half of the LDS word to use. Low half of LDS word is used by default. 777GFX9 and GFX10 only. 778 779 ======================================== ================================ 780 Syntax Description 781 ======================================== ================================ 782 high Use high half of LDS word. 783 ======================================== ================================ 784 785DPP8 Modifiers 786-------------- 787 788GFX10 only. 789 790.. _amdgpu_synid_dpp8_sel: 791 792dpp8_sel 793~~~~~~~~ 794 795Selects which lanes to pull data from, within a group of 8 lanes. This is a mandatory modifier. 796There is no default value. 797 798GFX10 only. 799 800The *dpp8_sel* modifier must specify exactly 8 values. 801First value selects which lane to read from to supply data into lane 0. 802Second value controls lane 1 and so on. 803 804Each value may be specified as either 805an :ref:`integer number<amdgpu_synid_integer_number>` or 806an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 807 808 =============================================================== =========================== 809 Syntax Description 810 =============================================================== =========================== 811 dpp8:[{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7}] Select lanes to read from. 812 =============================================================== =========================== 813 814Examples: 815 816.. parsed-literal:: 817 818 dpp8:[7,6,5,4,3,2,1,0] 819 dpp8:[0,1,0,1,0,1,0,1] 820 821.. _amdgpu_synid_fi8: 822 823fi 824~~ 825 826Controls interaction with inactive lanes for *dpp8* instructions. The default value is zero. 827 828Note: *inactive* lanes are those whose :ref:`exec<amdgpu_synid_exec>` mask bit is zero. 829 830GFX10 only. 831 832 ==================================== ===================================================== 833 Syntax Description 834 ==================================== ===================================================== 835 fi:0 Fetch zero when accessing data from inactive lanes. 836 fi:1 Fetch pre-exist values from inactive lanes. 837 ==================================== ===================================================== 838 839Note: numeric values may be specified as either :ref:`integer numbers<amdgpu_synid_integer_number>` or 840:ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 841 842DPP/DPP16 Modifiers 843------------------- 844 845GFX8, GFX9 and GFX10 only. 846 847.. _amdgpu_synid_dpp_ctrl: 848 849dpp_ctrl 850~~~~~~~~ 851 852Specifies how data are shared between threads. This is a mandatory modifier. 853There is no default value. 854 855GFX8 and GFX9 only. Use :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` for GFX10. 856 857Note: the lanes of a wavefront are organized in four *rows* and four *banks*. 858 859 ======================================== ================================================ 860 Syntax Description 861 ======================================== ================================================ 862 quad_perm:[{0..3},{0..3},{0..3},{0..3}] Full permute of 4 threads. 863 row_mirror Mirror threads within row. 864 row_half_mirror Mirror threads within 1/2 row (8 threads). 865 row_bcast:15 Broadcast 15th thread of each row to next row. 866 row_bcast:31 Broadcast thread 31 to rows 2 and 3. 867 wave_shl:1 Wavefront left shift by 1 thread. 868 wave_rol:1 Wavefront left rotate by 1 thread. 869 wave_shr:1 Wavefront right shift by 1 thread. 870 wave_ror:1 Wavefront right rotate by 1 thread. 871 row_shl:{1..15} Row shift left by 1-15 threads. 872 row_shr:{1..15} Row shift right by 1-15 threads. 873 row_ror:{1..15} Row rotate right by 1-15 threads. 874 ======================================== ================================================ 875 876Note: numeric values may be specified as either 877:ref:`integer numbers<amdgpu_synid_integer_number>` or 878:ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 879 880Examples: 881 882.. parsed-literal:: 883 884 quad_perm:[0, 1, 2, 3] 885 row_shl:3 886 887.. _amdgpu_synid_dpp16_ctrl: 888 889dpp16_ctrl 890~~~~~~~~~~ 891 892Specifies how data are shared between threads. This is a mandatory modifier. 893There is no default value. 894 895GFX10 only. Use :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` for GFX8 and GFX9. 896 897Note: the lanes of a wavefront are organized in four *rows* and four *banks*. 898(There are only two rows in *wave32* mode.) 899 900 ======================================== ==================================================== 901 Syntax Description 902 ======================================== ==================================================== 903 quad_perm:[{0..3},{0..3},{0..3},{0..3}] Full permute of 4 threads. 904 row_mirror Mirror threads within row. 905 row_half_mirror Mirror threads within 1/2 row (8 threads). 906 row_share:{0..15} Share the value from the specified lane with other 907 lanes in the row. 908 row_xmask:{0..15} Fetch from XOR(current lane id, specified lane id). 909 row_shl:{1..15} Row shift left by 1-15 threads. 910 row_shr:{1..15} Row shift right by 1-15 threads. 911 row_ror:{1..15} Row rotate right by 1-15 threads. 912 ======================================== ==================================================== 913 914Note: numeric values may be specified as either 915:ref:`integer numbers<amdgpu_synid_integer_number>` or 916:ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 917 918Examples: 919 920.. parsed-literal:: 921 922 quad_perm:[0, 1, 2, 3] 923 row_shl:3 924 925.. _amdgpu_synid_row_mask: 926 927row_mask 928~~~~~~~~ 929 930Controls which rows are enabled for data sharing. By default, all rows are enabled. 931 932Note: the lanes of a wavefront are organized in four *rows* and four *banks*. 933(There are only two rows in *wave32* mode.) 934 935 ================= ==================================================================== 936 Syntax Description 937 ================= ==================================================================== 938 row_mask:{0..15} Specifies a *row mask* as a positive 939 :ref:`integer number <amdgpu_synid_integer_number>` 940 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 941 942 Each of 4 bits in the mask controls one row 943 (0 - disabled, 1 - enabled). 944 945 In *wave32* mode the values should be limited to 0..7. 946 ================= ==================================================================== 947 948Examples: 949 950.. parsed-literal:: 951 952 row_mask:0xf 953 row_mask:0b1010 954 row_mask:x|y 955 956.. _amdgpu_synid_bank_mask: 957 958bank_mask 959~~~~~~~~~ 960 961Controls which banks are enabled for data sharing. By default, all banks are enabled. 962 963Note: the lanes of a wavefront are organized in four *rows* and four *banks*. 964(There are only two rows in *wave32* mode.) 965 966 ================== ==================================================================== 967 Syntax Description 968 ================== ==================================================================== 969 bank_mask:{0..15} Specifies a *bank mask* as a positive 970 :ref:`integer number <amdgpu_synid_integer_number>` 971 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 972 973 Each of 4 bits in the mask controls one bank 974 (0 - disabled, 1 - enabled). 975 ================== ==================================================================== 976 977Examples: 978 979.. parsed-literal:: 980 981 bank_mask:0x3 982 bank_mask:0b0011 983 bank_mask:x&y 984 985.. _amdgpu_synid_bound_ctrl: 986 987bound_ctrl 988~~~~~~~~~~ 989 990Controls data sharing when accessing an invalid lane. By default, data sharing with 991invalid lanes is disabled. 992 993 ======================================== ================================================ 994 Syntax Description 995 ======================================== ================================================ 996 bound_ctrl:0 Enables data sharing with invalid lanes. 997 998 Accessing data from an invalid lane will 999 return zero. 1000 ======================================== ================================================ 1001 1002.. _amdgpu_synid_fi16: 1003 1004fi 1005~~ 1006 1007Controls interaction with *inactive* lanes for *dpp16* instructions. The default value is zero. 1008 1009Note: *inactive* lanes are those whose :ref:`exec<amdgpu_synid_exec>` mask bit is zero. 1010 1011GFX10 only. 1012 1013 ======================================== ================================================== 1014 Syntax Description 1015 ======================================== ================================================== 1016 fi:0 Interaction with inactive lanes is controlled by 1017 :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`. 1018 1019 fi:1 Fetch pre-exist values from inactive lanes. 1020 ======================================== ================================================== 1021 1022Note: numeric values may be specified as either :ref:`integer numbers<amdgpu_synid_integer_number>` or 1023:ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 1024 1025SDWA Modifiers 1026-------------- 1027 1028GFX8, GFX9 and GFX10 only. 1029 1030clamp 1031~~~~~ 1032 1033See a description :ref:`here<amdgpu_synid_clamp>`. 1034 1035omod 1036~~~~ 1037 1038See a description :ref:`here<amdgpu_synid_omod>`. 1039 1040GFX9 and GFX10 only. 1041 1042.. _amdgpu_synid_dst_sel: 1043 1044dst_sel 1045~~~~~~~ 1046 1047Selects which bits in the destination are affected. By default, all bits are affected. 1048 1049 ======================================== ================================================ 1050 Syntax Description 1051 ======================================== ================================================ 1052 dst_sel:DWORD Use bits 31:0. 1053 dst_sel:BYTE_0 Use bits 7:0. 1054 dst_sel:BYTE_1 Use bits 15:8. 1055 dst_sel:BYTE_2 Use bits 23:16. 1056 dst_sel:BYTE_3 Use bits 31:24. 1057 dst_sel:WORD_0 Use bits 15:0. 1058 dst_sel:WORD_1 Use bits 31:16. 1059 ======================================== ================================================ 1060 1061.. _amdgpu_synid_dst_unused: 1062 1063dst_unused 1064~~~~~~~~~~ 1065 1066Controls what to do with the bits in the destination which are not selected 1067by :ref:`dst_sel<amdgpu_synid_dst_sel>`. 1068By default, unused bits are preserved. 1069 1070 ======================================== ================================================ 1071 Syntax Description 1072 ======================================== ================================================ 1073 dst_unused:UNUSED_PAD Pad with zeros. 1074 dst_unused:UNUSED_SEXT Sign-extend upper bits, zero lower bits. 1075 dst_unused:UNUSED_PRESERVE Preserve bits. 1076 ======================================== ================================================ 1077 1078.. _amdgpu_synid_src0_sel: 1079 1080src0_sel 1081~~~~~~~~ 1082 1083Controls which bits in the src0 are used. By default, all bits are used. 1084 1085 ======================================== ================================================ 1086 Syntax Description 1087 ======================================== ================================================ 1088 src0_sel:DWORD Use bits 31:0. 1089 src0_sel:BYTE_0 Use bits 7:0. 1090 src0_sel:BYTE_1 Use bits 15:8. 1091 src0_sel:BYTE_2 Use bits 23:16. 1092 src0_sel:BYTE_3 Use bits 31:24. 1093 src0_sel:WORD_0 Use bits 15:0. 1094 src0_sel:WORD_1 Use bits 31:16. 1095 ======================================== ================================================ 1096 1097.. _amdgpu_synid_src1_sel: 1098 1099src1_sel 1100~~~~~~~~ 1101 1102Controls which bits in the src1 are used. By default, all bits are used. 1103 1104 ======================================== ================================================ 1105 Syntax Description 1106 ======================================== ================================================ 1107 src1_sel:DWORD Use bits 31:0. 1108 src1_sel:BYTE_0 Use bits 7:0. 1109 src1_sel:BYTE_1 Use bits 15:8. 1110 src1_sel:BYTE_2 Use bits 23:16. 1111 src1_sel:BYTE_3 Use bits 31:24. 1112 src1_sel:WORD_0 Use bits 15:0. 1113 src1_sel:WORD_1 Use bits 31:16. 1114 ======================================== ================================================ 1115 1116.. _amdgpu_synid_sdwa_operand_modifiers: 1117 1118SDWA Operand Modifiers 1119---------------------- 1120 1121Operand modifiers are not used separately. They are applied to source operands. 1122 1123GFX8, GFX9 and GFX10 only. 1124 1125abs 1126~~~ 1127 1128See a description :ref:`here<amdgpu_synid_abs>`. 1129 1130neg 1131~~~ 1132 1133See a description :ref:`here<amdgpu_synid_neg>`. 1134 1135.. _amdgpu_synid_sext: 1136 1137sext 1138~~~~ 1139 1140Sign-extends value of a (sub-dword) operand to fill all 32 bits. 1141Has no effect for 32-bit operands. 1142 1143Valid for integer operands only. 1144 1145 ======================================== ================================================ 1146 Syntax Description 1147 ======================================== ================================================ 1148 sext(<operand>) Sign-extend operand value. 1149 ======================================== ================================================ 1150 1151Examples: 1152 1153.. parsed-literal:: 1154 1155 sext(v4) 1156 sext(v255) 1157 1158VOP3 Modifiers 1159-------------- 1160 1161.. _amdgpu_synid_vop3_op_sel: 1162 1163op_sel 1164~~~~~~ 1165 1166Selects the low [15:0] or high [31:16] operand bits for source and destination operands. 1167By default, low bits are used for all operands. 1168 1169The number of values specified with the op_sel modifier must match the number of instruction 1170operands (both source and destination). First value controls src0, second value controls src1 1171and so on, except that the last value controls destination. 1172The value 0 selects the low bits, while 1 selects the high bits. 1173 1174Note: op_sel modifier affects 16-bit operands only. For 32-bit operands the value specified 1175by op_sel must be 0. 1176 1177GFX9 and GFX10 only. 1178 1179 ======================================== ============================================================ 1180 Syntax Description 1181 ======================================== ============================================================ 1182 op_sel:[{0..1},{0..1}] Select operand bits for instructions with 1 source operand. 1183 op_sel:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 2 source operands. 1184 op_sel:[{0..1},{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands. 1185 ======================================== ============================================================ 1186 1187Note: numeric values may be specified as either 1188:ref:`integer numbers<amdgpu_synid_integer_number>` or 1189:ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 1190 1191Examples: 1192 1193.. parsed-literal:: 1194 1195 op_sel:[0,0] 1196 op_sel:[0,1] 1197 1198.. _amdgpu_synid_clamp: 1199 1200clamp 1201~~~~~ 1202 1203Clamp meaning depends on instruction. 1204 1205For *v_cmp* instructions, clamp modifier indicates that the compare signals 1206if a floating point exception occurs. By default, signaling is disabled. 1207Not supported by GFX7. 1208 1209For integer operations, clamp modifier indicates that the result must be clamped 1210to the largest and smallest representable value. By default, there is no clamping. 1211Integer clamping is not supported by GFX7. 1212 1213For floating point operations, clamp modifier indicates that the result must be clamped 1214to the range [0.0, 1.0]. By default, there is no clamping. 1215 1216Note: clamp modifier is applied after :ref:`output modifiers<amdgpu_synid_omod>` (if any). 1217 1218 ======================================== ================================================ 1219 Syntax Description 1220 ======================================== ================================================ 1221 clamp Enables clamping (or signaling). 1222 ======================================== ================================================ 1223 1224.. _amdgpu_synid_omod: 1225 1226omod 1227~~~~ 1228 1229Specifies if an output modifier must be applied to the result. 1230By default, no output modifiers are applied. 1231 1232Note: output modifiers are applied before :ref:`clamping<amdgpu_synid_clamp>` (if any). 1233 1234Output modifiers are valid for f32 and f64 floating point results only. 1235They must not be used with f16. 1236 1237Note: *v_cvt_f16_f32* is an exception. This instruction produces f16 result 1238but accepts output modifiers. 1239 1240 ======================================== ================================================ 1241 Syntax Description 1242 ======================================== ================================================ 1243 mul:2 Multiply the result by 2. 1244 mul:4 Multiply the result by 4. 1245 div:2 Multiply the result by 0.5. 1246 ======================================== ================================================ 1247 1248Note: numeric values may be specified as either :ref:`integer numbers<amdgpu_synid_integer_number>` or 1249:ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 1250 1251Examples: 1252 1253.. parsed-literal:: 1254 1255 mul:2 1256 mul:x // x must be equal to 2 or 4 1257 1258.. _amdgpu_synid_vop3_operand_modifiers: 1259 1260VOP3 Operand Modifiers 1261---------------------- 1262 1263Operand modifiers are not used separately. They are applied to source operands. 1264 1265.. _amdgpu_synid_abs: 1266 1267abs 1268~~~ 1269 1270Computes the absolute value of its operand. Must be applied before :ref:`neg<amdgpu_synid_neg>` 1271(if any). Valid for floating point operands only. 1272 1273 ======================================== ==================================================== 1274 Syntax Description 1275 ======================================== ==================================================== 1276 abs(<operand>) Get the absolute value of a floating-point operand. 1277 \|<operand>| The same as above (an SP3 syntax). 1278 ======================================== ==================================================== 1279 1280Note: avoid using SP3 syntax with operands specified as expressions because the trailing '|' 1281may be misinterpreted. Such operands should be enclosed into additional parentheses as shown 1282in examples below. 1283 1284Examples: 1285 1286.. parsed-literal:: 1287 1288 abs(v36) 1289 \|v36| 1290 abs(x|y) // ok 1291 \|(x|y)| // additional parentheses are required 1292 1293.. _amdgpu_synid_neg: 1294 1295neg 1296~~~ 1297 1298Computes the negative value of its operand. Must be applied after :ref:`abs<amdgpu_synid_abs>` 1299(if any). Valid for floating point operands only. 1300 1301 ================== ==================================================== 1302 Syntax Description 1303 ================== ==================================================== 1304 neg(<operand>) Get the negative value of a floating-point operand. 1305 The operand may include an optional 1306 :ref:`abs<amdgpu_synid_abs>` modifier. 1307 -<operand> The same as above (an SP3 syntax). 1308 ================== ==================================================== 1309 1310Note: SP3 syntax is supported with limitations because of a potential ambiguity. 1311Currently it is allowed in the following cases: 1312 1313* Before a register. 1314* Before an :ref:`abs<amdgpu_synid_abs>` modifier. 1315* Before an SP3 :ref:`abs<amdgpu_synid_abs>` modifier. 1316 1317In all other cases "-" is handled as a part of an expression that follows the sign. 1318 1319Examples: 1320 1321.. parsed-literal:: 1322 1323 // Operands with negate modifiers 1324 neg(v[0]) 1325 neg(1.0) 1326 neg(abs(v0)) 1327 -v5 1328 -abs(v5) 1329 -\|v5| 1330 1331 // Operands without negate modifiers 1332 -1 1333 -x+y 1334 1335VOP3P Modifiers 1336--------------- 1337 1338This section describes modifiers of *regular* VOP3P instructions. 1339 1340*v_mad_mix\** and *v_fma_mix\** 1341instructions use these modifiers :ref:`in a special manner<amdgpu_synid_mad_mix>`. 1342 1343GFX9 and GFX10 only. 1344 1345.. _amdgpu_synid_op_sel: 1346 1347op_sel 1348~~~~~~ 1349 1350Selects the low [15:0] or high [31:16] operand bits as input to the operation 1351which results in the lower-half of the destination. 1352By default, low bits are used for all operands. 1353 1354The number of values specified by the *op_sel* modifier must match the number of source 1355operands. First value controls src0, second value controls src1 and so on. 1356 1357The value 0 selects the low bits, while 1 selects the high bits. 1358 1359 ================================= ============================================================= 1360 Syntax Description 1361 ================================= ============================================================= 1362 op_sel:[{0..1}] Select operand bits for instructions with 1 source operand. 1363 op_sel:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands. 1364 op_sel:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands. 1365 ================================= ============================================================= 1366 1367Note: numeric values may be specified as either 1368:ref:`integer numbers<amdgpu_synid_integer_number>` or 1369:ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 1370 1371Examples: 1372 1373.. parsed-literal:: 1374 1375 op_sel:[0,0] 1376 op_sel:[0,1,0] 1377 1378.. _amdgpu_synid_op_sel_hi: 1379 1380op_sel_hi 1381~~~~~~~~~ 1382 1383Selects the low [15:0] or high [31:16] operand bits as input to the operation 1384which results in the upper-half of the destination. 1385By default, high bits are used for all operands. 1386 1387The number of values specified by the *op_sel_hi* modifier must match the number of source 1388operands. First value controls src0, second value controls src1 and so on. 1389 1390The value 0 selects the low bits, while 1 selects the high bits. 1391 1392 =================================== ============================================================= 1393 Syntax Description 1394 =================================== ============================================================= 1395 op_sel_hi:[{0..1}] Select operand bits for instructions with 1 source operand. 1396 op_sel_hi:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands. 1397 op_sel_hi:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands. 1398 =================================== ============================================================= 1399 1400Note: numeric values may be specified as either 1401:ref:`integer numbers<amdgpu_synid_integer_number>` or 1402:ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 1403 1404Examples: 1405 1406.. parsed-literal:: 1407 1408 op_sel_hi:[0,0] 1409 op_sel_hi:[0,0,1] 1410 1411.. _amdgpu_synid_neg_lo: 1412 1413neg_lo 1414~~~~~~ 1415 1416Specifies whether to change sign of operand values selected by 1417:ref:`op_sel<amdgpu_synid_op_sel>`. These values are then used 1418as input to the operation which results in the upper-half of the destination. 1419 1420The number of values specified by this modifier must match the number of source 1421operands. First value controls src0, second value controls src1 and so on. 1422 1423The value 0 indicates that the corresponding operand value is used unmodified, 1424the value 1 indicates that negative value of the operand must be used. 1425 1426By default, operand values are used unmodified. 1427 1428This modifier is valid for floating point operands only. 1429 1430 ================================ ================================================================== 1431 Syntax Description 1432 ================================ ================================================================== 1433 neg_lo:[{0..1}] Select affected operands for instructions with 1 source operand. 1434 neg_lo:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands. 1435 neg_lo:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands. 1436 ================================ ================================================================== 1437 1438Note: numeric values may be specified as either 1439:ref:`integer numbers<amdgpu_synid_integer_number>` or 1440:ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 1441 1442Examples: 1443 1444.. parsed-literal:: 1445 1446 neg_lo:[0] 1447 neg_lo:[0,1] 1448 1449.. _amdgpu_synid_neg_hi: 1450 1451neg_hi 1452~~~~~~ 1453 1454Specifies whether to change sign of operand values selected by 1455:ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`. These values are then used 1456as input to the operation which results in the upper-half of the destination. 1457 1458The number of values specified by this modifier must match the number of source 1459operands. First value controls src0, second value controls src1 and so on. 1460 1461The value 0 indicates that the corresponding operand value is used unmodified, 1462the value 1 indicates that negative value of the operand must be used. 1463 1464By default, operand values are used unmodified. 1465 1466This modifier is valid for floating point operands only. 1467 1468 =============================== ================================================================== 1469 Syntax Description 1470 =============================== ================================================================== 1471 neg_hi:[{0..1}] Select affected operands for instructions with 1 source operand. 1472 neg_hi:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands. 1473 neg_hi:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands. 1474 =============================== ================================================================== 1475 1476Note: numeric values may be specified as either 1477:ref:`integer numbers<amdgpu_synid_integer_number>` or 1478:ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 1479 1480Examples: 1481 1482.. parsed-literal:: 1483 1484 neg_hi:[1,0] 1485 neg_hi:[0,1,1] 1486 1487clamp 1488~~~~~ 1489 1490See a description :ref:`here<amdgpu_synid_clamp>`. 1491 1492.. _amdgpu_synid_mad_mix: 1493 1494VOP3P V_MAD_MIX Modifiers 1495------------------------- 1496 1497*v_mad_mix\** and *v_fma_mix\** 1498instructions use *op_sel* and *op_sel_hi* modifiers 1499in a manner different from *regular* VOP3P instructions. 1500 1501See a description below. 1502 1503GFX9 and GFX10 only. 1504 1505.. _amdgpu_synid_mad_mix_op_sel: 1506 1507m_op_sel 1508~~~~~~~~ 1509 1510This operand has meaning only for 16-bit source operands as indicated by 1511:ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`. 1512It specifies to select either the low [15:0] or high [31:16] operand bits 1513as input to the operation. 1514 1515The number of values specified by the *op_sel* modifier must match the number of source 1516operands. First value controls src0, second value controls src1 and so on. 1517 1518The value 0 indicates the low bits, the value 1 indicates the high 16 bits. 1519 1520By default, low bits are used for all operands. 1521 1522 =============================== ================================================ 1523 Syntax Description 1524 =============================== ================================================ 1525 op_sel:[{0..1},{0..1},{0..1}] Select location of each 16-bit source operand. 1526 =============================== ================================================ 1527 1528Note: numeric values may be specified as either 1529:ref:`integer numbers<amdgpu_synid_integer_number>` or 1530:ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 1531 1532Examples: 1533 1534.. parsed-literal:: 1535 1536 op_sel:[0,1] 1537 1538.. _amdgpu_synid_mad_mix_op_sel_hi: 1539 1540m_op_sel_hi 1541~~~~~~~~~~~ 1542 1543Selects the size of source operands: either 32 bits or 16 bits. 1544By default, 32 bits are used for all source operands. 1545 1546The number of values specified by the *op_sel_hi* modifier must match the number of source 1547operands. First value controls src0, second value controls src1 and so on. 1548 1549The value 0 indicates 32 bits, the value 1 indicates 16 bits. 1550 1551The location of 16 bits in the operand may be specified by 1552:ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`. 1553 1554 ======================================== ==================================== 1555 Syntax Description 1556 ======================================== ==================================== 1557 op_sel_hi:[{0..1},{0..1},{0..1}] Select size of each source operand. 1558 ======================================== ==================================== 1559 1560Note: numeric values may be specified as either 1561:ref:`integer numbers<amdgpu_synid_integer_number>` or 1562:ref:`absolute expressions<amdgpu_synid_absolute_expression>`. 1563 1564Examples: 1565 1566.. parsed-literal:: 1567 1568 op_sel_hi:[1,1,1] 1569 1570abs 1571~~~ 1572 1573See a description :ref:`here<amdgpu_synid_abs>`. 1574 1575neg 1576~~~ 1577 1578See a description :ref:`here<amdgpu_synid_neg>`. 1579 1580clamp 1581~~~~~ 1582 1583See a description :ref:`here<amdgpu_synid_clamp>`. 1584 1585VOP3P MFMA Modifiers 1586-------------------- 1587 1588.. _amdgpu_synid_cbsz: 1589 1590cbsz 1591~~~~ 1592 1593 =============================== ================================================================== 1594 Syntax Description 1595 =============================== ================================================================== 1596 cbsz:[{0..7}] TBD 1597 =============================== ================================================================== 1598 1599Note: numeric value may be specified as either 1600an :ref:`integer number<amdgpu_synid_integer_number>` or 1601an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 1602 1603.. _amdgpu_synid_abid: 1604 1605abid 1606~~~~ 1607 1608 =============================== ================================================================== 1609 Syntax Description 1610 =============================== ================================================================== 1611 abid:[{0..15}] TBD 1612 =============================== ================================================================== 1613 1614Note: numeric value may be specified as either 1615an :ref:`integer number<amdgpu_synid_integer_number>` or 1616an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 1617 1618.. _amdgpu_synid_blgp: 1619 1620blgp 1621~~~~ 1622 1623 =============================== ================================================================== 1624 Syntax Description 1625 =============================== ================================================================== 1626 blgp:[{0..7}] TBD 1627 =============================== ================================================================== 1628 1629Note: numeric value may be specified as either 1630an :ref:`integer number<amdgpu_synid_integer_number>` or 1631an :ref:`absolute expression<amdgpu_synid_absolute_expression>`. 1632 1633