1 //===-- DNBArchImplX86_64.cpp -----------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Created by Greg Clayton on 6/25/07. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #if defined (__i386__) || defined (__x86_64__) 15 16 #include <sys/cdefs.h> 17 #include <sys/types.h> 18 #include <sys/sysctl.h> 19 20 #include "MacOSX/x86_64/DNBArchImplX86_64.h" 21 #include "DNBLog.h" 22 #include "MachThread.h" 23 #include "MachProcess.h" 24 #include <mach/mach.h> 25 #include <stdlib.h> 26 27 #if defined (LLDB_DEBUGSERVER_RELEASE) || defined (LLDB_DEBUGSERVER_DEBUG) 28 enum debugState { 29 debugStateUnknown, 30 debugStateOff, 31 debugStateOn 32 }; 33 34 static debugState sFPUDebugState = debugStateUnknown; 35 static debugState sAVXForceState = debugStateUnknown; 36 37 static bool DebugFPURegs () 38 { 39 if (sFPUDebugState == debugStateUnknown) 40 { 41 if (getenv("DNB_DEBUG_FPU_REGS")) 42 sFPUDebugState = debugStateOn; 43 else 44 sFPUDebugState = debugStateOff; 45 } 46 47 return (sFPUDebugState == debugStateOn); 48 } 49 50 static bool ForceAVXRegs () 51 { 52 if (sFPUDebugState == debugStateUnknown) 53 { 54 if (getenv("DNB_DEBUG_X86_FORCE_AVX_REGS")) 55 sAVXForceState = debugStateOn; 56 else 57 sAVXForceState = debugStateOff; 58 } 59 60 return (sAVXForceState == debugStateOn); 61 } 62 63 #define DEBUG_FPU_REGS (DebugFPURegs()) 64 #define FORCE_AVX_REGS (ForceAVXRegs()) 65 #else 66 #define DEBUG_FPU_REGS (0) 67 #define FORCE_AVX_REGS (0) 68 #endif 69 70 71 extern "C" bool 72 CPUHasAVX() 73 { 74 enum AVXPresence 75 { 76 eAVXUnknown = -1, 77 eAVXNotPresent = 0, 78 eAVXPresent = 1 79 }; 80 81 static AVXPresence g_has_avx = eAVXUnknown; 82 if (g_has_avx == eAVXUnknown) 83 { 84 g_has_avx = eAVXNotPresent; 85 86 // Only xnu-2020 or later has AVX support, any versions before 87 // this have a busted thread_get_state RPC where it would truncate 88 // the thread state buffer (<rdar://problem/10122874>). So we need to 89 // verify the kernel version number manually or disable AVX support. 90 int mib[2]; 91 char buffer[1024]; 92 size_t length = sizeof(buffer); 93 uint64_t xnu_version = 0; 94 mib[0] = CTL_KERN; 95 mib[1] = KERN_VERSION; 96 int err = ::sysctl(mib, 2, &buffer, &length, NULL, 0); 97 if (err == 0) 98 { 99 const char *xnu = strstr (buffer, "xnu-"); 100 if (xnu) 101 { 102 const char *xnu_version_cstr = xnu + 4; 103 xnu_version = strtoull (xnu_version_cstr, NULL, 0); 104 if (xnu_version >= 2020 && xnu_version != ULLONG_MAX) 105 { 106 if (::HasAVX()) 107 { 108 g_has_avx = eAVXPresent; 109 } 110 } 111 } 112 } 113 DNBLogThreadedIf (LOG_THREAD, "CPUHasAVX(): g_has_avx = %i (err = %i, errno = %i, xnu_version = %llu)", g_has_avx, err, errno, xnu_version); 114 } 115 116 return (g_has_avx == eAVXPresent); 117 } 118 119 uint64_t 120 DNBArchImplX86_64::GetPC(uint64_t failValue) 121 { 122 // Get program counter 123 if (GetGPRState(false) == KERN_SUCCESS) 124 return m_state.context.gpr.__rip; 125 return failValue; 126 } 127 128 kern_return_t 129 DNBArchImplX86_64::SetPC(uint64_t value) 130 { 131 // Get program counter 132 kern_return_t err = GetGPRState(false); 133 if (err == KERN_SUCCESS) 134 { 135 m_state.context.gpr.__rip = value; 136 err = SetGPRState(); 137 } 138 return err == KERN_SUCCESS; 139 } 140 141 uint64_t 142 DNBArchImplX86_64::GetSP(uint64_t failValue) 143 { 144 // Get stack pointer 145 if (GetGPRState(false) == KERN_SUCCESS) 146 return m_state.context.gpr.__rsp; 147 return failValue; 148 } 149 150 // Uncomment the value below to verify the values in the debugger. 151 //#define DEBUG_GPR_VALUES 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED 152 153 kern_return_t 154 DNBArchImplX86_64::GetGPRState(bool force) 155 { 156 if (force || m_state.GetError(e_regSetGPR, Read)) 157 { 158 #if DEBUG_GPR_VALUES 159 m_state.context.gpr.__rax = ('a' << 8) + 'x'; 160 m_state.context.gpr.__rbx = ('b' << 8) + 'x'; 161 m_state.context.gpr.__rcx = ('c' << 8) + 'x'; 162 m_state.context.gpr.__rdx = ('d' << 8) + 'x'; 163 m_state.context.gpr.__rdi = ('d' << 8) + 'i'; 164 m_state.context.gpr.__rsi = ('s' << 8) + 'i'; 165 m_state.context.gpr.__rbp = ('b' << 8) + 'p'; 166 m_state.context.gpr.__rsp = ('s' << 8) + 'p'; 167 m_state.context.gpr.__r8 = ('r' << 8) + '8'; 168 m_state.context.gpr.__r9 = ('r' << 8) + '9'; 169 m_state.context.gpr.__r10 = ('r' << 8) + 'a'; 170 m_state.context.gpr.__r11 = ('r' << 8) + 'b'; 171 m_state.context.gpr.__r12 = ('r' << 8) + 'c'; 172 m_state.context.gpr.__r13 = ('r' << 8) + 'd'; 173 m_state.context.gpr.__r14 = ('r' << 8) + 'e'; 174 m_state.context.gpr.__r15 = ('r' << 8) + 'f'; 175 m_state.context.gpr.__rip = ('i' << 8) + 'p'; 176 m_state.context.gpr.__rflags = ('f' << 8) + 'l'; 177 m_state.context.gpr.__cs = ('c' << 8) + 's'; 178 m_state.context.gpr.__fs = ('f' << 8) + 's'; 179 m_state.context.gpr.__gs = ('g' << 8) + 's'; 180 m_state.SetError(e_regSetGPR, Read, 0); 181 #else 182 mach_msg_type_number_t count = e_regSetWordSizeGPR; 183 m_state.SetError(e_regSetGPR, Read, ::thread_get_state(m_thread->MachPortNumber(), __x86_64_THREAD_STATE, (thread_state_t)&m_state.context.gpr, &count)); 184 DNBLogThreadedIf (LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 185 "\n\trax = %16.16llx rbx = %16.16llx rcx = %16.16llx rdx = %16.16llx" 186 "\n\trdi = %16.16llx rsi = %16.16llx rbp = %16.16llx rsp = %16.16llx" 187 "\n\t r8 = %16.16llx r9 = %16.16llx r10 = %16.16llx r11 = %16.16llx" 188 "\n\tr12 = %16.16llx r13 = %16.16llx r14 = %16.16llx r15 = %16.16llx" 189 "\n\trip = %16.16llx" 190 "\n\tflg = %16.16llx cs = %16.16llx fs = %16.16llx gs = %16.16llx", 191 m_thread->MachPortNumber(), x86_THREAD_STATE64, x86_THREAD_STATE64_COUNT, 192 m_state.GetError(e_regSetGPR, Read), 193 m_state.context.gpr.__rax,m_state.context.gpr.__rbx,m_state.context.gpr.__rcx, 194 m_state.context.gpr.__rdx,m_state.context.gpr.__rdi,m_state.context.gpr.__rsi, 195 m_state.context.gpr.__rbp,m_state.context.gpr.__rsp,m_state.context.gpr.__r8, 196 m_state.context.gpr.__r9, m_state.context.gpr.__r10,m_state.context.gpr.__r11, 197 m_state.context.gpr.__r12,m_state.context.gpr.__r13,m_state.context.gpr.__r14, 198 m_state.context.gpr.__r15,m_state.context.gpr.__rip,m_state.context.gpr.__rflags, 199 m_state.context.gpr.__cs,m_state.context.gpr.__fs, m_state.context.gpr.__gs); 200 201 // DNBLogThreadedIf (LOG_THREAD, "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 202 // "\n\trax = %16.16llx" 203 // "\n\trbx = %16.16llx" 204 // "\n\trcx = %16.16llx" 205 // "\n\trdx = %16.16llx" 206 // "\n\trdi = %16.16llx" 207 // "\n\trsi = %16.16llx" 208 // "\n\trbp = %16.16llx" 209 // "\n\trsp = %16.16llx" 210 // "\n\t r8 = %16.16llx" 211 // "\n\t r9 = %16.16llx" 212 // "\n\tr10 = %16.16llx" 213 // "\n\tr11 = %16.16llx" 214 // "\n\tr12 = %16.16llx" 215 // "\n\tr13 = %16.16llx" 216 // "\n\tr14 = %16.16llx" 217 // "\n\tr15 = %16.16llx" 218 // "\n\trip = %16.16llx" 219 // "\n\tflg = %16.16llx" 220 // "\n\t cs = %16.16llx" 221 // "\n\t fs = %16.16llx" 222 // "\n\t gs = %16.16llx", 223 // m_thread->MachPortNumber(), 224 // x86_THREAD_STATE64, 225 // x86_THREAD_STATE64_COUNT, 226 // m_state.GetError(e_regSetGPR, Read), 227 // m_state.context.gpr.__rax, 228 // m_state.context.gpr.__rbx, 229 // m_state.context.gpr.__rcx, 230 // m_state.context.gpr.__rdx, 231 // m_state.context.gpr.__rdi, 232 // m_state.context.gpr.__rsi, 233 // m_state.context.gpr.__rbp, 234 // m_state.context.gpr.__rsp, 235 // m_state.context.gpr.__r8, 236 // m_state.context.gpr.__r9, 237 // m_state.context.gpr.__r10, 238 // m_state.context.gpr.__r11, 239 // m_state.context.gpr.__r12, 240 // m_state.context.gpr.__r13, 241 // m_state.context.gpr.__r14, 242 // m_state.context.gpr.__r15, 243 // m_state.context.gpr.__rip, 244 // m_state.context.gpr.__rflags, 245 // m_state.context.gpr.__cs, 246 // m_state.context.gpr.__fs, 247 // m_state.context.gpr.__gs); 248 #endif 249 } 250 return m_state.GetError(e_regSetGPR, Read); 251 } 252 253 // Uncomment the value below to verify the values in the debugger. 254 //#define DEBUG_FPU_REGS 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED 255 256 kern_return_t 257 DNBArchImplX86_64::GetFPUState(bool force) 258 { 259 if (force || m_state.GetError(e_regSetFPU, Read)) 260 { 261 if (DEBUG_FPU_REGS) { 262 if (CPUHasAVX() || FORCE_AVX_REGS) 263 { 264 m_state.context.fpu.avx.__fpu_reserved[0] = -1; 265 m_state.context.fpu.avx.__fpu_reserved[1] = -1; 266 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234; 267 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678; 268 m_state.context.fpu.avx.__fpu_ftw = 1; 269 m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX; 270 m_state.context.fpu.avx.__fpu_fop = 2; 271 m_state.context.fpu.avx.__fpu_ip = 3; 272 m_state.context.fpu.avx.__fpu_cs = 4; 273 m_state.context.fpu.avx.__fpu_rsrv2 = UINT8_MAX; 274 m_state.context.fpu.avx.__fpu_dp = 5; 275 m_state.context.fpu.avx.__fpu_ds = 6; 276 m_state.context.fpu.avx.__fpu_rsrv3 = UINT16_MAX; 277 m_state.context.fpu.avx.__fpu_mxcsr = 8; 278 m_state.context.fpu.avx.__fpu_mxcsrmask = 9; 279 int i; 280 for (i=0; i<16; ++i) 281 { 282 if (i<10) 283 { 284 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = 'a'; 285 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = 'b'; 286 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = 'c'; 287 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = 'd'; 288 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = 'e'; 289 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = 'f'; 290 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = 'g'; 291 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = 'h'; 292 } 293 else 294 { 295 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN; 296 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN; 297 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN; 298 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN; 299 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN; 300 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN; 301 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN; 302 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN; 303 } 304 305 m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0' + 2 * i; 306 m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1' + 2 * i; 307 m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2' + 2 * i; 308 m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3' + 2 * i; 309 m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4' + 2 * i; 310 m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5' + 2 * i; 311 m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6' + 2 * i; 312 m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7' + 2 * i; 313 m_state.context.fpu.avx.__fpu_xmm8.__xmm_reg[i] = '8' + 2 * i; 314 m_state.context.fpu.avx.__fpu_xmm9.__xmm_reg[i] = '9' + 2 * i; 315 m_state.context.fpu.avx.__fpu_xmm10.__xmm_reg[i] = 'A' + 2 * i; 316 m_state.context.fpu.avx.__fpu_xmm11.__xmm_reg[i] = 'B' + 2 * i; 317 m_state.context.fpu.avx.__fpu_xmm12.__xmm_reg[i] = 'C' + 2 * i; 318 m_state.context.fpu.avx.__fpu_xmm13.__xmm_reg[i] = 'D' + 2 * i; 319 m_state.context.fpu.avx.__fpu_xmm14.__xmm_reg[i] = 'E' + 2 * i; 320 m_state.context.fpu.avx.__fpu_xmm15.__xmm_reg[i] = 'F' + 2 * i; 321 322 m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0' + i; 323 m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1' + i; 324 m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2' + i; 325 m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3' + i; 326 m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4' + i; 327 m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5' + i; 328 m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6' + i; 329 m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7' + i; 330 m_state.context.fpu.avx.__fpu_ymmh8.__xmm_reg[i] = '8' + i; 331 m_state.context.fpu.avx.__fpu_ymmh9.__xmm_reg[i] = '9' + i; 332 m_state.context.fpu.avx.__fpu_ymmh10.__xmm_reg[i] = 'A' + i; 333 m_state.context.fpu.avx.__fpu_ymmh11.__xmm_reg[i] = 'B' + i; 334 m_state.context.fpu.avx.__fpu_ymmh12.__xmm_reg[i] = 'C' + i; 335 m_state.context.fpu.avx.__fpu_ymmh13.__xmm_reg[i] = 'D' + i; 336 m_state.context.fpu.avx.__fpu_ymmh14.__xmm_reg[i] = 'E' + i; 337 m_state.context.fpu.avx.__fpu_ymmh15.__xmm_reg[i] = 'F' + i; 338 } 339 for (i=0; i<sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i) 340 m_state.context.fpu.avx.__fpu_rsrv4[i] = INT8_MIN; 341 m_state.context.fpu.avx.__fpu_reserved1 = -1; 342 for (i=0; i<sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i) 343 m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN; 344 m_state.SetError(e_regSetFPU, Read, 0); 345 } 346 else 347 { 348 m_state.context.fpu.no_avx.__fpu_reserved[0] = -1; 349 m_state.context.fpu.no_avx.__fpu_reserved[1] = -1; 350 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234; 351 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678; 352 m_state.context.fpu.no_avx.__fpu_ftw = 1; 353 m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX; 354 m_state.context.fpu.no_avx.__fpu_fop = 2; 355 m_state.context.fpu.no_avx.__fpu_ip = 3; 356 m_state.context.fpu.no_avx.__fpu_cs = 4; 357 m_state.context.fpu.no_avx.__fpu_rsrv2 = 5; 358 m_state.context.fpu.no_avx.__fpu_dp = 6; 359 m_state.context.fpu.no_avx.__fpu_ds = 7; 360 m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX; 361 m_state.context.fpu.no_avx.__fpu_mxcsr = 8; 362 m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9; 363 int i; 364 for (i=0; i<16; ++i) 365 { 366 if (i<10) 367 { 368 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a'; 369 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b'; 370 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c'; 371 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd'; 372 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e'; 373 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f'; 374 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g'; 375 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h'; 376 } 377 else 378 { 379 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN; 380 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN; 381 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN; 382 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN; 383 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN; 384 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN; 385 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN; 386 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN; 387 } 388 389 m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0'; 390 m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1'; 391 m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2'; 392 m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3'; 393 m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4'; 394 m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5'; 395 m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6'; 396 m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7'; 397 m_state.context.fpu.no_avx.__fpu_xmm8.__xmm_reg[i] = '8'; 398 m_state.context.fpu.no_avx.__fpu_xmm9.__xmm_reg[i] = '9'; 399 m_state.context.fpu.no_avx.__fpu_xmm10.__xmm_reg[i] = 'A'; 400 m_state.context.fpu.no_avx.__fpu_xmm11.__xmm_reg[i] = 'B'; 401 m_state.context.fpu.no_avx.__fpu_xmm12.__xmm_reg[i] = 'C'; 402 m_state.context.fpu.no_avx.__fpu_xmm13.__xmm_reg[i] = 'D'; 403 m_state.context.fpu.no_avx.__fpu_xmm14.__xmm_reg[i] = 'E'; 404 m_state.context.fpu.no_avx.__fpu_xmm15.__xmm_reg[i] = 'F'; 405 } 406 for (i=0; i<sizeof(m_state.context.fpu.no_avx.__fpu_rsrv4); ++i) 407 m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN; 408 m_state.context.fpu.no_avx.__fpu_reserved1 = -1; 409 m_state.SetError(e_regSetFPU, Read, 0); 410 } 411 } 412 else 413 { 414 if (CPUHasAVX() || FORCE_AVX_REGS) 415 { 416 mach_msg_type_number_t count = e_regSetWordSizeAVX; 417 m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->MachPortNumber(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, &count)); 418 DNBLogThreadedIf (LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &avx, %u (%u passed in) carp) => 0x%8.8x", 419 m_thread->MachPortNumber(), __x86_64_AVX_STATE, (uint32_t)count, 420 e_regSetWordSizeAVX, m_state.GetError(e_regSetFPU, Read)); 421 } 422 else 423 { 424 mach_msg_type_number_t count = e_regSetWordSizeFPU; 425 m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->MachPortNumber(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, &count)); 426 DNBLogThreadedIf (LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &fpu, %u (%u passed in) => 0x%8.8x", 427 m_thread->MachPortNumber(), __x86_64_FLOAT_STATE, (uint32_t)count, 428 e_regSetWordSizeFPU, m_state.GetError(e_regSetFPU, Read)); 429 } 430 } 431 } 432 return m_state.GetError(e_regSetFPU, Read); 433 } 434 435 kern_return_t 436 DNBArchImplX86_64::GetEXCState(bool force) 437 { 438 if (force || m_state.GetError(e_regSetEXC, Read)) 439 { 440 mach_msg_type_number_t count = e_regSetWordSizeEXC; 441 m_state.SetError(e_regSetEXC, Read, ::thread_get_state(m_thread->MachPortNumber(), __x86_64_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, &count)); 442 } 443 return m_state.GetError(e_regSetEXC, Read); 444 } 445 446 kern_return_t 447 DNBArchImplX86_64::SetGPRState() 448 { 449 kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber()); 450 DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (SetGPRState() for stop_count = %u)", m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount()); 451 452 m_state.SetError(e_regSetGPR, Write, ::thread_set_state(m_thread->MachPortNumber(), __x86_64_THREAD_STATE, (thread_state_t)&m_state.context.gpr, e_regSetWordSizeGPR)); 453 DNBLogThreadedIf (LOG_THREAD, "::thread_set_state (0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 454 "\n\trax = %16.16llx rbx = %16.16llx rcx = %16.16llx rdx = %16.16llx" 455 "\n\trdi = %16.16llx rsi = %16.16llx rbp = %16.16llx rsp = %16.16llx" 456 "\n\t r8 = %16.16llx r9 = %16.16llx r10 = %16.16llx r11 = %16.16llx" 457 "\n\tr12 = %16.16llx r13 = %16.16llx r14 = %16.16llx r15 = %16.16llx" 458 "\n\trip = %16.16llx" 459 "\n\tflg = %16.16llx cs = %16.16llx fs = %16.16llx gs = %16.16llx", 460 m_thread->MachPortNumber(), __x86_64_THREAD_STATE, e_regSetWordSizeGPR, 461 m_state.GetError(e_regSetGPR, Write), 462 m_state.context.gpr.__rax,m_state.context.gpr.__rbx,m_state.context.gpr.__rcx, 463 m_state.context.gpr.__rdx,m_state.context.gpr.__rdi,m_state.context.gpr.__rsi, 464 m_state.context.gpr.__rbp,m_state.context.gpr.__rsp,m_state.context.gpr.__r8, 465 m_state.context.gpr.__r9, m_state.context.gpr.__r10,m_state.context.gpr.__r11, 466 m_state.context.gpr.__r12,m_state.context.gpr.__r13,m_state.context.gpr.__r14, 467 m_state.context.gpr.__r15,m_state.context.gpr.__rip,m_state.context.gpr.__rflags, 468 m_state.context.gpr.__cs, m_state.context.gpr.__fs, m_state.context.gpr.__gs); 469 return m_state.GetError(e_regSetGPR, Write); 470 } 471 472 kern_return_t 473 DNBArchImplX86_64::SetFPUState() 474 { 475 if (DEBUG_FPU_REGS) 476 { 477 m_state.SetError(e_regSetFPU, Write, 0); 478 return m_state.GetError(e_regSetFPU, Write); 479 } 480 else 481 { 482 if (CPUHasAVX() || FORCE_AVX_REGS) 483 { 484 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->MachPortNumber(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, e_regSetWordSizeAVX)); 485 return m_state.GetError(e_regSetFPU, Write); 486 } 487 else 488 { 489 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->MachPortNumber(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, e_regSetWordSizeFPU)); 490 return m_state.GetError(e_regSetFPU, Write); 491 } 492 } 493 } 494 495 kern_return_t 496 DNBArchImplX86_64::SetEXCState() 497 { 498 m_state.SetError(e_regSetEXC, Write, ::thread_set_state(m_thread->MachPortNumber(), __x86_64_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, e_regSetWordSizeEXC)); 499 return m_state.GetError(e_regSetEXC, Write); 500 } 501 502 kern_return_t 503 DNBArchImplX86_64::GetDBGState(bool force) 504 { 505 if (force || m_state.GetError(e_regSetDBG, Read)) 506 { 507 mach_msg_type_number_t count = e_regSetWordSizeDBG; 508 m_state.SetError(e_regSetDBG, Read, ::thread_get_state(m_thread->MachPortNumber(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, &count)); 509 } 510 return m_state.GetError(e_regSetDBG, Read); 511 } 512 513 kern_return_t 514 DNBArchImplX86_64::SetDBGState(bool also_set_on_task) 515 { 516 m_state.SetError(e_regSetDBG, Write, ::thread_set_state(m_thread->MachPortNumber(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG)); 517 if (also_set_on_task) 518 { 519 kern_return_t kret = ::task_set_state(m_thread->Process()->Task().TaskPort(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG); 520 if (kret != KERN_SUCCESS) 521 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::SetDBGState failed to set debug control register state: 0x%8.8x.", kret); 522 } 523 return m_state.GetError(e_regSetDBG, Write); 524 } 525 526 void 527 DNBArchImplX86_64::ThreadWillResume() 528 { 529 // Do we need to step this thread? If so, let the mach thread tell us so. 530 if (m_thread->IsStepping()) 531 { 532 // This is the primary thread, let the arch do anything it needs 533 EnableHardwareSingleStep(true); 534 } 535 536 // Reset the debug status register, if necessary, before we resume. 537 kern_return_t kret = GetDBGState(false); 538 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::ThreadWillResume() GetDBGState() => 0x%8.8x.", kret); 539 if (kret != KERN_SUCCESS) 540 return; 541 542 DBG &debug_state = m_state.context.dbg; 543 bool need_reset = false; 544 uint32_t i, num = NumSupportedHardwareWatchpoints(); 545 for (i = 0; i < num; ++i) 546 if (IsWatchpointHit(debug_state, i)) 547 need_reset = true; 548 549 if (need_reset) 550 { 551 ClearWatchpointHits(debug_state); 552 kret = SetDBGState(false); 553 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::ThreadWillResume() SetDBGState() => 0x%8.8x.", kret); 554 } 555 } 556 557 bool 558 DNBArchImplX86_64::ThreadDidStop() 559 { 560 bool success = true; 561 562 m_state.InvalidateAllRegisterStates(); 563 564 // Are we stepping a single instruction? 565 if (GetGPRState(true) == KERN_SUCCESS) 566 { 567 // We are single stepping, was this the primary thread? 568 if (m_thread->IsStepping()) 569 { 570 // This was the primary thread, we need to clear the trace 571 // bit if so. 572 success = EnableHardwareSingleStep(false) == KERN_SUCCESS; 573 } 574 else 575 { 576 // The MachThread will automatically restore the suspend count 577 // in ThreadDidStop(), so we don't need to do anything here if 578 // we weren't the primary thread the last time 579 } 580 } 581 return success; 582 } 583 584 bool 585 DNBArchImplX86_64::NotifyException(MachException::Data& exc) 586 { 587 switch (exc.exc_type) 588 { 589 case EXC_BAD_ACCESS: 590 break; 591 case EXC_BAD_INSTRUCTION: 592 break; 593 case EXC_ARITHMETIC: 594 break; 595 case EXC_EMULATION: 596 break; 597 case EXC_SOFTWARE: 598 break; 599 case EXC_BREAKPOINT: 600 if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 2) 601 { 602 // exc_code = EXC_I386_BPT 603 // 604 nub_addr_t pc = GetPC(INVALID_NUB_ADDRESS); 605 if (pc != INVALID_NUB_ADDRESS && pc > 0) 606 { 607 pc -= 1; 608 // Check for a breakpoint at one byte prior to the current PC value 609 // since the PC will be just past the trap. 610 611 DNBBreakpoint *bp = m_thread->Process()->Breakpoints().FindByAddress(pc); 612 if (bp) 613 { 614 // Backup the PC for i386 since the trap was taken and the PC 615 // is at the address following the single byte trap instruction. 616 if (m_state.context.gpr.__rip > 0) 617 { 618 m_state.context.gpr.__rip = pc; 619 // Write the new PC back out 620 SetGPRState (); 621 } 622 } 623 return true; 624 } 625 } 626 else if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 1) 627 { 628 // exc_code = EXC_I386_SGL 629 // 630 // Check whether this corresponds to a watchpoint hit event. 631 // If yes, set the exc_sub_code to the data break address. 632 nub_addr_t addr = 0; 633 uint32_t hw_index = GetHardwareWatchpointHit(addr); 634 if (hw_index != INVALID_NUB_HW_INDEX) 635 { 636 exc.exc_data[1] = addr; 637 // Piggyback the hw_index in the exc.data. 638 exc.exc_data.push_back(hw_index); 639 } 640 641 return true; 642 } 643 break; 644 case EXC_SYSCALL: 645 break; 646 case EXC_MACH_SYSCALL: 647 break; 648 case EXC_RPC_ALERT: 649 break; 650 } 651 return false; 652 } 653 654 uint32_t 655 DNBArchImplX86_64::NumSupportedHardwareWatchpoints() 656 { 657 // Available debug address registers: dr0, dr1, dr2, dr3. 658 return 4; 659 } 660 661 static uint32_t 662 size_and_rw_bits(nub_size_t size, bool read, bool write) 663 { 664 uint32_t rw; 665 if (read) { 666 rw = 0x3; // READ or READ/WRITE 667 } else if (write) { 668 rw = 0x1; // WRITE 669 } else { 670 assert(0 && "read and write cannot both be false"); 671 } 672 673 switch (size) { 674 case 1: 675 return rw; 676 case 2: 677 return (0x1 << 2) | rw; 678 case 4: 679 return (0x3 << 2) | rw; 680 case 8: 681 return (0x2 << 2) | rw; 682 default: 683 assert(0 && "invalid size, must be one of 1, 2, 4, or 8"); 684 } 685 } 686 void 687 DNBArchImplX86_64::SetWatchpoint(DBG &debug_state, uint32_t hw_index, nub_addr_t addr, nub_size_t size, bool read, bool write) 688 { 689 // Set both dr7 (debug control register) and dri (debug address register). 690 691 // dr7{7-0} encodes the local/gloabl enable bits: 692 // global enable --. .-- local enable 693 // | | 694 // v v 695 // dr0 -> bits{1-0} 696 // dr1 -> bits{3-2} 697 // dr2 -> bits{5-4} 698 // dr3 -> bits{7-6} 699 // 700 // dr7{31-16} encodes the rw/len bits: 701 // b_x+3, b_x+2, b_x+1, b_x 702 // where bits{x+1, x} => rw 703 // 0b00: execute, 0b01: write, 0b11: read-or-write, 0b10: io read-or-write (unused) 704 // and bits{x+3, x+2} => len 705 // 0b00: 1-byte, 0b01: 2-byte, 0b11: 4-byte, 0b10: 8-byte 706 // 707 // dr0 -> bits{19-16} 708 // dr1 -> bits{23-20} 709 // dr2 -> bits{27-24} 710 // dr3 -> bits{31-28} 711 debug_state.__dr7 |= (1 << (2*hw_index) | 712 size_and_rw_bits(size, read, write) << (16+4*hw_index)); 713 switch (hw_index) { 714 case 0: 715 debug_state.__dr0 = addr; break; 716 case 1: 717 debug_state.__dr1 = addr; break; 718 case 2: 719 debug_state.__dr2 = addr; break; 720 case 3: 721 debug_state.__dr3 = addr; break; 722 default: 723 assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 724 } 725 return; 726 } 727 728 void 729 DNBArchImplX86_64::ClearWatchpoint(DBG &debug_state, uint32_t hw_index) 730 { 731 debug_state.__dr7 &= ~(3 << (2*hw_index)); 732 switch (hw_index) { 733 case 0: 734 debug_state.__dr0 = 0; break; 735 case 1: 736 debug_state.__dr1 = 0; break; 737 case 2: 738 debug_state.__dr2 = 0; break; 739 case 3: 740 debug_state.__dr3 = 0; break; 741 default: 742 assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 743 } 744 return; 745 } 746 747 bool 748 DNBArchImplX86_64::IsWatchpointVacant(const DBG &debug_state, uint32_t hw_index) 749 { 750 // Check dr7 (debug control register) for local/global enable bits: 751 // global enable --. .-- local enable 752 // | | 753 // v v 754 // dr0 -> bits{1-0} 755 // dr1 -> bits{3-2} 756 // dr2 -> bits{5-4} 757 // dr3 -> bits{7-6} 758 return (debug_state.__dr7 & (3 << (2*hw_index))) == 0; 759 } 760 761 // Resets local copy of debug status register to wait for the next debug excpetion. 762 void 763 DNBArchImplX86_64::ClearWatchpointHits(DBG &debug_state) 764 { 765 // See also IsWatchpointHit(). 766 debug_state.__dr6 = 0; 767 return; 768 } 769 770 bool 771 DNBArchImplX86_64::IsWatchpointHit(const DBG &debug_state, uint32_t hw_index) 772 { 773 // Check dr6 (debug status register) whether a watchpoint hits: 774 // is watchpoint hit? 775 // | 776 // v 777 // dr0 -> bits{0} 778 // dr1 -> bits{1} 779 // dr2 -> bits{2} 780 // dr3 -> bits{3} 781 return (debug_state.__dr6 & (1 << hw_index)); 782 } 783 784 nub_addr_t 785 DNBArchImplX86_64::GetWatchAddress(const DBG &debug_state, uint32_t hw_index) 786 { 787 switch (hw_index) { 788 case 0: 789 return debug_state.__dr0; 790 case 1: 791 return debug_state.__dr1; 792 case 2: 793 return debug_state.__dr2; 794 case 3: 795 return debug_state.__dr3; 796 default: 797 assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 798 } 799 } 800 801 bool 802 DNBArchImplX86_64::StartTransForHWP() 803 { 804 if (m_2pc_trans_state != Trans_Done && m_2pc_trans_state != Trans_Rolled_Back) 805 DNBLogError ("%s inconsistent state detected, expected %d or %d, got: %d", __FUNCTION__, Trans_Done, Trans_Rolled_Back, m_2pc_trans_state); 806 m_2pc_dbg_checkpoint = m_state.context.dbg; 807 m_2pc_trans_state = Trans_Pending; 808 return true; 809 } 810 bool 811 DNBArchImplX86_64::RollbackTransForHWP() 812 { 813 m_state.context.dbg = m_2pc_dbg_checkpoint; 814 if (m_2pc_trans_state != Trans_Pending) 815 DNBLogError ("%s inconsistent state detected, expected %d, got: %d", __FUNCTION__, Trans_Pending, m_2pc_trans_state); 816 m_2pc_trans_state = Trans_Rolled_Back; 817 kern_return_t kret = SetDBGState(false); 818 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::RollbackTransForHWP() SetDBGState() => 0x%8.8x.", kret); 819 820 if (kret == KERN_SUCCESS) 821 return true; 822 else 823 return false; 824 } 825 bool 826 DNBArchImplX86_64::FinishTransForHWP() 827 { 828 m_2pc_trans_state = Trans_Done; 829 return true; 830 } 831 DNBArchImplX86_64::DBG 832 DNBArchImplX86_64::GetDBGCheckpoint() 833 { 834 return m_2pc_dbg_checkpoint; 835 } 836 837 uint32_t 838 DNBArchImplX86_64::EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write, bool also_set_on_task) 839 { 840 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint(addr = 0x%llx, size = %llu, read = %u, write = %u)", (uint64_t)addr, (uint64_t)size, read, write); 841 842 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 843 844 // Can only watch 1, 2, 4, or 8 bytes. 845 if (!(size == 1 || size == 2 || size == 4 || size == 8)) 846 return INVALID_NUB_HW_INDEX; 847 848 // We must watch for either read or write 849 if (read == false && write == false) 850 return INVALID_NUB_HW_INDEX; 851 852 // Read the debug state 853 kern_return_t kret = GetDBGState(false); 854 855 if (kret == KERN_SUCCESS) 856 { 857 // Check to make sure we have the needed hardware support 858 uint32_t i = 0; 859 860 DBG &debug_state = m_state.context.dbg; 861 for (i = 0; i < num_hw_watchpoints; ++i) 862 { 863 if (IsWatchpointVacant(debug_state, i)) 864 break; 865 } 866 867 // See if we found an available hw breakpoint slot above 868 if (i < num_hw_watchpoints) 869 { 870 StartTransForHWP(); 871 872 // Modify our local copy of the debug state, first. 873 SetWatchpoint(debug_state, i, addr, size, read, write); 874 // Now set the watch point in the inferior. 875 kret = SetDBGState(also_set_on_task); 876 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint() SetDBGState() => 0x%8.8x.", kret); 877 878 if (kret == KERN_SUCCESS) 879 return i; 880 else // Revert to the previous debug state voluntarily. The transaction coordinator knows that we have failed. 881 m_state.context.dbg = GetDBGCheckpoint(); 882 } 883 else 884 { 885 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint(): All hardware resources (%u) are in use.", num_hw_watchpoints); 886 } 887 } 888 return INVALID_NUB_HW_INDEX; 889 } 890 891 bool 892 DNBArchImplX86_64::DisableHardwareWatchpoint (uint32_t hw_index, bool also_set_on_task) 893 { 894 kern_return_t kret = GetDBGState(false); 895 896 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 897 if (kret == KERN_SUCCESS) 898 { 899 DBG &debug_state = m_state.context.dbg; 900 if (hw_index < num_hw_points && !IsWatchpointVacant(debug_state, hw_index)) 901 { 902 StartTransForHWP(); 903 904 // Modify our local copy of the debug state, first. 905 ClearWatchpoint(debug_state, hw_index); 906 // Now disable the watch point in the inferior. 907 kret = SetDBGState(also_set_on_task); 908 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::DisableHardwareWatchpoint( %u )", 909 hw_index); 910 911 if (kret == KERN_SUCCESS) 912 return true; 913 else // Revert to the previous debug state voluntarily. The transaction coordinator knows that we have failed. 914 m_state.context.dbg = GetDBGCheckpoint(); 915 } 916 } 917 return false; 918 } 919 920 // Iterate through the debug status register; return the index of the first hit. 921 uint32_t 922 DNBArchImplX86_64::GetHardwareWatchpointHit(nub_addr_t &addr) 923 { 924 // Read the debug state 925 kern_return_t kret = GetDBGState(true); 926 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", kret); 927 if (kret == KERN_SUCCESS) 928 { 929 DBG &debug_state = m_state.context.dbg; 930 uint32_t i, num = NumSupportedHardwareWatchpoints(); 931 for (i = 0; i < num; ++i) 932 { 933 if (IsWatchpointHit(debug_state, i)) 934 { 935 addr = GetWatchAddress(debug_state, i); 936 DNBLogThreadedIf(LOG_WATCHPOINTS, 937 "DNBArchImplX86_64::GetHardwareWatchpointHit() found => %u (addr = 0x%llx).", 938 i, 939 (uint64_t)addr); 940 return i; 941 } 942 } 943 } 944 return INVALID_NUB_HW_INDEX; 945 } 946 947 // Set the single step bit in the processor status register. 948 kern_return_t 949 DNBArchImplX86_64::EnableHardwareSingleStep (bool enable) 950 { 951 if (GetGPRState(false) == KERN_SUCCESS) 952 { 953 const uint32_t trace_bit = 0x100u; 954 if (enable) 955 m_state.context.gpr.__rflags |= trace_bit; 956 else 957 m_state.context.gpr.__rflags &= ~trace_bit; 958 return SetGPRState(); 959 } 960 return m_state.GetError(e_regSetGPR, Read); 961 } 962 963 964 //---------------------------------------------------------------------- 965 // Register information defintions 966 //---------------------------------------------------------------------- 967 968 enum 969 { 970 gpr_rax = 0, 971 gpr_rbx, 972 gpr_rcx, 973 gpr_rdx, 974 gpr_rdi, 975 gpr_rsi, 976 gpr_rbp, 977 gpr_rsp, 978 gpr_r8, 979 gpr_r9, 980 gpr_r10, 981 gpr_r11, 982 gpr_r12, 983 gpr_r13, 984 gpr_r14, 985 gpr_r15, 986 gpr_rip, 987 gpr_rflags, 988 gpr_cs, 989 gpr_fs, 990 gpr_gs, 991 gpr_eax, 992 gpr_ebx, 993 gpr_ecx, 994 gpr_edx, 995 gpr_edi, 996 gpr_esi, 997 gpr_ebp, 998 gpr_esp, 999 gpr_r8d, // Low 32 bits or r8 1000 gpr_r9d, // Low 32 bits or r9 1001 gpr_r10d, // Low 32 bits or r10 1002 gpr_r11d, // Low 32 bits or r11 1003 gpr_r12d, // Low 32 bits or r12 1004 gpr_r13d, // Low 32 bits or r13 1005 gpr_r14d, // Low 32 bits or r14 1006 gpr_r15d, // Low 32 bits or r15 1007 gpr_ax , 1008 gpr_bx , 1009 gpr_cx , 1010 gpr_dx , 1011 gpr_di , 1012 gpr_si , 1013 gpr_bp , 1014 gpr_sp , 1015 gpr_r8w, // Low 16 bits or r8 1016 gpr_r9w, // Low 16 bits or r9 1017 gpr_r10w, // Low 16 bits or r10 1018 gpr_r11w, // Low 16 bits or r11 1019 gpr_r12w, // Low 16 bits or r12 1020 gpr_r13w, // Low 16 bits or r13 1021 gpr_r14w, // Low 16 bits or r14 1022 gpr_r15w, // Low 16 bits or r15 1023 gpr_ah , 1024 gpr_bh , 1025 gpr_ch , 1026 gpr_dh , 1027 gpr_al , 1028 gpr_bl , 1029 gpr_cl , 1030 gpr_dl , 1031 gpr_dil, 1032 gpr_sil, 1033 gpr_bpl, 1034 gpr_spl, 1035 gpr_r8l, // Low 8 bits or r8 1036 gpr_r9l, // Low 8 bits or r9 1037 gpr_r10l, // Low 8 bits or r10 1038 gpr_r11l, // Low 8 bits or r11 1039 gpr_r12l, // Low 8 bits or r12 1040 gpr_r13l, // Low 8 bits or r13 1041 gpr_r14l, // Low 8 bits or r14 1042 gpr_r15l, // Low 8 bits or r15 1043 k_num_gpr_regs 1044 }; 1045 1046 enum { 1047 fpu_fcw, 1048 fpu_fsw, 1049 fpu_ftw, 1050 fpu_fop, 1051 fpu_ip, 1052 fpu_cs, 1053 fpu_dp, 1054 fpu_ds, 1055 fpu_mxcsr, 1056 fpu_mxcsrmask, 1057 fpu_stmm0, 1058 fpu_stmm1, 1059 fpu_stmm2, 1060 fpu_stmm3, 1061 fpu_stmm4, 1062 fpu_stmm5, 1063 fpu_stmm6, 1064 fpu_stmm7, 1065 fpu_xmm0, 1066 fpu_xmm1, 1067 fpu_xmm2, 1068 fpu_xmm3, 1069 fpu_xmm4, 1070 fpu_xmm5, 1071 fpu_xmm6, 1072 fpu_xmm7, 1073 fpu_xmm8, 1074 fpu_xmm9, 1075 fpu_xmm10, 1076 fpu_xmm11, 1077 fpu_xmm12, 1078 fpu_xmm13, 1079 fpu_xmm14, 1080 fpu_xmm15, 1081 fpu_ymm0, 1082 fpu_ymm1, 1083 fpu_ymm2, 1084 fpu_ymm3, 1085 fpu_ymm4, 1086 fpu_ymm5, 1087 fpu_ymm6, 1088 fpu_ymm7, 1089 fpu_ymm8, 1090 fpu_ymm9, 1091 fpu_ymm10, 1092 fpu_ymm11, 1093 fpu_ymm12, 1094 fpu_ymm13, 1095 fpu_ymm14, 1096 fpu_ymm15, 1097 k_num_fpu_regs, 1098 1099 // Aliases 1100 fpu_fctrl = fpu_fcw, 1101 fpu_fstat = fpu_fsw, 1102 fpu_ftag = fpu_ftw, 1103 fpu_fiseg = fpu_cs, 1104 fpu_fioff = fpu_ip, 1105 fpu_foseg = fpu_ds, 1106 fpu_fooff = fpu_dp 1107 }; 1108 1109 enum { 1110 exc_trapno, 1111 exc_err, 1112 exc_faultvaddr, 1113 k_num_exc_regs, 1114 }; 1115 1116 1117 enum gcc_dwarf_regnums 1118 { 1119 gcc_dwarf_rax = 0, 1120 gcc_dwarf_rdx = 1, 1121 gcc_dwarf_rcx = 2, 1122 gcc_dwarf_rbx = 3, 1123 gcc_dwarf_rsi = 4, 1124 gcc_dwarf_rdi = 5, 1125 gcc_dwarf_rbp = 6, 1126 gcc_dwarf_rsp = 7, 1127 gcc_dwarf_r8, 1128 gcc_dwarf_r9, 1129 gcc_dwarf_r10, 1130 gcc_dwarf_r11, 1131 gcc_dwarf_r12, 1132 gcc_dwarf_r13, 1133 gcc_dwarf_r14, 1134 gcc_dwarf_r15, 1135 gcc_dwarf_rip, 1136 gcc_dwarf_xmm0, 1137 gcc_dwarf_xmm1, 1138 gcc_dwarf_xmm2, 1139 gcc_dwarf_xmm3, 1140 gcc_dwarf_xmm4, 1141 gcc_dwarf_xmm5, 1142 gcc_dwarf_xmm6, 1143 gcc_dwarf_xmm7, 1144 gcc_dwarf_xmm8, 1145 gcc_dwarf_xmm9, 1146 gcc_dwarf_xmm10, 1147 gcc_dwarf_xmm11, 1148 gcc_dwarf_xmm12, 1149 gcc_dwarf_xmm13, 1150 gcc_dwarf_xmm14, 1151 gcc_dwarf_xmm15, 1152 gcc_dwarf_stmm0, 1153 gcc_dwarf_stmm1, 1154 gcc_dwarf_stmm2, 1155 gcc_dwarf_stmm3, 1156 gcc_dwarf_stmm4, 1157 gcc_dwarf_stmm5, 1158 gcc_dwarf_stmm6, 1159 gcc_dwarf_stmm7, 1160 gcc_dwarf_ymm0 = gcc_dwarf_xmm0, 1161 gcc_dwarf_ymm1 = gcc_dwarf_xmm1, 1162 gcc_dwarf_ymm2 = gcc_dwarf_xmm2, 1163 gcc_dwarf_ymm3 = gcc_dwarf_xmm3, 1164 gcc_dwarf_ymm4 = gcc_dwarf_xmm4, 1165 gcc_dwarf_ymm5 = gcc_dwarf_xmm5, 1166 gcc_dwarf_ymm6 = gcc_dwarf_xmm6, 1167 gcc_dwarf_ymm7 = gcc_dwarf_xmm7, 1168 gcc_dwarf_ymm8 = gcc_dwarf_xmm8, 1169 gcc_dwarf_ymm9 = gcc_dwarf_xmm9, 1170 gcc_dwarf_ymm10 = gcc_dwarf_xmm10, 1171 gcc_dwarf_ymm11 = gcc_dwarf_xmm11, 1172 gcc_dwarf_ymm12 = gcc_dwarf_xmm12, 1173 gcc_dwarf_ymm13 = gcc_dwarf_xmm13, 1174 gcc_dwarf_ymm14 = gcc_dwarf_xmm14, 1175 gcc_dwarf_ymm15 = gcc_dwarf_xmm15 1176 }; 1177 1178 enum gdb_regnums 1179 { 1180 gdb_rax = 0, 1181 gdb_rbx = 1, 1182 gdb_rcx = 2, 1183 gdb_rdx = 3, 1184 gdb_rsi = 4, 1185 gdb_rdi = 5, 1186 gdb_rbp = 6, 1187 gdb_rsp = 7, 1188 gdb_r8 = 8, 1189 gdb_r9 = 9, 1190 gdb_r10 = 10, 1191 gdb_r11 = 11, 1192 gdb_r12 = 12, 1193 gdb_r13 = 13, 1194 gdb_r14 = 14, 1195 gdb_r15 = 15, 1196 gdb_rip = 16, 1197 gdb_rflags = 17, 1198 gdb_cs = 18, 1199 gdb_ss = 19, 1200 gdb_ds = 20, 1201 gdb_es = 21, 1202 gdb_fs = 22, 1203 gdb_gs = 23, 1204 gdb_stmm0 = 24, 1205 gdb_stmm1 = 25, 1206 gdb_stmm2 = 26, 1207 gdb_stmm3 = 27, 1208 gdb_stmm4 = 28, 1209 gdb_stmm5 = 29, 1210 gdb_stmm6 = 30, 1211 gdb_stmm7 = 31, 1212 gdb_fctrl = 32, gdb_fcw = gdb_fctrl, 1213 gdb_fstat = 33, gdb_fsw = gdb_fstat, 1214 gdb_ftag = 34, gdb_ftw = gdb_ftag, 1215 gdb_fiseg = 35, gdb_fpu_cs = gdb_fiseg, 1216 gdb_fioff = 36, gdb_ip = gdb_fioff, 1217 gdb_foseg = 37, gdb_fpu_ds = gdb_foseg, 1218 gdb_fooff = 38, gdb_dp = gdb_fooff, 1219 gdb_fop = 39, 1220 gdb_xmm0 = 40, 1221 gdb_xmm1 = 41, 1222 gdb_xmm2 = 42, 1223 gdb_xmm3 = 43, 1224 gdb_xmm4 = 44, 1225 gdb_xmm5 = 45, 1226 gdb_xmm6 = 46, 1227 gdb_xmm7 = 47, 1228 gdb_xmm8 = 48, 1229 gdb_xmm9 = 49, 1230 gdb_xmm10 = 50, 1231 gdb_xmm11 = 51, 1232 gdb_xmm12 = 52, 1233 gdb_xmm13 = 53, 1234 gdb_xmm14 = 54, 1235 gdb_xmm15 = 55, 1236 gdb_mxcsr = 56, 1237 gdb_ymm0 = gdb_xmm0, 1238 gdb_ymm1 = gdb_xmm1, 1239 gdb_ymm2 = gdb_xmm2, 1240 gdb_ymm3 = gdb_xmm3, 1241 gdb_ymm4 = gdb_xmm4, 1242 gdb_ymm5 = gdb_xmm5, 1243 gdb_ymm6 = gdb_xmm6, 1244 gdb_ymm7 = gdb_xmm7, 1245 gdb_ymm8 = gdb_xmm8, 1246 gdb_ymm9 = gdb_xmm9, 1247 gdb_ymm10 = gdb_xmm10, 1248 gdb_ymm11 = gdb_xmm11, 1249 gdb_ymm12 = gdb_xmm12, 1250 gdb_ymm13 = gdb_xmm13, 1251 gdb_ymm14 = gdb_xmm14, 1252 gdb_ymm15 = gdb_xmm15 1253 }; 1254 1255 #define GPR_OFFSET(reg) (offsetof (DNBArchImplX86_64::GPR, __##reg)) 1256 #define FPU_OFFSET(reg) (offsetof (DNBArchImplX86_64::FPU, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.no_avx)) 1257 #define AVX_OFFSET(reg) (offsetof (DNBArchImplX86_64::AVX, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.avx)) 1258 #define EXC_OFFSET(reg) (offsetof (DNBArchImplX86_64::EXC, __##reg) + offsetof (DNBArchImplX86_64::Context, exc)) 1259 #define AVX_OFFSET_YMM(n) (AVX_OFFSET(ymmh0) + (32 * n)) 1260 1261 #define GPR_SIZE(reg) (sizeof(((DNBArchImplX86_64::GPR *)NULL)->__##reg)) 1262 #define FPU_SIZE_UINT(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg)) 1263 #define FPU_SIZE_MMST(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__mmst_reg)) 1264 #define FPU_SIZE_XMM(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__xmm_reg)) 1265 #define FPU_SIZE_YMM(reg) (32) 1266 #define EXC_SIZE(reg) (sizeof(((DNBArchImplX86_64::EXC *)NULL)->__##reg)) 1267 1268 // These macros will auto define the register name, alt name, register size, 1269 // register offset, encoding, format and native register. This ensures that 1270 // the register state structures are defined correctly and have the correct 1271 // sizes and offsets. 1272 #define DEFINE_GPR(reg) { e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, INVALID_NUB_REGNUM, gdb_##reg, NULL, g_invalidate_##reg } 1273 #define DEFINE_GPR_ALT(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, gen, gdb_##reg, NULL, g_invalidate_##reg } 1274 #define DEFINE_GPR_ALT2(reg, alt) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gdb_##reg, NULL, NULL } 1275 #define DEFINE_GPR_ALT3(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gen, gdb_##reg, NULL, NULL } 1276 #define DEFINE_GPR_ALT4(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, gen, gdb_##reg, NULL, NULL } 1277 1278 #define DEFINE_GPR_PSEUDO_32(reg32,reg64) { e_regSetGPR, gpr_##reg32, #reg32, NULL, Uint, Hex, 4, 0,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 } 1279 #define DEFINE_GPR_PSEUDO_16(reg16,reg64) { e_regSetGPR, gpr_##reg16, #reg16, NULL, Uint, Hex, 2, 0,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 } 1280 #define DEFINE_GPR_PSEUDO_8H(reg8,reg64) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, 1,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 } 1281 #define DEFINE_GPR_PSEUDO_8L(reg8,reg64) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, 0,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 } 1282 1283 // General purpose registers for 64 bit 1284 1285 const char *g_contained_rax[] = { "rax", NULL }; 1286 const char *g_contained_rbx[] = { "rbx", NULL }; 1287 const char *g_contained_rcx[] = { "rcx", NULL }; 1288 const char *g_contained_rdx[] = { "rdx", NULL }; 1289 const char *g_contained_rdi[] = { "rdi", NULL }; 1290 const char *g_contained_rsi[] = { "rsi", NULL }; 1291 const char *g_contained_rbp[] = { "rbp", NULL }; 1292 const char *g_contained_rsp[] = { "rsp", NULL }; 1293 const char *g_contained_r8[] = { "r8", NULL }; 1294 const char *g_contained_r9[] = { "r9", NULL }; 1295 const char *g_contained_r10[] = { "r10", NULL }; 1296 const char *g_contained_r11[] = { "r11", NULL }; 1297 const char *g_contained_r12[] = { "r12", NULL }; 1298 const char *g_contained_r13[] = { "r13", NULL }; 1299 const char *g_contained_r14[] = { "r14", NULL }; 1300 const char *g_contained_r15[] = { "r15", NULL }; 1301 1302 const char *g_invalidate_rax[] = { "rax", "eax", "ax", "ah", "al", NULL }; 1303 const char *g_invalidate_rbx[] = { "rbx", "ebx", "bx", "bh", "bl", NULL }; 1304 const char *g_invalidate_rcx[] = { "rcx", "ecx", "cx", "ch", "cl", NULL }; 1305 const char *g_invalidate_rdx[] = { "rdx", "edx", "dx", "dh", "dl", NULL }; 1306 const char *g_invalidate_rdi[] = { "rdi", "edi", "di", "dil", NULL }; 1307 const char *g_invalidate_rsi[] = { "rsi", "esi", "si", "sil", NULL }; 1308 const char *g_invalidate_rbp[] = { "rbp", "ebp", "bp", "bpl", NULL }; 1309 const char *g_invalidate_rsp[] = { "rsp", "esp", "sp", "spl", NULL }; 1310 const char *g_invalidate_r8 [] = { "r8", "r8d", "r8w", "r8l", NULL }; 1311 const char *g_invalidate_r9 [] = { "r9", "r9d", "r9w", "r9l", NULL }; 1312 const char *g_invalidate_r10[] = { "r10", "r10d", "r10w", "r10l", NULL }; 1313 const char *g_invalidate_r11[] = { "r11", "r11d", "r11w", "r11l", NULL }; 1314 const char *g_invalidate_r12[] = { "r12", "r12d", "r12w", "r12l", NULL }; 1315 const char *g_invalidate_r13[] = { "r13", "r13d", "r13w", "r13l", NULL }; 1316 const char *g_invalidate_r14[] = { "r14", "r14d", "r14w", "r14l", NULL }; 1317 const char *g_invalidate_r15[] = { "r15", "r15d", "r15w", "r15l", NULL }; 1318 1319 const DNBRegisterInfo 1320 DNBArchImplX86_64::g_gpr_registers[] = 1321 { 1322 DEFINE_GPR (rax), 1323 DEFINE_GPR (rbx), 1324 DEFINE_GPR_ALT (rcx , "arg4", GENERIC_REGNUM_ARG4), 1325 DEFINE_GPR_ALT (rdx , "arg3", GENERIC_REGNUM_ARG3), 1326 DEFINE_GPR_ALT (rdi , "arg1", GENERIC_REGNUM_ARG1), 1327 DEFINE_GPR_ALT (rsi , "arg2", GENERIC_REGNUM_ARG2), 1328 DEFINE_GPR_ALT (rbp , "fp" , GENERIC_REGNUM_FP), 1329 DEFINE_GPR_ALT (rsp , "sp" , GENERIC_REGNUM_SP), 1330 DEFINE_GPR_ALT (r8 , "arg5", GENERIC_REGNUM_ARG5), 1331 DEFINE_GPR_ALT (r9 , "arg6", GENERIC_REGNUM_ARG6), 1332 DEFINE_GPR (r10), 1333 DEFINE_GPR (r11), 1334 DEFINE_GPR (r12), 1335 DEFINE_GPR (r13), 1336 DEFINE_GPR (r14), 1337 DEFINE_GPR (r15), 1338 DEFINE_GPR_ALT4 (rip , "pc", GENERIC_REGNUM_PC), 1339 DEFINE_GPR_ALT3 (rflags, "flags", GENERIC_REGNUM_FLAGS), 1340 DEFINE_GPR_ALT2 (cs, NULL), 1341 DEFINE_GPR_ALT2 (fs, NULL), 1342 DEFINE_GPR_ALT2 (gs, NULL), 1343 DEFINE_GPR_PSEUDO_32 (eax, rax), 1344 DEFINE_GPR_PSEUDO_32 (ebx, rbx), 1345 DEFINE_GPR_PSEUDO_32 (ecx, rcx), 1346 DEFINE_GPR_PSEUDO_32 (edx, rdx), 1347 DEFINE_GPR_PSEUDO_32 (edi, rdi), 1348 DEFINE_GPR_PSEUDO_32 (esi, rsi), 1349 DEFINE_GPR_PSEUDO_32 (ebp, rbp), 1350 DEFINE_GPR_PSEUDO_32 (esp, rsp), 1351 DEFINE_GPR_PSEUDO_32 (r8d, r8), 1352 DEFINE_GPR_PSEUDO_32 (r9d, r9), 1353 DEFINE_GPR_PSEUDO_32 (r10d, r10), 1354 DEFINE_GPR_PSEUDO_32 (r11d, r11), 1355 DEFINE_GPR_PSEUDO_32 (r12d, r12), 1356 DEFINE_GPR_PSEUDO_32 (r13d, r13), 1357 DEFINE_GPR_PSEUDO_32 (r14d, r14), 1358 DEFINE_GPR_PSEUDO_32 (r15d, r15), 1359 DEFINE_GPR_PSEUDO_16 (ax , rax), 1360 DEFINE_GPR_PSEUDO_16 (bx , rbx), 1361 DEFINE_GPR_PSEUDO_16 (cx , rcx), 1362 DEFINE_GPR_PSEUDO_16 (dx , rdx), 1363 DEFINE_GPR_PSEUDO_16 (di , rdi), 1364 DEFINE_GPR_PSEUDO_16 (si , rsi), 1365 DEFINE_GPR_PSEUDO_16 (bp , rbp), 1366 DEFINE_GPR_PSEUDO_16 (sp , rsp), 1367 DEFINE_GPR_PSEUDO_16 (r8w, r8), 1368 DEFINE_GPR_PSEUDO_16 (r9w, r9), 1369 DEFINE_GPR_PSEUDO_16 (r10w, r10), 1370 DEFINE_GPR_PSEUDO_16 (r11w, r11), 1371 DEFINE_GPR_PSEUDO_16 (r12w, r12), 1372 DEFINE_GPR_PSEUDO_16 (r13w, r13), 1373 DEFINE_GPR_PSEUDO_16 (r14w, r14), 1374 DEFINE_GPR_PSEUDO_16 (r15w, r15), 1375 DEFINE_GPR_PSEUDO_8H (ah , rax), 1376 DEFINE_GPR_PSEUDO_8H (bh , rbx), 1377 DEFINE_GPR_PSEUDO_8H (ch , rcx), 1378 DEFINE_GPR_PSEUDO_8H (dh , rdx), 1379 DEFINE_GPR_PSEUDO_8L (al , rax), 1380 DEFINE_GPR_PSEUDO_8L (bl , rbx), 1381 DEFINE_GPR_PSEUDO_8L (cl , rcx), 1382 DEFINE_GPR_PSEUDO_8L (dl , rdx), 1383 DEFINE_GPR_PSEUDO_8L (dil, rdi), 1384 DEFINE_GPR_PSEUDO_8L (sil, rsi), 1385 DEFINE_GPR_PSEUDO_8L (bpl, rbp), 1386 DEFINE_GPR_PSEUDO_8L (spl, rsp), 1387 DEFINE_GPR_PSEUDO_8L (r8l, r8), 1388 DEFINE_GPR_PSEUDO_8L (r9l, r9), 1389 DEFINE_GPR_PSEUDO_8L (r10l, r10), 1390 DEFINE_GPR_PSEUDO_8L (r11l, r11), 1391 DEFINE_GPR_PSEUDO_8L (r12l, r12), 1392 DEFINE_GPR_PSEUDO_8L (r13l, r13), 1393 DEFINE_GPR_PSEUDO_8L (r14l, r14), 1394 DEFINE_GPR_PSEUDO_8L (r15l, r15) 1395 }; 1396 1397 // Floating point registers 64 bit 1398 const DNBRegisterInfo 1399 DNBArchImplX86_64::g_fpu_registers_no_avx[] = 1400 { 1401 { e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , FPU_OFFSET(fcw) , -1U, -1U, -1U, -1U, NULL, NULL }, 1402 { e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , FPU_OFFSET(fsw) , -1U, -1U, -1U, -1U, NULL, NULL }, 1403 { e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , FPU_OFFSET(ftw) , -1U, -1U, -1U, -1U, NULL, NULL }, 1404 { e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , FPU_OFFSET(fop) , -1U, -1U, -1U, -1U, NULL, NULL }, 1405 { e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , FPU_OFFSET(ip) , -1U, -1U, -1U, -1U, NULL, NULL }, 1406 { e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , FPU_OFFSET(cs) , -1U, -1U, -1U, -1U, NULL, NULL }, 1407 { e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , FPU_OFFSET(dp) , -1U, -1U, -1U, -1U, NULL, NULL }, 1408 { e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , FPU_OFFSET(ds) , -1U, -1U, -1U, -1U, NULL, NULL }, 1409 { e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , FPU_OFFSET(mxcsr) , -1U, -1U, -1U, -1U, NULL, NULL }, 1410 { e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , FPU_OFFSET(mxcsrmask) , -1U, -1U, -1U, -1U, NULL, NULL }, 1411 1412 { e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), FPU_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1U, gdb_stmm0, NULL, NULL }, 1413 { e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), FPU_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1U, gdb_stmm1, NULL, NULL }, 1414 { e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), FPU_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1U, gdb_stmm2, NULL, NULL }, 1415 { e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), FPU_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1U, gdb_stmm3, NULL, NULL }, 1416 { e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), FPU_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1U, gdb_stmm4, NULL, NULL }, 1417 { e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), FPU_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1U, gdb_stmm5, NULL, NULL }, 1418 { e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), FPU_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1U, gdb_stmm6, NULL, NULL }, 1419 { e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), FPU_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1U, gdb_stmm7, NULL, NULL }, 1420 1421 { e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , FPU_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1U, gdb_xmm0 , NULL, NULL }, 1422 { e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , FPU_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1U, gdb_xmm1 , NULL, NULL }, 1423 { e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , FPU_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1U, gdb_xmm2 , NULL, NULL }, 1424 { e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , FPU_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1U, gdb_xmm3 , NULL, NULL }, 1425 { e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , FPU_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1U, gdb_xmm4 , NULL, NULL }, 1426 { e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , FPU_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1U, gdb_xmm5 , NULL, NULL }, 1427 { e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , FPU_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1U, gdb_xmm6 , NULL, NULL }, 1428 { e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , FPU_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1U, gdb_xmm7 , NULL, NULL }, 1429 { e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , FPU_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1U, gdb_xmm8 , NULL, NULL }, 1430 { e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , FPU_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1U, gdb_xmm9 , NULL, NULL }, 1431 { e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , FPU_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1U, gdb_xmm10, NULL, NULL }, 1432 { e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , FPU_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1U, gdb_xmm11, NULL, NULL }, 1433 { e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , FPU_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1U, gdb_xmm12, NULL, NULL }, 1434 { e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , FPU_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1U, gdb_xmm13, NULL, NULL }, 1435 { e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , FPU_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1U, gdb_xmm14, NULL, NULL }, 1436 { e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , FPU_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1U, gdb_xmm15, NULL, NULL }, 1437 }; 1438 1439 static const char *g_contained_ymm0 [] = { "ymm0", NULL }; 1440 static const char *g_contained_ymm1 [] = { "ymm1", NULL }; 1441 static const char *g_contained_ymm2 [] = { "ymm2", NULL }; 1442 static const char *g_contained_ymm3 [] = { "ymm3", NULL }; 1443 static const char *g_contained_ymm4 [] = { "ymm4", NULL }; 1444 static const char *g_contained_ymm5 [] = { "ymm5", NULL }; 1445 static const char *g_contained_ymm6 [] = { "ymm6", NULL }; 1446 static const char *g_contained_ymm7 [] = { "ymm7", NULL }; 1447 static const char *g_contained_ymm8 [] = { "ymm8", NULL }; 1448 static const char *g_contained_ymm9 [] = { "ymm9", NULL }; 1449 static const char *g_contained_ymm10[] = { "ymm10", NULL }; 1450 static const char *g_contained_ymm11[] = { "ymm11", NULL }; 1451 static const char *g_contained_ymm12[] = { "ymm12", NULL }; 1452 static const char *g_contained_ymm13[] = { "ymm13", NULL }; 1453 static const char *g_contained_ymm14[] = { "ymm14", NULL }; 1454 static const char *g_contained_ymm15[] = { "ymm15", NULL }; 1455 1456 const DNBRegisterInfo 1457 DNBArchImplX86_64::g_fpu_registers_avx[] = 1458 { 1459 { e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , AVX_OFFSET(fcw) , -1U, -1U, -1U, -1U, NULL, NULL }, 1460 { e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , AVX_OFFSET(fsw) , -1U, -1U, -1U, -1U, NULL, NULL }, 1461 { e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , AVX_OFFSET(ftw) , -1U, -1U, -1U, -1U, NULL, NULL }, 1462 { e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , AVX_OFFSET(fop) , -1U, -1U, -1U, -1U, NULL, NULL }, 1463 { e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , AVX_OFFSET(ip) , -1U, -1U, -1U, -1U, NULL, NULL }, 1464 { e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , AVX_OFFSET(cs) , -1U, -1U, -1U, -1U, NULL, NULL }, 1465 { e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , AVX_OFFSET(dp) , -1U, -1U, -1U, -1U, NULL, NULL }, 1466 { e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , AVX_OFFSET(ds) , -1U, -1U, -1U, -1U, NULL, NULL }, 1467 { e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , AVX_OFFSET(mxcsr) , -1U, -1U, -1U, -1U, NULL, NULL }, 1468 { e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , AVX_OFFSET(mxcsrmask) , -1U, -1U, -1U, -1U, NULL, NULL }, 1469 1470 { e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1U, gdb_stmm0, NULL, NULL }, 1471 { e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1U, gdb_stmm1, NULL, NULL }, 1472 { e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1U, gdb_stmm2, NULL, NULL }, 1473 { e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1U, gdb_stmm3, NULL, NULL }, 1474 { e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1U, gdb_stmm4, NULL, NULL }, 1475 { e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1U, gdb_stmm5, NULL, NULL }, 1476 { e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1U, gdb_stmm6, NULL, NULL }, 1477 { e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1U, gdb_stmm7, NULL, NULL }, 1478 1479 { e_regSetFPU, fpu_ymm0 , "ymm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm0) , AVX_OFFSET_YMM(0) , gcc_dwarf_ymm0 , gcc_dwarf_ymm0 , -1U, gdb_ymm0, NULL, NULL }, 1480 { e_regSetFPU, fpu_ymm1 , "ymm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm1) , AVX_OFFSET_YMM(1) , gcc_dwarf_ymm1 , gcc_dwarf_ymm1 , -1U, gdb_ymm1, NULL, NULL }, 1481 { e_regSetFPU, fpu_ymm2 , "ymm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm2) , AVX_OFFSET_YMM(2) , gcc_dwarf_ymm2 , gcc_dwarf_ymm2 , -1U, gdb_ymm2, NULL, NULL }, 1482 { e_regSetFPU, fpu_ymm3 , "ymm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm3) , AVX_OFFSET_YMM(3) , gcc_dwarf_ymm3 , gcc_dwarf_ymm3 , -1U, gdb_ymm3, NULL, NULL }, 1483 { e_regSetFPU, fpu_ymm4 , "ymm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm4) , AVX_OFFSET_YMM(4) , gcc_dwarf_ymm4 , gcc_dwarf_ymm4 , -1U, gdb_ymm4, NULL, NULL }, 1484 { e_regSetFPU, fpu_ymm5 , "ymm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm5) , AVX_OFFSET_YMM(5) , gcc_dwarf_ymm5 , gcc_dwarf_ymm5 , -1U, gdb_ymm5, NULL, NULL }, 1485 { e_regSetFPU, fpu_ymm6 , "ymm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm6) , AVX_OFFSET_YMM(6) , gcc_dwarf_ymm6 , gcc_dwarf_ymm6 , -1U, gdb_ymm6, NULL, NULL }, 1486 { e_regSetFPU, fpu_ymm7 , "ymm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm7) , AVX_OFFSET_YMM(7) , gcc_dwarf_ymm7 , gcc_dwarf_ymm7 , -1U, gdb_ymm7, NULL, NULL }, 1487 { e_regSetFPU, fpu_ymm8 , "ymm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm8) , AVX_OFFSET_YMM(8) , gcc_dwarf_ymm8 , gcc_dwarf_ymm8 , -1U, gdb_ymm8 , NULL, NULL }, 1488 { e_regSetFPU, fpu_ymm9 , "ymm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm9) , AVX_OFFSET_YMM(9) , gcc_dwarf_ymm9 , gcc_dwarf_ymm9 , -1U, gdb_ymm9 , NULL, NULL }, 1489 { e_regSetFPU, fpu_ymm10, "ymm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm10) , AVX_OFFSET_YMM(10), gcc_dwarf_ymm10, gcc_dwarf_ymm10, -1U, gdb_ymm10, NULL, NULL }, 1490 { e_regSetFPU, fpu_ymm11, "ymm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm11) , AVX_OFFSET_YMM(11), gcc_dwarf_ymm11, gcc_dwarf_ymm11, -1U, gdb_ymm11, NULL, NULL }, 1491 { e_regSetFPU, fpu_ymm12, "ymm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm12) , AVX_OFFSET_YMM(12), gcc_dwarf_ymm12, gcc_dwarf_ymm12, -1U, gdb_ymm12, NULL, NULL }, 1492 { e_regSetFPU, fpu_ymm13, "ymm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm13) , AVX_OFFSET_YMM(13), gcc_dwarf_ymm13, gcc_dwarf_ymm13, -1U, gdb_ymm13, NULL, NULL }, 1493 { e_regSetFPU, fpu_ymm14, "ymm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm14) , AVX_OFFSET_YMM(14), gcc_dwarf_ymm14, gcc_dwarf_ymm14, -1U, gdb_ymm14, NULL, NULL }, 1494 { e_regSetFPU, fpu_ymm15, "ymm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm15) , AVX_OFFSET_YMM(15), gcc_dwarf_ymm15, gcc_dwarf_ymm15, -1U, gdb_ymm15, NULL, NULL }, 1495 1496 { e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , 0, gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1U, gdb_xmm0 , g_contained_ymm0 , NULL }, 1497 { e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , 0, gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1U, gdb_xmm1 , g_contained_ymm1 , NULL }, 1498 { e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , 0, gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1U, gdb_xmm2 , g_contained_ymm2 , NULL }, 1499 { e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , 0, gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1U, gdb_xmm3 , g_contained_ymm3 , NULL }, 1500 { e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , 0, gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1U, gdb_xmm4 , g_contained_ymm4 , NULL }, 1501 { e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , 0, gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1U, gdb_xmm5 , g_contained_ymm5 , NULL }, 1502 { e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , 0, gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1U, gdb_xmm6 , g_contained_ymm6 , NULL }, 1503 { e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , 0, gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1U, gdb_xmm7 , g_contained_ymm7 , NULL }, 1504 { e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , 0, gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1U, gdb_xmm8 , g_contained_ymm8 , NULL }, 1505 { e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , 0, gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1U, gdb_xmm9 , g_contained_ymm9 , NULL }, 1506 { e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , 0, gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1U, gdb_xmm10, g_contained_ymm10, NULL }, 1507 { e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , 0, gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1U, gdb_xmm11, g_contained_ymm11, NULL }, 1508 { e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , 0, gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1U, gdb_xmm12, g_contained_ymm12, NULL }, 1509 { e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , 0, gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1U, gdb_xmm13, g_contained_ymm13, NULL }, 1510 { e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , 0, gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1U, gdb_xmm14, g_contained_ymm14, NULL }, 1511 { e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , 0, gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1U, gdb_xmm15, g_contained_ymm15, NULL } 1512 1513 1514 }; 1515 1516 // Exception registers 1517 1518 const DNBRegisterInfo 1519 DNBArchImplX86_64::g_exc_registers[] = 1520 { 1521 { e_regSetEXC, exc_trapno, "trapno" , NULL, Uint, Hex, EXC_SIZE (trapno) , EXC_OFFSET (trapno) , -1U, -1U, -1U, -1U, NULL, NULL }, 1522 { e_regSetEXC, exc_err, "err" , NULL, Uint, Hex, EXC_SIZE (err) , EXC_OFFSET (err) , -1U, -1U, -1U, -1U, NULL, NULL }, 1523 { e_regSetEXC, exc_faultvaddr, "faultvaddr", NULL, Uint, Hex, EXC_SIZE (faultvaddr), EXC_OFFSET (faultvaddr) , -1U, -1U, -1U, -1U, NULL, NULL } 1524 }; 1525 1526 // Number of registers in each register set 1527 const size_t DNBArchImplX86_64::k_num_gpr_registers = sizeof(g_gpr_registers)/sizeof(DNBRegisterInfo); 1528 const size_t DNBArchImplX86_64::k_num_fpu_registers_no_avx = sizeof(g_fpu_registers_no_avx)/sizeof(DNBRegisterInfo); 1529 const size_t DNBArchImplX86_64::k_num_fpu_registers_avx = sizeof(g_fpu_registers_avx)/sizeof(DNBRegisterInfo); 1530 const size_t DNBArchImplX86_64::k_num_exc_registers = sizeof(g_exc_registers)/sizeof(DNBRegisterInfo); 1531 const size_t DNBArchImplX86_64::k_num_all_registers_no_avx = k_num_gpr_registers + k_num_fpu_registers_no_avx + k_num_exc_registers; 1532 const size_t DNBArchImplX86_64::k_num_all_registers_avx = k_num_gpr_registers + k_num_fpu_registers_avx + k_num_exc_registers; 1533 1534 //---------------------------------------------------------------------- 1535 // Register set definitions. The first definitions at register set index 1536 // of zero is for all registers, followed by other registers sets. The 1537 // register information for the all register set need not be filled in. 1538 //---------------------------------------------------------------------- 1539 const DNBRegisterSetInfo 1540 DNBArchImplX86_64::g_reg_sets_no_avx[] = 1541 { 1542 { "x86_64 Registers", NULL, k_num_all_registers_no_avx }, 1543 { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers }, 1544 { "Floating Point Registers", g_fpu_registers_no_avx, k_num_fpu_registers_no_avx }, 1545 { "Exception State Registers", g_exc_registers, k_num_exc_registers } 1546 }; 1547 1548 const DNBRegisterSetInfo 1549 DNBArchImplX86_64::g_reg_sets_avx[] = 1550 { 1551 { "x86_64 Registers", NULL, k_num_all_registers_avx }, 1552 { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers }, 1553 { "Floating Point Registers", g_fpu_registers_avx, k_num_fpu_registers_avx }, 1554 { "Exception State Registers", g_exc_registers, k_num_exc_registers } 1555 }; 1556 1557 // Total number of register sets for this architecture 1558 const size_t DNBArchImplX86_64::k_num_register_sets = sizeof(g_reg_sets_avx)/sizeof(DNBRegisterSetInfo); 1559 1560 1561 DNBArchProtocol * 1562 DNBArchImplX86_64::Create (MachThread *thread) 1563 { 1564 DNBArchImplX86_64 *obj = new DNBArchImplX86_64 (thread); 1565 return obj; 1566 } 1567 1568 const uint8_t * const 1569 DNBArchImplX86_64::SoftwareBreakpointOpcode (nub_size_t byte_size) 1570 { 1571 static const uint8_t g_breakpoint_opcode[] = { 0xCC }; 1572 if (byte_size == 1) 1573 return g_breakpoint_opcode; 1574 return NULL; 1575 } 1576 1577 const DNBRegisterSetInfo * 1578 DNBArchImplX86_64::GetRegisterSetInfo(nub_size_t *num_reg_sets) 1579 { 1580 *num_reg_sets = k_num_register_sets; 1581 1582 if (CPUHasAVX() || FORCE_AVX_REGS) 1583 return g_reg_sets_avx; 1584 else 1585 return g_reg_sets_no_avx; 1586 } 1587 1588 void 1589 DNBArchImplX86_64::Initialize() 1590 { 1591 DNBArchPluginInfo arch_plugin_info = 1592 { 1593 CPU_TYPE_X86_64, 1594 DNBArchImplX86_64::Create, 1595 DNBArchImplX86_64::GetRegisterSetInfo, 1596 DNBArchImplX86_64::SoftwareBreakpointOpcode 1597 }; 1598 1599 // Register this arch plug-in with the main protocol class 1600 DNBArchProtocol::RegisterArchPlugin (arch_plugin_info); 1601 } 1602 1603 bool 1604 DNBArchImplX86_64::GetRegisterValue(int set, int reg, DNBRegisterValue *value) 1605 { 1606 if (set == REGISTER_SET_GENERIC) 1607 { 1608 switch (reg) 1609 { 1610 case GENERIC_REGNUM_PC: // Program Counter 1611 set = e_regSetGPR; 1612 reg = gpr_rip; 1613 break; 1614 1615 case GENERIC_REGNUM_SP: // Stack Pointer 1616 set = e_regSetGPR; 1617 reg = gpr_rsp; 1618 break; 1619 1620 case GENERIC_REGNUM_FP: // Frame Pointer 1621 set = e_regSetGPR; 1622 reg = gpr_rbp; 1623 break; 1624 1625 case GENERIC_REGNUM_FLAGS: // Processor flags register 1626 set = e_regSetGPR; 1627 reg = gpr_rflags; 1628 break; 1629 1630 case GENERIC_REGNUM_RA: // Return Address 1631 default: 1632 return false; 1633 } 1634 } 1635 1636 if (GetRegisterState(set, false) != KERN_SUCCESS) 1637 return false; 1638 1639 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1640 if (regInfo) 1641 { 1642 value->info = *regInfo; 1643 switch (set) 1644 { 1645 case e_regSetGPR: 1646 if (reg < k_num_gpr_registers) 1647 { 1648 value->value.uint64 = ((uint64_t*)(&m_state.context.gpr))[reg]; 1649 return true; 1650 } 1651 break; 1652 1653 case e_regSetFPU: 1654 if (CPUHasAVX() || FORCE_AVX_REGS) 1655 { 1656 switch (reg) 1657 { 1658 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)); return true; 1659 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)); return true; 1660 case fpu_ftw: value->value.uint8 = m_state.context.fpu.avx.__fpu_ftw; return true; 1661 case fpu_fop: value->value.uint16 = m_state.context.fpu.avx.__fpu_fop; return true; 1662 case fpu_ip: value->value.uint32 = m_state.context.fpu.avx.__fpu_ip; return true; 1663 case fpu_cs: value->value.uint16 = m_state.context.fpu.avx.__fpu_cs; return true; 1664 case fpu_dp: value->value.uint32 = m_state.context.fpu.avx.__fpu_dp; return true; 1665 case fpu_ds: value->value.uint16 = m_state.context.fpu.avx.__fpu_ds; return true; 1666 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsr; return true; 1667 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsrmask; return true; 1668 1669 case fpu_stmm0: 1670 case fpu_stmm1: 1671 case fpu_stmm2: 1672 case fpu_stmm3: 1673 case fpu_stmm4: 1674 case fpu_stmm5: 1675 case fpu_stmm6: 1676 case fpu_stmm7: 1677 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), 10); 1678 return true; 1679 1680 case fpu_xmm0: 1681 case fpu_xmm1: 1682 case fpu_xmm2: 1683 case fpu_xmm3: 1684 case fpu_xmm4: 1685 case fpu_xmm5: 1686 case fpu_xmm6: 1687 case fpu_xmm7: 1688 case fpu_xmm8: 1689 case fpu_xmm9: 1690 case fpu_xmm10: 1691 case fpu_xmm11: 1692 case fpu_xmm12: 1693 case fpu_xmm13: 1694 case fpu_xmm14: 1695 case fpu_xmm15: 1696 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), 16); 1697 return true; 1698 1699 case fpu_ymm0: 1700 case fpu_ymm1: 1701 case fpu_ymm2: 1702 case fpu_ymm3: 1703 case fpu_ymm4: 1704 case fpu_ymm5: 1705 case fpu_ymm6: 1706 case fpu_ymm7: 1707 case fpu_ymm8: 1708 case fpu_ymm9: 1709 case fpu_ymm10: 1710 case fpu_ymm11: 1711 case fpu_ymm12: 1712 case fpu_ymm13: 1713 case fpu_ymm14: 1714 case fpu_ymm15: 1715 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), 16); 1716 memcpy((&value->value.uint8) + 16, &m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), 16); 1717 return true; 1718 } 1719 } 1720 else 1721 { 1722 switch (reg) 1723 { 1724 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)); return true; 1725 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)); return true; 1726 case fpu_ftw: value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw; return true; 1727 case fpu_fop: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop; return true; 1728 case fpu_ip: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip; return true; 1729 case fpu_cs: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs; return true; 1730 case fpu_dp: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp; return true; 1731 case fpu_ds: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds; return true; 1732 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr; return true; 1733 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask; return true; 1734 1735 case fpu_stmm0: 1736 case fpu_stmm1: 1737 case fpu_stmm2: 1738 case fpu_stmm3: 1739 case fpu_stmm4: 1740 case fpu_stmm5: 1741 case fpu_stmm6: 1742 case fpu_stmm7: 1743 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), 10); 1744 return true; 1745 1746 case fpu_xmm0: 1747 case fpu_xmm1: 1748 case fpu_xmm2: 1749 case fpu_xmm3: 1750 case fpu_xmm4: 1751 case fpu_xmm5: 1752 case fpu_xmm6: 1753 case fpu_xmm7: 1754 case fpu_xmm8: 1755 case fpu_xmm9: 1756 case fpu_xmm10: 1757 case fpu_xmm11: 1758 case fpu_xmm12: 1759 case fpu_xmm13: 1760 case fpu_xmm14: 1761 case fpu_xmm15: 1762 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), 16); 1763 return true; 1764 } 1765 } 1766 break; 1767 1768 case e_regSetEXC: 1769 switch (reg) 1770 { 1771 case exc_trapno: value->value.uint32 = m_state.context.exc.__trapno; return true; 1772 case exc_err: value->value.uint32 = m_state.context.exc.__err; return true; 1773 case exc_faultvaddr:value->value.uint64 = m_state.context.exc.__faultvaddr; return true; 1774 } 1775 break; 1776 } 1777 } 1778 return false; 1779 } 1780 1781 1782 bool 1783 DNBArchImplX86_64::SetRegisterValue(int set, int reg, const DNBRegisterValue *value) 1784 { 1785 if (set == REGISTER_SET_GENERIC) 1786 { 1787 switch (reg) 1788 { 1789 case GENERIC_REGNUM_PC: // Program Counter 1790 set = e_regSetGPR; 1791 reg = gpr_rip; 1792 break; 1793 1794 case GENERIC_REGNUM_SP: // Stack Pointer 1795 set = e_regSetGPR; 1796 reg = gpr_rsp; 1797 break; 1798 1799 case GENERIC_REGNUM_FP: // Frame Pointer 1800 set = e_regSetGPR; 1801 reg = gpr_rbp; 1802 break; 1803 1804 case GENERIC_REGNUM_FLAGS: // Processor flags register 1805 set = e_regSetGPR; 1806 reg = gpr_rflags; 1807 break; 1808 1809 case GENERIC_REGNUM_RA: // Return Address 1810 default: 1811 return false; 1812 } 1813 } 1814 1815 if (GetRegisterState(set, false) != KERN_SUCCESS) 1816 return false; 1817 1818 bool success = false; 1819 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1820 if (regInfo) 1821 { 1822 switch (set) 1823 { 1824 case e_regSetGPR: 1825 if (reg < k_num_gpr_registers) 1826 { 1827 ((uint64_t*)(&m_state.context.gpr))[reg] = value->value.uint64; 1828 success = true; 1829 } 1830 break; 1831 1832 case e_regSetFPU: 1833 if (CPUHasAVX() || FORCE_AVX_REGS) 1834 { 1835 switch (reg) 1836 { 1837 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)) = value->value.uint16; success = true; break; 1838 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)) = value->value.uint16; success = true; break; 1839 case fpu_ftw: m_state.context.fpu.avx.__fpu_ftw = value->value.uint8; success = true; break; 1840 case fpu_fop: m_state.context.fpu.avx.__fpu_fop = value->value.uint16; success = true; break; 1841 case fpu_ip: m_state.context.fpu.avx.__fpu_ip = value->value.uint32; success = true; break; 1842 case fpu_cs: m_state.context.fpu.avx.__fpu_cs = value->value.uint16; success = true; break; 1843 case fpu_dp: m_state.context.fpu.avx.__fpu_dp = value->value.uint32; success = true; break; 1844 case fpu_ds: m_state.context.fpu.avx.__fpu_ds = value->value.uint16; success = true; break; 1845 case fpu_mxcsr: m_state.context.fpu.avx.__fpu_mxcsr = value->value.uint32; success = true; break; 1846 case fpu_mxcsrmask: m_state.context.fpu.avx.__fpu_mxcsrmask = value->value.uint32; success = true; break; 1847 1848 case fpu_stmm0: 1849 case fpu_stmm1: 1850 case fpu_stmm2: 1851 case fpu_stmm3: 1852 case fpu_stmm4: 1853 case fpu_stmm5: 1854 case fpu_stmm6: 1855 case fpu_stmm7: 1856 memcpy (&m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10); 1857 success = true; 1858 break; 1859 1860 case fpu_xmm0: 1861 case fpu_xmm1: 1862 case fpu_xmm2: 1863 case fpu_xmm3: 1864 case fpu_xmm4: 1865 case fpu_xmm5: 1866 case fpu_xmm6: 1867 case fpu_xmm7: 1868 case fpu_xmm8: 1869 case fpu_xmm9: 1870 case fpu_xmm10: 1871 case fpu_xmm11: 1872 case fpu_xmm12: 1873 case fpu_xmm13: 1874 case fpu_xmm14: 1875 case fpu_xmm15: 1876 memcpy (&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16); 1877 success = true; 1878 break; 1879 1880 case fpu_ymm0: 1881 case fpu_ymm1: 1882 case fpu_ymm2: 1883 case fpu_ymm3: 1884 case fpu_ymm4: 1885 case fpu_ymm5: 1886 case fpu_ymm6: 1887 case fpu_ymm7: 1888 case fpu_ymm8: 1889 case fpu_ymm9: 1890 case fpu_ymm10: 1891 case fpu_ymm11: 1892 case fpu_ymm12: 1893 case fpu_ymm13: 1894 case fpu_ymm14: 1895 case fpu_ymm15: 1896 memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), &value->value.uint8, 16); 1897 memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), (&value->value.uint8) + 16, 16); 1898 return true; 1899 } 1900 } 1901 else 1902 { 1903 switch (reg) 1904 { 1905 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) = value->value.uint16; success = true; break; 1906 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) = value->value.uint16; success = true; break; 1907 case fpu_ftw: m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8; success = true; break; 1908 case fpu_fop: m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16; success = true; break; 1909 case fpu_ip: m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32; success = true; break; 1910 case fpu_cs: m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16; success = true; break; 1911 case fpu_dp: m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32; success = true; break; 1912 case fpu_ds: m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16; success = true; break; 1913 case fpu_mxcsr: m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32; success = true; break; 1914 case fpu_mxcsrmask: m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32; success = true; break; 1915 1916 case fpu_stmm0: 1917 case fpu_stmm1: 1918 case fpu_stmm2: 1919 case fpu_stmm3: 1920 case fpu_stmm4: 1921 case fpu_stmm5: 1922 case fpu_stmm6: 1923 case fpu_stmm7: 1924 memcpy (&m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10); 1925 success = true; 1926 break; 1927 1928 case fpu_xmm0: 1929 case fpu_xmm1: 1930 case fpu_xmm2: 1931 case fpu_xmm3: 1932 case fpu_xmm4: 1933 case fpu_xmm5: 1934 case fpu_xmm6: 1935 case fpu_xmm7: 1936 case fpu_xmm8: 1937 case fpu_xmm9: 1938 case fpu_xmm10: 1939 case fpu_xmm11: 1940 case fpu_xmm12: 1941 case fpu_xmm13: 1942 case fpu_xmm14: 1943 case fpu_xmm15: 1944 memcpy (&m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16); 1945 success = true; 1946 break; 1947 } 1948 } 1949 break; 1950 1951 case e_regSetEXC: 1952 switch (reg) 1953 { 1954 case exc_trapno: m_state.context.exc.__trapno = value->value.uint32; success = true; break; 1955 case exc_err: m_state.context.exc.__err = value->value.uint32; success = true; break; 1956 case exc_faultvaddr:m_state.context.exc.__faultvaddr = value->value.uint64; success = true; break; 1957 } 1958 break; 1959 } 1960 } 1961 1962 if (success) 1963 return SetRegisterState(set) == KERN_SUCCESS; 1964 return false; 1965 } 1966 1967 uint32_t 1968 DNBArchImplX86_64::GetRegisterContextSize() 1969 { 1970 static uint32_t g_cached_size = 0; 1971 if (g_cached_size == 0) 1972 { 1973 if (CPUHasAVX() || FORCE_AVX_REGS) 1974 { 1975 for (size_t i=0; i<k_num_fpu_registers_avx; ++i) 1976 { 1977 if (g_fpu_registers_avx[i].value_regs == NULL) 1978 g_cached_size += g_fpu_registers_avx[i].size; 1979 } 1980 } 1981 else 1982 { 1983 for (size_t i=0; i<k_num_fpu_registers_no_avx; ++i) 1984 { 1985 if (g_fpu_registers_no_avx[i].value_regs == NULL) 1986 g_cached_size += g_fpu_registers_no_avx[i].size; 1987 } 1988 } 1989 DNBLogThreaded ("DNBArchImplX86_64::GetRegisterContextSize() - GPR = %zu, FPU = %u, EXC = %zu", sizeof(GPR), g_cached_size, sizeof(EXC)); 1990 g_cached_size += sizeof(GPR); 1991 g_cached_size += sizeof(EXC); 1992 DNBLogThreaded ("DNBArchImplX86_64::GetRegisterContextSize() - GPR + FPU + EXC = %u", g_cached_size); 1993 } 1994 return g_cached_size; 1995 } 1996 1997 nub_size_t 1998 DNBArchImplX86_64::GetRegisterContext (void *buf, nub_size_t buf_len) 1999 { 2000 uint32_t size = GetRegisterContextSize(); 2001 2002 if (buf && buf_len) 2003 { 2004 bool force = false; 2005 kern_return_t kret; 2006 2007 if ((kret = GetGPRState(force)) != KERN_SUCCESS) 2008 { 2009 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %llu) error: GPR regs failed to read: %u ", buf, (uint64_t)buf_len, kret); 2010 size = 0; 2011 } 2012 else 2013 if ((kret = GetFPUState(force)) != KERN_SUCCESS) 2014 { 2015 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %llu) error: %s regs failed to read: %u", buf, (uint64_t)buf_len, CPUHasAVX() ? "AVX" : "FPU", kret); 2016 size = 0; 2017 } 2018 else 2019 if ((kret = GetEXCState(force)) != KERN_SUCCESS) 2020 { 2021 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %llu) error: EXC regs failed to read: %u", buf, (uint64_t)buf_len, kret); 2022 size = 0; 2023 } 2024 else 2025 { 2026 uint8_t *p = (uint8_t *)buf; 2027 // Copy the GPR registers 2028 memcpy(p, &m_state.context.gpr, sizeof(GPR)); 2029 p += sizeof(GPR); 2030 2031 if (CPUHasAVX() || FORCE_AVX_REGS) 2032 { 2033 // Walk around the gaps in the FPU regs 2034 memcpy(p, &m_state.context.fpu.avx.__fpu_fcw, 5); 2035 p += 5; 2036 memcpy(p, &m_state.context.fpu.avx.__fpu_fop, 8); 2037 p += 8; 2038 memcpy(p, &m_state.context.fpu.avx.__fpu_dp, 6); 2039 p += 6; 2040 memcpy(p, &m_state.context.fpu.avx.__fpu_mxcsr, 8); 2041 p += 8; 2042 2043 // Work around the padding between the stmm registers as they are 16 2044 // byte structs with 10 bytes of the value in each 2045 for (size_t i=0; i<8; ++i) 2046 { 2047 memcpy(p, &m_state.context.fpu.avx.__fpu_stmm0 + i, 10); 2048 p += 10; 2049 } 2050 2051 // Interleave the XMM and YMMH registers to make the YMM registers 2052 for (size_t i=0; i<16; ++i) 2053 { 2054 memcpy(p, &m_state.context.fpu.avx.__fpu_xmm0 + i, 16); 2055 p += 16; 2056 memcpy(p, &m_state.context.fpu.avx.__fpu_ymmh0 + i, 16); 2057 p += 16; 2058 } 2059 } 2060 else 2061 { 2062 // Walk around the gaps in the FPU regs 2063 memcpy(p, &m_state.context.fpu.no_avx.__fpu_fcw, 5); 2064 p += 5; 2065 memcpy(p, &m_state.context.fpu.no_avx.__fpu_fop, 8); 2066 p += 8; 2067 memcpy(p, &m_state.context.fpu.no_avx.__fpu_dp, 6); 2068 p += 6; 2069 memcpy(p, &m_state.context.fpu.no_avx.__fpu_mxcsr, 8); 2070 p += 8; 2071 2072 // Work around the padding between the stmm registers as they are 16 2073 // byte structs with 10 bytes of the value in each 2074 for (size_t i=0; i<8; ++i) 2075 { 2076 memcpy(p, &m_state.context.fpu.no_avx.__fpu_stmm0 + i, 10); 2077 p += 10; 2078 } 2079 2080 // Copy the XMM registers in a single block 2081 memcpy(p, &m_state.context.fpu.no_avx.__fpu_xmm0, 16 * 16); 2082 p += 16 * 16; 2083 } 2084 2085 // Copy the exception registers 2086 memcpy(p, &m_state.context.exc, sizeof(EXC)); 2087 p += sizeof(EXC); 2088 2089 // make sure we end up with exactly what we think we should have 2090 size_t bytes_written = p - (uint8_t *)buf; 2091 assert (bytes_written == size); 2092 } 2093 2094 } 2095 2096 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %llu) => %u", buf, (uint64_t)buf_len, size); 2097 // Return the size of the register context even if NULL was passed in 2098 return size; 2099 } 2100 2101 nub_size_t 2102 DNBArchImplX86_64::SetRegisterContext (const void *buf, nub_size_t buf_len) 2103 { 2104 uint32_t size = GetRegisterContextSize(); 2105 if (buf == NULL || buf_len == 0) 2106 size = 0; 2107 2108 if (size) 2109 { 2110 if (size > buf_len) 2111 size = buf_len; 2112 2113 uint8_t *p = (uint8_t *)buf; 2114 // Copy the GPR registers 2115 memcpy(&m_state.context.gpr, p, sizeof(GPR)); 2116 p += sizeof(GPR); 2117 2118 if (CPUHasAVX() || FORCE_AVX_REGS) 2119 { 2120 // Walk around the gaps in the FPU regs 2121 memcpy(&m_state.context.fpu.avx.__fpu_fcw, p, 5); 2122 p += 5; 2123 memcpy(&m_state.context.fpu.avx.__fpu_fop, p, 8); 2124 p += 8; 2125 memcpy(&m_state.context.fpu.avx.__fpu_dp, p, 6); 2126 p += 6; 2127 memcpy(&m_state.context.fpu.avx.__fpu_mxcsr, p, 8); 2128 p += 8; 2129 2130 // Work around the padding between the stmm registers as they are 16 2131 // byte structs with 10 bytes of the value in each 2132 for (size_t i=0; i<8; ++i) 2133 { 2134 memcpy(&m_state.context.fpu.avx.__fpu_stmm0 + i, p, 10); 2135 p += 10; 2136 } 2137 2138 // Interleave the XMM and YMMH registers to make the YMM registers 2139 for (size_t i=0; i<16; ++i) 2140 { 2141 memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + i, p, 16); 2142 p += 16; 2143 memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + i, p, 16); 2144 p += 16; 2145 } 2146 } 2147 else 2148 { 2149 // Copy fcw through mxcsrmask as there is no padding 2150 memcpy(&m_state.context.fpu.no_avx.__fpu_fcw, p, 5); 2151 p += 5; 2152 memcpy(&m_state.context.fpu.no_avx.__fpu_fop, p, 8); 2153 p += 8; 2154 memcpy(&m_state.context.fpu.no_avx.__fpu_dp, p, 6); 2155 p += 6; 2156 memcpy(&m_state.context.fpu.no_avx.__fpu_mxcsr, p, 8); 2157 p += 8; 2158 2159 // Work around the padding between the stmm registers as they are 16 2160 // byte structs with 10 bytes of the value in each 2161 for (size_t i=0; i<8; ++i) 2162 { 2163 memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + i, p, 10); 2164 p += 10; 2165 } 2166 2167 // Copy the XMM registers in a single block 2168 memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0, p, 16 * 16); 2169 p += 16 * 16; 2170 } 2171 2172 // Copy the exception registers 2173 memcpy(&m_state.context.exc, p, sizeof(EXC)); 2174 p += sizeof(EXC); 2175 2176 // make sure we end up with exactly what we think we should have 2177 size_t bytes_written = p - (uint8_t *)buf; 2178 assert (bytes_written == size); 2179 2180 kern_return_t kret; 2181 if ((kret = SetGPRState()) != KERN_SUCCESS) 2182 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SetRegisterContext (buf = %p, len = %llu) error: GPR regs failed to write: %u", buf, (uint64_t)buf_len, kret); 2183 if ((kret = SetFPUState()) != KERN_SUCCESS) 2184 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SetRegisterContext (buf = %p, len = %llu) error: %s regs failed to write: %u", buf, (uint64_t)buf_len, CPUHasAVX() ? "AVX" : "FPU", kret); 2185 if ((kret = SetEXCState()) != KERN_SUCCESS) 2186 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SetRegisterContext (buf = %p, len = %llu) error: EXP regs failed to write: %u", buf, (uint64_t)buf_len, kret); 2187 } 2188 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SetRegisterContext (buf = %p, len = %llu) => %llu", buf, (uint64_t)buf_len, (uint64_t)size); 2189 return size; 2190 } 2191 2192 uint32_t 2193 DNBArchImplX86_64::SaveRegisterState () 2194 { 2195 kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber()); 2196 DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (SetGPRState() for stop_count = %u)", m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount()); 2197 2198 // Always re-read the registers because above we call thread_abort_safely(); 2199 bool force = true; 2200 2201 if ((kret = GetGPRState(force)) != KERN_SUCCESS) 2202 { 2203 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SaveRegisterState () error: GPR regs failed to read: %u ", kret); 2204 } 2205 else if ((kret = GetFPUState(force)) != KERN_SUCCESS) 2206 { 2207 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SaveRegisterState () error: %s regs failed to read: %u", CPUHasAVX() ? "AVX" : "FPU", kret); 2208 } 2209 else 2210 { 2211 const uint32_t save_id = GetNextRegisterStateSaveID (); 2212 m_saved_register_states[save_id] = m_state.context; 2213 return save_id; 2214 } 2215 return 0; 2216 } 2217 bool 2218 DNBArchImplX86_64::RestoreRegisterState (uint32_t save_id) 2219 { 2220 SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id); 2221 if (pos != m_saved_register_states.end()) 2222 { 2223 m_state.context.gpr = pos->second.gpr; 2224 m_state.context.fpu = pos->second.fpu; 2225 m_state.SetError(e_regSetGPR, Read, 0); 2226 m_state.SetError(e_regSetFPU, Read, 0); 2227 kern_return_t kret; 2228 bool success = true; 2229 if ((kret = SetGPRState()) != KERN_SUCCESS) 2230 { 2231 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::RestoreRegisterState (save_id = %u) error: GPR regs failed to write: %u", save_id, kret); 2232 success = false; 2233 } 2234 else if ((kret = SetFPUState()) != KERN_SUCCESS) 2235 { 2236 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::RestoreRegisterState (save_id = %u) error: %s regs failed to write: %u", save_id, CPUHasAVX() ? "AVX" : "FPU", kret); 2237 success = false; 2238 } 2239 m_saved_register_states.erase(pos); 2240 return success; 2241 } 2242 return false; 2243 } 2244 2245 2246 kern_return_t 2247 DNBArchImplX86_64::GetRegisterState(int set, bool force) 2248 { 2249 switch (set) 2250 { 2251 case e_regSetALL: return GetGPRState(force) | GetFPUState(force) | GetEXCState(force); 2252 case e_regSetGPR: return GetGPRState(force); 2253 case e_regSetFPU: return GetFPUState(force); 2254 case e_regSetEXC: return GetEXCState(force); 2255 default: break; 2256 } 2257 return KERN_INVALID_ARGUMENT; 2258 } 2259 2260 kern_return_t 2261 DNBArchImplX86_64::SetRegisterState(int set) 2262 { 2263 // Make sure we have a valid context to set. 2264 if (RegisterSetStateIsValid(set)) 2265 { 2266 switch (set) 2267 { 2268 case e_regSetALL: return SetGPRState() | SetFPUState() | SetEXCState(); 2269 case e_regSetGPR: return SetGPRState(); 2270 case e_regSetFPU: return SetFPUState(); 2271 case e_regSetEXC: return SetEXCState(); 2272 default: break; 2273 } 2274 } 2275 return KERN_INVALID_ARGUMENT; 2276 } 2277 2278 bool 2279 DNBArchImplX86_64::RegisterSetStateIsValid (int set) const 2280 { 2281 return m_state.RegsAreValid(set); 2282 } 2283 2284 2285 2286 #endif // #if defined (__i386__) || defined (__x86_64__) 2287