1 //===-- DNBArchImplARM64.cpp ------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Created by Greg Clayton on 6/25/07. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #if defined(__arm__) || defined(__arm64__) || defined(__aarch64__) 14 15 #include "MacOSX/arm64/DNBArchImplARM64.h" 16 17 #if defined(ARM_THREAD_STATE64_COUNT) 18 19 #include "DNB.h" 20 #include "DNBBreakpoint.h" 21 #include "DNBLog.h" 22 #include "DNBRegisterInfo.h" 23 #include "MacOSX/MachProcess.h" 24 #include "MacOSX/MachThread.h" 25 26 #include <inttypes.h> 27 #include <sys/sysctl.h> 28 29 // Break only in privileged or user mode 30 // (PAC bits in the DBGWVRn_EL1 watchpoint control register) 31 #define S_USER ((uint32_t)(2u << 1)) 32 33 #define BCR_ENABLE ((uint32_t)(1u)) 34 #define WCR_ENABLE ((uint32_t)(1u)) 35 36 // Watchpoint load/store 37 // (LSC bits in the DBGWVRn_EL1 watchpoint control register) 38 #define WCR_LOAD ((uint32_t)(1u << 3)) 39 #define WCR_STORE ((uint32_t)(1u << 4)) 40 41 // Enable breakpoint, watchpoint, and vector catch debug exceptions. 42 // (MDE bit in the MDSCR_EL1 register. Equivalent to the MDBGen bit in 43 // DBGDSCRext in Aarch32) 44 #define MDE_ENABLE ((uint32_t)(1u << 15)) 45 46 // Single instruction step 47 // (SS bit in the MDSCR_EL1 register) 48 #define SS_ENABLE ((uint32_t)(1u)) 49 50 static const uint8_t g_arm64_breakpoint_opcode[] = { 51 0x00, 0x00, 0x20, 0xD4}; // "brk #0", 0xd4200000 in BE byte order 52 static const uint8_t g_arm_breakpoint_opcode[] = { 53 0xFE, 0xDE, 0xFF, 0xE7}; // this armv7 insn also works in arm64 54 55 // If we need to set one logical watchpoint by using 56 // two hardware watchpoint registers, the watchpoint 57 // will be split into a "high" and "low" watchpoint. 58 // Record both of them in the LoHi array. 59 60 // It's safe to initialize to all 0's since 61 // hi > lo and therefore LoHi[i] cannot be 0. 62 static uint32_t LoHi[16] = {0}; 63 64 void DNBArchMachARM64::Initialize() { 65 DNBArchPluginInfo arch_plugin_info = { 66 CPU_TYPE_ARM64, DNBArchMachARM64::Create, 67 DNBArchMachARM64::GetRegisterSetInfo, 68 DNBArchMachARM64::SoftwareBreakpointOpcode}; 69 70 // Register this arch plug-in with the main protocol class 71 DNBArchProtocol::RegisterArchPlugin(arch_plugin_info); 72 } 73 74 DNBArchProtocol *DNBArchMachARM64::Create(MachThread *thread) { 75 DNBArchMachARM64 *obj = new DNBArchMachARM64(thread); 76 77 return obj; 78 } 79 80 const uint8_t * 81 DNBArchMachARM64::SoftwareBreakpointOpcode(nub_size_t byte_size) { 82 return g_arm_breakpoint_opcode; 83 } 84 85 uint32_t DNBArchMachARM64::GetCPUType() { return CPU_TYPE_ARM64; } 86 87 uint64_t DNBArchMachARM64::GetPC(uint64_t failValue) { 88 // Get program counter 89 if (GetGPRState(false) == KERN_SUCCESS) 90 return m_state.context.gpr.__pc; 91 return failValue; 92 } 93 94 kern_return_t DNBArchMachARM64::SetPC(uint64_t value) { 95 // Get program counter 96 kern_return_t err = GetGPRState(false); 97 if (err == KERN_SUCCESS) { 98 m_state.context.gpr.__pc = value; 99 err = SetGPRState(); 100 } 101 return err == KERN_SUCCESS; 102 } 103 104 uint64_t DNBArchMachARM64::GetSP(uint64_t failValue) { 105 // Get stack pointer 106 if (GetGPRState(false) == KERN_SUCCESS) 107 return m_state.context.gpr.__sp; 108 return failValue; 109 } 110 111 kern_return_t DNBArchMachARM64::GetGPRState(bool force) { 112 int set = e_regSetGPR; 113 // Check if we have valid cached registers 114 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 115 return KERN_SUCCESS; 116 117 // Read the registers from our thread 118 mach_msg_type_number_t count = e_regSetGPRCount; 119 kern_return_t kret = 120 ::thread_get_state(m_thread->MachPortNumber(), ARM_THREAD_STATE64, 121 (thread_state_t)&m_state.context.gpr, &count); 122 if (DNBLogEnabledForAny(LOG_THREAD)) { 123 uint64_t *x = &m_state.context.gpr.__x[0]; 124 DNBLogThreaded( 125 "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count = %u) regs" 126 "\n x0=%16.16llx" 127 "\n x1=%16.16llx" 128 "\n x2=%16.16llx" 129 "\n x3=%16.16llx" 130 "\n x4=%16.16llx" 131 "\n x5=%16.16llx" 132 "\n x6=%16.16llx" 133 "\n x7=%16.16llx" 134 "\n x8=%16.16llx" 135 "\n x9=%16.16llx" 136 "\n x10=%16.16llx" 137 "\n x11=%16.16llx" 138 "\n x12=%16.16llx" 139 "\n x13=%16.16llx" 140 "\n x14=%16.16llx" 141 "\n x15=%16.16llx" 142 "\n x16=%16.16llx" 143 "\n x17=%16.16llx" 144 "\n x18=%16.16llx" 145 "\n x19=%16.16llx" 146 "\n x20=%16.16llx" 147 "\n x21=%16.16llx" 148 "\n x22=%16.16llx" 149 "\n x23=%16.16llx" 150 "\n x24=%16.16llx" 151 "\n x25=%16.16llx" 152 "\n x26=%16.16llx" 153 "\n x27=%16.16llx" 154 "\n x28=%16.16llx" 155 "\n fp=%16.16llx" 156 "\n lr=%16.16llx" 157 "\n sp=%16.16llx" 158 "\n pc=%16.16llx" 159 "\n cpsr=%8.8x", 160 m_thread->MachPortNumber(), e_regSetGPR, e_regSetGPRCount, kret, count, 161 x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[0], x[11], 162 x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], x[20], x[21], 163 x[22], x[23], x[24], x[25], x[26], x[27], x[28], 164 m_state.context.gpr.__fp, m_state.context.gpr.__lr, 165 m_state.context.gpr.__sp, m_state.context.gpr.__pc, 166 m_state.context.gpr.__cpsr); 167 } 168 m_state.SetError(set, Read, kret); 169 return kret; 170 } 171 172 kern_return_t DNBArchMachARM64::GetVFPState(bool force) { 173 int set = e_regSetVFP; 174 // Check if we have valid cached registers 175 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 176 return KERN_SUCCESS; 177 178 // Read the registers from our thread 179 mach_msg_type_number_t count = e_regSetVFPCount; 180 kern_return_t kret = 181 ::thread_get_state(m_thread->MachPortNumber(), ARM_NEON_STATE64, 182 (thread_state_t)&m_state.context.vfp, &count); 183 if (DNBLogEnabledForAny(LOG_THREAD)) { 184 #if defined(__arm64__) || defined(__aarch64__) 185 DNBLogThreaded( 186 "thread_get_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs" 187 "\n q0 = 0x%16.16llx%16.16llx" 188 "\n q1 = 0x%16.16llx%16.16llx" 189 "\n q2 = 0x%16.16llx%16.16llx" 190 "\n q3 = 0x%16.16llx%16.16llx" 191 "\n q4 = 0x%16.16llx%16.16llx" 192 "\n q5 = 0x%16.16llx%16.16llx" 193 "\n q6 = 0x%16.16llx%16.16llx" 194 "\n q7 = 0x%16.16llx%16.16llx" 195 "\n q8 = 0x%16.16llx%16.16llx" 196 "\n q9 = 0x%16.16llx%16.16llx" 197 "\n q10 = 0x%16.16llx%16.16llx" 198 "\n q11 = 0x%16.16llx%16.16llx" 199 "\n q12 = 0x%16.16llx%16.16llx" 200 "\n q13 = 0x%16.16llx%16.16llx" 201 "\n q14 = 0x%16.16llx%16.16llx" 202 "\n q15 = 0x%16.16llx%16.16llx" 203 "\n q16 = 0x%16.16llx%16.16llx" 204 "\n q17 = 0x%16.16llx%16.16llx" 205 "\n q18 = 0x%16.16llx%16.16llx" 206 "\n q19 = 0x%16.16llx%16.16llx" 207 "\n q20 = 0x%16.16llx%16.16llx" 208 "\n q21 = 0x%16.16llx%16.16llx" 209 "\n q22 = 0x%16.16llx%16.16llx" 210 "\n q23 = 0x%16.16llx%16.16llx" 211 "\n q24 = 0x%16.16llx%16.16llx" 212 "\n q25 = 0x%16.16llx%16.16llx" 213 "\n q26 = 0x%16.16llx%16.16llx" 214 "\n q27 = 0x%16.16llx%16.16llx" 215 "\n q28 = 0x%16.16llx%16.16llx" 216 "\n q29 = 0x%16.16llx%16.16llx" 217 "\n q30 = 0x%16.16llx%16.16llx" 218 "\n q31 = 0x%16.16llx%16.16llx" 219 "\n fpsr = 0x%8.8x" 220 "\n fpcr = 0x%8.8x\n\n", 221 m_thread->MachPortNumber(), e_regSetVFP, e_regSetVFPCount, kret, count, 222 ((uint64_t *)&m_state.context.vfp.__v[0])[0], 223 ((uint64_t *)&m_state.context.vfp.__v[0])[1], 224 ((uint64_t *)&m_state.context.vfp.__v[1])[0], 225 ((uint64_t *)&m_state.context.vfp.__v[1])[1], 226 ((uint64_t *)&m_state.context.vfp.__v[2])[0], 227 ((uint64_t *)&m_state.context.vfp.__v[2])[1], 228 ((uint64_t *)&m_state.context.vfp.__v[3])[0], 229 ((uint64_t *)&m_state.context.vfp.__v[3])[1], 230 ((uint64_t *)&m_state.context.vfp.__v[4])[0], 231 ((uint64_t *)&m_state.context.vfp.__v[4])[1], 232 ((uint64_t *)&m_state.context.vfp.__v[5])[0], 233 ((uint64_t *)&m_state.context.vfp.__v[5])[1], 234 ((uint64_t *)&m_state.context.vfp.__v[6])[0], 235 ((uint64_t *)&m_state.context.vfp.__v[6])[1], 236 ((uint64_t *)&m_state.context.vfp.__v[7])[0], 237 ((uint64_t *)&m_state.context.vfp.__v[7])[1], 238 ((uint64_t *)&m_state.context.vfp.__v[8])[0], 239 ((uint64_t *)&m_state.context.vfp.__v[8])[1], 240 ((uint64_t *)&m_state.context.vfp.__v[9])[0], 241 ((uint64_t *)&m_state.context.vfp.__v[9])[1], 242 ((uint64_t *)&m_state.context.vfp.__v[10])[0], 243 ((uint64_t *)&m_state.context.vfp.__v[10])[1], 244 ((uint64_t *)&m_state.context.vfp.__v[11])[0], 245 ((uint64_t *)&m_state.context.vfp.__v[11])[1], 246 ((uint64_t *)&m_state.context.vfp.__v[12])[0], 247 ((uint64_t *)&m_state.context.vfp.__v[12])[1], 248 ((uint64_t *)&m_state.context.vfp.__v[13])[0], 249 ((uint64_t *)&m_state.context.vfp.__v[13])[1], 250 ((uint64_t *)&m_state.context.vfp.__v[14])[0], 251 ((uint64_t *)&m_state.context.vfp.__v[14])[1], 252 ((uint64_t *)&m_state.context.vfp.__v[15])[0], 253 ((uint64_t *)&m_state.context.vfp.__v[15])[1], 254 ((uint64_t *)&m_state.context.vfp.__v[16])[0], 255 ((uint64_t *)&m_state.context.vfp.__v[16])[1], 256 ((uint64_t *)&m_state.context.vfp.__v[17])[0], 257 ((uint64_t *)&m_state.context.vfp.__v[17])[1], 258 ((uint64_t *)&m_state.context.vfp.__v[18])[0], 259 ((uint64_t *)&m_state.context.vfp.__v[18])[1], 260 ((uint64_t *)&m_state.context.vfp.__v[19])[0], 261 ((uint64_t *)&m_state.context.vfp.__v[19])[1], 262 ((uint64_t *)&m_state.context.vfp.__v[20])[0], 263 ((uint64_t *)&m_state.context.vfp.__v[20])[1], 264 ((uint64_t *)&m_state.context.vfp.__v[21])[0], 265 ((uint64_t *)&m_state.context.vfp.__v[21])[1], 266 ((uint64_t *)&m_state.context.vfp.__v[22])[0], 267 ((uint64_t *)&m_state.context.vfp.__v[22])[1], 268 ((uint64_t *)&m_state.context.vfp.__v[23])[0], 269 ((uint64_t *)&m_state.context.vfp.__v[23])[1], 270 ((uint64_t *)&m_state.context.vfp.__v[24])[0], 271 ((uint64_t *)&m_state.context.vfp.__v[24])[1], 272 ((uint64_t *)&m_state.context.vfp.__v[25])[0], 273 ((uint64_t *)&m_state.context.vfp.__v[25])[1], 274 ((uint64_t *)&m_state.context.vfp.__v[26])[0], 275 ((uint64_t *)&m_state.context.vfp.__v[26])[1], 276 ((uint64_t *)&m_state.context.vfp.__v[27])[0], 277 ((uint64_t *)&m_state.context.vfp.__v[27])[1], 278 ((uint64_t *)&m_state.context.vfp.__v[28])[0], 279 ((uint64_t *)&m_state.context.vfp.__v[28])[1], 280 ((uint64_t *)&m_state.context.vfp.__v[29])[0], 281 ((uint64_t *)&m_state.context.vfp.__v[29])[1], 282 ((uint64_t *)&m_state.context.vfp.__v[30])[0], 283 ((uint64_t *)&m_state.context.vfp.__v[30])[1], 284 ((uint64_t *)&m_state.context.vfp.__v[31])[0], 285 ((uint64_t *)&m_state.context.vfp.__v[31])[1], 286 m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr); 287 #endif 288 } 289 m_state.SetError(set, Read, kret); 290 return kret; 291 } 292 293 kern_return_t DNBArchMachARM64::GetEXCState(bool force) { 294 int set = e_regSetEXC; 295 // Check if we have valid cached registers 296 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 297 return KERN_SUCCESS; 298 299 // Read the registers from our thread 300 mach_msg_type_number_t count = e_regSetEXCCount; 301 kern_return_t kret = 302 ::thread_get_state(m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, 303 (thread_state_t)&m_state.context.exc, &count); 304 m_state.SetError(set, Read, kret); 305 return kret; 306 } 307 308 static void DumpDBGState(const arm_debug_state_t &dbg) { 309 uint32_t i = 0; 310 for (i = 0; i < 16; i++) 311 DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } " 312 "WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }", 313 i, i, dbg.__bvr[i], dbg.__bcr[i], i, i, dbg.__wvr[i], 314 dbg.__wcr[i]); 315 } 316 317 kern_return_t DNBArchMachARM64::GetDBGState(bool force) { 318 int set = e_regSetDBG; 319 320 // Check if we have valid cached registers 321 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 322 return KERN_SUCCESS; 323 324 // Read the registers from our thread 325 mach_msg_type_number_t count = e_regSetDBGCount; 326 kern_return_t kret = 327 ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64, 328 (thread_state_t)&m_state.dbg, &count); 329 m_state.SetError(set, Read, kret); 330 331 return kret; 332 } 333 334 kern_return_t DNBArchMachARM64::SetGPRState() { 335 int set = e_regSetGPR; 336 kern_return_t kret = ::thread_set_state( 337 m_thread->MachPortNumber(), ARM_THREAD_STATE64, 338 (thread_state_t)&m_state.context.gpr, e_regSetGPRCount); 339 m_state.SetError(set, Write, 340 kret); // Set the current write error for this register set 341 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 342 // state in case registers are read 343 // back differently 344 return kret; // Return the error code 345 } 346 347 kern_return_t DNBArchMachARM64::SetVFPState() { 348 int set = e_regSetVFP; 349 kern_return_t kret = ::thread_set_state( 350 m_thread->MachPortNumber(), ARM_NEON_STATE64, 351 (thread_state_t)&m_state.context.vfp, e_regSetVFPCount); 352 m_state.SetError(set, Write, 353 kret); // Set the current write error for this register set 354 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 355 // state in case registers are read 356 // back differently 357 return kret; // Return the error code 358 } 359 360 kern_return_t DNBArchMachARM64::SetEXCState() { 361 int set = e_regSetEXC; 362 kern_return_t kret = ::thread_set_state( 363 m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, 364 (thread_state_t)&m_state.context.exc, e_regSetEXCCount); 365 m_state.SetError(set, Write, 366 kret); // Set the current write error for this register set 367 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 368 // state in case registers are read 369 // back differently 370 return kret; // Return the error code 371 } 372 373 kern_return_t DNBArchMachARM64::SetDBGState(bool also_set_on_task) { 374 int set = e_regSetDBG; 375 kern_return_t kret = 376 ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64, 377 (thread_state_t)&m_state.dbg, e_regSetDBGCount); 378 if (also_set_on_task) { 379 kern_return_t task_kret = task_set_state( 380 m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE64, 381 (thread_state_t)&m_state.dbg, e_regSetDBGCount); 382 if (task_kret != KERN_SUCCESS) 383 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::SetDBGState failed " 384 "to set debug control register state: " 385 "0x%8.8x.", 386 task_kret); 387 } 388 m_state.SetError(set, Write, 389 kret); // Set the current write error for this register set 390 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 391 // state in case registers are read 392 // back differently 393 394 return kret; // Return the error code 395 } 396 397 void DNBArchMachARM64::ThreadWillResume() { 398 // Do we need to step this thread? If so, let the mach thread tell us so. 399 if (m_thread->IsStepping()) { 400 EnableHardwareSingleStep(true); 401 } 402 403 // Disable the triggered watchpoint temporarily before we resume. 404 // Plus, we try to enable hardware single step to execute past the instruction 405 // which triggered our watchpoint. 406 if (m_watchpoint_did_occur) { 407 if (m_watchpoint_hw_index >= 0) { 408 kern_return_t kret = GetDBGState(false); 409 if (kret == KERN_SUCCESS && 410 !IsWatchpointEnabled(m_state.dbg, m_watchpoint_hw_index)) { 411 // The watchpoint might have been disabled by the user. We don't need 412 // to do anything at all 413 // to enable hardware single stepping. 414 m_watchpoint_did_occur = false; 415 m_watchpoint_hw_index = -1; 416 return; 417 } 418 419 DisableHardwareWatchpoint(m_watchpoint_hw_index, false); 420 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 421 "DisableHardwareWatchpoint(%d) called", 422 m_watchpoint_hw_index); 423 424 // Enable hardware single step to move past the watchpoint-triggering 425 // instruction. 426 m_watchpoint_resume_single_step_enabled = 427 (EnableHardwareSingleStep(true) == KERN_SUCCESS); 428 429 // If we are not able to enable single step to move past the 430 // watchpoint-triggering instruction, 431 // at least we should reset the two watchpoint member variables so that 432 // the next time around 433 // this callback function is invoked, the enclosing logical branch is 434 // skipped. 435 if (!m_watchpoint_resume_single_step_enabled) { 436 // Reset the two watchpoint member variables. 437 m_watchpoint_did_occur = false; 438 m_watchpoint_hw_index = -1; 439 DNBLogThreadedIf( 440 LOG_WATCHPOINTS, 441 "DNBArchMachARM::ThreadWillResume() failed to enable single step"); 442 } else 443 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 444 "succeeded to enable single step"); 445 } 446 } 447 } 448 449 bool DNBArchMachARM64::NotifyException(MachException::Data &exc) { 450 451 switch (exc.exc_type) { 452 default: 453 break; 454 case EXC_BREAKPOINT: 455 if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_DA_DEBUG) { 456 // The data break address is passed as exc_data[1]. 457 nub_addr_t addr = exc.exc_data[1]; 458 // Find the hardware index with the side effect of possibly massaging the 459 // addr to return the starting address as seen from the debugger side. 460 uint32_t hw_index = GetHardwareWatchpointHit(addr); 461 462 // One logical watchpoint was split into two watchpoint locations because 463 // it was too big. If the watchpoint exception is indicating the 2nd half 464 // of the two-parter, find the address of the 1st half and report that -- 465 // that's what lldb is going to expect to see. 466 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 467 "watchpoint %d was hit on address " 468 "0x%llx", 469 hw_index, (uint64_t)addr); 470 const int num_watchpoints = NumSupportedHardwareWatchpoints(); 471 for (int i = 0; i < num_watchpoints; i++) { 472 if (LoHi[i] != 0 && LoHi[i] == hw_index && LoHi[i] != i && 473 GetWatchpointAddressByIndex(i) != INVALID_NUB_ADDRESS) { 474 addr = GetWatchpointAddressByIndex(i); 475 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 476 "It is a linked watchpoint; " 477 "rewritten to index %d addr 0x%llx", 478 LoHi[i], (uint64_t)addr); 479 } 480 } 481 482 if (hw_index != INVALID_NUB_HW_INDEX) { 483 m_watchpoint_did_occur = true; 484 m_watchpoint_hw_index = hw_index; 485 exc.exc_data[1] = addr; 486 // Piggyback the hw_index in the exc.data. 487 exc.exc_data.push_back(hw_index); 488 } 489 490 return true; 491 } 492 break; 493 } 494 return false; 495 } 496 497 bool DNBArchMachARM64::ThreadDidStop() { 498 bool success = true; 499 500 m_state.InvalidateAllRegisterStates(); 501 502 if (m_watchpoint_resume_single_step_enabled) { 503 // Great! We now disable the hardware single step as well as re-enable the 504 // hardware watchpoint. 505 // See also ThreadWillResume(). 506 if (EnableHardwareSingleStep(false) == KERN_SUCCESS) { 507 if (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0) { 508 ReenableHardwareWatchpoint(m_watchpoint_hw_index); 509 m_watchpoint_resume_single_step_enabled = false; 510 m_watchpoint_did_occur = false; 511 m_watchpoint_hw_index = -1; 512 } else { 513 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 514 "is true but (m_watchpoint_did_occur && " 515 "m_watchpoint_hw_index >= 0) does not hold!"); 516 } 517 } else { 518 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 519 "is true but unable to disable single step!"); 520 } 521 } 522 523 // Are we stepping a single instruction? 524 if (GetGPRState(true) == KERN_SUCCESS) { 525 // We are single stepping, was this the primary thread? 526 if (m_thread->IsStepping()) { 527 // This was the primary thread, we need to clear the trace 528 // bit if so. 529 success = EnableHardwareSingleStep(false) == KERN_SUCCESS; 530 } else { 531 // The MachThread will automatically restore the suspend count 532 // in ThreadDidStop(), so we don't need to do anything here if 533 // we weren't the primary thread the last time 534 } 535 } 536 return success; 537 } 538 539 // Set the single step bit in the processor status register. 540 kern_return_t DNBArchMachARM64::EnableHardwareSingleStep(bool enable) { 541 DNBError err; 542 DNBLogThreadedIf(LOG_STEP, "%s( enable = %d )", __FUNCTION__, enable); 543 544 err = GetGPRState(false); 545 546 if (err.Fail()) { 547 err.LogThreaded("%s: failed to read the GPR registers", __FUNCTION__); 548 return err.Status(); 549 } 550 551 err = GetDBGState(false); 552 553 if (err.Fail()) { 554 err.LogThreaded("%s: failed to read the DBG registers", __FUNCTION__); 555 return err.Status(); 556 } 557 558 if (enable) { 559 DNBLogThreadedIf(LOG_STEP, 560 "%s: Setting MDSCR_EL1 Single Step bit at pc 0x%llx", 561 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc); 562 m_state.dbg.__mdscr_el1 |= SS_ENABLE; 563 } else { 564 DNBLogThreadedIf(LOG_STEP, 565 "%s: Clearing MDSCR_EL1 Single Step bit at pc 0x%llx", 566 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc); 567 m_state.dbg.__mdscr_el1 &= ~(SS_ENABLE); 568 } 569 570 return SetDBGState(false); 571 } 572 573 // return 1 if bit "BIT" is set in "value" 574 static inline uint32_t bit(uint32_t value, uint32_t bit) { 575 return (value >> bit) & 1u; 576 } 577 578 // return the bitfield "value[msbit:lsbit]". 579 static inline uint64_t bits(uint64_t value, uint32_t msbit, uint32_t lsbit) { 580 assert(msbit >= lsbit); 581 uint64_t shift_left = sizeof(value) * 8 - 1 - msbit; 582 value <<= 583 shift_left; // shift anything above the msbit off of the unsigned edge 584 value >>= shift_left + lsbit; // shift it back again down to the lsbit 585 // (including undoing any shift from above) 586 return value; // return our result 587 } 588 589 uint32_t DNBArchMachARM64::NumSupportedHardwareWatchpoints() { 590 // Set the init value to something that will let us know that we need to 591 // autodetect how many watchpoints are supported dynamically... 592 static uint32_t g_num_supported_hw_watchpoints = UINT_MAX; 593 if (g_num_supported_hw_watchpoints == UINT_MAX) { 594 // Set this to zero in case we can't tell if there are any HW breakpoints 595 g_num_supported_hw_watchpoints = 0; 596 597 size_t len; 598 uint32_t n = 0; 599 len = sizeof(n); 600 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) { 601 g_num_supported_hw_watchpoints = n; 602 DNBLogThreadedIf(LOG_THREAD, "hw.optional.watchpoint=%u", n); 603 } else { 604 // For AArch64 we would need to look at ID_AA64DFR0_EL1 but debugserver runs in 605 // EL0 so it can't 606 // access that reg. The kernel should have filled in the sysctls based on it 607 // though. 608 #if defined(__arm__) 609 uint32_t register_DBGDIDR; 610 611 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 612 uint32_t numWRPs = bits(register_DBGDIDR, 31, 28); 613 // Zero is reserved for the WRP count, so don't increment it if it is zero 614 if (numWRPs > 0) 615 numWRPs++; 616 g_num_supported_hw_watchpoints = numWRPs; 617 DNBLogThreadedIf(LOG_THREAD, 618 "Number of supported hw watchpoints via asm(): %d", 619 g_num_supported_hw_watchpoints); 620 #endif 621 } 622 } 623 return g_num_supported_hw_watchpoints; 624 } 625 626 uint32_t DNBArchMachARM64::EnableHardwareWatchpoint(nub_addr_t addr, 627 nub_size_t size, bool read, 628 bool write, 629 bool also_set_on_task) { 630 DNBLogThreadedIf(LOG_WATCHPOINTS, 631 "DNBArchMachARM64::EnableHardwareWatchpoint(addr = " 632 "0x%8.8llx, size = %zu, read = %u, write = %u)", 633 (uint64_t)addr, size, read, write); 634 635 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 636 637 // Can't watch zero bytes 638 if (size == 0) 639 return INVALID_NUB_HW_INDEX; 640 641 // We must watch for either read or write 642 if (read == false && write == false) 643 return INVALID_NUB_HW_INDEX; 644 645 // Otherwise, can't watch more than 8 bytes per WVR/WCR pair 646 if (size > 8) 647 return INVALID_NUB_HW_INDEX; 648 649 // arm64 watchpoints really have an 8-byte alignment requirement. You can put 650 // a watchpoint on a 4-byte 651 // offset address but you can only watch 4 bytes with that watchpoint. 652 653 // arm64 watchpoints on an 8-byte (double word) aligned addr can watch any 654 // bytes in that 655 // 8-byte long region of memory. They can watch the 1st byte, the 2nd byte, 656 // 3rd byte, etc, or any 657 // combination therein by setting the bits in the BAS [12:5] (Byte Address 658 // Select) field of 659 // the DBGWCRn_EL1 reg for the watchpoint. 660 661 // If the MASK [28:24] bits in the DBGWCRn_EL1 allow a single watchpoint to 662 // monitor a larger region 663 // of memory (16 bytes, 32 bytes, or 2GB) but the Byte Address Select bitfield 664 // then selects a larger 665 // range of bytes, instead of individual bytes. See the ARMv8 Debug 666 // Architecture manual for details. 667 // This implementation does not currently use the MASK bits; the largest 668 // single region watched by a single 669 // watchpoint right now is 8-bytes. 670 671 nub_addr_t aligned_wp_address = addr & ~0x7; 672 uint32_t addr_dword_offset = addr & 0x7; 673 674 // Do we need to split up this logical watchpoint into two hardware watchpoint 675 // registers? 676 // e.g. a watchpoint of length 4 on address 6. We need do this with 677 // one watchpoint on address 0 with bytes 6 & 7 being monitored 678 // one watchpoint on address 8 with bytes 0, 1, 2, 3 being monitored 679 680 if (addr_dword_offset + size > 8) { 681 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 682 "EnableHardwareWatchpoint(addr = " 683 "0x%8.8llx, size = %zu) needs two " 684 "hardware watchpoints slots to monitor", 685 (uint64_t)addr, size); 686 int low_watchpoint_size = 8 - addr_dword_offset; 687 int high_watchpoint_size = addr_dword_offset + size - 8; 688 689 uint32_t lo = EnableHardwareWatchpoint(addr, low_watchpoint_size, read, 690 write, also_set_on_task); 691 if (lo == INVALID_NUB_HW_INDEX) 692 return INVALID_NUB_HW_INDEX; 693 uint32_t hi = 694 EnableHardwareWatchpoint(aligned_wp_address + 8, high_watchpoint_size, 695 read, write, also_set_on_task); 696 if (hi == INVALID_NUB_HW_INDEX) { 697 DisableHardwareWatchpoint(lo, also_set_on_task); 698 return INVALID_NUB_HW_INDEX; 699 } 700 // Tag this lo->hi mapping in our database. 701 LoHi[lo] = hi; 702 return lo; 703 } 704 705 // At this point 706 // 1 aligned_wp_address is the requested address rounded down to 8-byte 707 // alignment 708 // 2 addr_dword_offset is the offset into that double word (8-byte) region 709 // that we are watching 710 // 3 size is the number of bytes within that 8-byte region that we are 711 // watching 712 713 // Set the Byte Address Selects bits DBGWCRn_EL1 bits [12:5] based on the 714 // above. 715 // The bit shift and negation operation will give us 0b11 for 2, 0b1111 for 4, 716 // etc, up to 0b11111111 for 8. 717 // then we shift those bits left by the offset into this dword that we are 718 // interested in. 719 // e.g. if we are watching bytes 4,5,6,7 in a dword we want a BAS of 720 // 0b11110000. 721 uint32_t byte_address_select = ((1 << size) - 1) << addr_dword_offset; 722 723 // Read the debug state 724 kern_return_t kret = GetDBGState(false); 725 726 if (kret == KERN_SUCCESS) { 727 // Check to make sure we have the needed hardware support 728 uint32_t i = 0; 729 730 for (i = 0; i < num_hw_watchpoints; ++i) { 731 if ((m_state.dbg.__wcr[i] & WCR_ENABLE) == 0) 732 break; // We found an available hw watchpoint slot (in i) 733 } 734 735 // See if we found an available hw watchpoint slot above 736 if (i < num_hw_watchpoints) { 737 // DumpDBGState(m_state.dbg); 738 739 // Clear any previous LoHi joined-watchpoint that may have been in use 740 LoHi[i] = 0; 741 742 // shift our Byte Address Select bits up to the correct bit range for the 743 // DBGWCRn_EL1 744 byte_address_select = byte_address_select << 5; 745 746 // Make sure bits 1:0 are clear in our address 747 m_state.dbg.__wvr[i] = aligned_wp_address; // DVA (Data Virtual Address) 748 m_state.dbg.__wcr[i] = byte_address_select | // Which bytes that follow 749 // the DVA that we will watch 750 S_USER | // Stop only in user mode 751 (read ? WCR_LOAD : 0) | // Stop on read access? 752 (write ? WCR_STORE : 0) | // Stop on write access? 753 WCR_ENABLE; // Enable this watchpoint; 754 755 DNBLogThreadedIf( 756 LOG_WATCHPOINTS, "DNBArchMachARM64::EnableHardwareWatchpoint() " 757 "adding watchpoint on address 0x%llx with control " 758 "register value 0x%x", 759 (uint64_t)m_state.dbg.__wvr[i], (uint32_t)m_state.dbg.__wcr[i]); 760 761 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 762 // automatically, don't need to do it here. 763 764 kret = SetDBGState(also_set_on_task); 765 // DumpDBGState(m_state.dbg); 766 767 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 768 "EnableHardwareWatchpoint() " 769 "SetDBGState() => 0x%8.8x.", 770 kret); 771 772 if (kret == KERN_SUCCESS) 773 return i; 774 } else { 775 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 776 "EnableHardwareWatchpoint(): All " 777 "hardware resources (%u) are in use.", 778 num_hw_watchpoints); 779 } 780 } 781 return INVALID_NUB_HW_INDEX; 782 } 783 784 bool DNBArchMachARM64::ReenableHardwareWatchpoint(uint32_t hw_index) { 785 // If this logical watchpoint # is actually implemented using 786 // two hardware watchpoint registers, re-enable both of them. 787 788 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 789 return ReenableHardwareWatchpoint_helper(hw_index) && 790 ReenableHardwareWatchpoint_helper(LoHi[hw_index]); 791 } else { 792 return ReenableHardwareWatchpoint_helper(hw_index); 793 } 794 } 795 796 bool DNBArchMachARM64::ReenableHardwareWatchpoint_helper(uint32_t hw_index) { 797 kern_return_t kret = GetDBGState(false); 798 if (kret != KERN_SUCCESS) 799 return false; 800 801 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 802 if (hw_index >= num_hw_points) 803 return false; 804 805 m_state.dbg.__wvr[hw_index] = m_disabled_watchpoints[hw_index].addr; 806 m_state.dbg.__wcr[hw_index] = m_disabled_watchpoints[hw_index].control; 807 808 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 809 "EnableHardwareWatchpoint( %u ) - WVR%u = " 810 "0x%8.8llx WCR%u = 0x%8.8llx", 811 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 812 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 813 814 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 815 // automatically, don't need to do it here. 816 817 kret = SetDBGState(false); 818 819 return (kret == KERN_SUCCESS); 820 } 821 822 bool DNBArchMachARM64::DisableHardwareWatchpoint(uint32_t hw_index, 823 bool also_set_on_task) { 824 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 825 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task) && 826 DisableHardwareWatchpoint_helper(LoHi[hw_index], also_set_on_task); 827 } else { 828 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task); 829 } 830 } 831 832 bool DNBArchMachARM64::DisableHardwareWatchpoint_helper(uint32_t hw_index, 833 bool also_set_on_task) { 834 kern_return_t kret = GetDBGState(false); 835 if (kret != KERN_SUCCESS) 836 return false; 837 838 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 839 if (hw_index >= num_hw_points) 840 return false; 841 842 m_disabled_watchpoints[hw_index].addr = m_state.dbg.__wvr[hw_index]; 843 m_disabled_watchpoints[hw_index].control = m_state.dbg.__wcr[hw_index]; 844 845 m_state.dbg.__wcr[hw_index] &= ~((nub_addr_t)WCR_ENABLE); 846 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 847 "DisableHardwareWatchpoint( %u ) - WVR%u = " 848 "0x%8.8llx WCR%u = 0x%8.8llx", 849 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 850 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 851 852 kret = SetDBGState(also_set_on_task); 853 854 return (kret == KERN_SUCCESS); 855 } 856 857 // This is for checking the Byte Address Select bits in the DBRWCRn_EL1 control 858 // register. 859 // Returns -1 if the trailing bit patterns are not one of: 860 // { 0b???????1, 0b??????10, 0b?????100, 0b????1000, 0b???10000, 0b??100000, 861 // 0b?1000000, 0b10000000 }. 862 static inline int32_t LowestBitSet(uint32_t val) { 863 for (unsigned i = 0; i < 8; ++i) { 864 if (bit(val, i)) 865 return i; 866 } 867 return -1; 868 } 869 870 // Iterate through the debug registers; return the index of the first watchpoint 871 // whose address matches. 872 // As a side effect, the starting address as understood by the debugger is 873 // returned which could be 874 // different from 'addr' passed as an in/out argument. 875 uint32_t DNBArchMachARM64::GetHardwareWatchpointHit(nub_addr_t &addr) { 876 // Read the debug state 877 kern_return_t kret = GetDBGState(true); 878 // DumpDBGState(m_state.dbg); 879 DNBLogThreadedIf( 880 LOG_WATCHPOINTS, 881 "DNBArchMachARM64::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", 882 kret); 883 DNBLogThreadedIf(LOG_WATCHPOINTS, 884 "DNBArchMachARM64::GetHardwareWatchpointHit() addr = 0x%llx", 885 (uint64_t)addr); 886 887 // This is the watchpoint value to match against, i.e., word address. 888 nub_addr_t wp_val = addr & ~((nub_addr_t)3); 889 if (kret == KERN_SUCCESS) { 890 DBG &debug_state = m_state.dbg; 891 uint32_t i, num = NumSupportedHardwareWatchpoints(); 892 for (i = 0; i < num; ++i) { 893 nub_addr_t wp_addr = GetWatchAddress(debug_state, i); 894 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 895 "GetHardwareWatchpointHit() slot: %u " 896 "(addr = 0x%llx).", 897 i, (uint64_t)wp_addr); 898 if (wp_val == wp_addr) { 899 uint32_t byte_mask = bits(debug_state.__wcr[i], 12, 5); 900 901 // Sanity check the byte_mask, first. 902 if (LowestBitSet(byte_mask) < 0) 903 continue; 904 905 // Check that the watchpoint is enabled. 906 if (!IsWatchpointEnabled(debug_state, i)) 907 continue; 908 909 // Compute the starting address (from the point of view of the 910 // debugger). 911 addr = wp_addr + LowestBitSet(byte_mask); 912 return i; 913 } 914 } 915 } 916 return INVALID_NUB_HW_INDEX; 917 } 918 919 nub_addr_t DNBArchMachARM64::GetWatchpointAddressByIndex(uint32_t hw_index) { 920 kern_return_t kret = GetDBGState(true); 921 if (kret != KERN_SUCCESS) 922 return INVALID_NUB_ADDRESS; 923 const uint32_t num = NumSupportedHardwareWatchpoints(); 924 if (hw_index >= num) 925 return INVALID_NUB_ADDRESS; 926 if (IsWatchpointEnabled(m_state.dbg, hw_index)) 927 return GetWatchAddress(m_state.dbg, hw_index); 928 return INVALID_NUB_ADDRESS; 929 } 930 931 bool DNBArchMachARM64::IsWatchpointEnabled(const DBG &debug_state, 932 uint32_t hw_index) { 933 // Watchpoint Control Registers, bitfield definitions 934 // ... 935 // Bits Value Description 936 // [0] 0 Watchpoint disabled 937 // 1 Watchpoint enabled. 938 return (debug_state.__wcr[hw_index] & 1u); 939 } 940 941 nub_addr_t DNBArchMachARM64::GetWatchAddress(const DBG &debug_state, 942 uint32_t hw_index) { 943 // Watchpoint Value Registers, bitfield definitions 944 // Bits Description 945 // [31:2] Watchpoint value (word address, i.e., 4-byte aligned) 946 // [1:0] RAZ/SBZP 947 return bits(debug_state.__wvr[hw_index], 63, 0); 948 } 949 950 // Register information definitions for 64 bit ARMv8. 951 enum gpr_regnums { 952 gpr_x0 = 0, 953 gpr_x1, 954 gpr_x2, 955 gpr_x3, 956 gpr_x4, 957 gpr_x5, 958 gpr_x6, 959 gpr_x7, 960 gpr_x8, 961 gpr_x9, 962 gpr_x10, 963 gpr_x11, 964 gpr_x12, 965 gpr_x13, 966 gpr_x14, 967 gpr_x15, 968 gpr_x16, 969 gpr_x17, 970 gpr_x18, 971 gpr_x19, 972 gpr_x20, 973 gpr_x21, 974 gpr_x22, 975 gpr_x23, 976 gpr_x24, 977 gpr_x25, 978 gpr_x26, 979 gpr_x27, 980 gpr_x28, 981 gpr_fp, 982 gpr_x29 = gpr_fp, 983 gpr_lr, 984 gpr_x30 = gpr_lr, 985 gpr_sp, 986 gpr_x31 = gpr_sp, 987 gpr_pc, 988 gpr_cpsr, 989 gpr_w0, 990 gpr_w1, 991 gpr_w2, 992 gpr_w3, 993 gpr_w4, 994 gpr_w5, 995 gpr_w6, 996 gpr_w7, 997 gpr_w8, 998 gpr_w9, 999 gpr_w10, 1000 gpr_w11, 1001 gpr_w12, 1002 gpr_w13, 1003 gpr_w14, 1004 gpr_w15, 1005 gpr_w16, 1006 gpr_w17, 1007 gpr_w18, 1008 gpr_w19, 1009 gpr_w20, 1010 gpr_w21, 1011 gpr_w22, 1012 gpr_w23, 1013 gpr_w24, 1014 gpr_w25, 1015 gpr_w26, 1016 gpr_w27, 1017 gpr_w28 1018 1019 }; 1020 1021 enum { 1022 vfp_v0 = 0, 1023 vfp_v1, 1024 vfp_v2, 1025 vfp_v3, 1026 vfp_v4, 1027 vfp_v5, 1028 vfp_v6, 1029 vfp_v7, 1030 vfp_v8, 1031 vfp_v9, 1032 vfp_v10, 1033 vfp_v11, 1034 vfp_v12, 1035 vfp_v13, 1036 vfp_v14, 1037 vfp_v15, 1038 vfp_v16, 1039 vfp_v17, 1040 vfp_v18, 1041 vfp_v19, 1042 vfp_v20, 1043 vfp_v21, 1044 vfp_v22, 1045 vfp_v23, 1046 vfp_v24, 1047 vfp_v25, 1048 vfp_v26, 1049 vfp_v27, 1050 vfp_v28, 1051 vfp_v29, 1052 vfp_v30, 1053 vfp_v31, 1054 vfp_fpsr, 1055 vfp_fpcr, 1056 1057 // lower 32 bits of the corresponding vfp_v<n> reg. 1058 vfp_s0, 1059 vfp_s1, 1060 vfp_s2, 1061 vfp_s3, 1062 vfp_s4, 1063 vfp_s5, 1064 vfp_s6, 1065 vfp_s7, 1066 vfp_s8, 1067 vfp_s9, 1068 vfp_s10, 1069 vfp_s11, 1070 vfp_s12, 1071 vfp_s13, 1072 vfp_s14, 1073 vfp_s15, 1074 vfp_s16, 1075 vfp_s17, 1076 vfp_s18, 1077 vfp_s19, 1078 vfp_s20, 1079 vfp_s21, 1080 vfp_s22, 1081 vfp_s23, 1082 vfp_s24, 1083 vfp_s25, 1084 vfp_s26, 1085 vfp_s27, 1086 vfp_s28, 1087 vfp_s29, 1088 vfp_s30, 1089 vfp_s31, 1090 1091 // lower 64 bits of the corresponding vfp_v<n> reg. 1092 vfp_d0, 1093 vfp_d1, 1094 vfp_d2, 1095 vfp_d3, 1096 vfp_d4, 1097 vfp_d5, 1098 vfp_d6, 1099 vfp_d7, 1100 vfp_d8, 1101 vfp_d9, 1102 vfp_d10, 1103 vfp_d11, 1104 vfp_d12, 1105 vfp_d13, 1106 vfp_d14, 1107 vfp_d15, 1108 vfp_d16, 1109 vfp_d17, 1110 vfp_d18, 1111 vfp_d19, 1112 vfp_d20, 1113 vfp_d21, 1114 vfp_d22, 1115 vfp_d23, 1116 vfp_d24, 1117 vfp_d25, 1118 vfp_d26, 1119 vfp_d27, 1120 vfp_d28, 1121 vfp_d29, 1122 vfp_d30, 1123 vfp_d31 1124 }; 1125 1126 enum { exc_far = 0, exc_esr, exc_exception }; 1127 1128 // These numbers from the "DWARF for the ARM 64-bit Architecture (AArch64)" 1129 // document. 1130 1131 enum { 1132 dwarf_x0 = 0, 1133 dwarf_x1, 1134 dwarf_x2, 1135 dwarf_x3, 1136 dwarf_x4, 1137 dwarf_x5, 1138 dwarf_x6, 1139 dwarf_x7, 1140 dwarf_x8, 1141 dwarf_x9, 1142 dwarf_x10, 1143 dwarf_x11, 1144 dwarf_x12, 1145 dwarf_x13, 1146 dwarf_x14, 1147 dwarf_x15, 1148 dwarf_x16, 1149 dwarf_x17, 1150 dwarf_x18, 1151 dwarf_x19, 1152 dwarf_x20, 1153 dwarf_x21, 1154 dwarf_x22, 1155 dwarf_x23, 1156 dwarf_x24, 1157 dwarf_x25, 1158 dwarf_x26, 1159 dwarf_x27, 1160 dwarf_x28, 1161 dwarf_x29, 1162 dwarf_x30, 1163 dwarf_x31, 1164 dwarf_pc = 32, 1165 dwarf_elr_mode = 33, 1166 dwarf_fp = dwarf_x29, 1167 dwarf_lr = dwarf_x30, 1168 dwarf_sp = dwarf_x31, 1169 // 34-63 reserved 1170 1171 // V0-V31 (128 bit vector registers) 1172 dwarf_v0 = 64, 1173 dwarf_v1, 1174 dwarf_v2, 1175 dwarf_v3, 1176 dwarf_v4, 1177 dwarf_v5, 1178 dwarf_v6, 1179 dwarf_v7, 1180 dwarf_v8, 1181 dwarf_v9, 1182 dwarf_v10, 1183 dwarf_v11, 1184 dwarf_v12, 1185 dwarf_v13, 1186 dwarf_v14, 1187 dwarf_v15, 1188 dwarf_v16, 1189 dwarf_v17, 1190 dwarf_v18, 1191 dwarf_v19, 1192 dwarf_v20, 1193 dwarf_v21, 1194 dwarf_v22, 1195 dwarf_v23, 1196 dwarf_v24, 1197 dwarf_v25, 1198 dwarf_v26, 1199 dwarf_v27, 1200 dwarf_v28, 1201 dwarf_v29, 1202 dwarf_v30, 1203 dwarf_v31 1204 1205 // 96-127 reserved 1206 }; 1207 1208 enum { 1209 debugserver_gpr_x0 = 0, 1210 debugserver_gpr_x1, 1211 debugserver_gpr_x2, 1212 debugserver_gpr_x3, 1213 debugserver_gpr_x4, 1214 debugserver_gpr_x5, 1215 debugserver_gpr_x6, 1216 debugserver_gpr_x7, 1217 debugserver_gpr_x8, 1218 debugserver_gpr_x9, 1219 debugserver_gpr_x10, 1220 debugserver_gpr_x11, 1221 debugserver_gpr_x12, 1222 debugserver_gpr_x13, 1223 debugserver_gpr_x14, 1224 debugserver_gpr_x15, 1225 debugserver_gpr_x16, 1226 debugserver_gpr_x17, 1227 debugserver_gpr_x18, 1228 debugserver_gpr_x19, 1229 debugserver_gpr_x20, 1230 debugserver_gpr_x21, 1231 debugserver_gpr_x22, 1232 debugserver_gpr_x23, 1233 debugserver_gpr_x24, 1234 debugserver_gpr_x25, 1235 debugserver_gpr_x26, 1236 debugserver_gpr_x27, 1237 debugserver_gpr_x28, 1238 debugserver_gpr_fp, // x29 1239 debugserver_gpr_lr, // x30 1240 debugserver_gpr_sp, // sp aka xsp 1241 debugserver_gpr_pc, 1242 debugserver_gpr_cpsr, 1243 debugserver_vfp_v0, 1244 debugserver_vfp_v1, 1245 debugserver_vfp_v2, 1246 debugserver_vfp_v3, 1247 debugserver_vfp_v4, 1248 debugserver_vfp_v5, 1249 debugserver_vfp_v6, 1250 debugserver_vfp_v7, 1251 debugserver_vfp_v8, 1252 debugserver_vfp_v9, 1253 debugserver_vfp_v10, 1254 debugserver_vfp_v11, 1255 debugserver_vfp_v12, 1256 debugserver_vfp_v13, 1257 debugserver_vfp_v14, 1258 debugserver_vfp_v15, 1259 debugserver_vfp_v16, 1260 debugserver_vfp_v17, 1261 debugserver_vfp_v18, 1262 debugserver_vfp_v19, 1263 debugserver_vfp_v20, 1264 debugserver_vfp_v21, 1265 debugserver_vfp_v22, 1266 debugserver_vfp_v23, 1267 debugserver_vfp_v24, 1268 debugserver_vfp_v25, 1269 debugserver_vfp_v26, 1270 debugserver_vfp_v27, 1271 debugserver_vfp_v28, 1272 debugserver_vfp_v29, 1273 debugserver_vfp_v30, 1274 debugserver_vfp_v31, 1275 debugserver_vfp_fpsr, 1276 debugserver_vfp_fpcr 1277 }; 1278 1279 const char *g_contained_x0[]{"x0", NULL}; 1280 const char *g_contained_x1[]{"x1", NULL}; 1281 const char *g_contained_x2[]{"x2", NULL}; 1282 const char *g_contained_x3[]{"x3", NULL}; 1283 const char *g_contained_x4[]{"x4", NULL}; 1284 const char *g_contained_x5[]{"x5", NULL}; 1285 const char *g_contained_x6[]{"x6", NULL}; 1286 const char *g_contained_x7[]{"x7", NULL}; 1287 const char *g_contained_x8[]{"x8", NULL}; 1288 const char *g_contained_x9[]{"x9", NULL}; 1289 const char *g_contained_x10[]{"x10", NULL}; 1290 const char *g_contained_x11[]{"x11", NULL}; 1291 const char *g_contained_x12[]{"x12", NULL}; 1292 const char *g_contained_x13[]{"x13", NULL}; 1293 const char *g_contained_x14[]{"x14", NULL}; 1294 const char *g_contained_x15[]{"x15", NULL}; 1295 const char *g_contained_x16[]{"x16", NULL}; 1296 const char *g_contained_x17[]{"x17", NULL}; 1297 const char *g_contained_x18[]{"x18", NULL}; 1298 const char *g_contained_x19[]{"x19", NULL}; 1299 const char *g_contained_x20[]{"x20", NULL}; 1300 const char *g_contained_x21[]{"x21", NULL}; 1301 const char *g_contained_x22[]{"x22", NULL}; 1302 const char *g_contained_x23[]{"x23", NULL}; 1303 const char *g_contained_x24[]{"x24", NULL}; 1304 const char *g_contained_x25[]{"x25", NULL}; 1305 const char *g_contained_x26[]{"x26", NULL}; 1306 const char *g_contained_x27[]{"x27", NULL}; 1307 const char *g_contained_x28[]{"x28", NULL}; 1308 1309 const char *g_invalidate_x0[]{"x0", "w0", NULL}; 1310 const char *g_invalidate_x1[]{"x1", "w1", NULL}; 1311 const char *g_invalidate_x2[]{"x2", "w2", NULL}; 1312 const char *g_invalidate_x3[]{"x3", "w3", NULL}; 1313 const char *g_invalidate_x4[]{"x4", "w4", NULL}; 1314 const char *g_invalidate_x5[]{"x5", "w5", NULL}; 1315 const char *g_invalidate_x6[]{"x6", "w6", NULL}; 1316 const char *g_invalidate_x7[]{"x7", "w7", NULL}; 1317 const char *g_invalidate_x8[]{"x8", "w8", NULL}; 1318 const char *g_invalidate_x9[]{"x9", "w9", NULL}; 1319 const char *g_invalidate_x10[]{"x10", "w10", NULL}; 1320 const char *g_invalidate_x11[]{"x11", "w11", NULL}; 1321 const char *g_invalidate_x12[]{"x12", "w12", NULL}; 1322 const char *g_invalidate_x13[]{"x13", "w13", NULL}; 1323 const char *g_invalidate_x14[]{"x14", "w14", NULL}; 1324 const char *g_invalidate_x15[]{"x15", "w15", NULL}; 1325 const char *g_invalidate_x16[]{"x16", "w16", NULL}; 1326 const char *g_invalidate_x17[]{"x17", "w17", NULL}; 1327 const char *g_invalidate_x18[]{"x18", "w18", NULL}; 1328 const char *g_invalidate_x19[]{"x19", "w19", NULL}; 1329 const char *g_invalidate_x20[]{"x20", "w20", NULL}; 1330 const char *g_invalidate_x21[]{"x21", "w21", NULL}; 1331 const char *g_invalidate_x22[]{"x22", "w22", NULL}; 1332 const char *g_invalidate_x23[]{"x23", "w23", NULL}; 1333 const char *g_invalidate_x24[]{"x24", "w24", NULL}; 1334 const char *g_invalidate_x25[]{"x25", "w25", NULL}; 1335 const char *g_invalidate_x26[]{"x26", "w26", NULL}; 1336 const char *g_invalidate_x27[]{"x27", "w27", NULL}; 1337 const char *g_invalidate_x28[]{"x28", "w28", NULL}; 1338 1339 #define GPR_OFFSET_IDX(idx) (offsetof(DNBArchMachARM64::GPR, __x[idx])) 1340 1341 #define GPR_OFFSET_NAME(reg) (offsetof(DNBArchMachARM64::GPR, __##reg)) 1342 1343 // These macros will auto define the register name, alt name, register size, 1344 // register offset, encoding, format and native register. This ensures that 1345 // the register state structures are defined correctly and have the correct 1346 // sizes and offsets. 1347 #define DEFINE_GPR_IDX(idx, reg, alt, gen) \ 1348 { \ 1349 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_IDX(idx), \ 1350 dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, \ 1351 g_invalidate_x##idx \ 1352 } 1353 #define DEFINE_GPR_NAME(reg, alt, gen) \ 1354 { \ 1355 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_NAME(reg), \ 1356 dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, NULL \ 1357 } 1358 #define DEFINE_PSEUDO_GPR_IDX(idx, reg) \ 1359 { \ 1360 e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, 4, 0, INVALID_NUB_REGNUM, \ 1361 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1362 g_contained_x##idx, g_invalidate_x##idx \ 1363 } 1364 1365 //_STRUCT_ARM_THREAD_STATE64 1366 //{ 1367 // uint64_t x[29]; /* General purpose registers x0-x28 */ 1368 // uint64_t fp; /* Frame pointer x29 */ 1369 // uint64_t lr; /* Link register x30 */ 1370 // uint64_t sp; /* Stack pointer x31 */ 1371 // uint64_t pc; /* Program counter */ 1372 // uint32_t cpsr; /* Current program status register */ 1373 //}; 1374 1375 // General purpose registers 1376 const DNBRegisterInfo DNBArchMachARM64::g_gpr_registers[] = { 1377 DEFINE_GPR_IDX(0, x0, "arg1", GENERIC_REGNUM_ARG1), 1378 DEFINE_GPR_IDX(1, x1, "arg2", GENERIC_REGNUM_ARG2), 1379 DEFINE_GPR_IDX(2, x2, "arg3", GENERIC_REGNUM_ARG3), 1380 DEFINE_GPR_IDX(3, x3, "arg4", GENERIC_REGNUM_ARG4), 1381 DEFINE_GPR_IDX(4, x4, "arg5", GENERIC_REGNUM_ARG5), 1382 DEFINE_GPR_IDX(5, x5, "arg6", GENERIC_REGNUM_ARG6), 1383 DEFINE_GPR_IDX(6, x6, "arg7", GENERIC_REGNUM_ARG7), 1384 DEFINE_GPR_IDX(7, x7, "arg8", GENERIC_REGNUM_ARG8), 1385 DEFINE_GPR_IDX(8, x8, NULL, INVALID_NUB_REGNUM), 1386 DEFINE_GPR_IDX(9, x9, NULL, INVALID_NUB_REGNUM), 1387 DEFINE_GPR_IDX(10, x10, NULL, INVALID_NUB_REGNUM), 1388 DEFINE_GPR_IDX(11, x11, NULL, INVALID_NUB_REGNUM), 1389 DEFINE_GPR_IDX(12, x12, NULL, INVALID_NUB_REGNUM), 1390 DEFINE_GPR_IDX(13, x13, NULL, INVALID_NUB_REGNUM), 1391 DEFINE_GPR_IDX(14, x14, NULL, INVALID_NUB_REGNUM), 1392 DEFINE_GPR_IDX(15, x15, NULL, INVALID_NUB_REGNUM), 1393 DEFINE_GPR_IDX(16, x16, NULL, INVALID_NUB_REGNUM), 1394 DEFINE_GPR_IDX(17, x17, NULL, INVALID_NUB_REGNUM), 1395 DEFINE_GPR_IDX(18, x18, NULL, INVALID_NUB_REGNUM), 1396 DEFINE_GPR_IDX(19, x19, NULL, INVALID_NUB_REGNUM), 1397 DEFINE_GPR_IDX(20, x20, NULL, INVALID_NUB_REGNUM), 1398 DEFINE_GPR_IDX(21, x21, NULL, INVALID_NUB_REGNUM), 1399 DEFINE_GPR_IDX(22, x22, NULL, INVALID_NUB_REGNUM), 1400 DEFINE_GPR_IDX(23, x23, NULL, INVALID_NUB_REGNUM), 1401 DEFINE_GPR_IDX(24, x24, NULL, INVALID_NUB_REGNUM), 1402 DEFINE_GPR_IDX(25, x25, NULL, INVALID_NUB_REGNUM), 1403 DEFINE_GPR_IDX(26, x26, NULL, INVALID_NUB_REGNUM), 1404 DEFINE_GPR_IDX(27, x27, NULL, INVALID_NUB_REGNUM), 1405 DEFINE_GPR_IDX(28, x28, NULL, INVALID_NUB_REGNUM), 1406 DEFINE_GPR_NAME(fp, "x29", GENERIC_REGNUM_FP), 1407 DEFINE_GPR_NAME(lr, "x30", GENERIC_REGNUM_RA), 1408 DEFINE_GPR_NAME(sp, "xsp", GENERIC_REGNUM_SP), 1409 DEFINE_GPR_NAME(pc, NULL, GENERIC_REGNUM_PC), 1410 1411 // in armv7 we specify that writing to the CPSR should invalidate r8-12, sp, 1412 // lr. 1413 // this should be specified for arm64 too even though debugserver is only 1414 // used for 1415 // userland debugging. 1416 {e_regSetGPR, gpr_cpsr, "cpsr", "flags", Uint, Hex, 4, 1417 GPR_OFFSET_NAME(cpsr), dwarf_elr_mode, dwarf_elr_mode, INVALID_NUB_REGNUM, 1418 debugserver_gpr_cpsr, NULL, NULL}, 1419 1420 DEFINE_PSEUDO_GPR_IDX(0, w0), 1421 DEFINE_PSEUDO_GPR_IDX(1, w1), 1422 DEFINE_PSEUDO_GPR_IDX(2, w2), 1423 DEFINE_PSEUDO_GPR_IDX(3, w3), 1424 DEFINE_PSEUDO_GPR_IDX(4, w4), 1425 DEFINE_PSEUDO_GPR_IDX(5, w5), 1426 DEFINE_PSEUDO_GPR_IDX(6, w6), 1427 DEFINE_PSEUDO_GPR_IDX(7, w7), 1428 DEFINE_PSEUDO_GPR_IDX(8, w8), 1429 DEFINE_PSEUDO_GPR_IDX(9, w9), 1430 DEFINE_PSEUDO_GPR_IDX(10, w10), 1431 DEFINE_PSEUDO_GPR_IDX(11, w11), 1432 DEFINE_PSEUDO_GPR_IDX(12, w12), 1433 DEFINE_PSEUDO_GPR_IDX(13, w13), 1434 DEFINE_PSEUDO_GPR_IDX(14, w14), 1435 DEFINE_PSEUDO_GPR_IDX(15, w15), 1436 DEFINE_PSEUDO_GPR_IDX(16, w16), 1437 DEFINE_PSEUDO_GPR_IDX(17, w17), 1438 DEFINE_PSEUDO_GPR_IDX(18, w18), 1439 DEFINE_PSEUDO_GPR_IDX(19, w19), 1440 DEFINE_PSEUDO_GPR_IDX(20, w20), 1441 DEFINE_PSEUDO_GPR_IDX(21, w21), 1442 DEFINE_PSEUDO_GPR_IDX(22, w22), 1443 DEFINE_PSEUDO_GPR_IDX(23, w23), 1444 DEFINE_PSEUDO_GPR_IDX(24, w24), 1445 DEFINE_PSEUDO_GPR_IDX(25, w25), 1446 DEFINE_PSEUDO_GPR_IDX(26, w26), 1447 DEFINE_PSEUDO_GPR_IDX(27, w27), 1448 DEFINE_PSEUDO_GPR_IDX(28, w28)}; 1449 1450 const char *g_contained_v0[]{"v0", NULL}; 1451 const char *g_contained_v1[]{"v1", NULL}; 1452 const char *g_contained_v2[]{"v2", NULL}; 1453 const char *g_contained_v3[]{"v3", NULL}; 1454 const char *g_contained_v4[]{"v4", NULL}; 1455 const char *g_contained_v5[]{"v5", NULL}; 1456 const char *g_contained_v6[]{"v6", NULL}; 1457 const char *g_contained_v7[]{"v7", NULL}; 1458 const char *g_contained_v8[]{"v8", NULL}; 1459 const char *g_contained_v9[]{"v9", NULL}; 1460 const char *g_contained_v10[]{"v10", NULL}; 1461 const char *g_contained_v11[]{"v11", NULL}; 1462 const char *g_contained_v12[]{"v12", NULL}; 1463 const char *g_contained_v13[]{"v13", NULL}; 1464 const char *g_contained_v14[]{"v14", NULL}; 1465 const char *g_contained_v15[]{"v15", NULL}; 1466 const char *g_contained_v16[]{"v16", NULL}; 1467 const char *g_contained_v17[]{"v17", NULL}; 1468 const char *g_contained_v18[]{"v18", NULL}; 1469 const char *g_contained_v19[]{"v19", NULL}; 1470 const char *g_contained_v20[]{"v20", NULL}; 1471 const char *g_contained_v21[]{"v21", NULL}; 1472 const char *g_contained_v22[]{"v22", NULL}; 1473 const char *g_contained_v23[]{"v23", NULL}; 1474 const char *g_contained_v24[]{"v24", NULL}; 1475 const char *g_contained_v25[]{"v25", NULL}; 1476 const char *g_contained_v26[]{"v26", NULL}; 1477 const char *g_contained_v27[]{"v27", NULL}; 1478 const char *g_contained_v28[]{"v28", NULL}; 1479 const char *g_contained_v29[]{"v29", NULL}; 1480 const char *g_contained_v30[]{"v30", NULL}; 1481 const char *g_contained_v31[]{"v31", NULL}; 1482 1483 const char *g_invalidate_v0[]{"v0", "d0", "s0", NULL}; 1484 const char *g_invalidate_v1[]{"v1", "d1", "s1", NULL}; 1485 const char *g_invalidate_v2[]{"v2", "d2", "s2", NULL}; 1486 const char *g_invalidate_v3[]{"v3", "d3", "s3", NULL}; 1487 const char *g_invalidate_v4[]{"v4", "d4", "s4", NULL}; 1488 const char *g_invalidate_v5[]{"v5", "d5", "s5", NULL}; 1489 const char *g_invalidate_v6[]{"v6", "d6", "s6", NULL}; 1490 const char *g_invalidate_v7[]{"v7", "d7", "s7", NULL}; 1491 const char *g_invalidate_v8[]{"v8", "d8", "s8", NULL}; 1492 const char *g_invalidate_v9[]{"v9", "d9", "s9", NULL}; 1493 const char *g_invalidate_v10[]{"v10", "d10", "s10", NULL}; 1494 const char *g_invalidate_v11[]{"v11", "d11", "s11", NULL}; 1495 const char *g_invalidate_v12[]{"v12", "d12", "s12", NULL}; 1496 const char *g_invalidate_v13[]{"v13", "d13", "s13", NULL}; 1497 const char *g_invalidate_v14[]{"v14", "d14", "s14", NULL}; 1498 const char *g_invalidate_v15[]{"v15", "d15", "s15", NULL}; 1499 const char *g_invalidate_v16[]{"v16", "d16", "s16", NULL}; 1500 const char *g_invalidate_v17[]{"v17", "d17", "s17", NULL}; 1501 const char *g_invalidate_v18[]{"v18", "d18", "s18", NULL}; 1502 const char *g_invalidate_v19[]{"v19", "d19", "s19", NULL}; 1503 const char *g_invalidate_v20[]{"v20", "d20", "s20", NULL}; 1504 const char *g_invalidate_v21[]{"v21", "d21", "s21", NULL}; 1505 const char *g_invalidate_v22[]{"v22", "d22", "s22", NULL}; 1506 const char *g_invalidate_v23[]{"v23", "d23", "s23", NULL}; 1507 const char *g_invalidate_v24[]{"v24", "d24", "s24", NULL}; 1508 const char *g_invalidate_v25[]{"v25", "d25", "s25", NULL}; 1509 const char *g_invalidate_v26[]{"v26", "d26", "s26", NULL}; 1510 const char *g_invalidate_v27[]{"v27", "d27", "s27", NULL}; 1511 const char *g_invalidate_v28[]{"v28", "d28", "s28", NULL}; 1512 const char *g_invalidate_v29[]{"v29", "d29", "s29", NULL}; 1513 const char *g_invalidate_v30[]{"v30", "d30", "s30", NULL}; 1514 const char *g_invalidate_v31[]{"v31", "d31", "s31", NULL}; 1515 1516 #if defined(__arm64__) || defined(__aarch64__) 1517 #define VFP_V_OFFSET_IDX(idx) \ 1518 (offsetof(DNBArchMachARM64::FPU, __v) + (idx * 16) + \ 1519 offsetof(DNBArchMachARM64::Context, vfp)) 1520 #else 1521 #define VFP_V_OFFSET_IDX(idx) \ 1522 (offsetof(DNBArchMachARM64::FPU, opaque) + (idx * 16) + \ 1523 offsetof(DNBArchMachARM64::Context, vfp)) 1524 #endif 1525 #define VFP_OFFSET_NAME(reg) \ 1526 (offsetof(DNBArchMachARM64::FPU, reg) + \ 1527 offsetof(DNBArchMachARM64::Context, vfp)) 1528 #define EXC_OFFSET(reg) \ 1529 (offsetof(DNBArchMachARM64::EXC, reg) + \ 1530 offsetof(DNBArchMachARM64::Context, exc)) 1531 1532 //#define FLOAT_FORMAT Float 1533 #define DEFINE_VFP_V_IDX(idx) \ 1534 { \ 1535 e_regSetVFP, vfp_v##idx, "v" #idx, "q" #idx, Vector, VectorOfUInt8, 16, \ 1536 VFP_V_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_v##idx, \ 1537 INVALID_NUB_REGNUM, debugserver_vfp_v##idx, NULL, g_invalidate_v##idx \ 1538 } 1539 #define DEFINE_PSEUDO_VFP_S_IDX(idx) \ 1540 { \ 1541 e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, Float, 4, 0, \ 1542 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1543 INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \ 1544 } 1545 #define DEFINE_PSEUDO_VFP_D_IDX(idx) \ 1546 { \ 1547 e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, Float, 8, 0, \ 1548 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1549 INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \ 1550 } 1551 1552 // Floating point registers 1553 const DNBRegisterInfo DNBArchMachARM64::g_vfp_registers[] = { 1554 DEFINE_VFP_V_IDX(0), 1555 DEFINE_VFP_V_IDX(1), 1556 DEFINE_VFP_V_IDX(2), 1557 DEFINE_VFP_V_IDX(3), 1558 DEFINE_VFP_V_IDX(4), 1559 DEFINE_VFP_V_IDX(5), 1560 DEFINE_VFP_V_IDX(6), 1561 DEFINE_VFP_V_IDX(7), 1562 DEFINE_VFP_V_IDX(8), 1563 DEFINE_VFP_V_IDX(9), 1564 DEFINE_VFP_V_IDX(10), 1565 DEFINE_VFP_V_IDX(11), 1566 DEFINE_VFP_V_IDX(12), 1567 DEFINE_VFP_V_IDX(13), 1568 DEFINE_VFP_V_IDX(14), 1569 DEFINE_VFP_V_IDX(15), 1570 DEFINE_VFP_V_IDX(16), 1571 DEFINE_VFP_V_IDX(17), 1572 DEFINE_VFP_V_IDX(18), 1573 DEFINE_VFP_V_IDX(19), 1574 DEFINE_VFP_V_IDX(20), 1575 DEFINE_VFP_V_IDX(21), 1576 DEFINE_VFP_V_IDX(22), 1577 DEFINE_VFP_V_IDX(23), 1578 DEFINE_VFP_V_IDX(24), 1579 DEFINE_VFP_V_IDX(25), 1580 DEFINE_VFP_V_IDX(26), 1581 DEFINE_VFP_V_IDX(27), 1582 DEFINE_VFP_V_IDX(28), 1583 DEFINE_VFP_V_IDX(29), 1584 DEFINE_VFP_V_IDX(30), 1585 DEFINE_VFP_V_IDX(31), 1586 {e_regSetVFP, vfp_fpsr, "fpsr", NULL, Uint, Hex, 4, 1587 VFP_V_OFFSET_IDX(32) + 0, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1588 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}, 1589 {e_regSetVFP, vfp_fpcr, "fpcr", NULL, Uint, Hex, 4, 1590 VFP_V_OFFSET_IDX(32) + 4, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1591 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}, 1592 1593 DEFINE_PSEUDO_VFP_S_IDX(0), 1594 DEFINE_PSEUDO_VFP_S_IDX(1), 1595 DEFINE_PSEUDO_VFP_S_IDX(2), 1596 DEFINE_PSEUDO_VFP_S_IDX(3), 1597 DEFINE_PSEUDO_VFP_S_IDX(4), 1598 DEFINE_PSEUDO_VFP_S_IDX(5), 1599 DEFINE_PSEUDO_VFP_S_IDX(6), 1600 DEFINE_PSEUDO_VFP_S_IDX(7), 1601 DEFINE_PSEUDO_VFP_S_IDX(8), 1602 DEFINE_PSEUDO_VFP_S_IDX(9), 1603 DEFINE_PSEUDO_VFP_S_IDX(10), 1604 DEFINE_PSEUDO_VFP_S_IDX(11), 1605 DEFINE_PSEUDO_VFP_S_IDX(12), 1606 DEFINE_PSEUDO_VFP_S_IDX(13), 1607 DEFINE_PSEUDO_VFP_S_IDX(14), 1608 DEFINE_PSEUDO_VFP_S_IDX(15), 1609 DEFINE_PSEUDO_VFP_S_IDX(16), 1610 DEFINE_PSEUDO_VFP_S_IDX(17), 1611 DEFINE_PSEUDO_VFP_S_IDX(18), 1612 DEFINE_PSEUDO_VFP_S_IDX(19), 1613 DEFINE_PSEUDO_VFP_S_IDX(20), 1614 DEFINE_PSEUDO_VFP_S_IDX(21), 1615 DEFINE_PSEUDO_VFP_S_IDX(22), 1616 DEFINE_PSEUDO_VFP_S_IDX(23), 1617 DEFINE_PSEUDO_VFP_S_IDX(24), 1618 DEFINE_PSEUDO_VFP_S_IDX(25), 1619 DEFINE_PSEUDO_VFP_S_IDX(26), 1620 DEFINE_PSEUDO_VFP_S_IDX(27), 1621 DEFINE_PSEUDO_VFP_S_IDX(28), 1622 DEFINE_PSEUDO_VFP_S_IDX(29), 1623 DEFINE_PSEUDO_VFP_S_IDX(30), 1624 DEFINE_PSEUDO_VFP_S_IDX(31), 1625 1626 DEFINE_PSEUDO_VFP_D_IDX(0), 1627 DEFINE_PSEUDO_VFP_D_IDX(1), 1628 DEFINE_PSEUDO_VFP_D_IDX(2), 1629 DEFINE_PSEUDO_VFP_D_IDX(3), 1630 DEFINE_PSEUDO_VFP_D_IDX(4), 1631 DEFINE_PSEUDO_VFP_D_IDX(5), 1632 DEFINE_PSEUDO_VFP_D_IDX(6), 1633 DEFINE_PSEUDO_VFP_D_IDX(7), 1634 DEFINE_PSEUDO_VFP_D_IDX(8), 1635 DEFINE_PSEUDO_VFP_D_IDX(9), 1636 DEFINE_PSEUDO_VFP_D_IDX(10), 1637 DEFINE_PSEUDO_VFP_D_IDX(11), 1638 DEFINE_PSEUDO_VFP_D_IDX(12), 1639 DEFINE_PSEUDO_VFP_D_IDX(13), 1640 DEFINE_PSEUDO_VFP_D_IDX(14), 1641 DEFINE_PSEUDO_VFP_D_IDX(15), 1642 DEFINE_PSEUDO_VFP_D_IDX(16), 1643 DEFINE_PSEUDO_VFP_D_IDX(17), 1644 DEFINE_PSEUDO_VFP_D_IDX(18), 1645 DEFINE_PSEUDO_VFP_D_IDX(19), 1646 DEFINE_PSEUDO_VFP_D_IDX(20), 1647 DEFINE_PSEUDO_VFP_D_IDX(21), 1648 DEFINE_PSEUDO_VFP_D_IDX(22), 1649 DEFINE_PSEUDO_VFP_D_IDX(23), 1650 DEFINE_PSEUDO_VFP_D_IDX(24), 1651 DEFINE_PSEUDO_VFP_D_IDX(25), 1652 DEFINE_PSEUDO_VFP_D_IDX(26), 1653 DEFINE_PSEUDO_VFP_D_IDX(27), 1654 DEFINE_PSEUDO_VFP_D_IDX(28), 1655 DEFINE_PSEUDO_VFP_D_IDX(29), 1656 DEFINE_PSEUDO_VFP_D_IDX(30), 1657 DEFINE_PSEUDO_VFP_D_IDX(31) 1658 1659 }; 1660 1661 //_STRUCT_ARM_EXCEPTION_STATE64 1662 //{ 1663 // uint64_t far; /* Virtual Fault Address */ 1664 // uint32_t esr; /* Exception syndrome */ 1665 // uint32_t exception; /* number of arm exception taken */ 1666 //}; 1667 1668 // Exception registers 1669 const DNBRegisterInfo DNBArchMachARM64::g_exc_registers[] = { 1670 {e_regSetEXC, exc_far, "far", NULL, Uint, Hex, 8, EXC_OFFSET(__far), 1671 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1672 INVALID_NUB_REGNUM, NULL, NULL}, 1673 {e_regSetEXC, exc_esr, "esr", NULL, Uint, Hex, 4, EXC_OFFSET(__esr), 1674 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1675 INVALID_NUB_REGNUM, NULL, NULL}, 1676 {e_regSetEXC, exc_exception, "exception", NULL, Uint, Hex, 4, 1677 EXC_OFFSET(__exception), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1678 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}}; 1679 1680 // Number of registers in each register set 1681 const size_t DNBArchMachARM64::k_num_gpr_registers = 1682 sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo); 1683 const size_t DNBArchMachARM64::k_num_vfp_registers = 1684 sizeof(g_vfp_registers) / sizeof(DNBRegisterInfo); 1685 const size_t DNBArchMachARM64::k_num_exc_registers = 1686 sizeof(g_exc_registers) / sizeof(DNBRegisterInfo); 1687 const size_t DNBArchMachARM64::k_num_all_registers = 1688 k_num_gpr_registers + k_num_vfp_registers + k_num_exc_registers; 1689 1690 // Register set definitions. The first definitions at register set index 1691 // of zero is for all registers, followed by other registers sets. The 1692 // register information for the all register set need not be filled in. 1693 const DNBRegisterSetInfo DNBArchMachARM64::g_reg_sets[] = { 1694 {"ARM64 Registers", NULL, k_num_all_registers}, 1695 {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers}, 1696 {"Floating Point Registers", g_vfp_registers, k_num_vfp_registers}, 1697 {"Exception State Registers", g_exc_registers, k_num_exc_registers}}; 1698 // Total number of register sets for this architecture 1699 const size_t DNBArchMachARM64::k_num_register_sets = 1700 sizeof(g_reg_sets) / sizeof(DNBRegisterSetInfo); 1701 1702 const DNBRegisterSetInfo * 1703 DNBArchMachARM64::GetRegisterSetInfo(nub_size_t *num_reg_sets) { 1704 *num_reg_sets = k_num_register_sets; 1705 return g_reg_sets; 1706 } 1707 1708 bool DNBArchMachARM64::FixGenericRegisterNumber(uint32_t &set, uint32_t ®) { 1709 if (set == REGISTER_SET_GENERIC) { 1710 switch (reg) { 1711 case GENERIC_REGNUM_PC: // Program Counter 1712 set = e_regSetGPR; 1713 reg = gpr_pc; 1714 break; 1715 1716 case GENERIC_REGNUM_SP: // Stack Pointer 1717 set = e_regSetGPR; 1718 reg = gpr_sp; 1719 break; 1720 1721 case GENERIC_REGNUM_FP: // Frame Pointer 1722 set = e_regSetGPR; 1723 reg = gpr_fp; 1724 break; 1725 1726 case GENERIC_REGNUM_RA: // Return Address 1727 set = e_regSetGPR; 1728 reg = gpr_lr; 1729 break; 1730 1731 case GENERIC_REGNUM_FLAGS: // Processor flags register 1732 set = e_regSetGPR; 1733 reg = gpr_cpsr; 1734 break; 1735 1736 case GENERIC_REGNUM_ARG1: 1737 case GENERIC_REGNUM_ARG2: 1738 case GENERIC_REGNUM_ARG3: 1739 case GENERIC_REGNUM_ARG4: 1740 case GENERIC_REGNUM_ARG5: 1741 case GENERIC_REGNUM_ARG6: 1742 set = e_regSetGPR; 1743 reg = gpr_x0 + reg - GENERIC_REGNUM_ARG1; 1744 break; 1745 1746 default: 1747 return false; 1748 } 1749 } 1750 return true; 1751 } 1752 bool DNBArchMachARM64::GetRegisterValue(uint32_t set, uint32_t reg, 1753 DNBRegisterValue *value) { 1754 if (!FixGenericRegisterNumber(set, reg)) 1755 return false; 1756 1757 if (GetRegisterState(set, false) != KERN_SUCCESS) 1758 return false; 1759 1760 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1761 if (regInfo) { 1762 value->info = *regInfo; 1763 switch (set) { 1764 case e_regSetGPR: 1765 if (reg <= gpr_pc) { 1766 value->value.uint64 = m_state.context.gpr.__x[reg]; 1767 return true; 1768 } else if (reg == gpr_cpsr) { 1769 value->value.uint32 = m_state.context.gpr.__cpsr; 1770 return true; 1771 } 1772 break; 1773 1774 case e_regSetVFP: 1775 1776 if (reg >= vfp_v0 && reg <= vfp_v31) { 1777 #if defined(__arm64__) || defined(__aarch64__) 1778 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_v0], 1779 16); 1780 #else 1781 memcpy(&value->value.v_uint8, 1782 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), 1783 16); 1784 #endif 1785 return true; 1786 } else if (reg == vfp_fpsr) { 1787 #if defined(__arm64__) || defined(__aarch64__) 1788 memcpy(&value->value.uint32, &m_state.context.vfp.__fpsr, 4); 1789 #else 1790 memcpy(&value->value.uint32, 1791 ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0, 4); 1792 #endif 1793 return true; 1794 } else if (reg == vfp_fpcr) { 1795 #if defined(__arm64__) || defined(__aarch64__) 1796 memcpy(&value->value.uint32, &m_state.context.vfp.__fpcr, 4); 1797 #else 1798 memcpy(&value->value.uint32, 1799 ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 4, 4); 1800 #endif 1801 return true; 1802 } else if (reg >= vfp_s0 && reg <= vfp_s31) { 1803 #if defined(__arm64__) || defined(__aarch64__) 1804 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_s0], 1805 4); 1806 #else 1807 memcpy(&value->value.v_uint8, 1808 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), 1809 4); 1810 #endif 1811 return true; 1812 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 1813 #if defined(__arm64__) || defined(__aarch64__) 1814 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_d0], 1815 8); 1816 #else 1817 memcpy(&value->value.v_uint8, 1818 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), 1819 8); 1820 #endif 1821 return true; 1822 } 1823 break; 1824 1825 case e_regSetEXC: 1826 if (reg == exc_far) { 1827 value->value.uint64 = m_state.context.exc.__far; 1828 return true; 1829 } else if (reg == exc_esr) { 1830 value->value.uint32 = m_state.context.exc.__esr; 1831 return true; 1832 } else if (reg == exc_exception) { 1833 value->value.uint32 = m_state.context.exc.__exception; 1834 return true; 1835 } 1836 break; 1837 } 1838 } 1839 return false; 1840 } 1841 1842 bool DNBArchMachARM64::SetRegisterValue(uint32_t set, uint32_t reg, 1843 const DNBRegisterValue *value) { 1844 if (!FixGenericRegisterNumber(set, reg)) 1845 return false; 1846 1847 if (GetRegisterState(set, false) != KERN_SUCCESS) 1848 return false; 1849 1850 bool success = false; 1851 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1852 if (regInfo) { 1853 switch (set) { 1854 case e_regSetGPR: 1855 if (reg <= gpr_pc) { 1856 m_state.context.gpr.__x[reg] = value->value.uint64; 1857 success = true; 1858 } else if (reg == gpr_cpsr) { 1859 m_state.context.gpr.__cpsr = value->value.uint32; 1860 success = true; 1861 } 1862 break; 1863 1864 case e_regSetVFP: 1865 if (reg >= vfp_v0 && reg <= vfp_v31) { 1866 #if defined(__arm64__) || defined(__aarch64__) 1867 memcpy(&m_state.context.vfp.__v[reg - vfp_v0], &value->value.v_uint8, 1868 16); 1869 #else 1870 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), 1871 &value->value.v_uint8, 16); 1872 #endif 1873 success = true; 1874 } else if (reg == vfp_fpsr) { 1875 #if defined(__arm64__) || defined(__aarch64__) 1876 memcpy(&m_state.context.vfp.__fpsr, &value->value.uint32, 4); 1877 #else 1878 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0, 1879 &value->value.uint32, 4); 1880 #endif 1881 success = true; 1882 } else if (reg == vfp_fpcr) { 1883 #if defined(__arm64__) || defined(__aarch64__) 1884 memcpy(&m_state.context.vfp.__fpcr, &value->value.uint32, 4); 1885 #else 1886 memcpy(((uint8_t *)m_state.context.vfp.opaque) + (32 * 16) + 4, 1887 &value->value.uint32, 4); 1888 #endif 1889 success = true; 1890 } else if (reg >= vfp_s0 && reg <= vfp_s31) { 1891 #if defined(__arm64__) || defined(__aarch64__) 1892 memcpy(&m_state.context.vfp.__v[reg - vfp_s0], &value->value.v_uint8, 1893 4); 1894 #else 1895 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), 1896 &value->value.v_uint8, 4); 1897 #endif 1898 success = true; 1899 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 1900 #if defined(__arm64__) || defined(__aarch64__) 1901 memcpy(&m_state.context.vfp.__v[reg - vfp_d0], &value->value.v_uint8, 1902 8); 1903 #else 1904 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), 1905 &value->value.v_uint8, 8); 1906 #endif 1907 success = true; 1908 } 1909 break; 1910 1911 case e_regSetEXC: 1912 if (reg == exc_far) { 1913 m_state.context.exc.__far = value->value.uint64; 1914 success = true; 1915 } else if (reg == exc_esr) { 1916 m_state.context.exc.__esr = value->value.uint32; 1917 success = true; 1918 } else if (reg == exc_exception) { 1919 m_state.context.exc.__exception = value->value.uint32; 1920 success = true; 1921 } 1922 break; 1923 } 1924 } 1925 if (success) 1926 return SetRegisterState(set) == KERN_SUCCESS; 1927 return false; 1928 } 1929 1930 kern_return_t DNBArchMachARM64::GetRegisterState(int set, bool force) { 1931 switch (set) { 1932 case e_regSetALL: 1933 return GetGPRState(force) | GetVFPState(force) | GetEXCState(force) | 1934 GetDBGState(force); 1935 case e_regSetGPR: 1936 return GetGPRState(force); 1937 case e_regSetVFP: 1938 return GetVFPState(force); 1939 case e_regSetEXC: 1940 return GetEXCState(force); 1941 case e_regSetDBG: 1942 return GetDBGState(force); 1943 default: 1944 break; 1945 } 1946 return KERN_INVALID_ARGUMENT; 1947 } 1948 1949 kern_return_t DNBArchMachARM64::SetRegisterState(int set) { 1950 // Make sure we have a valid context to set. 1951 kern_return_t err = GetRegisterState(set, false); 1952 if (err != KERN_SUCCESS) 1953 return err; 1954 1955 switch (set) { 1956 case e_regSetALL: 1957 return SetGPRState() | SetVFPState() | SetEXCState() | SetDBGState(false); 1958 case e_regSetGPR: 1959 return SetGPRState(); 1960 case e_regSetVFP: 1961 return SetVFPState(); 1962 case e_regSetEXC: 1963 return SetEXCState(); 1964 case e_regSetDBG: 1965 return SetDBGState(false); 1966 default: 1967 break; 1968 } 1969 return KERN_INVALID_ARGUMENT; 1970 } 1971 1972 bool DNBArchMachARM64::RegisterSetStateIsValid(int set) const { 1973 return m_state.RegsAreValid(set); 1974 } 1975 1976 nub_size_t DNBArchMachARM64::GetRegisterContext(void *buf, nub_size_t buf_len) { 1977 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 1978 sizeof(m_state.context.exc); 1979 1980 if (buf && buf_len) { 1981 if (size > buf_len) 1982 size = buf_len; 1983 1984 bool force = false; 1985 if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force)) 1986 return 0; 1987 1988 // Copy each struct individually to avoid any padding that might be between 1989 // the structs in m_state.context 1990 uint8_t *p = (uint8_t *)buf; 1991 ::memcpy(p, &m_state.context.gpr, sizeof(m_state.context.gpr)); 1992 p += sizeof(m_state.context.gpr); 1993 ::memcpy(p, &m_state.context.vfp, sizeof(m_state.context.vfp)); 1994 p += sizeof(m_state.context.vfp); 1995 ::memcpy(p, &m_state.context.exc, sizeof(m_state.context.exc)); 1996 p += sizeof(m_state.context.exc); 1997 1998 size_t bytes_written = p - (uint8_t *)buf; 1999 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2000 assert(bytes_written == size); 2001 } 2002 DNBLogThreadedIf( 2003 LOG_THREAD, 2004 "DNBArchMachARM64::GetRegisterContext (buf = %p, len = %zu) => %zu", buf, 2005 buf_len, size); 2006 // Return the size of the register context even if NULL was passed in 2007 return size; 2008 } 2009 2010 nub_size_t DNBArchMachARM64::SetRegisterContext(const void *buf, 2011 nub_size_t buf_len) { 2012 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 2013 sizeof(m_state.context.exc); 2014 2015 if (buf == NULL || buf_len == 0) 2016 size = 0; 2017 2018 if (size) { 2019 if (size > buf_len) 2020 size = buf_len; 2021 2022 // Copy each struct individually to avoid any padding that might be between 2023 // the structs in m_state.context 2024 uint8_t *p = (uint8_t *)buf; 2025 ::memcpy(&m_state.context.gpr, p, sizeof(m_state.context.gpr)); 2026 p += sizeof(m_state.context.gpr); 2027 ::memcpy(&m_state.context.vfp, p, sizeof(m_state.context.vfp)); 2028 p += sizeof(m_state.context.vfp); 2029 ::memcpy(&m_state.context.exc, p, sizeof(m_state.context.exc)); 2030 p += sizeof(m_state.context.exc); 2031 2032 size_t bytes_written = p - (uint8_t *)buf; 2033 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2034 assert(bytes_written == size); 2035 SetGPRState(); 2036 SetVFPState(); 2037 SetEXCState(); 2038 } 2039 DNBLogThreadedIf( 2040 LOG_THREAD, 2041 "DNBArchMachARM64::SetRegisterContext (buf = %p, len = %zu) => %zu", buf, 2042 buf_len, size); 2043 return size; 2044 } 2045 2046 uint32_t DNBArchMachARM64::SaveRegisterState() { 2047 kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber()); 2048 DNBLogThreadedIf( 2049 LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u " 2050 "(SetGPRState() for stop_count = %u)", 2051 m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount()); 2052 2053 // Always re-read the registers because above we call thread_abort_safely(); 2054 bool force = true; 2055 2056 if ((kret = GetGPRState(force)) != KERN_SUCCESS) { 2057 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () " 2058 "error: GPR regs failed to read: %u ", 2059 kret); 2060 } else if ((kret = GetVFPState(force)) != KERN_SUCCESS) { 2061 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () " 2062 "error: %s regs failed to read: %u", 2063 "VFP", kret); 2064 } else { 2065 const uint32_t save_id = GetNextRegisterStateSaveID(); 2066 m_saved_register_states[save_id] = m_state.context; 2067 return save_id; 2068 } 2069 return UINT32_MAX; 2070 } 2071 2072 bool DNBArchMachARM64::RestoreRegisterState(uint32_t save_id) { 2073 SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id); 2074 if (pos != m_saved_register_states.end()) { 2075 m_state.context.gpr = pos->second.gpr; 2076 m_state.context.vfp = pos->second.vfp; 2077 kern_return_t kret; 2078 bool success = true; 2079 if ((kret = SetGPRState()) != KERN_SUCCESS) { 2080 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState " 2081 "(save_id = %u) error: GPR regs failed to " 2082 "write: %u", 2083 save_id, kret); 2084 success = false; 2085 } else if ((kret = SetVFPState()) != KERN_SUCCESS) { 2086 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState " 2087 "(save_id = %u) error: %s regs failed to " 2088 "write: %u", 2089 save_id, "VFP", kret); 2090 success = false; 2091 } 2092 m_saved_register_states.erase(pos); 2093 return success; 2094 } 2095 return false; 2096 } 2097 2098 #endif // #if defined (ARM_THREAD_STATE64_COUNT) 2099 #endif // #if defined (__arm__) || defined (__arm64__) || defined (__aarch64__) 2100