1 //===-- DNBArchImplARM64.cpp ------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Created by Greg Clayton on 6/25/07. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #if defined(__arm__) || defined(__arm64__) || defined(__aarch64__) 14 15 #include "MacOSX/arm64/DNBArchImplARM64.h" 16 17 #if defined(ARM_THREAD_STATE64_COUNT) 18 19 #include "DNB.h" 20 #include "DNBBreakpoint.h" 21 #include "DNBLog.h" 22 #include "DNBRegisterInfo.h" 23 #include "MacOSX/MachProcess.h" 24 #include "MacOSX/MachThread.h" 25 26 #include <inttypes.h> 27 #include <sys/sysctl.h> 28 29 #if __has_feature(ptrauth_calls) 30 #include <ptrauth.h> 31 #endif 32 33 // Break only in privileged or user mode 34 // (PAC bits in the DBGWVRn_EL1 watchpoint control register) 35 #define S_USER ((uint32_t)(2u << 1)) 36 37 #define BCR_ENABLE ((uint32_t)(1u)) 38 #define WCR_ENABLE ((uint32_t)(1u)) 39 40 // Watchpoint load/store 41 // (LSC bits in the DBGWVRn_EL1 watchpoint control register) 42 #define WCR_LOAD ((uint32_t)(1u << 3)) 43 #define WCR_STORE ((uint32_t)(1u << 4)) 44 45 // Enable breakpoint, watchpoint, and vector catch debug exceptions. 46 // (MDE bit in the MDSCR_EL1 register. Equivalent to the MDBGen bit in 47 // DBGDSCRext in Aarch32) 48 #define MDE_ENABLE ((uint32_t)(1u << 15)) 49 50 // Single instruction step 51 // (SS bit in the MDSCR_EL1 register) 52 #define SS_ENABLE ((uint32_t)(1u)) 53 54 static const uint8_t g_arm64_breakpoint_opcode[] = { 55 0x00, 0x00, 0x20, 0xD4}; // "brk #0", 0xd4200000 in BE byte order 56 57 // If we need to set one logical watchpoint by using 58 // two hardware watchpoint registers, the watchpoint 59 // will be split into a "high" and "low" watchpoint. 60 // Record both of them in the LoHi array. 61 62 // It's safe to initialize to all 0's since 63 // hi > lo and therefore LoHi[i] cannot be 0. 64 static uint32_t LoHi[16] = {0}; 65 66 void DNBArchMachARM64::Initialize() { 67 DNBArchPluginInfo arch_plugin_info = { 68 CPU_TYPE_ARM64, DNBArchMachARM64::Create, 69 DNBArchMachARM64::GetRegisterSetInfo, 70 DNBArchMachARM64::SoftwareBreakpointOpcode}; 71 72 // Register this arch plug-in with the main protocol class 73 DNBArchProtocol::RegisterArchPlugin(arch_plugin_info); 74 75 DNBArchPluginInfo arch_plugin_info_32 = { 76 CPU_TYPE_ARM64_32, DNBArchMachARM64::Create, 77 DNBArchMachARM64::GetRegisterSetInfo, 78 DNBArchMachARM64::SoftwareBreakpointOpcode}; 79 80 // Register this arch plug-in with the main protocol class 81 DNBArchProtocol::RegisterArchPlugin(arch_plugin_info_32); 82 } 83 84 DNBArchProtocol *DNBArchMachARM64::Create(MachThread *thread) { 85 DNBArchMachARM64 *obj = new DNBArchMachARM64(thread); 86 87 return obj; 88 } 89 90 const uint8_t * 91 DNBArchMachARM64::SoftwareBreakpointOpcode(nub_size_t byte_size) { 92 return g_arm64_breakpoint_opcode; 93 } 94 95 uint32_t DNBArchMachARM64::GetCPUType() { return CPU_TYPE_ARM64; } 96 97 uint64_t DNBArchMachARM64::GetPC(uint64_t failValue) { 98 // Get program counter 99 if (GetGPRState(false) == KERN_SUCCESS) 100 #if defined(__LP64__) 101 return arm_thread_state64_get_pc(m_state.context.gpr); 102 #else 103 return m_state.context.gpr.__pc; 104 #endif 105 return failValue; 106 } 107 108 kern_return_t DNBArchMachARM64::SetPC(uint64_t value) { 109 // Get program counter 110 kern_return_t err = GetGPRState(false); 111 if (err == KERN_SUCCESS) { 112 #if defined(__LP64__) 113 #if __has_feature(ptrauth_calls) 114 // The incoming value could be garbage. Strip it to avoid 115 // trapping when it gets resigned in the thread state. 116 value = (uint64_t) ptrauth_strip((void*) value, ptrauth_key_function_pointer); 117 value = (uint64_t) ptrauth_sign_unauthenticated((void*) value, ptrauth_key_function_pointer, 0); 118 #endif 119 arm_thread_state64_set_pc_fptr (m_state.context.gpr, (void*) value); 120 #else 121 m_state.context.gpr.__pc = value; 122 #endif 123 err = SetGPRState(); 124 } 125 return err == KERN_SUCCESS; 126 } 127 128 uint64_t DNBArchMachARM64::GetSP(uint64_t failValue) { 129 // Get stack pointer 130 if (GetGPRState(false) == KERN_SUCCESS) 131 #if defined(__LP64__) 132 return arm_thread_state64_get_sp(m_state.context.gpr); 133 #else 134 return m_state.context.gpr.__sp; 135 #endif 136 return failValue; 137 } 138 139 kern_return_t DNBArchMachARM64::GetGPRState(bool force) { 140 int set = e_regSetGPR; 141 // Check if we have valid cached registers 142 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 143 return KERN_SUCCESS; 144 145 // Read the registers from our thread 146 mach_msg_type_number_t count = e_regSetGPRCount; 147 kern_return_t kret = 148 ::thread_get_state(m_thread->MachPortNumber(), ARM_THREAD_STATE64, 149 (thread_state_t)&m_state.context.gpr, &count); 150 if (DNBLogEnabledForAny(LOG_THREAD)) { 151 uint64_t *x = &m_state.context.gpr.__x[0]; 152 DNBLogThreaded( 153 "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count = %u) regs" 154 "\n x0=%16.16llx" 155 "\n x1=%16.16llx" 156 "\n x2=%16.16llx" 157 "\n x3=%16.16llx" 158 "\n x4=%16.16llx" 159 "\n x5=%16.16llx" 160 "\n x6=%16.16llx" 161 "\n x7=%16.16llx" 162 "\n x8=%16.16llx" 163 "\n x9=%16.16llx" 164 "\n x10=%16.16llx" 165 "\n x11=%16.16llx" 166 "\n x12=%16.16llx" 167 "\n x13=%16.16llx" 168 "\n x14=%16.16llx" 169 "\n x15=%16.16llx" 170 "\n x16=%16.16llx" 171 "\n x17=%16.16llx" 172 "\n x18=%16.16llx" 173 "\n x19=%16.16llx" 174 "\n x20=%16.16llx" 175 "\n x21=%16.16llx" 176 "\n x22=%16.16llx" 177 "\n x23=%16.16llx" 178 "\n x24=%16.16llx" 179 "\n x25=%16.16llx" 180 "\n x26=%16.16llx" 181 "\n x27=%16.16llx" 182 "\n x28=%16.16llx" 183 "\n fp=%16.16llx" 184 "\n lr=%16.16llx" 185 "\n sp=%16.16llx" 186 "\n pc=%16.16llx" 187 "\n cpsr=%8.8x", 188 m_thread->MachPortNumber(), e_regSetGPR, e_regSetGPRCount, kret, count, 189 x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[0], x[11], 190 x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], x[20], x[21], 191 x[22], x[23], x[24], x[25], x[26], x[27], x[28], 192 #if defined(__LP64__) 193 (uint64_t) arm_thread_state64_get_fp (m_state.context.gpr), 194 (uint64_t) arm_thread_state64_get_lr (m_state.context.gpr), 195 (uint64_t) arm_thread_state64_get_sp (m_state.context.gpr), 196 (uint64_t) arm_thread_state64_get_pc (m_state.context.gpr), 197 #else 198 m_state.context.gpr.__fp, m_state.context.gpr.__lr, 199 m_state.context.gpr.__sp, m_state.context.gpr.__pc, 200 #endif 201 m_state.context.gpr.__cpsr); 202 } 203 m_state.SetError(set, Read, kret); 204 return kret; 205 } 206 207 kern_return_t DNBArchMachARM64::GetVFPState(bool force) { 208 int set = e_regSetVFP; 209 // Check if we have valid cached registers 210 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 211 return KERN_SUCCESS; 212 213 // Read the registers from our thread 214 mach_msg_type_number_t count = e_regSetVFPCount; 215 kern_return_t kret = 216 ::thread_get_state(m_thread->MachPortNumber(), ARM_NEON_STATE64, 217 (thread_state_t)&m_state.context.vfp, &count); 218 if (DNBLogEnabledForAny(LOG_THREAD)) { 219 #if defined(__arm64__) || defined(__aarch64__) 220 DNBLogThreaded( 221 "thread_get_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs" 222 "\n q0 = 0x%16.16llx%16.16llx" 223 "\n q1 = 0x%16.16llx%16.16llx" 224 "\n q2 = 0x%16.16llx%16.16llx" 225 "\n q3 = 0x%16.16llx%16.16llx" 226 "\n q4 = 0x%16.16llx%16.16llx" 227 "\n q5 = 0x%16.16llx%16.16llx" 228 "\n q6 = 0x%16.16llx%16.16llx" 229 "\n q7 = 0x%16.16llx%16.16llx" 230 "\n q8 = 0x%16.16llx%16.16llx" 231 "\n q9 = 0x%16.16llx%16.16llx" 232 "\n q10 = 0x%16.16llx%16.16llx" 233 "\n q11 = 0x%16.16llx%16.16llx" 234 "\n q12 = 0x%16.16llx%16.16llx" 235 "\n q13 = 0x%16.16llx%16.16llx" 236 "\n q14 = 0x%16.16llx%16.16llx" 237 "\n q15 = 0x%16.16llx%16.16llx" 238 "\n q16 = 0x%16.16llx%16.16llx" 239 "\n q17 = 0x%16.16llx%16.16llx" 240 "\n q18 = 0x%16.16llx%16.16llx" 241 "\n q19 = 0x%16.16llx%16.16llx" 242 "\n q20 = 0x%16.16llx%16.16llx" 243 "\n q21 = 0x%16.16llx%16.16llx" 244 "\n q22 = 0x%16.16llx%16.16llx" 245 "\n q23 = 0x%16.16llx%16.16llx" 246 "\n q24 = 0x%16.16llx%16.16llx" 247 "\n q25 = 0x%16.16llx%16.16llx" 248 "\n q26 = 0x%16.16llx%16.16llx" 249 "\n q27 = 0x%16.16llx%16.16llx" 250 "\n q28 = 0x%16.16llx%16.16llx" 251 "\n q29 = 0x%16.16llx%16.16llx" 252 "\n q30 = 0x%16.16llx%16.16llx" 253 "\n q31 = 0x%16.16llx%16.16llx" 254 "\n fpsr = 0x%8.8x" 255 "\n fpcr = 0x%8.8x\n\n", 256 m_thread->MachPortNumber(), e_regSetVFP, e_regSetVFPCount, kret, count, 257 ((uint64_t *)&m_state.context.vfp.__v[0])[0], 258 ((uint64_t *)&m_state.context.vfp.__v[0])[1], 259 ((uint64_t *)&m_state.context.vfp.__v[1])[0], 260 ((uint64_t *)&m_state.context.vfp.__v[1])[1], 261 ((uint64_t *)&m_state.context.vfp.__v[2])[0], 262 ((uint64_t *)&m_state.context.vfp.__v[2])[1], 263 ((uint64_t *)&m_state.context.vfp.__v[3])[0], 264 ((uint64_t *)&m_state.context.vfp.__v[3])[1], 265 ((uint64_t *)&m_state.context.vfp.__v[4])[0], 266 ((uint64_t *)&m_state.context.vfp.__v[4])[1], 267 ((uint64_t *)&m_state.context.vfp.__v[5])[0], 268 ((uint64_t *)&m_state.context.vfp.__v[5])[1], 269 ((uint64_t *)&m_state.context.vfp.__v[6])[0], 270 ((uint64_t *)&m_state.context.vfp.__v[6])[1], 271 ((uint64_t *)&m_state.context.vfp.__v[7])[0], 272 ((uint64_t *)&m_state.context.vfp.__v[7])[1], 273 ((uint64_t *)&m_state.context.vfp.__v[8])[0], 274 ((uint64_t *)&m_state.context.vfp.__v[8])[1], 275 ((uint64_t *)&m_state.context.vfp.__v[9])[0], 276 ((uint64_t *)&m_state.context.vfp.__v[9])[1], 277 ((uint64_t *)&m_state.context.vfp.__v[10])[0], 278 ((uint64_t *)&m_state.context.vfp.__v[10])[1], 279 ((uint64_t *)&m_state.context.vfp.__v[11])[0], 280 ((uint64_t *)&m_state.context.vfp.__v[11])[1], 281 ((uint64_t *)&m_state.context.vfp.__v[12])[0], 282 ((uint64_t *)&m_state.context.vfp.__v[12])[1], 283 ((uint64_t *)&m_state.context.vfp.__v[13])[0], 284 ((uint64_t *)&m_state.context.vfp.__v[13])[1], 285 ((uint64_t *)&m_state.context.vfp.__v[14])[0], 286 ((uint64_t *)&m_state.context.vfp.__v[14])[1], 287 ((uint64_t *)&m_state.context.vfp.__v[15])[0], 288 ((uint64_t *)&m_state.context.vfp.__v[15])[1], 289 ((uint64_t *)&m_state.context.vfp.__v[16])[0], 290 ((uint64_t *)&m_state.context.vfp.__v[16])[1], 291 ((uint64_t *)&m_state.context.vfp.__v[17])[0], 292 ((uint64_t *)&m_state.context.vfp.__v[17])[1], 293 ((uint64_t *)&m_state.context.vfp.__v[18])[0], 294 ((uint64_t *)&m_state.context.vfp.__v[18])[1], 295 ((uint64_t *)&m_state.context.vfp.__v[19])[0], 296 ((uint64_t *)&m_state.context.vfp.__v[19])[1], 297 ((uint64_t *)&m_state.context.vfp.__v[20])[0], 298 ((uint64_t *)&m_state.context.vfp.__v[20])[1], 299 ((uint64_t *)&m_state.context.vfp.__v[21])[0], 300 ((uint64_t *)&m_state.context.vfp.__v[21])[1], 301 ((uint64_t *)&m_state.context.vfp.__v[22])[0], 302 ((uint64_t *)&m_state.context.vfp.__v[22])[1], 303 ((uint64_t *)&m_state.context.vfp.__v[23])[0], 304 ((uint64_t *)&m_state.context.vfp.__v[23])[1], 305 ((uint64_t *)&m_state.context.vfp.__v[24])[0], 306 ((uint64_t *)&m_state.context.vfp.__v[24])[1], 307 ((uint64_t *)&m_state.context.vfp.__v[25])[0], 308 ((uint64_t *)&m_state.context.vfp.__v[25])[1], 309 ((uint64_t *)&m_state.context.vfp.__v[26])[0], 310 ((uint64_t *)&m_state.context.vfp.__v[26])[1], 311 ((uint64_t *)&m_state.context.vfp.__v[27])[0], 312 ((uint64_t *)&m_state.context.vfp.__v[27])[1], 313 ((uint64_t *)&m_state.context.vfp.__v[28])[0], 314 ((uint64_t *)&m_state.context.vfp.__v[28])[1], 315 ((uint64_t *)&m_state.context.vfp.__v[29])[0], 316 ((uint64_t *)&m_state.context.vfp.__v[29])[1], 317 ((uint64_t *)&m_state.context.vfp.__v[30])[0], 318 ((uint64_t *)&m_state.context.vfp.__v[30])[1], 319 ((uint64_t *)&m_state.context.vfp.__v[31])[0], 320 ((uint64_t *)&m_state.context.vfp.__v[31])[1], 321 m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr); 322 #endif 323 } 324 m_state.SetError(set, Read, kret); 325 return kret; 326 } 327 328 kern_return_t DNBArchMachARM64::GetEXCState(bool force) { 329 int set = e_regSetEXC; 330 // Check if we have valid cached registers 331 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 332 return KERN_SUCCESS; 333 334 // Read the registers from our thread 335 mach_msg_type_number_t count = e_regSetEXCCount; 336 kern_return_t kret = 337 ::thread_get_state(m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, 338 (thread_state_t)&m_state.context.exc, &count); 339 m_state.SetError(set, Read, kret); 340 return kret; 341 } 342 343 static void DumpDBGState(const arm_debug_state_t &dbg) { 344 uint32_t i = 0; 345 for (i = 0; i < 16; i++) 346 DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } " 347 "WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }", 348 i, i, dbg.__bvr[i], dbg.__bcr[i], i, i, dbg.__wvr[i], 349 dbg.__wcr[i]); 350 } 351 352 kern_return_t DNBArchMachARM64::GetDBGState(bool force) { 353 int set = e_regSetDBG; 354 355 // Check if we have valid cached registers 356 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 357 return KERN_SUCCESS; 358 359 // Read the registers from our thread 360 mach_msg_type_number_t count = e_regSetDBGCount; 361 kern_return_t kret = 362 ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64, 363 (thread_state_t)&m_state.dbg, &count); 364 m_state.SetError(set, Read, kret); 365 366 return kret; 367 } 368 369 kern_return_t DNBArchMachARM64::SetGPRState() { 370 int set = e_regSetGPR; 371 kern_return_t kret = ::thread_set_state( 372 m_thread->MachPortNumber(), ARM_THREAD_STATE64, 373 (thread_state_t)&m_state.context.gpr, e_regSetGPRCount); 374 m_state.SetError(set, Write, 375 kret); // Set the current write error for this register set 376 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 377 // state in case registers are read 378 // back differently 379 return kret; // Return the error code 380 } 381 382 kern_return_t DNBArchMachARM64::SetVFPState() { 383 int set = e_regSetVFP; 384 kern_return_t kret = ::thread_set_state( 385 m_thread->MachPortNumber(), ARM_NEON_STATE64, 386 (thread_state_t)&m_state.context.vfp, e_regSetVFPCount); 387 m_state.SetError(set, Write, 388 kret); // Set the current write error for this register set 389 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 390 // state in case registers are read 391 // back differently 392 return kret; // Return the error code 393 } 394 395 kern_return_t DNBArchMachARM64::SetEXCState() { 396 int set = e_regSetEXC; 397 kern_return_t kret = ::thread_set_state( 398 m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, 399 (thread_state_t)&m_state.context.exc, e_regSetEXCCount); 400 m_state.SetError(set, Write, 401 kret); // Set the current write error for this register set 402 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 403 // state in case registers are read 404 // back differently 405 return kret; // Return the error code 406 } 407 408 kern_return_t DNBArchMachARM64::SetDBGState(bool also_set_on_task) { 409 int set = e_regSetDBG; 410 kern_return_t kret = 411 ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64, 412 (thread_state_t)&m_state.dbg, e_regSetDBGCount); 413 if (also_set_on_task) { 414 kern_return_t task_kret = task_set_state( 415 m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE64, 416 (thread_state_t)&m_state.dbg, e_regSetDBGCount); 417 if (task_kret != KERN_SUCCESS) 418 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::SetDBGState failed " 419 "to set debug control register state: " 420 "0x%8.8x.", 421 task_kret); 422 } 423 m_state.SetError(set, Write, 424 kret); // Set the current write error for this register set 425 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 426 // state in case registers are read 427 // back differently 428 429 return kret; // Return the error code 430 } 431 432 void DNBArchMachARM64::ThreadWillResume() { 433 // Do we need to step this thread? If so, let the mach thread tell us so. 434 if (m_thread->IsStepping()) { 435 EnableHardwareSingleStep(true); 436 } 437 438 // Disable the triggered watchpoint temporarily before we resume. 439 // Plus, we try to enable hardware single step to execute past the instruction 440 // which triggered our watchpoint. 441 if (m_watchpoint_did_occur) { 442 if (m_watchpoint_hw_index >= 0) { 443 kern_return_t kret = GetDBGState(false); 444 if (kret == KERN_SUCCESS && 445 !IsWatchpointEnabled(m_state.dbg, m_watchpoint_hw_index)) { 446 // The watchpoint might have been disabled by the user. We don't need 447 // to do anything at all 448 // to enable hardware single stepping. 449 m_watchpoint_did_occur = false; 450 m_watchpoint_hw_index = -1; 451 return; 452 } 453 454 DisableHardwareWatchpoint(m_watchpoint_hw_index, false); 455 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 456 "DisableHardwareWatchpoint(%d) called", 457 m_watchpoint_hw_index); 458 459 // Enable hardware single step to move past the watchpoint-triggering 460 // instruction. 461 m_watchpoint_resume_single_step_enabled = 462 (EnableHardwareSingleStep(true) == KERN_SUCCESS); 463 464 // If we are not able to enable single step to move past the 465 // watchpoint-triggering instruction, 466 // at least we should reset the two watchpoint member variables so that 467 // the next time around 468 // this callback function is invoked, the enclosing logical branch is 469 // skipped. 470 if (!m_watchpoint_resume_single_step_enabled) { 471 // Reset the two watchpoint member variables. 472 m_watchpoint_did_occur = false; 473 m_watchpoint_hw_index = -1; 474 DNBLogThreadedIf( 475 LOG_WATCHPOINTS, 476 "DNBArchMachARM::ThreadWillResume() failed to enable single step"); 477 } else 478 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 479 "succeeded to enable single step"); 480 } 481 } 482 } 483 484 bool DNBArchMachARM64::NotifyException(MachException::Data &exc) { 485 486 switch (exc.exc_type) { 487 default: 488 break; 489 case EXC_BREAKPOINT: 490 if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_DA_DEBUG) { 491 // The data break address is passed as exc_data[1]. 492 nub_addr_t addr = exc.exc_data[1]; 493 // Find the hardware index with the side effect of possibly massaging the 494 // addr to return the starting address as seen from the debugger side. 495 uint32_t hw_index = GetHardwareWatchpointHit(addr); 496 497 // One logical watchpoint was split into two watchpoint locations because 498 // it was too big. If the watchpoint exception is indicating the 2nd half 499 // of the two-parter, find the address of the 1st half and report that -- 500 // that's what lldb is going to expect to see. 501 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 502 "watchpoint %d was hit on address " 503 "0x%llx", 504 hw_index, (uint64_t)addr); 505 const int num_watchpoints = NumSupportedHardwareWatchpoints(); 506 for (int i = 0; i < num_watchpoints; i++) { 507 if (LoHi[i] != 0 && LoHi[i] == hw_index && LoHi[i] != i && 508 GetWatchpointAddressByIndex(i) != INVALID_NUB_ADDRESS) { 509 addr = GetWatchpointAddressByIndex(i); 510 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 511 "It is a linked watchpoint; " 512 "rewritten to index %d addr 0x%llx", 513 LoHi[i], (uint64_t)addr); 514 } 515 } 516 517 if (hw_index != INVALID_NUB_HW_INDEX) { 518 m_watchpoint_did_occur = true; 519 m_watchpoint_hw_index = hw_index; 520 exc.exc_data[1] = addr; 521 // Piggyback the hw_index in the exc.data. 522 exc.exc_data.push_back(hw_index); 523 } 524 525 return true; 526 } 527 break; 528 } 529 return false; 530 } 531 532 bool DNBArchMachARM64::ThreadDidStop() { 533 bool success = true; 534 535 m_state.InvalidateAllRegisterStates(); 536 537 if (m_watchpoint_resume_single_step_enabled) { 538 // Great! We now disable the hardware single step as well as re-enable the 539 // hardware watchpoint. 540 // See also ThreadWillResume(). 541 if (EnableHardwareSingleStep(false) == KERN_SUCCESS) { 542 if (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0) { 543 ReenableHardwareWatchpoint(m_watchpoint_hw_index); 544 m_watchpoint_resume_single_step_enabled = false; 545 m_watchpoint_did_occur = false; 546 m_watchpoint_hw_index = -1; 547 } else { 548 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 549 "is true but (m_watchpoint_did_occur && " 550 "m_watchpoint_hw_index >= 0) does not hold!"); 551 } 552 } else { 553 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 554 "is true but unable to disable single step!"); 555 } 556 } 557 558 // Are we stepping a single instruction? 559 if (GetGPRState(true) == KERN_SUCCESS) { 560 // We are single stepping, was this the primary thread? 561 if (m_thread->IsStepping()) { 562 // This was the primary thread, we need to clear the trace 563 // bit if so. 564 success = EnableHardwareSingleStep(false) == KERN_SUCCESS; 565 } else { 566 // The MachThread will automatically restore the suspend count 567 // in ThreadDidStop(), so we don't need to do anything here if 568 // we weren't the primary thread the last time 569 } 570 } 571 return success; 572 } 573 574 // Set the single step bit in the processor status register. 575 kern_return_t DNBArchMachARM64::EnableHardwareSingleStep(bool enable) { 576 DNBError err; 577 DNBLogThreadedIf(LOG_STEP, "%s( enable = %d )", __FUNCTION__, enable); 578 579 err = GetGPRState(false); 580 581 if (err.Fail()) { 582 err.LogThreaded("%s: failed to read the GPR registers", __FUNCTION__); 583 return err.Status(); 584 } 585 586 err = GetDBGState(false); 587 588 if (err.Fail()) { 589 err.LogThreaded("%s: failed to read the DBG registers", __FUNCTION__); 590 return err.Status(); 591 } 592 593 if (enable) { 594 DNBLogThreadedIf(LOG_STEP, 595 "%s: Setting MDSCR_EL1 Single Step bit at pc 0x%llx", 596 #if defined(__LP64__) 597 __FUNCTION__, (uint64_t)arm_thread_state64_get_pc (m_state.context.gpr)); 598 #else 599 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc); 600 #endif 601 m_state.dbg.__mdscr_el1 |= SS_ENABLE; 602 } else { 603 DNBLogThreadedIf(LOG_STEP, 604 "%s: Clearing MDSCR_EL1 Single Step bit at pc 0x%llx", 605 #if defined(__LP64__) 606 __FUNCTION__, (uint64_t)arm_thread_state64_get_pc (m_state.context.gpr)); 607 #else 608 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc); 609 #endif 610 m_state.dbg.__mdscr_el1 &= ~(SS_ENABLE); 611 } 612 613 return SetDBGState(false); 614 } 615 616 // return 1 if bit "BIT" is set in "value" 617 static inline uint32_t bit(uint32_t value, uint32_t bit) { 618 return (value >> bit) & 1u; 619 } 620 621 // return the bitfield "value[msbit:lsbit]". 622 static inline uint64_t bits(uint64_t value, uint32_t msbit, uint32_t lsbit) { 623 assert(msbit >= lsbit); 624 uint64_t shift_left = sizeof(value) * 8 - 1 - msbit; 625 value <<= 626 shift_left; // shift anything above the msbit off of the unsigned edge 627 value >>= shift_left + lsbit; // shift it back again down to the lsbit 628 // (including undoing any shift from above) 629 return value; // return our result 630 } 631 632 uint32_t DNBArchMachARM64::NumSupportedHardwareWatchpoints() { 633 // Set the init value to something that will let us know that we need to 634 // autodetect how many watchpoints are supported dynamically... 635 static uint32_t g_num_supported_hw_watchpoints = UINT_MAX; 636 if (g_num_supported_hw_watchpoints == UINT_MAX) { 637 // Set this to zero in case we can't tell if there are any HW breakpoints 638 g_num_supported_hw_watchpoints = 0; 639 640 size_t len; 641 uint32_t n = 0; 642 len = sizeof(n); 643 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) { 644 g_num_supported_hw_watchpoints = n; 645 DNBLogThreadedIf(LOG_THREAD, "hw.optional.watchpoint=%u", n); 646 } else { 647 // For AArch64 we would need to look at ID_AA64DFR0_EL1 but debugserver runs in 648 // EL0 so it can't 649 // access that reg. The kernel should have filled in the sysctls based on it 650 // though. 651 #if defined(__arm__) 652 uint32_t register_DBGDIDR; 653 654 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 655 uint32_t numWRPs = bits(register_DBGDIDR, 31, 28); 656 // Zero is reserved for the WRP count, so don't increment it if it is zero 657 if (numWRPs > 0) 658 numWRPs++; 659 g_num_supported_hw_watchpoints = numWRPs; 660 DNBLogThreadedIf(LOG_THREAD, 661 "Number of supported hw watchpoints via asm(): %d", 662 g_num_supported_hw_watchpoints); 663 #endif 664 } 665 } 666 return g_num_supported_hw_watchpoints; 667 } 668 669 uint32_t DNBArchMachARM64::EnableHardwareWatchpoint(nub_addr_t addr, 670 nub_size_t size, bool read, 671 bool write, 672 bool also_set_on_task) { 673 DNBLogThreadedIf(LOG_WATCHPOINTS, 674 "DNBArchMachARM64::EnableHardwareWatchpoint(addr = " 675 "0x%8.8llx, size = %zu, read = %u, write = %u)", 676 (uint64_t)addr, size, read, write); 677 678 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 679 680 // Can't watch zero bytes 681 if (size == 0) 682 return INVALID_NUB_HW_INDEX; 683 684 // We must watch for either read or write 685 if (read == false && write == false) 686 return INVALID_NUB_HW_INDEX; 687 688 // Otherwise, can't watch more than 8 bytes per WVR/WCR pair 689 if (size > 8) 690 return INVALID_NUB_HW_INDEX; 691 692 // arm64 watchpoints really have an 8-byte alignment requirement. You can put 693 // a watchpoint on a 4-byte 694 // offset address but you can only watch 4 bytes with that watchpoint. 695 696 // arm64 watchpoints on an 8-byte (double word) aligned addr can watch any 697 // bytes in that 698 // 8-byte long region of memory. They can watch the 1st byte, the 2nd byte, 699 // 3rd byte, etc, or any 700 // combination therein by setting the bits in the BAS [12:5] (Byte Address 701 // Select) field of 702 // the DBGWCRn_EL1 reg for the watchpoint. 703 704 // If the MASK [28:24] bits in the DBGWCRn_EL1 allow a single watchpoint to 705 // monitor a larger region 706 // of memory (16 bytes, 32 bytes, or 2GB) but the Byte Address Select bitfield 707 // then selects a larger 708 // range of bytes, instead of individual bytes. See the ARMv8 Debug 709 // Architecture manual for details. 710 // This implementation does not currently use the MASK bits; the largest 711 // single region watched by a single 712 // watchpoint right now is 8-bytes. 713 714 nub_addr_t aligned_wp_address = addr & ~0x7; 715 uint32_t addr_dword_offset = addr & 0x7; 716 717 // Do we need to split up this logical watchpoint into two hardware watchpoint 718 // registers? 719 // e.g. a watchpoint of length 4 on address 6. We need do this with 720 // one watchpoint on address 0 with bytes 6 & 7 being monitored 721 // one watchpoint on address 8 with bytes 0, 1, 2, 3 being monitored 722 723 if (addr_dword_offset + size > 8) { 724 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 725 "EnableHardwareWatchpoint(addr = " 726 "0x%8.8llx, size = %zu) needs two " 727 "hardware watchpoints slots to monitor", 728 (uint64_t)addr, size); 729 int low_watchpoint_size = 8 - addr_dword_offset; 730 int high_watchpoint_size = addr_dword_offset + size - 8; 731 732 uint32_t lo = EnableHardwareWatchpoint(addr, low_watchpoint_size, read, 733 write, also_set_on_task); 734 if (lo == INVALID_NUB_HW_INDEX) 735 return INVALID_NUB_HW_INDEX; 736 uint32_t hi = 737 EnableHardwareWatchpoint(aligned_wp_address + 8, high_watchpoint_size, 738 read, write, also_set_on_task); 739 if (hi == INVALID_NUB_HW_INDEX) { 740 DisableHardwareWatchpoint(lo, also_set_on_task); 741 return INVALID_NUB_HW_INDEX; 742 } 743 // Tag this lo->hi mapping in our database. 744 LoHi[lo] = hi; 745 return lo; 746 } 747 748 // At this point 749 // 1 aligned_wp_address is the requested address rounded down to 8-byte 750 // alignment 751 // 2 addr_dword_offset is the offset into that double word (8-byte) region 752 // that we are watching 753 // 3 size is the number of bytes within that 8-byte region that we are 754 // watching 755 756 // Set the Byte Address Selects bits DBGWCRn_EL1 bits [12:5] based on the 757 // above. 758 // The bit shift and negation operation will give us 0b11 for 2, 0b1111 for 4, 759 // etc, up to 0b11111111 for 8. 760 // then we shift those bits left by the offset into this dword that we are 761 // interested in. 762 // e.g. if we are watching bytes 4,5,6,7 in a dword we want a BAS of 763 // 0b11110000. 764 uint32_t byte_address_select = ((1 << size) - 1) << addr_dword_offset; 765 766 // Read the debug state 767 kern_return_t kret = GetDBGState(false); 768 769 if (kret == KERN_SUCCESS) { 770 // Check to make sure we have the needed hardware support 771 uint32_t i = 0; 772 773 for (i = 0; i < num_hw_watchpoints; ++i) { 774 if ((m_state.dbg.__wcr[i] & WCR_ENABLE) == 0) 775 break; // We found an available hw watchpoint slot (in i) 776 } 777 778 // See if we found an available hw watchpoint slot above 779 if (i < num_hw_watchpoints) { 780 // DumpDBGState(m_state.dbg); 781 782 // Clear any previous LoHi joined-watchpoint that may have been in use 783 LoHi[i] = 0; 784 785 // shift our Byte Address Select bits up to the correct bit range for the 786 // DBGWCRn_EL1 787 byte_address_select = byte_address_select << 5; 788 789 // Make sure bits 1:0 are clear in our address 790 m_state.dbg.__wvr[i] = aligned_wp_address; // DVA (Data Virtual Address) 791 m_state.dbg.__wcr[i] = byte_address_select | // Which bytes that follow 792 // the DVA that we will watch 793 S_USER | // Stop only in user mode 794 (read ? WCR_LOAD : 0) | // Stop on read access? 795 (write ? WCR_STORE : 0) | // Stop on write access? 796 WCR_ENABLE; // Enable this watchpoint; 797 798 DNBLogThreadedIf( 799 LOG_WATCHPOINTS, "DNBArchMachARM64::EnableHardwareWatchpoint() " 800 "adding watchpoint on address 0x%llx with control " 801 "register value 0x%x", 802 (uint64_t)m_state.dbg.__wvr[i], (uint32_t)m_state.dbg.__wcr[i]); 803 804 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 805 // automatically, don't need to do it here. 806 807 kret = SetDBGState(also_set_on_task); 808 // DumpDBGState(m_state.dbg); 809 810 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 811 "EnableHardwareWatchpoint() " 812 "SetDBGState() => 0x%8.8x.", 813 kret); 814 815 if (kret == KERN_SUCCESS) 816 return i; 817 } else { 818 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 819 "EnableHardwareWatchpoint(): All " 820 "hardware resources (%u) are in use.", 821 num_hw_watchpoints); 822 } 823 } 824 return INVALID_NUB_HW_INDEX; 825 } 826 827 bool DNBArchMachARM64::ReenableHardwareWatchpoint(uint32_t hw_index) { 828 // If this logical watchpoint # is actually implemented using 829 // two hardware watchpoint registers, re-enable both of them. 830 831 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 832 return ReenableHardwareWatchpoint_helper(hw_index) && 833 ReenableHardwareWatchpoint_helper(LoHi[hw_index]); 834 } else { 835 return ReenableHardwareWatchpoint_helper(hw_index); 836 } 837 } 838 839 bool DNBArchMachARM64::ReenableHardwareWatchpoint_helper(uint32_t hw_index) { 840 kern_return_t kret = GetDBGState(false); 841 if (kret != KERN_SUCCESS) 842 return false; 843 844 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 845 if (hw_index >= num_hw_points) 846 return false; 847 848 m_state.dbg.__wvr[hw_index] = m_disabled_watchpoints[hw_index].addr; 849 m_state.dbg.__wcr[hw_index] = m_disabled_watchpoints[hw_index].control; 850 851 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 852 "EnableHardwareWatchpoint( %u ) - WVR%u = " 853 "0x%8.8llx WCR%u = 0x%8.8llx", 854 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 855 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 856 857 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 858 // automatically, don't need to do it here. 859 860 kret = SetDBGState(false); 861 862 return (kret == KERN_SUCCESS); 863 } 864 865 bool DNBArchMachARM64::DisableHardwareWatchpoint(uint32_t hw_index, 866 bool also_set_on_task) { 867 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 868 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task) && 869 DisableHardwareWatchpoint_helper(LoHi[hw_index], also_set_on_task); 870 } else { 871 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task); 872 } 873 } 874 875 bool DNBArchMachARM64::DisableHardwareWatchpoint_helper(uint32_t hw_index, 876 bool also_set_on_task) { 877 kern_return_t kret = GetDBGState(false); 878 if (kret != KERN_SUCCESS) 879 return false; 880 881 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 882 if (hw_index >= num_hw_points) 883 return false; 884 885 m_disabled_watchpoints[hw_index].addr = m_state.dbg.__wvr[hw_index]; 886 m_disabled_watchpoints[hw_index].control = m_state.dbg.__wcr[hw_index]; 887 888 m_state.dbg.__wcr[hw_index] &= ~((nub_addr_t)WCR_ENABLE); 889 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 890 "DisableHardwareWatchpoint( %u ) - WVR%u = " 891 "0x%8.8llx WCR%u = 0x%8.8llx", 892 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 893 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 894 895 kret = SetDBGState(also_set_on_task); 896 897 return (kret == KERN_SUCCESS); 898 } 899 900 // This is for checking the Byte Address Select bits in the DBRWCRn_EL1 control 901 // register. 902 // Returns -1 if the trailing bit patterns are not one of: 903 // { 0b???????1, 0b??????10, 0b?????100, 0b????1000, 0b???10000, 0b??100000, 904 // 0b?1000000, 0b10000000 }. 905 static inline int32_t LowestBitSet(uint32_t val) { 906 for (unsigned i = 0; i < 8; ++i) { 907 if (bit(val, i)) 908 return i; 909 } 910 return -1; 911 } 912 913 // Iterate through the debug registers; return the index of the first watchpoint 914 // whose address matches. 915 // As a side effect, the starting address as understood by the debugger is 916 // returned which could be 917 // different from 'addr' passed as an in/out argument. 918 uint32_t DNBArchMachARM64::GetHardwareWatchpointHit(nub_addr_t &addr) { 919 // Read the debug state 920 kern_return_t kret = GetDBGState(true); 921 // DumpDBGState(m_state.dbg); 922 DNBLogThreadedIf( 923 LOG_WATCHPOINTS, 924 "DNBArchMachARM64::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", 925 kret); 926 DNBLogThreadedIf(LOG_WATCHPOINTS, 927 "DNBArchMachARM64::GetHardwareWatchpointHit() addr = 0x%llx", 928 (uint64_t)addr); 929 930 // This is the watchpoint value to match against, i.e., word address. 931 nub_addr_t wp_val = addr & ~((nub_addr_t)3); 932 if (kret == KERN_SUCCESS) { 933 DBG &debug_state = m_state.dbg; 934 uint32_t i, num = NumSupportedHardwareWatchpoints(); 935 for (i = 0; i < num; ++i) { 936 nub_addr_t wp_addr = GetWatchAddress(debug_state, i); 937 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 938 "GetHardwareWatchpointHit() slot: %u " 939 "(addr = 0x%llx).", 940 i, (uint64_t)wp_addr); 941 if (wp_val == wp_addr) { 942 uint32_t byte_mask = bits(debug_state.__wcr[i], 12, 5); 943 944 // Sanity check the byte_mask, first. 945 if (LowestBitSet(byte_mask) < 0) 946 continue; 947 948 // Check that the watchpoint is enabled. 949 if (!IsWatchpointEnabled(debug_state, i)) 950 continue; 951 952 // Compute the starting address (from the point of view of the 953 // debugger). 954 addr = wp_addr + LowestBitSet(byte_mask); 955 return i; 956 } 957 } 958 } 959 return INVALID_NUB_HW_INDEX; 960 } 961 962 nub_addr_t DNBArchMachARM64::GetWatchpointAddressByIndex(uint32_t hw_index) { 963 kern_return_t kret = GetDBGState(true); 964 if (kret != KERN_SUCCESS) 965 return INVALID_NUB_ADDRESS; 966 const uint32_t num = NumSupportedHardwareWatchpoints(); 967 if (hw_index >= num) 968 return INVALID_NUB_ADDRESS; 969 if (IsWatchpointEnabled(m_state.dbg, hw_index)) 970 return GetWatchAddress(m_state.dbg, hw_index); 971 return INVALID_NUB_ADDRESS; 972 } 973 974 bool DNBArchMachARM64::IsWatchpointEnabled(const DBG &debug_state, 975 uint32_t hw_index) { 976 // Watchpoint Control Registers, bitfield definitions 977 // ... 978 // Bits Value Description 979 // [0] 0 Watchpoint disabled 980 // 1 Watchpoint enabled. 981 return (debug_state.__wcr[hw_index] & 1u); 982 } 983 984 nub_addr_t DNBArchMachARM64::GetWatchAddress(const DBG &debug_state, 985 uint32_t hw_index) { 986 // Watchpoint Value Registers, bitfield definitions 987 // Bits Description 988 // [31:2] Watchpoint value (word address, i.e., 4-byte aligned) 989 // [1:0] RAZ/SBZP 990 return bits(debug_state.__wvr[hw_index], 63, 0); 991 } 992 993 // Register information definitions for 64 bit ARMv8. 994 enum gpr_regnums { 995 gpr_x0 = 0, 996 gpr_x1, 997 gpr_x2, 998 gpr_x3, 999 gpr_x4, 1000 gpr_x5, 1001 gpr_x6, 1002 gpr_x7, 1003 gpr_x8, 1004 gpr_x9, 1005 gpr_x10, 1006 gpr_x11, 1007 gpr_x12, 1008 gpr_x13, 1009 gpr_x14, 1010 gpr_x15, 1011 gpr_x16, 1012 gpr_x17, 1013 gpr_x18, 1014 gpr_x19, 1015 gpr_x20, 1016 gpr_x21, 1017 gpr_x22, 1018 gpr_x23, 1019 gpr_x24, 1020 gpr_x25, 1021 gpr_x26, 1022 gpr_x27, 1023 gpr_x28, 1024 gpr_fp, 1025 gpr_x29 = gpr_fp, 1026 gpr_lr, 1027 gpr_x30 = gpr_lr, 1028 gpr_sp, 1029 gpr_x31 = gpr_sp, 1030 gpr_pc, 1031 gpr_cpsr, 1032 gpr_w0, 1033 gpr_w1, 1034 gpr_w2, 1035 gpr_w3, 1036 gpr_w4, 1037 gpr_w5, 1038 gpr_w6, 1039 gpr_w7, 1040 gpr_w8, 1041 gpr_w9, 1042 gpr_w10, 1043 gpr_w11, 1044 gpr_w12, 1045 gpr_w13, 1046 gpr_w14, 1047 gpr_w15, 1048 gpr_w16, 1049 gpr_w17, 1050 gpr_w18, 1051 gpr_w19, 1052 gpr_w20, 1053 gpr_w21, 1054 gpr_w22, 1055 gpr_w23, 1056 gpr_w24, 1057 gpr_w25, 1058 gpr_w26, 1059 gpr_w27, 1060 gpr_w28 1061 1062 }; 1063 1064 enum { 1065 vfp_v0 = 0, 1066 vfp_v1, 1067 vfp_v2, 1068 vfp_v3, 1069 vfp_v4, 1070 vfp_v5, 1071 vfp_v6, 1072 vfp_v7, 1073 vfp_v8, 1074 vfp_v9, 1075 vfp_v10, 1076 vfp_v11, 1077 vfp_v12, 1078 vfp_v13, 1079 vfp_v14, 1080 vfp_v15, 1081 vfp_v16, 1082 vfp_v17, 1083 vfp_v18, 1084 vfp_v19, 1085 vfp_v20, 1086 vfp_v21, 1087 vfp_v22, 1088 vfp_v23, 1089 vfp_v24, 1090 vfp_v25, 1091 vfp_v26, 1092 vfp_v27, 1093 vfp_v28, 1094 vfp_v29, 1095 vfp_v30, 1096 vfp_v31, 1097 vfp_fpsr, 1098 vfp_fpcr, 1099 1100 // lower 32 bits of the corresponding vfp_v<n> reg. 1101 vfp_s0, 1102 vfp_s1, 1103 vfp_s2, 1104 vfp_s3, 1105 vfp_s4, 1106 vfp_s5, 1107 vfp_s6, 1108 vfp_s7, 1109 vfp_s8, 1110 vfp_s9, 1111 vfp_s10, 1112 vfp_s11, 1113 vfp_s12, 1114 vfp_s13, 1115 vfp_s14, 1116 vfp_s15, 1117 vfp_s16, 1118 vfp_s17, 1119 vfp_s18, 1120 vfp_s19, 1121 vfp_s20, 1122 vfp_s21, 1123 vfp_s22, 1124 vfp_s23, 1125 vfp_s24, 1126 vfp_s25, 1127 vfp_s26, 1128 vfp_s27, 1129 vfp_s28, 1130 vfp_s29, 1131 vfp_s30, 1132 vfp_s31, 1133 1134 // lower 64 bits of the corresponding vfp_v<n> reg. 1135 vfp_d0, 1136 vfp_d1, 1137 vfp_d2, 1138 vfp_d3, 1139 vfp_d4, 1140 vfp_d5, 1141 vfp_d6, 1142 vfp_d7, 1143 vfp_d8, 1144 vfp_d9, 1145 vfp_d10, 1146 vfp_d11, 1147 vfp_d12, 1148 vfp_d13, 1149 vfp_d14, 1150 vfp_d15, 1151 vfp_d16, 1152 vfp_d17, 1153 vfp_d18, 1154 vfp_d19, 1155 vfp_d20, 1156 vfp_d21, 1157 vfp_d22, 1158 vfp_d23, 1159 vfp_d24, 1160 vfp_d25, 1161 vfp_d26, 1162 vfp_d27, 1163 vfp_d28, 1164 vfp_d29, 1165 vfp_d30, 1166 vfp_d31 1167 }; 1168 1169 enum { exc_far = 0, exc_esr, exc_exception }; 1170 1171 // These numbers from the "DWARF for the ARM 64-bit Architecture (AArch64)" 1172 // document. 1173 1174 enum { 1175 dwarf_x0 = 0, 1176 dwarf_x1, 1177 dwarf_x2, 1178 dwarf_x3, 1179 dwarf_x4, 1180 dwarf_x5, 1181 dwarf_x6, 1182 dwarf_x7, 1183 dwarf_x8, 1184 dwarf_x9, 1185 dwarf_x10, 1186 dwarf_x11, 1187 dwarf_x12, 1188 dwarf_x13, 1189 dwarf_x14, 1190 dwarf_x15, 1191 dwarf_x16, 1192 dwarf_x17, 1193 dwarf_x18, 1194 dwarf_x19, 1195 dwarf_x20, 1196 dwarf_x21, 1197 dwarf_x22, 1198 dwarf_x23, 1199 dwarf_x24, 1200 dwarf_x25, 1201 dwarf_x26, 1202 dwarf_x27, 1203 dwarf_x28, 1204 dwarf_x29, 1205 dwarf_x30, 1206 dwarf_x31, 1207 dwarf_pc = 32, 1208 dwarf_elr_mode = 33, 1209 dwarf_fp = dwarf_x29, 1210 dwarf_lr = dwarf_x30, 1211 dwarf_sp = dwarf_x31, 1212 // 34-63 reserved 1213 1214 // V0-V31 (128 bit vector registers) 1215 dwarf_v0 = 64, 1216 dwarf_v1, 1217 dwarf_v2, 1218 dwarf_v3, 1219 dwarf_v4, 1220 dwarf_v5, 1221 dwarf_v6, 1222 dwarf_v7, 1223 dwarf_v8, 1224 dwarf_v9, 1225 dwarf_v10, 1226 dwarf_v11, 1227 dwarf_v12, 1228 dwarf_v13, 1229 dwarf_v14, 1230 dwarf_v15, 1231 dwarf_v16, 1232 dwarf_v17, 1233 dwarf_v18, 1234 dwarf_v19, 1235 dwarf_v20, 1236 dwarf_v21, 1237 dwarf_v22, 1238 dwarf_v23, 1239 dwarf_v24, 1240 dwarf_v25, 1241 dwarf_v26, 1242 dwarf_v27, 1243 dwarf_v28, 1244 dwarf_v29, 1245 dwarf_v30, 1246 dwarf_v31 1247 1248 // 96-127 reserved 1249 }; 1250 1251 enum { 1252 debugserver_gpr_x0 = 0, 1253 debugserver_gpr_x1, 1254 debugserver_gpr_x2, 1255 debugserver_gpr_x3, 1256 debugserver_gpr_x4, 1257 debugserver_gpr_x5, 1258 debugserver_gpr_x6, 1259 debugserver_gpr_x7, 1260 debugserver_gpr_x8, 1261 debugserver_gpr_x9, 1262 debugserver_gpr_x10, 1263 debugserver_gpr_x11, 1264 debugserver_gpr_x12, 1265 debugserver_gpr_x13, 1266 debugserver_gpr_x14, 1267 debugserver_gpr_x15, 1268 debugserver_gpr_x16, 1269 debugserver_gpr_x17, 1270 debugserver_gpr_x18, 1271 debugserver_gpr_x19, 1272 debugserver_gpr_x20, 1273 debugserver_gpr_x21, 1274 debugserver_gpr_x22, 1275 debugserver_gpr_x23, 1276 debugserver_gpr_x24, 1277 debugserver_gpr_x25, 1278 debugserver_gpr_x26, 1279 debugserver_gpr_x27, 1280 debugserver_gpr_x28, 1281 debugserver_gpr_fp, // x29 1282 debugserver_gpr_lr, // x30 1283 debugserver_gpr_sp, // sp aka xsp 1284 debugserver_gpr_pc, 1285 debugserver_gpr_cpsr, 1286 debugserver_vfp_v0, 1287 debugserver_vfp_v1, 1288 debugserver_vfp_v2, 1289 debugserver_vfp_v3, 1290 debugserver_vfp_v4, 1291 debugserver_vfp_v5, 1292 debugserver_vfp_v6, 1293 debugserver_vfp_v7, 1294 debugserver_vfp_v8, 1295 debugserver_vfp_v9, 1296 debugserver_vfp_v10, 1297 debugserver_vfp_v11, 1298 debugserver_vfp_v12, 1299 debugserver_vfp_v13, 1300 debugserver_vfp_v14, 1301 debugserver_vfp_v15, 1302 debugserver_vfp_v16, 1303 debugserver_vfp_v17, 1304 debugserver_vfp_v18, 1305 debugserver_vfp_v19, 1306 debugserver_vfp_v20, 1307 debugserver_vfp_v21, 1308 debugserver_vfp_v22, 1309 debugserver_vfp_v23, 1310 debugserver_vfp_v24, 1311 debugserver_vfp_v25, 1312 debugserver_vfp_v26, 1313 debugserver_vfp_v27, 1314 debugserver_vfp_v28, 1315 debugserver_vfp_v29, 1316 debugserver_vfp_v30, 1317 debugserver_vfp_v31, 1318 debugserver_vfp_fpsr, 1319 debugserver_vfp_fpcr 1320 }; 1321 1322 const char *g_contained_x0[]{"x0", NULL}; 1323 const char *g_contained_x1[]{"x1", NULL}; 1324 const char *g_contained_x2[]{"x2", NULL}; 1325 const char *g_contained_x3[]{"x3", NULL}; 1326 const char *g_contained_x4[]{"x4", NULL}; 1327 const char *g_contained_x5[]{"x5", NULL}; 1328 const char *g_contained_x6[]{"x6", NULL}; 1329 const char *g_contained_x7[]{"x7", NULL}; 1330 const char *g_contained_x8[]{"x8", NULL}; 1331 const char *g_contained_x9[]{"x9", NULL}; 1332 const char *g_contained_x10[]{"x10", NULL}; 1333 const char *g_contained_x11[]{"x11", NULL}; 1334 const char *g_contained_x12[]{"x12", NULL}; 1335 const char *g_contained_x13[]{"x13", NULL}; 1336 const char *g_contained_x14[]{"x14", NULL}; 1337 const char *g_contained_x15[]{"x15", NULL}; 1338 const char *g_contained_x16[]{"x16", NULL}; 1339 const char *g_contained_x17[]{"x17", NULL}; 1340 const char *g_contained_x18[]{"x18", NULL}; 1341 const char *g_contained_x19[]{"x19", NULL}; 1342 const char *g_contained_x20[]{"x20", NULL}; 1343 const char *g_contained_x21[]{"x21", NULL}; 1344 const char *g_contained_x22[]{"x22", NULL}; 1345 const char *g_contained_x23[]{"x23", NULL}; 1346 const char *g_contained_x24[]{"x24", NULL}; 1347 const char *g_contained_x25[]{"x25", NULL}; 1348 const char *g_contained_x26[]{"x26", NULL}; 1349 const char *g_contained_x27[]{"x27", NULL}; 1350 const char *g_contained_x28[]{"x28", NULL}; 1351 1352 const char *g_invalidate_x0[]{"x0", "w0", NULL}; 1353 const char *g_invalidate_x1[]{"x1", "w1", NULL}; 1354 const char *g_invalidate_x2[]{"x2", "w2", NULL}; 1355 const char *g_invalidate_x3[]{"x3", "w3", NULL}; 1356 const char *g_invalidate_x4[]{"x4", "w4", NULL}; 1357 const char *g_invalidate_x5[]{"x5", "w5", NULL}; 1358 const char *g_invalidate_x6[]{"x6", "w6", NULL}; 1359 const char *g_invalidate_x7[]{"x7", "w7", NULL}; 1360 const char *g_invalidate_x8[]{"x8", "w8", NULL}; 1361 const char *g_invalidate_x9[]{"x9", "w9", NULL}; 1362 const char *g_invalidate_x10[]{"x10", "w10", NULL}; 1363 const char *g_invalidate_x11[]{"x11", "w11", NULL}; 1364 const char *g_invalidate_x12[]{"x12", "w12", NULL}; 1365 const char *g_invalidate_x13[]{"x13", "w13", NULL}; 1366 const char *g_invalidate_x14[]{"x14", "w14", NULL}; 1367 const char *g_invalidate_x15[]{"x15", "w15", NULL}; 1368 const char *g_invalidate_x16[]{"x16", "w16", NULL}; 1369 const char *g_invalidate_x17[]{"x17", "w17", NULL}; 1370 const char *g_invalidate_x18[]{"x18", "w18", NULL}; 1371 const char *g_invalidate_x19[]{"x19", "w19", NULL}; 1372 const char *g_invalidate_x20[]{"x20", "w20", NULL}; 1373 const char *g_invalidate_x21[]{"x21", "w21", NULL}; 1374 const char *g_invalidate_x22[]{"x22", "w22", NULL}; 1375 const char *g_invalidate_x23[]{"x23", "w23", NULL}; 1376 const char *g_invalidate_x24[]{"x24", "w24", NULL}; 1377 const char *g_invalidate_x25[]{"x25", "w25", NULL}; 1378 const char *g_invalidate_x26[]{"x26", "w26", NULL}; 1379 const char *g_invalidate_x27[]{"x27", "w27", NULL}; 1380 const char *g_invalidate_x28[]{"x28", "w28", NULL}; 1381 1382 #define GPR_OFFSET_IDX(idx) (offsetof(DNBArchMachARM64::GPR, __x[idx])) 1383 1384 #define GPR_OFFSET_NAME(reg) (offsetof(DNBArchMachARM64::GPR, __##reg)) 1385 1386 // These macros will auto define the register name, alt name, register size, 1387 // register offset, encoding, format and native register. This ensures that 1388 // the register state structures are defined correctly and have the correct 1389 // sizes and offsets. 1390 #define DEFINE_GPR_IDX(idx, reg, alt, gen) \ 1391 { \ 1392 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_IDX(idx), \ 1393 dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, \ 1394 g_invalidate_x##idx \ 1395 } 1396 #define DEFINE_GPR_NAME(reg, alt, gen) \ 1397 { \ 1398 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_NAME(reg), \ 1399 dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, NULL \ 1400 } 1401 #define DEFINE_PSEUDO_GPR_IDX(idx, reg) \ 1402 { \ 1403 e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, 4, 0, INVALID_NUB_REGNUM, \ 1404 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1405 g_contained_x##idx, g_invalidate_x##idx \ 1406 } 1407 1408 //_STRUCT_ARM_THREAD_STATE64 1409 //{ 1410 // uint64_t x[29]; /* General purpose registers x0-x28 */ 1411 // uint64_t fp; /* Frame pointer x29 */ 1412 // uint64_t lr; /* Link register x30 */ 1413 // uint64_t sp; /* Stack pointer x31 */ 1414 // uint64_t pc; /* Program counter */ 1415 // uint32_t cpsr; /* Current program status register */ 1416 //}; 1417 1418 // General purpose registers 1419 const DNBRegisterInfo DNBArchMachARM64::g_gpr_registers[] = { 1420 DEFINE_GPR_IDX(0, x0, "arg1", GENERIC_REGNUM_ARG1), 1421 DEFINE_GPR_IDX(1, x1, "arg2", GENERIC_REGNUM_ARG2), 1422 DEFINE_GPR_IDX(2, x2, "arg3", GENERIC_REGNUM_ARG3), 1423 DEFINE_GPR_IDX(3, x3, "arg4", GENERIC_REGNUM_ARG4), 1424 DEFINE_GPR_IDX(4, x4, "arg5", GENERIC_REGNUM_ARG5), 1425 DEFINE_GPR_IDX(5, x5, "arg6", GENERIC_REGNUM_ARG6), 1426 DEFINE_GPR_IDX(6, x6, "arg7", GENERIC_REGNUM_ARG7), 1427 DEFINE_GPR_IDX(7, x7, "arg8", GENERIC_REGNUM_ARG8), 1428 DEFINE_GPR_IDX(8, x8, NULL, INVALID_NUB_REGNUM), 1429 DEFINE_GPR_IDX(9, x9, NULL, INVALID_NUB_REGNUM), 1430 DEFINE_GPR_IDX(10, x10, NULL, INVALID_NUB_REGNUM), 1431 DEFINE_GPR_IDX(11, x11, NULL, INVALID_NUB_REGNUM), 1432 DEFINE_GPR_IDX(12, x12, NULL, INVALID_NUB_REGNUM), 1433 DEFINE_GPR_IDX(13, x13, NULL, INVALID_NUB_REGNUM), 1434 DEFINE_GPR_IDX(14, x14, NULL, INVALID_NUB_REGNUM), 1435 DEFINE_GPR_IDX(15, x15, NULL, INVALID_NUB_REGNUM), 1436 DEFINE_GPR_IDX(16, x16, NULL, INVALID_NUB_REGNUM), 1437 DEFINE_GPR_IDX(17, x17, NULL, INVALID_NUB_REGNUM), 1438 DEFINE_GPR_IDX(18, x18, NULL, INVALID_NUB_REGNUM), 1439 DEFINE_GPR_IDX(19, x19, NULL, INVALID_NUB_REGNUM), 1440 DEFINE_GPR_IDX(20, x20, NULL, INVALID_NUB_REGNUM), 1441 DEFINE_GPR_IDX(21, x21, NULL, INVALID_NUB_REGNUM), 1442 DEFINE_GPR_IDX(22, x22, NULL, INVALID_NUB_REGNUM), 1443 DEFINE_GPR_IDX(23, x23, NULL, INVALID_NUB_REGNUM), 1444 DEFINE_GPR_IDX(24, x24, NULL, INVALID_NUB_REGNUM), 1445 DEFINE_GPR_IDX(25, x25, NULL, INVALID_NUB_REGNUM), 1446 DEFINE_GPR_IDX(26, x26, NULL, INVALID_NUB_REGNUM), 1447 DEFINE_GPR_IDX(27, x27, NULL, INVALID_NUB_REGNUM), 1448 DEFINE_GPR_IDX(28, x28, NULL, INVALID_NUB_REGNUM), 1449 // For the G/g packet we want to show where the offset into the regctx 1450 // is for fp/lr/sp/pc, but we cannot directly access them on arm64e 1451 // devices (and therefore can't offsetof() them)) - add the offset based 1452 // on the last accessible register by hand for advertising the location 1453 // in the regctx to lldb. We'll go through the accessor functions when 1454 // we read/write them here. 1455 { 1456 e_regSetGPR, gpr_fp, "fp", "x29", Uint, Hex, 8, GPR_OFFSET_IDX(28) + 8, 1457 dwarf_fp, dwarf_fp, GENERIC_REGNUM_FP, debugserver_gpr_fp, NULL, NULL 1458 }, 1459 { 1460 e_regSetGPR, gpr_lr, "lr", "x30", Uint, Hex, 8, GPR_OFFSET_IDX(28) + 16, 1461 dwarf_lr, dwarf_lr, GENERIC_REGNUM_RA, debugserver_gpr_lr, NULL, NULL 1462 }, 1463 { 1464 e_regSetGPR, gpr_sp, "sp", "xsp", Uint, Hex, 8, GPR_OFFSET_IDX(28) + 24, 1465 dwarf_sp, dwarf_sp, GENERIC_REGNUM_SP, debugserver_gpr_sp, NULL, NULL 1466 }, 1467 { 1468 e_regSetGPR, gpr_pc, "pc", NULL, Uint, Hex, 8, GPR_OFFSET_IDX(28) + 32, 1469 dwarf_pc, dwarf_pc, GENERIC_REGNUM_PC, debugserver_gpr_pc, NULL, NULL 1470 }, 1471 1472 // in armv7 we specify that writing to the CPSR should invalidate r8-12, sp, 1473 // lr. 1474 // this should be specified for arm64 too even though debugserver is only 1475 // used for 1476 // userland debugging. 1477 {e_regSetGPR, gpr_cpsr, "cpsr", "flags", Uint, Hex, 4, 1478 GPR_OFFSET_NAME(cpsr), dwarf_elr_mode, dwarf_elr_mode, INVALID_NUB_REGNUM, 1479 debugserver_gpr_cpsr, NULL, NULL}, 1480 1481 DEFINE_PSEUDO_GPR_IDX(0, w0), 1482 DEFINE_PSEUDO_GPR_IDX(1, w1), 1483 DEFINE_PSEUDO_GPR_IDX(2, w2), 1484 DEFINE_PSEUDO_GPR_IDX(3, w3), 1485 DEFINE_PSEUDO_GPR_IDX(4, w4), 1486 DEFINE_PSEUDO_GPR_IDX(5, w5), 1487 DEFINE_PSEUDO_GPR_IDX(6, w6), 1488 DEFINE_PSEUDO_GPR_IDX(7, w7), 1489 DEFINE_PSEUDO_GPR_IDX(8, w8), 1490 DEFINE_PSEUDO_GPR_IDX(9, w9), 1491 DEFINE_PSEUDO_GPR_IDX(10, w10), 1492 DEFINE_PSEUDO_GPR_IDX(11, w11), 1493 DEFINE_PSEUDO_GPR_IDX(12, w12), 1494 DEFINE_PSEUDO_GPR_IDX(13, w13), 1495 DEFINE_PSEUDO_GPR_IDX(14, w14), 1496 DEFINE_PSEUDO_GPR_IDX(15, w15), 1497 DEFINE_PSEUDO_GPR_IDX(16, w16), 1498 DEFINE_PSEUDO_GPR_IDX(17, w17), 1499 DEFINE_PSEUDO_GPR_IDX(18, w18), 1500 DEFINE_PSEUDO_GPR_IDX(19, w19), 1501 DEFINE_PSEUDO_GPR_IDX(20, w20), 1502 DEFINE_PSEUDO_GPR_IDX(21, w21), 1503 DEFINE_PSEUDO_GPR_IDX(22, w22), 1504 DEFINE_PSEUDO_GPR_IDX(23, w23), 1505 DEFINE_PSEUDO_GPR_IDX(24, w24), 1506 DEFINE_PSEUDO_GPR_IDX(25, w25), 1507 DEFINE_PSEUDO_GPR_IDX(26, w26), 1508 DEFINE_PSEUDO_GPR_IDX(27, w27), 1509 DEFINE_PSEUDO_GPR_IDX(28, w28)}; 1510 1511 const char *g_contained_v0[]{"v0", NULL}; 1512 const char *g_contained_v1[]{"v1", NULL}; 1513 const char *g_contained_v2[]{"v2", NULL}; 1514 const char *g_contained_v3[]{"v3", NULL}; 1515 const char *g_contained_v4[]{"v4", NULL}; 1516 const char *g_contained_v5[]{"v5", NULL}; 1517 const char *g_contained_v6[]{"v6", NULL}; 1518 const char *g_contained_v7[]{"v7", NULL}; 1519 const char *g_contained_v8[]{"v8", NULL}; 1520 const char *g_contained_v9[]{"v9", NULL}; 1521 const char *g_contained_v10[]{"v10", NULL}; 1522 const char *g_contained_v11[]{"v11", NULL}; 1523 const char *g_contained_v12[]{"v12", NULL}; 1524 const char *g_contained_v13[]{"v13", NULL}; 1525 const char *g_contained_v14[]{"v14", NULL}; 1526 const char *g_contained_v15[]{"v15", NULL}; 1527 const char *g_contained_v16[]{"v16", NULL}; 1528 const char *g_contained_v17[]{"v17", NULL}; 1529 const char *g_contained_v18[]{"v18", NULL}; 1530 const char *g_contained_v19[]{"v19", NULL}; 1531 const char *g_contained_v20[]{"v20", NULL}; 1532 const char *g_contained_v21[]{"v21", NULL}; 1533 const char *g_contained_v22[]{"v22", NULL}; 1534 const char *g_contained_v23[]{"v23", NULL}; 1535 const char *g_contained_v24[]{"v24", NULL}; 1536 const char *g_contained_v25[]{"v25", NULL}; 1537 const char *g_contained_v26[]{"v26", NULL}; 1538 const char *g_contained_v27[]{"v27", NULL}; 1539 const char *g_contained_v28[]{"v28", NULL}; 1540 const char *g_contained_v29[]{"v29", NULL}; 1541 const char *g_contained_v30[]{"v30", NULL}; 1542 const char *g_contained_v31[]{"v31", NULL}; 1543 1544 const char *g_invalidate_v0[]{"v0", "d0", "s0", NULL}; 1545 const char *g_invalidate_v1[]{"v1", "d1", "s1", NULL}; 1546 const char *g_invalidate_v2[]{"v2", "d2", "s2", NULL}; 1547 const char *g_invalidate_v3[]{"v3", "d3", "s3", NULL}; 1548 const char *g_invalidate_v4[]{"v4", "d4", "s4", NULL}; 1549 const char *g_invalidate_v5[]{"v5", "d5", "s5", NULL}; 1550 const char *g_invalidate_v6[]{"v6", "d6", "s6", NULL}; 1551 const char *g_invalidate_v7[]{"v7", "d7", "s7", NULL}; 1552 const char *g_invalidate_v8[]{"v8", "d8", "s8", NULL}; 1553 const char *g_invalidate_v9[]{"v9", "d9", "s9", NULL}; 1554 const char *g_invalidate_v10[]{"v10", "d10", "s10", NULL}; 1555 const char *g_invalidate_v11[]{"v11", "d11", "s11", NULL}; 1556 const char *g_invalidate_v12[]{"v12", "d12", "s12", NULL}; 1557 const char *g_invalidate_v13[]{"v13", "d13", "s13", NULL}; 1558 const char *g_invalidate_v14[]{"v14", "d14", "s14", NULL}; 1559 const char *g_invalidate_v15[]{"v15", "d15", "s15", NULL}; 1560 const char *g_invalidate_v16[]{"v16", "d16", "s16", NULL}; 1561 const char *g_invalidate_v17[]{"v17", "d17", "s17", NULL}; 1562 const char *g_invalidate_v18[]{"v18", "d18", "s18", NULL}; 1563 const char *g_invalidate_v19[]{"v19", "d19", "s19", NULL}; 1564 const char *g_invalidate_v20[]{"v20", "d20", "s20", NULL}; 1565 const char *g_invalidate_v21[]{"v21", "d21", "s21", NULL}; 1566 const char *g_invalidate_v22[]{"v22", "d22", "s22", NULL}; 1567 const char *g_invalidate_v23[]{"v23", "d23", "s23", NULL}; 1568 const char *g_invalidate_v24[]{"v24", "d24", "s24", NULL}; 1569 const char *g_invalidate_v25[]{"v25", "d25", "s25", NULL}; 1570 const char *g_invalidate_v26[]{"v26", "d26", "s26", NULL}; 1571 const char *g_invalidate_v27[]{"v27", "d27", "s27", NULL}; 1572 const char *g_invalidate_v28[]{"v28", "d28", "s28", NULL}; 1573 const char *g_invalidate_v29[]{"v29", "d29", "s29", NULL}; 1574 const char *g_invalidate_v30[]{"v30", "d30", "s30", NULL}; 1575 const char *g_invalidate_v31[]{"v31", "d31", "s31", NULL}; 1576 1577 #if defined(__arm64__) || defined(__aarch64__) 1578 #define VFP_V_OFFSET_IDX(idx) \ 1579 (offsetof(DNBArchMachARM64::FPU, __v) + (idx * 16) + \ 1580 offsetof(DNBArchMachARM64::Context, vfp)) 1581 #else 1582 #define VFP_V_OFFSET_IDX(idx) \ 1583 (offsetof(DNBArchMachARM64::FPU, opaque) + (idx * 16) + \ 1584 offsetof(DNBArchMachARM64::Context, vfp)) 1585 #endif 1586 #define VFP_OFFSET_NAME(reg) \ 1587 (offsetof(DNBArchMachARM64::FPU, reg) + \ 1588 offsetof(DNBArchMachARM64::Context, vfp)) 1589 #define EXC_OFFSET(reg) \ 1590 (offsetof(DNBArchMachARM64::EXC, reg) + \ 1591 offsetof(DNBArchMachARM64::Context, exc)) 1592 1593 //#define FLOAT_FORMAT Float 1594 #define DEFINE_VFP_V_IDX(idx) \ 1595 { \ 1596 e_regSetVFP, vfp_v##idx, "v" #idx, "q" #idx, Vector, VectorOfUInt8, 16, \ 1597 VFP_V_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_v##idx, \ 1598 INVALID_NUB_REGNUM, debugserver_vfp_v##idx, NULL, g_invalidate_v##idx \ 1599 } 1600 #define DEFINE_PSEUDO_VFP_S_IDX(idx) \ 1601 { \ 1602 e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, Float, 4, 0, \ 1603 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1604 INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \ 1605 } 1606 #define DEFINE_PSEUDO_VFP_D_IDX(idx) \ 1607 { \ 1608 e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, Float, 8, 0, \ 1609 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1610 INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \ 1611 } 1612 1613 // Floating point registers 1614 const DNBRegisterInfo DNBArchMachARM64::g_vfp_registers[] = { 1615 DEFINE_VFP_V_IDX(0), 1616 DEFINE_VFP_V_IDX(1), 1617 DEFINE_VFP_V_IDX(2), 1618 DEFINE_VFP_V_IDX(3), 1619 DEFINE_VFP_V_IDX(4), 1620 DEFINE_VFP_V_IDX(5), 1621 DEFINE_VFP_V_IDX(6), 1622 DEFINE_VFP_V_IDX(7), 1623 DEFINE_VFP_V_IDX(8), 1624 DEFINE_VFP_V_IDX(9), 1625 DEFINE_VFP_V_IDX(10), 1626 DEFINE_VFP_V_IDX(11), 1627 DEFINE_VFP_V_IDX(12), 1628 DEFINE_VFP_V_IDX(13), 1629 DEFINE_VFP_V_IDX(14), 1630 DEFINE_VFP_V_IDX(15), 1631 DEFINE_VFP_V_IDX(16), 1632 DEFINE_VFP_V_IDX(17), 1633 DEFINE_VFP_V_IDX(18), 1634 DEFINE_VFP_V_IDX(19), 1635 DEFINE_VFP_V_IDX(20), 1636 DEFINE_VFP_V_IDX(21), 1637 DEFINE_VFP_V_IDX(22), 1638 DEFINE_VFP_V_IDX(23), 1639 DEFINE_VFP_V_IDX(24), 1640 DEFINE_VFP_V_IDX(25), 1641 DEFINE_VFP_V_IDX(26), 1642 DEFINE_VFP_V_IDX(27), 1643 DEFINE_VFP_V_IDX(28), 1644 DEFINE_VFP_V_IDX(29), 1645 DEFINE_VFP_V_IDX(30), 1646 DEFINE_VFP_V_IDX(31), 1647 {e_regSetVFP, vfp_fpsr, "fpsr", NULL, Uint, Hex, 4, 1648 VFP_V_OFFSET_IDX(32) + 0, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1649 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}, 1650 {e_regSetVFP, vfp_fpcr, "fpcr", NULL, Uint, Hex, 4, 1651 VFP_V_OFFSET_IDX(32) + 4, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1652 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}, 1653 1654 DEFINE_PSEUDO_VFP_S_IDX(0), 1655 DEFINE_PSEUDO_VFP_S_IDX(1), 1656 DEFINE_PSEUDO_VFP_S_IDX(2), 1657 DEFINE_PSEUDO_VFP_S_IDX(3), 1658 DEFINE_PSEUDO_VFP_S_IDX(4), 1659 DEFINE_PSEUDO_VFP_S_IDX(5), 1660 DEFINE_PSEUDO_VFP_S_IDX(6), 1661 DEFINE_PSEUDO_VFP_S_IDX(7), 1662 DEFINE_PSEUDO_VFP_S_IDX(8), 1663 DEFINE_PSEUDO_VFP_S_IDX(9), 1664 DEFINE_PSEUDO_VFP_S_IDX(10), 1665 DEFINE_PSEUDO_VFP_S_IDX(11), 1666 DEFINE_PSEUDO_VFP_S_IDX(12), 1667 DEFINE_PSEUDO_VFP_S_IDX(13), 1668 DEFINE_PSEUDO_VFP_S_IDX(14), 1669 DEFINE_PSEUDO_VFP_S_IDX(15), 1670 DEFINE_PSEUDO_VFP_S_IDX(16), 1671 DEFINE_PSEUDO_VFP_S_IDX(17), 1672 DEFINE_PSEUDO_VFP_S_IDX(18), 1673 DEFINE_PSEUDO_VFP_S_IDX(19), 1674 DEFINE_PSEUDO_VFP_S_IDX(20), 1675 DEFINE_PSEUDO_VFP_S_IDX(21), 1676 DEFINE_PSEUDO_VFP_S_IDX(22), 1677 DEFINE_PSEUDO_VFP_S_IDX(23), 1678 DEFINE_PSEUDO_VFP_S_IDX(24), 1679 DEFINE_PSEUDO_VFP_S_IDX(25), 1680 DEFINE_PSEUDO_VFP_S_IDX(26), 1681 DEFINE_PSEUDO_VFP_S_IDX(27), 1682 DEFINE_PSEUDO_VFP_S_IDX(28), 1683 DEFINE_PSEUDO_VFP_S_IDX(29), 1684 DEFINE_PSEUDO_VFP_S_IDX(30), 1685 DEFINE_PSEUDO_VFP_S_IDX(31), 1686 1687 DEFINE_PSEUDO_VFP_D_IDX(0), 1688 DEFINE_PSEUDO_VFP_D_IDX(1), 1689 DEFINE_PSEUDO_VFP_D_IDX(2), 1690 DEFINE_PSEUDO_VFP_D_IDX(3), 1691 DEFINE_PSEUDO_VFP_D_IDX(4), 1692 DEFINE_PSEUDO_VFP_D_IDX(5), 1693 DEFINE_PSEUDO_VFP_D_IDX(6), 1694 DEFINE_PSEUDO_VFP_D_IDX(7), 1695 DEFINE_PSEUDO_VFP_D_IDX(8), 1696 DEFINE_PSEUDO_VFP_D_IDX(9), 1697 DEFINE_PSEUDO_VFP_D_IDX(10), 1698 DEFINE_PSEUDO_VFP_D_IDX(11), 1699 DEFINE_PSEUDO_VFP_D_IDX(12), 1700 DEFINE_PSEUDO_VFP_D_IDX(13), 1701 DEFINE_PSEUDO_VFP_D_IDX(14), 1702 DEFINE_PSEUDO_VFP_D_IDX(15), 1703 DEFINE_PSEUDO_VFP_D_IDX(16), 1704 DEFINE_PSEUDO_VFP_D_IDX(17), 1705 DEFINE_PSEUDO_VFP_D_IDX(18), 1706 DEFINE_PSEUDO_VFP_D_IDX(19), 1707 DEFINE_PSEUDO_VFP_D_IDX(20), 1708 DEFINE_PSEUDO_VFP_D_IDX(21), 1709 DEFINE_PSEUDO_VFP_D_IDX(22), 1710 DEFINE_PSEUDO_VFP_D_IDX(23), 1711 DEFINE_PSEUDO_VFP_D_IDX(24), 1712 DEFINE_PSEUDO_VFP_D_IDX(25), 1713 DEFINE_PSEUDO_VFP_D_IDX(26), 1714 DEFINE_PSEUDO_VFP_D_IDX(27), 1715 DEFINE_PSEUDO_VFP_D_IDX(28), 1716 DEFINE_PSEUDO_VFP_D_IDX(29), 1717 DEFINE_PSEUDO_VFP_D_IDX(30), 1718 DEFINE_PSEUDO_VFP_D_IDX(31) 1719 1720 }; 1721 1722 //_STRUCT_ARM_EXCEPTION_STATE64 1723 //{ 1724 // uint64_t far; /* Virtual Fault Address */ 1725 // uint32_t esr; /* Exception syndrome */ 1726 // uint32_t exception; /* number of arm exception taken */ 1727 //}; 1728 1729 // Exception registers 1730 const DNBRegisterInfo DNBArchMachARM64::g_exc_registers[] = { 1731 {e_regSetEXC, exc_far, "far", NULL, Uint, Hex, 8, EXC_OFFSET(__far), 1732 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1733 INVALID_NUB_REGNUM, NULL, NULL}, 1734 {e_regSetEXC, exc_esr, "esr", NULL, Uint, Hex, 4, EXC_OFFSET(__esr), 1735 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1736 INVALID_NUB_REGNUM, NULL, NULL}, 1737 {e_regSetEXC, exc_exception, "exception", NULL, Uint, Hex, 4, 1738 EXC_OFFSET(__exception), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1739 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}}; 1740 1741 // Number of registers in each register set 1742 const size_t DNBArchMachARM64::k_num_gpr_registers = 1743 sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo); 1744 const size_t DNBArchMachARM64::k_num_vfp_registers = 1745 sizeof(g_vfp_registers) / sizeof(DNBRegisterInfo); 1746 const size_t DNBArchMachARM64::k_num_exc_registers = 1747 sizeof(g_exc_registers) / sizeof(DNBRegisterInfo); 1748 const size_t DNBArchMachARM64::k_num_all_registers = 1749 k_num_gpr_registers + k_num_vfp_registers + k_num_exc_registers; 1750 1751 // Register set definitions. The first definitions at register set index 1752 // of zero is for all registers, followed by other registers sets. The 1753 // register information for the all register set need not be filled in. 1754 const DNBRegisterSetInfo DNBArchMachARM64::g_reg_sets[] = { 1755 {"ARM64 Registers", NULL, k_num_all_registers}, 1756 {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers}, 1757 {"Floating Point Registers", g_vfp_registers, k_num_vfp_registers}, 1758 {"Exception State Registers", g_exc_registers, k_num_exc_registers}}; 1759 // Total number of register sets for this architecture 1760 const size_t DNBArchMachARM64::k_num_register_sets = 1761 sizeof(g_reg_sets) / sizeof(DNBRegisterSetInfo); 1762 1763 const DNBRegisterSetInfo * 1764 DNBArchMachARM64::GetRegisterSetInfo(nub_size_t *num_reg_sets) { 1765 *num_reg_sets = k_num_register_sets; 1766 return g_reg_sets; 1767 } 1768 1769 bool DNBArchMachARM64::FixGenericRegisterNumber(uint32_t &set, uint32_t ®) { 1770 if (set == REGISTER_SET_GENERIC) { 1771 switch (reg) { 1772 case GENERIC_REGNUM_PC: // Program Counter 1773 set = e_regSetGPR; 1774 reg = gpr_pc; 1775 break; 1776 1777 case GENERIC_REGNUM_SP: // Stack Pointer 1778 set = e_regSetGPR; 1779 reg = gpr_sp; 1780 break; 1781 1782 case GENERIC_REGNUM_FP: // Frame Pointer 1783 set = e_regSetGPR; 1784 reg = gpr_fp; 1785 break; 1786 1787 case GENERIC_REGNUM_RA: // Return Address 1788 set = e_regSetGPR; 1789 reg = gpr_lr; 1790 break; 1791 1792 case GENERIC_REGNUM_FLAGS: // Processor flags register 1793 set = e_regSetGPR; 1794 reg = gpr_cpsr; 1795 break; 1796 1797 case GENERIC_REGNUM_ARG1: 1798 case GENERIC_REGNUM_ARG2: 1799 case GENERIC_REGNUM_ARG3: 1800 case GENERIC_REGNUM_ARG4: 1801 case GENERIC_REGNUM_ARG5: 1802 case GENERIC_REGNUM_ARG6: 1803 set = e_regSetGPR; 1804 reg = gpr_x0 + reg - GENERIC_REGNUM_ARG1; 1805 break; 1806 1807 default: 1808 return false; 1809 } 1810 } 1811 return true; 1812 } 1813 bool DNBArchMachARM64::GetRegisterValue(uint32_t set, uint32_t reg, 1814 DNBRegisterValue *value) { 1815 if (!FixGenericRegisterNumber(set, reg)) 1816 return false; 1817 1818 if (GetRegisterState(set, false) != KERN_SUCCESS) 1819 return false; 1820 1821 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1822 if (regInfo) { 1823 value->info = *regInfo; 1824 switch (set) { 1825 case e_regSetGPR: 1826 if (reg <= gpr_pc) { 1827 #if defined(__LP64__) 1828 if (reg == gpr_pc) 1829 value->value.uint64 = arm_thread_state64_get_pc (m_state.context.gpr); 1830 else if (reg == gpr_lr) 1831 value->value.uint64 = arm_thread_state64_get_lr (m_state.context.gpr); 1832 else if (reg == gpr_sp) 1833 value->value.uint64 = arm_thread_state64_get_sp (m_state.context.gpr); 1834 else if (reg == gpr_fp) 1835 value->value.uint64 = arm_thread_state64_get_fp (m_state.context.gpr); 1836 else 1837 value->value.uint64 = m_state.context.gpr.__x[reg]; 1838 #else 1839 value->value.uint64 = m_state.context.gpr.__x[reg]; 1840 #endif 1841 return true; 1842 } else if (reg == gpr_cpsr) { 1843 value->value.uint32 = m_state.context.gpr.__cpsr; 1844 return true; 1845 } 1846 break; 1847 1848 case e_regSetVFP: 1849 1850 if (reg >= vfp_v0 && reg <= vfp_v31) { 1851 #if defined(__arm64__) || defined(__aarch64__) 1852 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_v0], 1853 16); 1854 #else 1855 memcpy(&value->value.v_uint8, 1856 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), 1857 16); 1858 #endif 1859 return true; 1860 } else if (reg == vfp_fpsr) { 1861 #if defined(__arm64__) || defined(__aarch64__) 1862 memcpy(&value->value.uint32, &m_state.context.vfp.__fpsr, 4); 1863 #else 1864 memcpy(&value->value.uint32, 1865 ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0, 4); 1866 #endif 1867 return true; 1868 } else if (reg == vfp_fpcr) { 1869 #if defined(__arm64__) || defined(__aarch64__) 1870 memcpy(&value->value.uint32, &m_state.context.vfp.__fpcr, 4); 1871 #else 1872 memcpy(&value->value.uint32, 1873 ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 4, 4); 1874 #endif 1875 return true; 1876 } else if (reg >= vfp_s0 && reg <= vfp_s31) { 1877 #if defined(__arm64__) || defined(__aarch64__) 1878 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_s0], 1879 4); 1880 #else 1881 memcpy(&value->value.v_uint8, 1882 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), 1883 4); 1884 #endif 1885 return true; 1886 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 1887 #if defined(__arm64__) || defined(__aarch64__) 1888 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_d0], 1889 8); 1890 #else 1891 memcpy(&value->value.v_uint8, 1892 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), 1893 8); 1894 #endif 1895 return true; 1896 } 1897 break; 1898 1899 case e_regSetEXC: 1900 if (reg == exc_far) { 1901 value->value.uint64 = m_state.context.exc.__far; 1902 return true; 1903 } else if (reg == exc_esr) { 1904 value->value.uint32 = m_state.context.exc.__esr; 1905 return true; 1906 } else if (reg == exc_exception) { 1907 value->value.uint32 = m_state.context.exc.__exception; 1908 return true; 1909 } 1910 break; 1911 } 1912 } 1913 return false; 1914 } 1915 1916 bool DNBArchMachARM64::SetRegisterValue(uint32_t set, uint32_t reg, 1917 const DNBRegisterValue *value) { 1918 if (!FixGenericRegisterNumber(set, reg)) 1919 return false; 1920 1921 if (GetRegisterState(set, false) != KERN_SUCCESS) 1922 return false; 1923 1924 bool success = false; 1925 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1926 if (regInfo) { 1927 switch (set) { 1928 case e_regSetGPR: 1929 if (reg <= gpr_pc) { 1930 #if defined(__LP64__) 1931 uint64_t signed_value = value->value.uint64; 1932 #if __has_feature(ptrauth_calls) 1933 // The incoming value could be garbage. Strip it to avoid 1934 // trapping when it gets resigned in the thread state. 1935 signed_value = (uint64_t) ptrauth_strip((void*) signed_value, ptrauth_key_function_pointer); 1936 signed_value = (uint64_t) ptrauth_sign_unauthenticated((void*) signed_value, ptrauth_key_function_pointer, 0); 1937 #endif 1938 if (reg == gpr_pc) 1939 arm_thread_state64_set_pc_fptr (m_state.context.gpr, (void*) signed_value); 1940 else if (reg == gpr_lr) 1941 arm_thread_state64_set_lr_fptr (m_state.context.gpr, (void*) signed_value); 1942 else if (reg == gpr_sp) 1943 arm_thread_state64_set_sp (m_state.context.gpr, value->value.uint64); 1944 else if (reg == gpr_fp) 1945 arm_thread_state64_set_fp (m_state.context.gpr, value->value.uint64); 1946 else 1947 m_state.context.gpr.__x[reg] = value->value.uint64; 1948 #else 1949 m_state.context.gpr.__x[reg] = value->value.uint64; 1950 #endif 1951 success = true; 1952 } else if (reg == gpr_cpsr) { 1953 m_state.context.gpr.__cpsr = value->value.uint32; 1954 success = true; 1955 } 1956 break; 1957 1958 case e_regSetVFP: 1959 if (reg >= vfp_v0 && reg <= vfp_v31) { 1960 #if defined(__arm64__) || defined(__aarch64__) 1961 memcpy(&m_state.context.vfp.__v[reg - vfp_v0], &value->value.v_uint8, 1962 16); 1963 #else 1964 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), 1965 &value->value.v_uint8, 16); 1966 #endif 1967 success = true; 1968 } else if (reg == vfp_fpsr) { 1969 #if defined(__arm64__) || defined(__aarch64__) 1970 memcpy(&m_state.context.vfp.__fpsr, &value->value.uint32, 4); 1971 #else 1972 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0, 1973 &value->value.uint32, 4); 1974 #endif 1975 success = true; 1976 } else if (reg == vfp_fpcr) { 1977 #if defined(__arm64__) || defined(__aarch64__) 1978 memcpy(&m_state.context.vfp.__fpcr, &value->value.uint32, 4); 1979 #else 1980 memcpy(((uint8_t *)m_state.context.vfp.opaque) + (32 * 16) + 4, 1981 &value->value.uint32, 4); 1982 #endif 1983 success = true; 1984 } else if (reg >= vfp_s0 && reg <= vfp_s31) { 1985 #if defined(__arm64__) || defined(__aarch64__) 1986 memcpy(&m_state.context.vfp.__v[reg - vfp_s0], &value->value.v_uint8, 1987 4); 1988 #else 1989 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), 1990 &value->value.v_uint8, 4); 1991 #endif 1992 success = true; 1993 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 1994 #if defined(__arm64__) || defined(__aarch64__) 1995 memcpy(&m_state.context.vfp.__v[reg - vfp_d0], &value->value.v_uint8, 1996 8); 1997 #else 1998 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), 1999 &value->value.v_uint8, 8); 2000 #endif 2001 success = true; 2002 } 2003 break; 2004 2005 case e_regSetEXC: 2006 if (reg == exc_far) { 2007 m_state.context.exc.__far = value->value.uint64; 2008 success = true; 2009 } else if (reg == exc_esr) { 2010 m_state.context.exc.__esr = value->value.uint32; 2011 success = true; 2012 } else if (reg == exc_exception) { 2013 m_state.context.exc.__exception = value->value.uint32; 2014 success = true; 2015 } 2016 break; 2017 } 2018 } 2019 if (success) 2020 return SetRegisterState(set) == KERN_SUCCESS; 2021 return false; 2022 } 2023 2024 kern_return_t DNBArchMachARM64::GetRegisterState(int set, bool force) { 2025 switch (set) { 2026 case e_regSetALL: 2027 return GetGPRState(force) | GetVFPState(force) | GetEXCState(force) | 2028 GetDBGState(force); 2029 case e_regSetGPR: 2030 return GetGPRState(force); 2031 case e_regSetVFP: 2032 return GetVFPState(force); 2033 case e_regSetEXC: 2034 return GetEXCState(force); 2035 case e_regSetDBG: 2036 return GetDBGState(force); 2037 default: 2038 break; 2039 } 2040 return KERN_INVALID_ARGUMENT; 2041 } 2042 2043 kern_return_t DNBArchMachARM64::SetRegisterState(int set) { 2044 // Make sure we have a valid context to set. 2045 kern_return_t err = GetRegisterState(set, false); 2046 if (err != KERN_SUCCESS) 2047 return err; 2048 2049 switch (set) { 2050 case e_regSetALL: 2051 return SetGPRState() | SetVFPState() | SetEXCState() | SetDBGState(false); 2052 case e_regSetGPR: 2053 return SetGPRState(); 2054 case e_regSetVFP: 2055 return SetVFPState(); 2056 case e_regSetEXC: 2057 return SetEXCState(); 2058 case e_regSetDBG: 2059 return SetDBGState(false); 2060 default: 2061 break; 2062 } 2063 return KERN_INVALID_ARGUMENT; 2064 } 2065 2066 bool DNBArchMachARM64::RegisterSetStateIsValid(int set) const { 2067 return m_state.RegsAreValid(set); 2068 } 2069 2070 nub_size_t DNBArchMachARM64::GetRegisterContext(void *buf, nub_size_t buf_len) { 2071 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 2072 sizeof(m_state.context.exc); 2073 2074 if (buf && buf_len) { 2075 if (size > buf_len) 2076 size = buf_len; 2077 2078 bool force = false; 2079 if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force)) 2080 return 0; 2081 2082 // Copy each struct individually to avoid any padding that might be between 2083 // the structs in m_state.context 2084 uint8_t *p = (uint8_t *)buf; 2085 ::memcpy(p, &m_state.context.gpr, sizeof(m_state.context.gpr)); 2086 p += sizeof(m_state.context.gpr); 2087 ::memcpy(p, &m_state.context.vfp, sizeof(m_state.context.vfp)); 2088 p += sizeof(m_state.context.vfp); 2089 ::memcpy(p, &m_state.context.exc, sizeof(m_state.context.exc)); 2090 p += sizeof(m_state.context.exc); 2091 2092 size_t bytes_written = p - (uint8_t *)buf; 2093 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2094 assert(bytes_written == size); 2095 } 2096 DNBLogThreadedIf( 2097 LOG_THREAD, 2098 "DNBArchMachARM64::GetRegisterContext (buf = %p, len = %zu) => %zu", buf, 2099 buf_len, size); 2100 // Return the size of the register context even if NULL was passed in 2101 return size; 2102 } 2103 2104 nub_size_t DNBArchMachARM64::SetRegisterContext(const void *buf, 2105 nub_size_t buf_len) { 2106 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 2107 sizeof(m_state.context.exc); 2108 2109 if (buf == NULL || buf_len == 0) 2110 size = 0; 2111 2112 if (size) { 2113 if (size > buf_len) 2114 size = buf_len; 2115 2116 // Copy each struct individually to avoid any padding that might be between 2117 // the structs in m_state.context 2118 uint8_t *p = (uint8_t *)buf; 2119 ::memcpy(&m_state.context.gpr, p, sizeof(m_state.context.gpr)); 2120 p += sizeof(m_state.context.gpr); 2121 ::memcpy(&m_state.context.vfp, p, sizeof(m_state.context.vfp)); 2122 p += sizeof(m_state.context.vfp); 2123 ::memcpy(&m_state.context.exc, p, sizeof(m_state.context.exc)); 2124 p += sizeof(m_state.context.exc); 2125 2126 size_t bytes_written = p - (uint8_t *)buf; 2127 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2128 assert(bytes_written == size); 2129 SetGPRState(); 2130 SetVFPState(); 2131 SetEXCState(); 2132 } 2133 DNBLogThreadedIf( 2134 LOG_THREAD, 2135 "DNBArchMachARM64::SetRegisterContext (buf = %p, len = %zu) => %zu", buf, 2136 buf_len, size); 2137 return size; 2138 } 2139 2140 uint32_t DNBArchMachARM64::SaveRegisterState() { 2141 kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber()); 2142 DNBLogThreadedIf( 2143 LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u " 2144 "(SetGPRState() for stop_count = %u)", 2145 m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount()); 2146 2147 // Always re-read the registers because above we call thread_abort_safely(); 2148 bool force = true; 2149 2150 if ((kret = GetGPRState(force)) != KERN_SUCCESS) { 2151 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () " 2152 "error: GPR regs failed to read: %u ", 2153 kret); 2154 } else if ((kret = GetVFPState(force)) != KERN_SUCCESS) { 2155 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () " 2156 "error: %s regs failed to read: %u", 2157 "VFP", kret); 2158 } else { 2159 const uint32_t save_id = GetNextRegisterStateSaveID(); 2160 m_saved_register_states[save_id] = m_state.context; 2161 return save_id; 2162 } 2163 return UINT32_MAX; 2164 } 2165 2166 bool DNBArchMachARM64::RestoreRegisterState(uint32_t save_id) { 2167 SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id); 2168 if (pos != m_saved_register_states.end()) { 2169 m_state.context.gpr = pos->second.gpr; 2170 m_state.context.vfp = pos->second.vfp; 2171 kern_return_t kret; 2172 bool success = true; 2173 if ((kret = SetGPRState()) != KERN_SUCCESS) { 2174 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState " 2175 "(save_id = %u) error: GPR regs failed to " 2176 "write: %u", 2177 save_id, kret); 2178 success = false; 2179 } else if ((kret = SetVFPState()) != KERN_SUCCESS) { 2180 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState " 2181 "(save_id = %u) error: %s regs failed to " 2182 "write: %u", 2183 save_id, "VFP", kret); 2184 success = false; 2185 } 2186 m_saved_register_states.erase(pos); 2187 return success; 2188 } 2189 return false; 2190 } 2191 2192 #endif // #if defined (ARM_THREAD_STATE64_COUNT) 2193 #endif // #if defined (__arm__) || defined (__arm64__) || defined (__aarch64__) 2194