1 //===-- DNBArchImplARM64.cpp ------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Created by Greg Clayton on 6/25/07. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #if defined(__arm__) || defined(__arm64__) || defined(__aarch64__) 14 15 #include "MacOSX/arm64/DNBArchImplARM64.h" 16 17 #if defined(ARM_THREAD_STATE64_COUNT) 18 19 #include "DNB.h" 20 #include "DNBBreakpoint.h" 21 #include "DNBLog.h" 22 #include "DNBRegisterInfo.h" 23 #include "MacOSX/MachProcess.h" 24 #include "MacOSX/MachThread.h" 25 26 #include <inttypes.h> 27 #include <sys/sysctl.h> 28 29 #if __has_feature(ptrauth_calls) 30 #include <ptrauth.h> 31 #endif 32 33 // Break only in privileged or user mode 34 // (PAC bits in the DBGWVRn_EL1 watchpoint control register) 35 #define S_USER ((uint32_t)(2u << 1)) 36 37 #define BCR_ENABLE ((uint32_t)(1u)) 38 #define WCR_ENABLE ((uint32_t)(1u)) 39 40 // Watchpoint load/store 41 // (LSC bits in the DBGWVRn_EL1 watchpoint control register) 42 #define WCR_LOAD ((uint32_t)(1u << 3)) 43 #define WCR_STORE ((uint32_t)(1u << 4)) 44 45 // Enable breakpoint, watchpoint, and vector catch debug exceptions. 46 // (MDE bit in the MDSCR_EL1 register. Equivalent to the MDBGen bit in 47 // DBGDSCRext in Aarch32) 48 #define MDE_ENABLE ((uint32_t)(1u << 15)) 49 50 // Single instruction step 51 // (SS bit in the MDSCR_EL1 register) 52 #define SS_ENABLE ((uint32_t)(1u)) 53 54 static const uint8_t g_arm64_breakpoint_opcode[] = { 55 0x00, 0x00, 0x20, 0xD4}; // "brk #0", 0xd4200000 in BE byte order 56 57 // If we need to set one logical watchpoint by using 58 // two hardware watchpoint registers, the watchpoint 59 // will be split into a "high" and "low" watchpoint. 60 // Record both of them in the LoHi array. 61 62 // It's safe to initialize to all 0's since 63 // hi > lo and therefore LoHi[i] cannot be 0. 64 static uint32_t LoHi[16] = {0}; 65 66 void DNBArchMachARM64::Initialize() { 67 DNBArchPluginInfo arch_plugin_info = { 68 CPU_TYPE_ARM64, DNBArchMachARM64::Create, 69 DNBArchMachARM64::GetRegisterSetInfo, 70 DNBArchMachARM64::SoftwareBreakpointOpcode}; 71 72 // Register this arch plug-in with the main protocol class 73 DNBArchProtocol::RegisterArchPlugin(arch_plugin_info); 74 75 DNBArchPluginInfo arch_plugin_info_32 = { 76 CPU_TYPE_ARM64_32, DNBArchMachARM64::Create, 77 DNBArchMachARM64::GetRegisterSetInfo, 78 DNBArchMachARM64::SoftwareBreakpointOpcode}; 79 80 // Register this arch plug-in with the main protocol class 81 DNBArchProtocol::RegisterArchPlugin(arch_plugin_info_32); 82 } 83 84 DNBArchProtocol *DNBArchMachARM64::Create(MachThread *thread) { 85 DNBArchMachARM64 *obj = new DNBArchMachARM64(thread); 86 87 return obj; 88 } 89 90 const uint8_t * 91 DNBArchMachARM64::SoftwareBreakpointOpcode(nub_size_t byte_size) { 92 return g_arm64_breakpoint_opcode; 93 } 94 95 uint32_t DNBArchMachARM64::GetCPUType() { return CPU_TYPE_ARM64; } 96 97 uint64_t DNBArchMachARM64::GetPC(uint64_t failValue) { 98 // Get program counter 99 if (GetGPRState(false) == KERN_SUCCESS) 100 #if defined(__LP64__) 101 return arm_thread_state64_get_pc(m_state.context.gpr); 102 #else 103 return m_state.context.gpr.__pc; 104 #endif 105 return failValue; 106 } 107 108 kern_return_t DNBArchMachARM64::SetPC(uint64_t value) { 109 // Get program counter 110 kern_return_t err = GetGPRState(false); 111 if (err == KERN_SUCCESS) { 112 #if defined(__LP64__) 113 #if __has_feature(ptrauth_calls) 114 // The incoming value could be garbage. Strip it to avoid 115 // trapping when it gets resigned in the thread state. 116 value = (uint64_t) ptrauth_strip((void*) value, ptrauth_key_function_pointer); 117 value = (uint64_t) ptrauth_sign_unauthenticated((void*) value, ptrauth_key_function_pointer, 0); 118 #endif 119 arm_thread_state64_set_pc_fptr (m_state.context.gpr, (void*) value); 120 #else 121 m_state.context.gpr.__pc = value; 122 #endif 123 err = SetGPRState(); 124 } 125 return err == KERN_SUCCESS; 126 } 127 128 uint64_t DNBArchMachARM64::GetSP(uint64_t failValue) { 129 // Get stack pointer 130 if (GetGPRState(false) == KERN_SUCCESS) 131 #if defined(__LP64__) 132 return arm_thread_state64_get_sp(m_state.context.gpr); 133 #else 134 return m_state.context.gpr.__sp; 135 #endif 136 return failValue; 137 } 138 139 kern_return_t DNBArchMachARM64::GetGPRState(bool force) { 140 int set = e_regSetGPR; 141 // Check if we have valid cached registers 142 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 143 return KERN_SUCCESS; 144 145 // Read the registers from our thread 146 mach_msg_type_number_t count = e_regSetGPRCount; 147 kern_return_t kret = 148 ::thread_get_state(m_thread->MachPortNumber(), ARM_THREAD_STATE64, 149 (thread_state_t)&m_state.context.gpr, &count); 150 if (DNBLogEnabledForAny(LOG_THREAD)) { 151 uint64_t *x = &m_state.context.gpr.__x[0]; 152 DNBLogThreaded( 153 "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count = %u) regs" 154 "\n x0=%16.16llx" 155 "\n x1=%16.16llx" 156 "\n x2=%16.16llx" 157 "\n x3=%16.16llx" 158 "\n x4=%16.16llx" 159 "\n x5=%16.16llx" 160 "\n x6=%16.16llx" 161 "\n x7=%16.16llx" 162 "\n x8=%16.16llx" 163 "\n x9=%16.16llx" 164 "\n x10=%16.16llx" 165 "\n x11=%16.16llx" 166 "\n x12=%16.16llx" 167 "\n x13=%16.16llx" 168 "\n x14=%16.16llx" 169 "\n x15=%16.16llx" 170 "\n x16=%16.16llx" 171 "\n x17=%16.16llx" 172 "\n x18=%16.16llx" 173 "\n x19=%16.16llx" 174 "\n x20=%16.16llx" 175 "\n x21=%16.16llx" 176 "\n x22=%16.16llx" 177 "\n x23=%16.16llx" 178 "\n x24=%16.16llx" 179 "\n x25=%16.16llx" 180 "\n x26=%16.16llx" 181 "\n x27=%16.16llx" 182 "\n x28=%16.16llx" 183 "\n fp=%16.16llx" 184 "\n lr=%16.16llx" 185 "\n sp=%16.16llx" 186 "\n pc=%16.16llx" 187 "\n cpsr=%8.8x", 188 m_thread->MachPortNumber(), e_regSetGPR, e_regSetGPRCount, kret, count, 189 x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[0], x[11], 190 x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], x[20], x[21], 191 x[22], x[23], x[24], x[25], x[26], x[27], x[28], 192 #if defined(__LP64__) 193 (uint64_t) arm_thread_state64_get_fp (m_state.context.gpr), 194 (uint64_t) arm_thread_state64_get_lr (m_state.context.gpr), 195 (uint64_t) arm_thread_state64_get_sp (m_state.context.gpr), 196 (uint64_t) arm_thread_state64_get_pc (m_state.context.gpr), 197 #else 198 m_state.context.gpr.__fp, m_state.context.gpr.__lr, 199 m_state.context.gpr.__sp, m_state.context.gpr.__pc, 200 #endif 201 m_state.context.gpr.__cpsr); 202 } 203 m_state.SetError(set, Read, kret); 204 return kret; 205 } 206 207 kern_return_t DNBArchMachARM64::GetVFPState(bool force) { 208 int set = e_regSetVFP; 209 // Check if we have valid cached registers 210 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 211 return KERN_SUCCESS; 212 213 // Read the registers from our thread 214 mach_msg_type_number_t count = e_regSetVFPCount; 215 kern_return_t kret = 216 ::thread_get_state(m_thread->MachPortNumber(), ARM_NEON_STATE64, 217 (thread_state_t)&m_state.context.vfp, &count); 218 if (DNBLogEnabledForAny(LOG_THREAD)) { 219 #if defined(__arm64__) || defined(__aarch64__) 220 DNBLogThreaded( 221 "thread_get_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs" 222 "\n q0 = 0x%16.16llx%16.16llx" 223 "\n q1 = 0x%16.16llx%16.16llx" 224 "\n q2 = 0x%16.16llx%16.16llx" 225 "\n q3 = 0x%16.16llx%16.16llx" 226 "\n q4 = 0x%16.16llx%16.16llx" 227 "\n q5 = 0x%16.16llx%16.16llx" 228 "\n q6 = 0x%16.16llx%16.16llx" 229 "\n q7 = 0x%16.16llx%16.16llx" 230 "\n q8 = 0x%16.16llx%16.16llx" 231 "\n q9 = 0x%16.16llx%16.16llx" 232 "\n q10 = 0x%16.16llx%16.16llx" 233 "\n q11 = 0x%16.16llx%16.16llx" 234 "\n q12 = 0x%16.16llx%16.16llx" 235 "\n q13 = 0x%16.16llx%16.16llx" 236 "\n q14 = 0x%16.16llx%16.16llx" 237 "\n q15 = 0x%16.16llx%16.16llx" 238 "\n q16 = 0x%16.16llx%16.16llx" 239 "\n q17 = 0x%16.16llx%16.16llx" 240 "\n q18 = 0x%16.16llx%16.16llx" 241 "\n q19 = 0x%16.16llx%16.16llx" 242 "\n q20 = 0x%16.16llx%16.16llx" 243 "\n q21 = 0x%16.16llx%16.16llx" 244 "\n q22 = 0x%16.16llx%16.16llx" 245 "\n q23 = 0x%16.16llx%16.16llx" 246 "\n q24 = 0x%16.16llx%16.16llx" 247 "\n q25 = 0x%16.16llx%16.16llx" 248 "\n q26 = 0x%16.16llx%16.16llx" 249 "\n q27 = 0x%16.16llx%16.16llx" 250 "\n q28 = 0x%16.16llx%16.16llx" 251 "\n q29 = 0x%16.16llx%16.16llx" 252 "\n q30 = 0x%16.16llx%16.16llx" 253 "\n q31 = 0x%16.16llx%16.16llx" 254 "\n fpsr = 0x%8.8x" 255 "\n fpcr = 0x%8.8x\n\n", 256 m_thread->MachPortNumber(), e_regSetVFP, e_regSetVFPCount, kret, count, 257 ((uint64_t *)&m_state.context.vfp.__v[0])[0], 258 ((uint64_t *)&m_state.context.vfp.__v[0])[1], 259 ((uint64_t *)&m_state.context.vfp.__v[1])[0], 260 ((uint64_t *)&m_state.context.vfp.__v[1])[1], 261 ((uint64_t *)&m_state.context.vfp.__v[2])[0], 262 ((uint64_t *)&m_state.context.vfp.__v[2])[1], 263 ((uint64_t *)&m_state.context.vfp.__v[3])[0], 264 ((uint64_t *)&m_state.context.vfp.__v[3])[1], 265 ((uint64_t *)&m_state.context.vfp.__v[4])[0], 266 ((uint64_t *)&m_state.context.vfp.__v[4])[1], 267 ((uint64_t *)&m_state.context.vfp.__v[5])[0], 268 ((uint64_t *)&m_state.context.vfp.__v[5])[1], 269 ((uint64_t *)&m_state.context.vfp.__v[6])[0], 270 ((uint64_t *)&m_state.context.vfp.__v[6])[1], 271 ((uint64_t *)&m_state.context.vfp.__v[7])[0], 272 ((uint64_t *)&m_state.context.vfp.__v[7])[1], 273 ((uint64_t *)&m_state.context.vfp.__v[8])[0], 274 ((uint64_t *)&m_state.context.vfp.__v[8])[1], 275 ((uint64_t *)&m_state.context.vfp.__v[9])[0], 276 ((uint64_t *)&m_state.context.vfp.__v[9])[1], 277 ((uint64_t *)&m_state.context.vfp.__v[10])[0], 278 ((uint64_t *)&m_state.context.vfp.__v[10])[1], 279 ((uint64_t *)&m_state.context.vfp.__v[11])[0], 280 ((uint64_t *)&m_state.context.vfp.__v[11])[1], 281 ((uint64_t *)&m_state.context.vfp.__v[12])[0], 282 ((uint64_t *)&m_state.context.vfp.__v[12])[1], 283 ((uint64_t *)&m_state.context.vfp.__v[13])[0], 284 ((uint64_t *)&m_state.context.vfp.__v[13])[1], 285 ((uint64_t *)&m_state.context.vfp.__v[14])[0], 286 ((uint64_t *)&m_state.context.vfp.__v[14])[1], 287 ((uint64_t *)&m_state.context.vfp.__v[15])[0], 288 ((uint64_t *)&m_state.context.vfp.__v[15])[1], 289 ((uint64_t *)&m_state.context.vfp.__v[16])[0], 290 ((uint64_t *)&m_state.context.vfp.__v[16])[1], 291 ((uint64_t *)&m_state.context.vfp.__v[17])[0], 292 ((uint64_t *)&m_state.context.vfp.__v[17])[1], 293 ((uint64_t *)&m_state.context.vfp.__v[18])[0], 294 ((uint64_t *)&m_state.context.vfp.__v[18])[1], 295 ((uint64_t *)&m_state.context.vfp.__v[19])[0], 296 ((uint64_t *)&m_state.context.vfp.__v[19])[1], 297 ((uint64_t *)&m_state.context.vfp.__v[20])[0], 298 ((uint64_t *)&m_state.context.vfp.__v[20])[1], 299 ((uint64_t *)&m_state.context.vfp.__v[21])[0], 300 ((uint64_t *)&m_state.context.vfp.__v[21])[1], 301 ((uint64_t *)&m_state.context.vfp.__v[22])[0], 302 ((uint64_t *)&m_state.context.vfp.__v[22])[1], 303 ((uint64_t *)&m_state.context.vfp.__v[23])[0], 304 ((uint64_t *)&m_state.context.vfp.__v[23])[1], 305 ((uint64_t *)&m_state.context.vfp.__v[24])[0], 306 ((uint64_t *)&m_state.context.vfp.__v[24])[1], 307 ((uint64_t *)&m_state.context.vfp.__v[25])[0], 308 ((uint64_t *)&m_state.context.vfp.__v[25])[1], 309 ((uint64_t *)&m_state.context.vfp.__v[26])[0], 310 ((uint64_t *)&m_state.context.vfp.__v[26])[1], 311 ((uint64_t *)&m_state.context.vfp.__v[27])[0], 312 ((uint64_t *)&m_state.context.vfp.__v[27])[1], 313 ((uint64_t *)&m_state.context.vfp.__v[28])[0], 314 ((uint64_t *)&m_state.context.vfp.__v[28])[1], 315 ((uint64_t *)&m_state.context.vfp.__v[29])[0], 316 ((uint64_t *)&m_state.context.vfp.__v[29])[1], 317 ((uint64_t *)&m_state.context.vfp.__v[30])[0], 318 ((uint64_t *)&m_state.context.vfp.__v[30])[1], 319 ((uint64_t *)&m_state.context.vfp.__v[31])[0], 320 ((uint64_t *)&m_state.context.vfp.__v[31])[1], 321 m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr); 322 #endif 323 } 324 m_state.SetError(set, Read, kret); 325 return kret; 326 } 327 328 kern_return_t DNBArchMachARM64::GetEXCState(bool force) { 329 int set = e_regSetEXC; 330 // Check if we have valid cached registers 331 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 332 return KERN_SUCCESS; 333 334 // Read the registers from our thread 335 mach_msg_type_number_t count = e_regSetEXCCount; 336 kern_return_t kret = 337 ::thread_get_state(m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, 338 (thread_state_t)&m_state.context.exc, &count); 339 m_state.SetError(set, Read, kret); 340 return kret; 341 } 342 343 static void DumpDBGState(const arm_debug_state_t &dbg) { 344 uint32_t i = 0; 345 for (i = 0; i < 16; i++) 346 DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } " 347 "WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }", 348 i, i, dbg.__bvr[i], dbg.__bcr[i], i, i, dbg.__wvr[i], 349 dbg.__wcr[i]); 350 } 351 352 kern_return_t DNBArchMachARM64::GetDBGState(bool force) { 353 int set = e_regSetDBG; 354 355 // Check if we have valid cached registers 356 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 357 return KERN_SUCCESS; 358 359 // Read the registers from our thread 360 mach_msg_type_number_t count = e_regSetDBGCount; 361 kern_return_t kret = 362 ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64, 363 (thread_state_t)&m_state.dbg, &count); 364 m_state.SetError(set, Read, kret); 365 366 return kret; 367 } 368 369 kern_return_t DNBArchMachARM64::SetGPRState() { 370 int set = e_regSetGPR; 371 kern_return_t kret = ::thread_set_state( 372 m_thread->MachPortNumber(), ARM_THREAD_STATE64, 373 (thread_state_t)&m_state.context.gpr, e_regSetGPRCount); 374 m_state.SetError(set, Write, 375 kret); // Set the current write error for this register set 376 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 377 // state in case registers are read 378 // back differently 379 return kret; // Return the error code 380 } 381 382 kern_return_t DNBArchMachARM64::SetVFPState() { 383 int set = e_regSetVFP; 384 kern_return_t kret = ::thread_set_state( 385 m_thread->MachPortNumber(), ARM_NEON_STATE64, 386 (thread_state_t)&m_state.context.vfp, e_regSetVFPCount); 387 m_state.SetError(set, Write, 388 kret); // Set the current write error for this register set 389 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 390 // state in case registers are read 391 // back differently 392 return kret; // Return the error code 393 } 394 395 kern_return_t DNBArchMachARM64::SetEXCState() { 396 int set = e_regSetEXC; 397 kern_return_t kret = ::thread_set_state( 398 m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, 399 (thread_state_t)&m_state.context.exc, e_regSetEXCCount); 400 m_state.SetError(set, Write, 401 kret); // Set the current write error for this register set 402 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 403 // state in case registers are read 404 // back differently 405 return kret; // Return the error code 406 } 407 408 kern_return_t DNBArchMachARM64::SetDBGState(bool also_set_on_task) { 409 int set = e_regSetDBG; 410 kern_return_t kret = 411 ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64, 412 (thread_state_t)&m_state.dbg, e_regSetDBGCount); 413 if (also_set_on_task) { 414 kern_return_t task_kret = task_set_state( 415 m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE64, 416 (thread_state_t)&m_state.dbg, e_regSetDBGCount); 417 if (task_kret != KERN_SUCCESS) 418 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::SetDBGState failed " 419 "to set debug control register state: " 420 "0x%8.8x.", 421 task_kret); 422 } 423 m_state.SetError(set, Write, 424 kret); // Set the current write error for this register set 425 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 426 // state in case registers are read 427 // back differently 428 429 return kret; // Return the error code 430 } 431 432 void DNBArchMachARM64::ThreadWillResume() { 433 // Do we need to step this thread? If so, let the mach thread tell us so. 434 if (m_thread->IsStepping()) { 435 EnableHardwareSingleStep(true); 436 } 437 438 // Disable the triggered watchpoint temporarily before we resume. 439 // Plus, we try to enable hardware single step to execute past the instruction 440 // which triggered our watchpoint. 441 if (m_watchpoint_did_occur) { 442 if (m_watchpoint_hw_index >= 0) { 443 kern_return_t kret = GetDBGState(false); 444 if (kret == KERN_SUCCESS && 445 !IsWatchpointEnabled(m_state.dbg, m_watchpoint_hw_index)) { 446 // The watchpoint might have been disabled by the user. We don't need 447 // to do anything at all 448 // to enable hardware single stepping. 449 m_watchpoint_did_occur = false; 450 m_watchpoint_hw_index = -1; 451 return; 452 } 453 454 DisableHardwareWatchpoint(m_watchpoint_hw_index, false); 455 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 456 "DisableHardwareWatchpoint(%d) called", 457 m_watchpoint_hw_index); 458 459 // Enable hardware single step to move past the watchpoint-triggering 460 // instruction. 461 m_watchpoint_resume_single_step_enabled = 462 (EnableHardwareSingleStep(true) == KERN_SUCCESS); 463 464 // If we are not able to enable single step to move past the 465 // watchpoint-triggering instruction, 466 // at least we should reset the two watchpoint member variables so that 467 // the next time around 468 // this callback function is invoked, the enclosing logical branch is 469 // skipped. 470 if (!m_watchpoint_resume_single_step_enabled) { 471 // Reset the two watchpoint member variables. 472 m_watchpoint_did_occur = false; 473 m_watchpoint_hw_index = -1; 474 DNBLogThreadedIf( 475 LOG_WATCHPOINTS, 476 "DNBArchMachARM::ThreadWillResume() failed to enable single step"); 477 } else 478 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 479 "succeeded to enable single step"); 480 } 481 } 482 } 483 484 bool DNBArchMachARM64::NotifyException(MachException::Data &exc) { 485 486 switch (exc.exc_type) { 487 default: 488 break; 489 case EXC_BREAKPOINT: 490 if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_DA_DEBUG) { 491 // The data break address is passed as exc_data[1]. 492 nub_addr_t addr = exc.exc_data[1]; 493 // Find the hardware index with the side effect of possibly massaging the 494 // addr to return the starting address as seen from the debugger side. 495 uint32_t hw_index = GetHardwareWatchpointHit(addr); 496 497 // One logical watchpoint was split into two watchpoint locations because 498 // it was too big. If the watchpoint exception is indicating the 2nd half 499 // of the two-parter, find the address of the 1st half and report that -- 500 // that's what lldb is going to expect to see. 501 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 502 "watchpoint %d was hit on address " 503 "0x%llx", 504 hw_index, (uint64_t)addr); 505 const int num_watchpoints = NumSupportedHardwareWatchpoints(); 506 for (int i = 0; i < num_watchpoints; i++) { 507 if (LoHi[i] != 0 && LoHi[i] == hw_index && LoHi[i] != i && 508 GetWatchpointAddressByIndex(i) != INVALID_NUB_ADDRESS) { 509 addr = GetWatchpointAddressByIndex(i); 510 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 511 "It is a linked watchpoint; " 512 "rewritten to index %d addr 0x%llx", 513 LoHi[i], (uint64_t)addr); 514 } 515 } 516 517 if (hw_index != INVALID_NUB_HW_INDEX) { 518 m_watchpoint_did_occur = true; 519 m_watchpoint_hw_index = hw_index; 520 exc.exc_data[1] = addr; 521 // Piggyback the hw_index in the exc.data. 522 exc.exc_data.push_back(hw_index); 523 } 524 525 return true; 526 } 527 break; 528 } 529 return false; 530 } 531 532 bool DNBArchMachARM64::ThreadDidStop() { 533 bool success = true; 534 535 m_state.InvalidateAllRegisterStates(); 536 537 if (m_watchpoint_resume_single_step_enabled) { 538 // Great! We now disable the hardware single step as well as re-enable the 539 // hardware watchpoint. 540 // See also ThreadWillResume(). 541 if (EnableHardwareSingleStep(false) == KERN_SUCCESS) { 542 if (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0) { 543 ReenableHardwareWatchpoint(m_watchpoint_hw_index); 544 m_watchpoint_resume_single_step_enabled = false; 545 m_watchpoint_did_occur = false; 546 m_watchpoint_hw_index = -1; 547 } else { 548 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 549 "is true but (m_watchpoint_did_occur && " 550 "m_watchpoint_hw_index >= 0) does not hold!"); 551 } 552 } else { 553 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 554 "is true but unable to disable single step!"); 555 } 556 } 557 558 // Are we stepping a single instruction? 559 if (GetGPRState(true) == KERN_SUCCESS) { 560 // We are single stepping, was this the primary thread? 561 if (m_thread->IsStepping()) { 562 // This was the primary thread, we need to clear the trace 563 // bit if so. 564 success = EnableHardwareSingleStep(false) == KERN_SUCCESS; 565 } else { 566 // The MachThread will automatically restore the suspend count 567 // in ThreadDidStop(), so we don't need to do anything here if 568 // we weren't the primary thread the last time 569 } 570 } 571 return success; 572 } 573 574 // Set the single step bit in the processor status register. 575 kern_return_t DNBArchMachARM64::EnableHardwareSingleStep(bool enable) { 576 DNBError err; 577 DNBLogThreadedIf(LOG_STEP, "%s( enable = %d )", __FUNCTION__, enable); 578 579 err = GetGPRState(false); 580 581 if (err.Fail()) { 582 err.LogThreaded("%s: failed to read the GPR registers", __FUNCTION__); 583 return err.Status(); 584 } 585 586 err = GetDBGState(false); 587 588 if (err.Fail()) { 589 err.LogThreaded("%s: failed to read the DBG registers", __FUNCTION__); 590 return err.Status(); 591 } 592 593 if (enable) { 594 DNBLogThreadedIf(LOG_STEP, 595 "%s: Setting MDSCR_EL1 Single Step bit at pc 0x%llx", 596 #if defined(__LP64__) 597 __FUNCTION__, (uint64_t)arm_thread_state64_get_pc (m_state.context.gpr)); 598 #else 599 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc); 600 #endif 601 m_state.dbg.__mdscr_el1 |= SS_ENABLE; 602 } else { 603 DNBLogThreadedIf(LOG_STEP, 604 "%s: Clearing MDSCR_EL1 Single Step bit at pc 0x%llx", 605 #if defined(__LP64__) 606 __FUNCTION__, (uint64_t)arm_thread_state64_get_pc (m_state.context.gpr)); 607 #else 608 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc); 609 #endif 610 m_state.dbg.__mdscr_el1 &= ~(SS_ENABLE); 611 } 612 613 return SetDBGState(false); 614 } 615 616 // return 1 if bit "BIT" is set in "value" 617 static inline uint32_t bit(uint32_t value, uint32_t bit) { 618 return (value >> bit) & 1u; 619 } 620 621 // return the bitfield "value[msbit:lsbit]". 622 static inline uint64_t bits(uint64_t value, uint32_t msbit, uint32_t lsbit) { 623 assert(msbit >= lsbit); 624 uint64_t shift_left = sizeof(value) * 8 - 1 - msbit; 625 value <<= 626 shift_left; // shift anything above the msbit off of the unsigned edge 627 value >>= shift_left + lsbit; // shift it back again down to the lsbit 628 // (including undoing any shift from above) 629 return value; // return our result 630 } 631 632 uint32_t DNBArchMachARM64::NumSupportedHardwareWatchpoints() { 633 // Set the init value to something that will let us know that we need to 634 // autodetect how many watchpoints are supported dynamically... 635 static uint32_t g_num_supported_hw_watchpoints = UINT_MAX; 636 if (g_num_supported_hw_watchpoints == UINT_MAX) { 637 // Set this to zero in case we can't tell if there are any HW breakpoints 638 g_num_supported_hw_watchpoints = 0; 639 640 size_t len; 641 uint32_t n = 0; 642 len = sizeof(n); 643 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) { 644 g_num_supported_hw_watchpoints = n; 645 DNBLogThreadedIf(LOG_THREAD, "hw.optional.watchpoint=%u", n); 646 } else { 647 // For AArch64 we would need to look at ID_AA64DFR0_EL1 but debugserver runs in 648 // EL0 so it can't 649 // access that reg. The kernel should have filled in the sysctls based on it 650 // though. 651 #if defined(__arm__) 652 uint32_t register_DBGDIDR; 653 654 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 655 uint32_t numWRPs = bits(register_DBGDIDR, 31, 28); 656 // Zero is reserved for the WRP count, so don't increment it if it is zero 657 if (numWRPs > 0) 658 numWRPs++; 659 g_num_supported_hw_watchpoints = numWRPs; 660 DNBLogThreadedIf(LOG_THREAD, 661 "Number of supported hw watchpoints via asm(): %d", 662 g_num_supported_hw_watchpoints); 663 #endif 664 } 665 } 666 return g_num_supported_hw_watchpoints; 667 } 668 669 uint32_t DNBArchMachARM64::NumSupportedHardwareBreakpoints() { 670 // Set the init value to something that will let us know that we need to 671 // autodetect how many breakpoints are supported dynamically... 672 static uint32_t g_num_supported_hw_breakpoints = UINT_MAX; 673 if (g_num_supported_hw_breakpoints == UINT_MAX) { 674 // Set this to zero in case we can't tell if there are any HW breakpoints 675 g_num_supported_hw_breakpoints = 0; 676 677 size_t len; 678 uint32_t n = 0; 679 len = sizeof(n); 680 if (::sysctlbyname("hw.optional.breakpoint", &n, &len, NULL, 0) == 0) { 681 g_num_supported_hw_breakpoints = n; 682 DNBLogThreadedIf(LOG_THREAD, "hw.optional.breakpoint=%u", n); 683 } else { 684 // For AArch64 we would need to look at ID_AA64DFR0_EL1 but debugserver runs in 685 // EL0 so it can't access that reg. The kernel should have filled in the 686 // sysctls based on it though. 687 #if defined(__arm__) 688 uint32_t register_DBGDIDR; 689 690 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 691 uint32_t numWRPs = bits(register_DBGDIDR, 31, 28); 692 // Zero is reserved for the WRP count, so don't increment it if it is zero 693 if (numWRPs > 0) 694 numWRPs++; 695 g_num_supported_hw_breakpoints = numWRPs; 696 DNBLogThreadedIf(LOG_THREAD, 697 "Number of supported hw breakpoint via asm(): %d", 698 g_num_supported_hw_breakpoints); 699 #endif 700 } 701 } 702 return g_num_supported_hw_breakpoints; 703 } 704 705 uint32_t DNBArchMachARM64::EnableHardwareBreakpoint(nub_addr_t addr, 706 nub_size_t size, 707 bool also_set_on_task) { 708 DNBLogThreadedIf(LOG_WATCHPOINTS, 709 "DNBArchMachARM64::EnableHardwareBreakpoint(addr = " 710 "0x%8.8llx, size = %zu)", 711 (uint64_t)addr, size); 712 713 const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints(); 714 715 nub_addr_t aligned_bp_address = addr; 716 uint32_t control_value = 0; 717 718 switch (size) { 719 case 2: 720 control_value = (0x3 << 5) | 7; 721 aligned_bp_address &= ~1; 722 break; 723 case 4: 724 control_value = (0xfu << 5) | 7; 725 aligned_bp_address &= ~3; 726 break; 727 }; 728 729 // Read the debug state 730 kern_return_t kret = GetDBGState(false); 731 if (kret == KERN_SUCCESS) { 732 // Check to make sure we have the needed hardware support 733 uint32_t i = 0; 734 735 for (i = 0; i < num_hw_breakpoints; ++i) { 736 if ((m_state.dbg.__bcr[i] & BCR_ENABLE) == 0) 737 break; // We found an available hw breakpoint slot (in i) 738 } 739 740 // See if we found an available hw breakpoint slot above 741 if (i < num_hw_breakpoints) { 742 m_state.dbg.__bvr[i] = aligned_bp_address; 743 m_state.dbg.__bcr[i] = control_value; 744 745 DNBLogThreadedIf(LOG_WATCHPOINTS, 746 "DNBArchMachARM64::EnableHardwareBreakpoint() " 747 "adding breakpoint on address 0x%llx with control " 748 "register value 0x%x", 749 (uint64_t)m_state.dbg.__bvr[i], 750 (uint32_t)m_state.dbg.__bcr[i]); 751 752 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 753 // automatically, don't need to do it here. 754 kret = SetDBGState(also_set_on_task); 755 756 DNBLogThreadedIf(LOG_WATCHPOINTS, 757 "DNBArchMachARM64::" 758 "EnableHardwareBreakpoint() " 759 "SetDBGState() => 0x%8.8x.", 760 kret); 761 762 if (kret == KERN_SUCCESS) 763 return i; 764 } else { 765 DNBLogThreadedIf(LOG_WATCHPOINTS, 766 "DNBArchMachARM64::" 767 "EnableHardwareBreakpoint(): All " 768 "hardware resources (%u) are in use.", 769 num_hw_breakpoints); 770 } 771 } 772 return INVALID_NUB_HW_INDEX; 773 } 774 775 uint32_t DNBArchMachARM64::EnableHardwareWatchpoint(nub_addr_t addr, 776 nub_size_t size, bool read, 777 bool write, 778 bool also_set_on_task) { 779 DNBLogThreadedIf(LOG_WATCHPOINTS, 780 "DNBArchMachARM64::EnableHardwareWatchpoint(addr = " 781 "0x%8.8llx, size = %zu, read = %u, write = %u)", 782 (uint64_t)addr, size, read, write); 783 784 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 785 786 // Can't watch zero bytes 787 if (size == 0) 788 return INVALID_NUB_HW_INDEX; 789 790 // We must watch for either read or write 791 if (read == false && write == false) 792 return INVALID_NUB_HW_INDEX; 793 794 // Otherwise, can't watch more than 8 bytes per WVR/WCR pair 795 if (size > 8) 796 return INVALID_NUB_HW_INDEX; 797 798 // Aarch64 watchpoints are in one of two forms: (1) 1-8 bytes, aligned to 799 // an 8 byte address, or (2) a power-of-two size region of memory; minimum 800 // 8 bytes, maximum 2GB; the starting address must be aligned to that power 801 // of two. 802 // 803 // For (1), 1-8 byte watchpoints, using the Byte Address Selector field in 804 // DBGWCR<n>.BAS. Any of the bytes may be watched, but if multiple bytes 805 // are watched, the bytes selected must be contiguous. The start address 806 // watched must be doubleword (8-byte) aligned; if the start address is 807 // word (4-byte) aligned, only 4 bytes can be watched. 808 // 809 // For (2), the MASK field in DBGWCR<n>.MASK is used. 810 // 811 // See the ARM ARM, section "Watchpoint exceptions", and more specifically, 812 // "Watchpoint data address comparisons". 813 // 814 // debugserver today only supports (1) - the Byte Address Selector 1-8 byte 815 // watchpoints that are 8-byte aligned. To support larger watchpoints, 816 // debugserver would need to interpret the mach exception when the watched 817 // region was hit, see if the address accessed lies within the subset 818 // of the power-of-two region that lldb asked us to watch (v. ARM ARM, 819 // "Determining the memory location that caused a Watchpoint exception"), 820 // and silently resume the inferior (disable watchpoint, stepi, re-enable 821 // watchpoint) if the address lies outside the region that lldb asked us 822 // to watch. 823 // 824 // Alternatively, lldb would need to be prepared for a larger region 825 // being watched than it requested, and silently resume the inferior if 826 // the accessed address is outside the region lldb wants to watch. 827 828 nub_addr_t aligned_wp_address = addr & ~0x7; 829 uint32_t addr_dword_offset = addr & 0x7; 830 831 // Do we need to split up this logical watchpoint into two hardware watchpoint 832 // registers? 833 // e.g. a watchpoint of length 4 on address 6. We need do this with 834 // one watchpoint on address 0 with bytes 6 & 7 being monitored 835 // one watchpoint on address 8 with bytes 0, 1, 2, 3 being monitored 836 837 if (addr_dword_offset + size > 8) { 838 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 839 "EnableHardwareWatchpoint(addr = " 840 "0x%8.8llx, size = %zu) needs two " 841 "hardware watchpoints slots to monitor", 842 (uint64_t)addr, size); 843 int low_watchpoint_size = 8 - addr_dword_offset; 844 int high_watchpoint_size = addr_dword_offset + size - 8; 845 846 uint32_t lo = EnableHardwareWatchpoint(addr, low_watchpoint_size, read, 847 write, also_set_on_task); 848 if (lo == INVALID_NUB_HW_INDEX) 849 return INVALID_NUB_HW_INDEX; 850 uint32_t hi = 851 EnableHardwareWatchpoint(aligned_wp_address + 8, high_watchpoint_size, 852 read, write, also_set_on_task); 853 if (hi == INVALID_NUB_HW_INDEX) { 854 DisableHardwareWatchpoint(lo, also_set_on_task); 855 return INVALID_NUB_HW_INDEX; 856 } 857 // Tag this lo->hi mapping in our database. 858 LoHi[lo] = hi; 859 return lo; 860 } 861 862 // At this point 863 // 1 aligned_wp_address is the requested address rounded down to 8-byte 864 // alignment 865 // 2 addr_dword_offset is the offset into that double word (8-byte) region 866 // that we are watching 867 // 3 size is the number of bytes within that 8-byte region that we are 868 // watching 869 870 // Set the Byte Address Selects bits DBGWCRn_EL1 bits [12:5] based on the 871 // above. 872 // The bit shift and negation operation will give us 0b11 for 2, 0b1111 for 4, 873 // etc, up to 0b11111111 for 8. 874 // then we shift those bits left by the offset into this dword that we are 875 // interested in. 876 // e.g. if we are watching bytes 4,5,6,7 in a dword we want a BAS of 877 // 0b11110000. 878 uint32_t byte_address_select = ((1 << size) - 1) << addr_dword_offset; 879 880 // Read the debug state 881 kern_return_t kret = GetDBGState(false); 882 883 if (kret == KERN_SUCCESS) { 884 // Check to make sure we have the needed hardware support 885 uint32_t i = 0; 886 887 for (i = 0; i < num_hw_watchpoints; ++i) { 888 if ((m_state.dbg.__wcr[i] & WCR_ENABLE) == 0) 889 break; // We found an available hw watchpoint slot (in i) 890 } 891 892 // See if we found an available hw watchpoint slot above 893 if (i < num_hw_watchpoints) { 894 // DumpDBGState(m_state.dbg); 895 896 // Clear any previous LoHi joined-watchpoint that may have been in use 897 LoHi[i] = 0; 898 899 // shift our Byte Address Select bits up to the correct bit range for the 900 // DBGWCRn_EL1 901 byte_address_select = byte_address_select << 5; 902 903 // Make sure bits 1:0 are clear in our address 904 m_state.dbg.__wvr[i] = aligned_wp_address; // DVA (Data Virtual Address) 905 m_state.dbg.__wcr[i] = byte_address_select | // Which bytes that follow 906 // the DVA that we will watch 907 S_USER | // Stop only in user mode 908 (read ? WCR_LOAD : 0) | // Stop on read access? 909 (write ? WCR_STORE : 0) | // Stop on write access? 910 WCR_ENABLE; // Enable this watchpoint; 911 912 DNBLogThreadedIf( 913 LOG_WATCHPOINTS, "DNBArchMachARM64::EnableHardwareWatchpoint() " 914 "adding watchpoint on address 0x%llx with control " 915 "register value 0x%x", 916 (uint64_t)m_state.dbg.__wvr[i], (uint32_t)m_state.dbg.__wcr[i]); 917 918 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 919 // automatically, don't need to do it here. 920 921 kret = SetDBGState(also_set_on_task); 922 // DumpDBGState(m_state.dbg); 923 924 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 925 "EnableHardwareWatchpoint() " 926 "SetDBGState() => 0x%8.8x.", 927 kret); 928 929 if (kret == KERN_SUCCESS) 930 return i; 931 } else { 932 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 933 "EnableHardwareWatchpoint(): All " 934 "hardware resources (%u) are in use.", 935 num_hw_watchpoints); 936 } 937 } 938 return INVALID_NUB_HW_INDEX; 939 } 940 941 bool DNBArchMachARM64::ReenableHardwareWatchpoint(uint32_t hw_index) { 942 // If this logical watchpoint # is actually implemented using 943 // two hardware watchpoint registers, re-enable both of them. 944 945 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 946 return ReenableHardwareWatchpoint_helper(hw_index) && 947 ReenableHardwareWatchpoint_helper(LoHi[hw_index]); 948 } else { 949 return ReenableHardwareWatchpoint_helper(hw_index); 950 } 951 } 952 953 bool DNBArchMachARM64::ReenableHardwareWatchpoint_helper(uint32_t hw_index) { 954 kern_return_t kret = GetDBGState(false); 955 if (kret != KERN_SUCCESS) 956 return false; 957 958 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 959 if (hw_index >= num_hw_points) 960 return false; 961 962 m_state.dbg.__wvr[hw_index] = m_disabled_watchpoints[hw_index].addr; 963 m_state.dbg.__wcr[hw_index] = m_disabled_watchpoints[hw_index].control; 964 965 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 966 "EnableHardwareWatchpoint( %u ) - WVR%u = " 967 "0x%8.8llx WCR%u = 0x%8.8llx", 968 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 969 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 970 971 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 972 // automatically, don't need to do it here. 973 974 kret = SetDBGState(false); 975 976 return (kret == KERN_SUCCESS); 977 } 978 979 bool DNBArchMachARM64::DisableHardwareWatchpoint(uint32_t hw_index, 980 bool also_set_on_task) { 981 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 982 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task) && 983 DisableHardwareWatchpoint_helper(LoHi[hw_index], also_set_on_task); 984 } else { 985 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task); 986 } 987 } 988 989 bool DNBArchMachARM64::DisableHardwareWatchpoint_helper(uint32_t hw_index, 990 bool also_set_on_task) { 991 kern_return_t kret = GetDBGState(false); 992 if (kret != KERN_SUCCESS) 993 return false; 994 995 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 996 if (hw_index >= num_hw_points) 997 return false; 998 999 m_disabled_watchpoints[hw_index].addr = m_state.dbg.__wvr[hw_index]; 1000 m_disabled_watchpoints[hw_index].control = m_state.dbg.__wcr[hw_index]; 1001 1002 m_state.dbg.__wcr[hw_index] &= ~((nub_addr_t)WCR_ENABLE); 1003 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 1004 "DisableHardwareWatchpoint( %u ) - WVR%u = " 1005 "0x%8.8llx WCR%u = 0x%8.8llx", 1006 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 1007 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 1008 1009 kret = SetDBGState(also_set_on_task); 1010 1011 return (kret == KERN_SUCCESS); 1012 } 1013 1014 bool DNBArchMachARM64::DisableHardwareBreakpoint(uint32_t hw_index, 1015 bool also_set_on_task) { 1016 kern_return_t kret = GetDBGState(false); 1017 if (kret != KERN_SUCCESS) 1018 return false; 1019 1020 const uint32_t num_hw_points = NumSupportedHardwareBreakpoints(); 1021 if (hw_index >= num_hw_points) 1022 return false; 1023 1024 m_disabled_breakpoints[hw_index].addr = m_state.dbg.__bvr[hw_index]; 1025 m_disabled_breakpoints[hw_index].control = m_state.dbg.__bcr[hw_index]; 1026 1027 m_state.dbg.__bcr[hw_index] = 0; 1028 DNBLogThreadedIf(LOG_WATCHPOINTS, 1029 "DNBArchMachARM64::" 1030 "DisableHardwareBreakpoint( %u ) - WVR%u = " 1031 "0x%8.8llx BCR%u = 0x%8.8llx", 1032 hw_index, hw_index, (uint64_t)m_state.dbg.__bvr[hw_index], 1033 hw_index, (uint64_t)m_state.dbg.__bcr[hw_index]); 1034 1035 kret = SetDBGState(also_set_on_task); 1036 1037 return (kret == KERN_SUCCESS); 1038 } 1039 1040 // This is for checking the Byte Address Select bits in the DBRWCRn_EL1 control 1041 // register. 1042 // Returns -1 if the trailing bit patterns are not one of: 1043 // { 0b???????1, 0b??????10, 0b?????100, 0b????1000, 0b???10000, 0b??100000, 1044 // 0b?1000000, 0b10000000 }. 1045 static inline int32_t LowestBitSet(uint32_t val) { 1046 for (unsigned i = 0; i < 8; ++i) { 1047 if (bit(val, i)) 1048 return i; 1049 } 1050 return -1; 1051 } 1052 1053 // Iterate through the debug registers; return the index of the first watchpoint 1054 // whose address matches. 1055 // As a side effect, the starting address as understood by the debugger is 1056 // returned which could be 1057 // different from 'addr' passed as an in/out argument. 1058 uint32_t DNBArchMachARM64::GetHardwareWatchpointHit(nub_addr_t &addr) { 1059 // Read the debug state 1060 kern_return_t kret = GetDBGState(true); 1061 // DumpDBGState(m_state.dbg); 1062 DNBLogThreadedIf( 1063 LOG_WATCHPOINTS, 1064 "DNBArchMachARM64::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", 1065 kret); 1066 DNBLogThreadedIf(LOG_WATCHPOINTS, 1067 "DNBArchMachARM64::GetHardwareWatchpointHit() addr = 0x%llx", 1068 (uint64_t)addr); 1069 1070 if (kret == KERN_SUCCESS) { 1071 DBG &debug_state = m_state.dbg; 1072 uint32_t i, num = NumSupportedHardwareWatchpoints(); 1073 for (i = 0; i < num; ++i) { 1074 nub_addr_t wp_addr = GetWatchAddress(debug_state, i); 1075 uint32_t byte_mask = bits(debug_state.__wcr[i], 12, 5); 1076 1077 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::" 1078 "GetHardwareWatchpointHit() slot: %u " 1079 "(addr = 0x%llx; byte_mask = 0x%x)", 1080 i, static_cast<uint64_t>(wp_addr), 1081 byte_mask); 1082 1083 if (!IsWatchpointEnabled(debug_state, i)) 1084 continue; 1085 1086 if (bits(wp_addr, 48, 3) != bits(addr, 48, 3)) 1087 continue; 1088 1089 // Sanity check the byte_mask 1090 uint32_t lsb = LowestBitSet(byte_mask); 1091 if (lsb < 0) 1092 continue; 1093 1094 uint64_t byte_to_match = bits(addr, 2, 0); 1095 1096 if (byte_mask & (1 << byte_to_match)) { 1097 addr = wp_addr + lsb; 1098 return i; 1099 } 1100 } 1101 } 1102 return INVALID_NUB_HW_INDEX; 1103 } 1104 1105 nub_addr_t DNBArchMachARM64::GetWatchpointAddressByIndex(uint32_t hw_index) { 1106 kern_return_t kret = GetDBGState(true); 1107 if (kret != KERN_SUCCESS) 1108 return INVALID_NUB_ADDRESS; 1109 const uint32_t num = NumSupportedHardwareWatchpoints(); 1110 if (hw_index >= num) 1111 return INVALID_NUB_ADDRESS; 1112 if (IsWatchpointEnabled(m_state.dbg, hw_index)) 1113 return GetWatchAddress(m_state.dbg, hw_index); 1114 return INVALID_NUB_ADDRESS; 1115 } 1116 1117 bool DNBArchMachARM64::IsWatchpointEnabled(const DBG &debug_state, 1118 uint32_t hw_index) { 1119 // Watchpoint Control Registers, bitfield definitions 1120 // ... 1121 // Bits Value Description 1122 // [0] 0 Watchpoint disabled 1123 // 1 Watchpoint enabled. 1124 return (debug_state.__wcr[hw_index] & 1u); 1125 } 1126 1127 nub_addr_t DNBArchMachARM64::GetWatchAddress(const DBG &debug_state, 1128 uint32_t hw_index) { 1129 // Watchpoint Value Registers, bitfield definitions 1130 // Bits Description 1131 // [31:2] Watchpoint value (word address, i.e., 4-byte aligned) 1132 // [1:0] RAZ/SBZP 1133 return bits(debug_state.__wvr[hw_index], 63, 0); 1134 } 1135 1136 // Register information definitions for 64 bit ARMv8. 1137 enum gpr_regnums { 1138 gpr_x0 = 0, 1139 gpr_x1, 1140 gpr_x2, 1141 gpr_x3, 1142 gpr_x4, 1143 gpr_x5, 1144 gpr_x6, 1145 gpr_x7, 1146 gpr_x8, 1147 gpr_x9, 1148 gpr_x10, 1149 gpr_x11, 1150 gpr_x12, 1151 gpr_x13, 1152 gpr_x14, 1153 gpr_x15, 1154 gpr_x16, 1155 gpr_x17, 1156 gpr_x18, 1157 gpr_x19, 1158 gpr_x20, 1159 gpr_x21, 1160 gpr_x22, 1161 gpr_x23, 1162 gpr_x24, 1163 gpr_x25, 1164 gpr_x26, 1165 gpr_x27, 1166 gpr_x28, 1167 gpr_fp, 1168 gpr_x29 = gpr_fp, 1169 gpr_lr, 1170 gpr_x30 = gpr_lr, 1171 gpr_sp, 1172 gpr_x31 = gpr_sp, 1173 gpr_pc, 1174 gpr_cpsr, 1175 gpr_w0, 1176 gpr_w1, 1177 gpr_w2, 1178 gpr_w3, 1179 gpr_w4, 1180 gpr_w5, 1181 gpr_w6, 1182 gpr_w7, 1183 gpr_w8, 1184 gpr_w9, 1185 gpr_w10, 1186 gpr_w11, 1187 gpr_w12, 1188 gpr_w13, 1189 gpr_w14, 1190 gpr_w15, 1191 gpr_w16, 1192 gpr_w17, 1193 gpr_w18, 1194 gpr_w19, 1195 gpr_w20, 1196 gpr_w21, 1197 gpr_w22, 1198 gpr_w23, 1199 gpr_w24, 1200 gpr_w25, 1201 gpr_w26, 1202 gpr_w27, 1203 gpr_w28 1204 1205 }; 1206 1207 enum { 1208 vfp_v0 = 0, 1209 vfp_v1, 1210 vfp_v2, 1211 vfp_v3, 1212 vfp_v4, 1213 vfp_v5, 1214 vfp_v6, 1215 vfp_v7, 1216 vfp_v8, 1217 vfp_v9, 1218 vfp_v10, 1219 vfp_v11, 1220 vfp_v12, 1221 vfp_v13, 1222 vfp_v14, 1223 vfp_v15, 1224 vfp_v16, 1225 vfp_v17, 1226 vfp_v18, 1227 vfp_v19, 1228 vfp_v20, 1229 vfp_v21, 1230 vfp_v22, 1231 vfp_v23, 1232 vfp_v24, 1233 vfp_v25, 1234 vfp_v26, 1235 vfp_v27, 1236 vfp_v28, 1237 vfp_v29, 1238 vfp_v30, 1239 vfp_v31, 1240 vfp_fpsr, 1241 vfp_fpcr, 1242 1243 // lower 32 bits of the corresponding vfp_v<n> reg. 1244 vfp_s0, 1245 vfp_s1, 1246 vfp_s2, 1247 vfp_s3, 1248 vfp_s4, 1249 vfp_s5, 1250 vfp_s6, 1251 vfp_s7, 1252 vfp_s8, 1253 vfp_s9, 1254 vfp_s10, 1255 vfp_s11, 1256 vfp_s12, 1257 vfp_s13, 1258 vfp_s14, 1259 vfp_s15, 1260 vfp_s16, 1261 vfp_s17, 1262 vfp_s18, 1263 vfp_s19, 1264 vfp_s20, 1265 vfp_s21, 1266 vfp_s22, 1267 vfp_s23, 1268 vfp_s24, 1269 vfp_s25, 1270 vfp_s26, 1271 vfp_s27, 1272 vfp_s28, 1273 vfp_s29, 1274 vfp_s30, 1275 vfp_s31, 1276 1277 // lower 64 bits of the corresponding vfp_v<n> reg. 1278 vfp_d0, 1279 vfp_d1, 1280 vfp_d2, 1281 vfp_d3, 1282 vfp_d4, 1283 vfp_d5, 1284 vfp_d6, 1285 vfp_d7, 1286 vfp_d8, 1287 vfp_d9, 1288 vfp_d10, 1289 vfp_d11, 1290 vfp_d12, 1291 vfp_d13, 1292 vfp_d14, 1293 vfp_d15, 1294 vfp_d16, 1295 vfp_d17, 1296 vfp_d18, 1297 vfp_d19, 1298 vfp_d20, 1299 vfp_d21, 1300 vfp_d22, 1301 vfp_d23, 1302 vfp_d24, 1303 vfp_d25, 1304 vfp_d26, 1305 vfp_d27, 1306 vfp_d28, 1307 vfp_d29, 1308 vfp_d30, 1309 vfp_d31 1310 }; 1311 1312 enum { exc_far = 0, exc_esr, exc_exception }; 1313 1314 // These numbers from the "DWARF for the ARM 64-bit Architecture (AArch64)" 1315 // document. 1316 1317 enum { 1318 dwarf_x0 = 0, 1319 dwarf_x1, 1320 dwarf_x2, 1321 dwarf_x3, 1322 dwarf_x4, 1323 dwarf_x5, 1324 dwarf_x6, 1325 dwarf_x7, 1326 dwarf_x8, 1327 dwarf_x9, 1328 dwarf_x10, 1329 dwarf_x11, 1330 dwarf_x12, 1331 dwarf_x13, 1332 dwarf_x14, 1333 dwarf_x15, 1334 dwarf_x16, 1335 dwarf_x17, 1336 dwarf_x18, 1337 dwarf_x19, 1338 dwarf_x20, 1339 dwarf_x21, 1340 dwarf_x22, 1341 dwarf_x23, 1342 dwarf_x24, 1343 dwarf_x25, 1344 dwarf_x26, 1345 dwarf_x27, 1346 dwarf_x28, 1347 dwarf_x29, 1348 dwarf_x30, 1349 dwarf_x31, 1350 dwarf_pc = 32, 1351 dwarf_elr_mode = 33, 1352 dwarf_fp = dwarf_x29, 1353 dwarf_lr = dwarf_x30, 1354 dwarf_sp = dwarf_x31, 1355 // 34-63 reserved 1356 1357 // V0-V31 (128 bit vector registers) 1358 dwarf_v0 = 64, 1359 dwarf_v1, 1360 dwarf_v2, 1361 dwarf_v3, 1362 dwarf_v4, 1363 dwarf_v5, 1364 dwarf_v6, 1365 dwarf_v7, 1366 dwarf_v8, 1367 dwarf_v9, 1368 dwarf_v10, 1369 dwarf_v11, 1370 dwarf_v12, 1371 dwarf_v13, 1372 dwarf_v14, 1373 dwarf_v15, 1374 dwarf_v16, 1375 dwarf_v17, 1376 dwarf_v18, 1377 dwarf_v19, 1378 dwarf_v20, 1379 dwarf_v21, 1380 dwarf_v22, 1381 dwarf_v23, 1382 dwarf_v24, 1383 dwarf_v25, 1384 dwarf_v26, 1385 dwarf_v27, 1386 dwarf_v28, 1387 dwarf_v29, 1388 dwarf_v30, 1389 dwarf_v31 1390 1391 // 96-127 reserved 1392 }; 1393 1394 enum { 1395 debugserver_gpr_x0 = 0, 1396 debugserver_gpr_x1, 1397 debugserver_gpr_x2, 1398 debugserver_gpr_x3, 1399 debugserver_gpr_x4, 1400 debugserver_gpr_x5, 1401 debugserver_gpr_x6, 1402 debugserver_gpr_x7, 1403 debugserver_gpr_x8, 1404 debugserver_gpr_x9, 1405 debugserver_gpr_x10, 1406 debugserver_gpr_x11, 1407 debugserver_gpr_x12, 1408 debugserver_gpr_x13, 1409 debugserver_gpr_x14, 1410 debugserver_gpr_x15, 1411 debugserver_gpr_x16, 1412 debugserver_gpr_x17, 1413 debugserver_gpr_x18, 1414 debugserver_gpr_x19, 1415 debugserver_gpr_x20, 1416 debugserver_gpr_x21, 1417 debugserver_gpr_x22, 1418 debugserver_gpr_x23, 1419 debugserver_gpr_x24, 1420 debugserver_gpr_x25, 1421 debugserver_gpr_x26, 1422 debugserver_gpr_x27, 1423 debugserver_gpr_x28, 1424 debugserver_gpr_fp, // x29 1425 debugserver_gpr_lr, // x30 1426 debugserver_gpr_sp, // sp aka xsp 1427 debugserver_gpr_pc, 1428 debugserver_gpr_cpsr, 1429 debugserver_vfp_v0, 1430 debugserver_vfp_v1, 1431 debugserver_vfp_v2, 1432 debugserver_vfp_v3, 1433 debugserver_vfp_v4, 1434 debugserver_vfp_v5, 1435 debugserver_vfp_v6, 1436 debugserver_vfp_v7, 1437 debugserver_vfp_v8, 1438 debugserver_vfp_v9, 1439 debugserver_vfp_v10, 1440 debugserver_vfp_v11, 1441 debugserver_vfp_v12, 1442 debugserver_vfp_v13, 1443 debugserver_vfp_v14, 1444 debugserver_vfp_v15, 1445 debugserver_vfp_v16, 1446 debugserver_vfp_v17, 1447 debugserver_vfp_v18, 1448 debugserver_vfp_v19, 1449 debugserver_vfp_v20, 1450 debugserver_vfp_v21, 1451 debugserver_vfp_v22, 1452 debugserver_vfp_v23, 1453 debugserver_vfp_v24, 1454 debugserver_vfp_v25, 1455 debugserver_vfp_v26, 1456 debugserver_vfp_v27, 1457 debugserver_vfp_v28, 1458 debugserver_vfp_v29, 1459 debugserver_vfp_v30, 1460 debugserver_vfp_v31, 1461 debugserver_vfp_fpsr, 1462 debugserver_vfp_fpcr 1463 }; 1464 1465 const char *g_contained_x0[]{"x0", NULL}; 1466 const char *g_contained_x1[]{"x1", NULL}; 1467 const char *g_contained_x2[]{"x2", NULL}; 1468 const char *g_contained_x3[]{"x3", NULL}; 1469 const char *g_contained_x4[]{"x4", NULL}; 1470 const char *g_contained_x5[]{"x5", NULL}; 1471 const char *g_contained_x6[]{"x6", NULL}; 1472 const char *g_contained_x7[]{"x7", NULL}; 1473 const char *g_contained_x8[]{"x8", NULL}; 1474 const char *g_contained_x9[]{"x9", NULL}; 1475 const char *g_contained_x10[]{"x10", NULL}; 1476 const char *g_contained_x11[]{"x11", NULL}; 1477 const char *g_contained_x12[]{"x12", NULL}; 1478 const char *g_contained_x13[]{"x13", NULL}; 1479 const char *g_contained_x14[]{"x14", NULL}; 1480 const char *g_contained_x15[]{"x15", NULL}; 1481 const char *g_contained_x16[]{"x16", NULL}; 1482 const char *g_contained_x17[]{"x17", NULL}; 1483 const char *g_contained_x18[]{"x18", NULL}; 1484 const char *g_contained_x19[]{"x19", NULL}; 1485 const char *g_contained_x20[]{"x20", NULL}; 1486 const char *g_contained_x21[]{"x21", NULL}; 1487 const char *g_contained_x22[]{"x22", NULL}; 1488 const char *g_contained_x23[]{"x23", NULL}; 1489 const char *g_contained_x24[]{"x24", NULL}; 1490 const char *g_contained_x25[]{"x25", NULL}; 1491 const char *g_contained_x26[]{"x26", NULL}; 1492 const char *g_contained_x27[]{"x27", NULL}; 1493 const char *g_contained_x28[]{"x28", NULL}; 1494 1495 const char *g_invalidate_x0[]{"x0", "w0", NULL}; 1496 const char *g_invalidate_x1[]{"x1", "w1", NULL}; 1497 const char *g_invalidate_x2[]{"x2", "w2", NULL}; 1498 const char *g_invalidate_x3[]{"x3", "w3", NULL}; 1499 const char *g_invalidate_x4[]{"x4", "w4", NULL}; 1500 const char *g_invalidate_x5[]{"x5", "w5", NULL}; 1501 const char *g_invalidate_x6[]{"x6", "w6", NULL}; 1502 const char *g_invalidate_x7[]{"x7", "w7", NULL}; 1503 const char *g_invalidate_x8[]{"x8", "w8", NULL}; 1504 const char *g_invalidate_x9[]{"x9", "w9", NULL}; 1505 const char *g_invalidate_x10[]{"x10", "w10", NULL}; 1506 const char *g_invalidate_x11[]{"x11", "w11", NULL}; 1507 const char *g_invalidate_x12[]{"x12", "w12", NULL}; 1508 const char *g_invalidate_x13[]{"x13", "w13", NULL}; 1509 const char *g_invalidate_x14[]{"x14", "w14", NULL}; 1510 const char *g_invalidate_x15[]{"x15", "w15", NULL}; 1511 const char *g_invalidate_x16[]{"x16", "w16", NULL}; 1512 const char *g_invalidate_x17[]{"x17", "w17", NULL}; 1513 const char *g_invalidate_x18[]{"x18", "w18", NULL}; 1514 const char *g_invalidate_x19[]{"x19", "w19", NULL}; 1515 const char *g_invalidate_x20[]{"x20", "w20", NULL}; 1516 const char *g_invalidate_x21[]{"x21", "w21", NULL}; 1517 const char *g_invalidate_x22[]{"x22", "w22", NULL}; 1518 const char *g_invalidate_x23[]{"x23", "w23", NULL}; 1519 const char *g_invalidate_x24[]{"x24", "w24", NULL}; 1520 const char *g_invalidate_x25[]{"x25", "w25", NULL}; 1521 const char *g_invalidate_x26[]{"x26", "w26", NULL}; 1522 const char *g_invalidate_x27[]{"x27", "w27", NULL}; 1523 const char *g_invalidate_x28[]{"x28", "w28", NULL}; 1524 1525 #define GPR_OFFSET_IDX(idx) (offsetof(DNBArchMachARM64::GPR, __x[idx])) 1526 1527 #define GPR_OFFSET_NAME(reg) (offsetof(DNBArchMachARM64::GPR, __##reg)) 1528 1529 // These macros will auto define the register name, alt name, register size, 1530 // register offset, encoding, format and native register. This ensures that 1531 // the register state structures are defined correctly and have the correct 1532 // sizes and offsets. 1533 #define DEFINE_GPR_IDX(idx, reg, alt, gen) \ 1534 { \ 1535 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_IDX(idx), \ 1536 dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, \ 1537 g_invalidate_x##idx \ 1538 } 1539 #define DEFINE_GPR_NAME(reg, alt, gen) \ 1540 { \ 1541 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_NAME(reg), \ 1542 dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, NULL \ 1543 } 1544 #define DEFINE_PSEUDO_GPR_IDX(idx, reg) \ 1545 { \ 1546 e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, 4, 0, INVALID_NUB_REGNUM, \ 1547 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1548 g_contained_x##idx, g_invalidate_x##idx \ 1549 } 1550 1551 //_STRUCT_ARM_THREAD_STATE64 1552 //{ 1553 // uint64_t x[29]; /* General purpose registers x0-x28 */ 1554 // uint64_t fp; /* Frame pointer x29 */ 1555 // uint64_t lr; /* Link register x30 */ 1556 // uint64_t sp; /* Stack pointer x31 */ 1557 // uint64_t pc; /* Program counter */ 1558 // uint32_t cpsr; /* Current program status register */ 1559 //}; 1560 1561 // General purpose registers 1562 const DNBRegisterInfo DNBArchMachARM64::g_gpr_registers[] = { 1563 DEFINE_GPR_IDX(0, x0, "arg1", GENERIC_REGNUM_ARG1), 1564 DEFINE_GPR_IDX(1, x1, "arg2", GENERIC_REGNUM_ARG2), 1565 DEFINE_GPR_IDX(2, x2, "arg3", GENERIC_REGNUM_ARG3), 1566 DEFINE_GPR_IDX(3, x3, "arg4", GENERIC_REGNUM_ARG4), 1567 DEFINE_GPR_IDX(4, x4, "arg5", GENERIC_REGNUM_ARG5), 1568 DEFINE_GPR_IDX(5, x5, "arg6", GENERIC_REGNUM_ARG6), 1569 DEFINE_GPR_IDX(6, x6, "arg7", GENERIC_REGNUM_ARG7), 1570 DEFINE_GPR_IDX(7, x7, "arg8", GENERIC_REGNUM_ARG8), 1571 DEFINE_GPR_IDX(8, x8, NULL, INVALID_NUB_REGNUM), 1572 DEFINE_GPR_IDX(9, x9, NULL, INVALID_NUB_REGNUM), 1573 DEFINE_GPR_IDX(10, x10, NULL, INVALID_NUB_REGNUM), 1574 DEFINE_GPR_IDX(11, x11, NULL, INVALID_NUB_REGNUM), 1575 DEFINE_GPR_IDX(12, x12, NULL, INVALID_NUB_REGNUM), 1576 DEFINE_GPR_IDX(13, x13, NULL, INVALID_NUB_REGNUM), 1577 DEFINE_GPR_IDX(14, x14, NULL, INVALID_NUB_REGNUM), 1578 DEFINE_GPR_IDX(15, x15, NULL, INVALID_NUB_REGNUM), 1579 DEFINE_GPR_IDX(16, x16, NULL, INVALID_NUB_REGNUM), 1580 DEFINE_GPR_IDX(17, x17, NULL, INVALID_NUB_REGNUM), 1581 DEFINE_GPR_IDX(18, x18, NULL, INVALID_NUB_REGNUM), 1582 DEFINE_GPR_IDX(19, x19, NULL, INVALID_NUB_REGNUM), 1583 DEFINE_GPR_IDX(20, x20, NULL, INVALID_NUB_REGNUM), 1584 DEFINE_GPR_IDX(21, x21, NULL, INVALID_NUB_REGNUM), 1585 DEFINE_GPR_IDX(22, x22, NULL, INVALID_NUB_REGNUM), 1586 DEFINE_GPR_IDX(23, x23, NULL, INVALID_NUB_REGNUM), 1587 DEFINE_GPR_IDX(24, x24, NULL, INVALID_NUB_REGNUM), 1588 DEFINE_GPR_IDX(25, x25, NULL, INVALID_NUB_REGNUM), 1589 DEFINE_GPR_IDX(26, x26, NULL, INVALID_NUB_REGNUM), 1590 DEFINE_GPR_IDX(27, x27, NULL, INVALID_NUB_REGNUM), 1591 DEFINE_GPR_IDX(28, x28, NULL, INVALID_NUB_REGNUM), 1592 // For the G/g packet we want to show where the offset into the regctx 1593 // is for fp/lr/sp/pc, but we cannot directly access them on arm64e 1594 // devices (and therefore can't offsetof() them)) - add the offset based 1595 // on the last accessible register by hand for advertising the location 1596 // in the regctx to lldb. We'll go through the accessor functions when 1597 // we read/write them here. 1598 { 1599 e_regSetGPR, gpr_fp, "fp", "x29", Uint, Hex, 8, GPR_OFFSET_IDX(28) + 8, 1600 dwarf_fp, dwarf_fp, GENERIC_REGNUM_FP, debugserver_gpr_fp, NULL, NULL 1601 }, 1602 { 1603 e_regSetGPR, gpr_lr, "lr", "x30", Uint, Hex, 8, GPR_OFFSET_IDX(28) + 16, 1604 dwarf_lr, dwarf_lr, GENERIC_REGNUM_RA, debugserver_gpr_lr, NULL, NULL 1605 }, 1606 { 1607 e_regSetGPR, gpr_sp, "sp", "xsp", Uint, Hex, 8, GPR_OFFSET_IDX(28) + 24, 1608 dwarf_sp, dwarf_sp, GENERIC_REGNUM_SP, debugserver_gpr_sp, NULL, NULL 1609 }, 1610 { 1611 e_regSetGPR, gpr_pc, "pc", NULL, Uint, Hex, 8, GPR_OFFSET_IDX(28) + 32, 1612 dwarf_pc, dwarf_pc, GENERIC_REGNUM_PC, debugserver_gpr_pc, NULL, NULL 1613 }, 1614 1615 // in armv7 we specify that writing to the CPSR should invalidate r8-12, sp, 1616 // lr. 1617 // this should be specified for arm64 too even though debugserver is only 1618 // used for 1619 // userland debugging. 1620 {e_regSetGPR, gpr_cpsr, "cpsr", "flags", Uint, Hex, 4, 1621 GPR_OFFSET_NAME(cpsr), dwarf_elr_mode, dwarf_elr_mode, INVALID_NUB_REGNUM, 1622 debugserver_gpr_cpsr, NULL, NULL}, 1623 1624 DEFINE_PSEUDO_GPR_IDX(0, w0), 1625 DEFINE_PSEUDO_GPR_IDX(1, w1), 1626 DEFINE_PSEUDO_GPR_IDX(2, w2), 1627 DEFINE_PSEUDO_GPR_IDX(3, w3), 1628 DEFINE_PSEUDO_GPR_IDX(4, w4), 1629 DEFINE_PSEUDO_GPR_IDX(5, w5), 1630 DEFINE_PSEUDO_GPR_IDX(6, w6), 1631 DEFINE_PSEUDO_GPR_IDX(7, w7), 1632 DEFINE_PSEUDO_GPR_IDX(8, w8), 1633 DEFINE_PSEUDO_GPR_IDX(9, w9), 1634 DEFINE_PSEUDO_GPR_IDX(10, w10), 1635 DEFINE_PSEUDO_GPR_IDX(11, w11), 1636 DEFINE_PSEUDO_GPR_IDX(12, w12), 1637 DEFINE_PSEUDO_GPR_IDX(13, w13), 1638 DEFINE_PSEUDO_GPR_IDX(14, w14), 1639 DEFINE_PSEUDO_GPR_IDX(15, w15), 1640 DEFINE_PSEUDO_GPR_IDX(16, w16), 1641 DEFINE_PSEUDO_GPR_IDX(17, w17), 1642 DEFINE_PSEUDO_GPR_IDX(18, w18), 1643 DEFINE_PSEUDO_GPR_IDX(19, w19), 1644 DEFINE_PSEUDO_GPR_IDX(20, w20), 1645 DEFINE_PSEUDO_GPR_IDX(21, w21), 1646 DEFINE_PSEUDO_GPR_IDX(22, w22), 1647 DEFINE_PSEUDO_GPR_IDX(23, w23), 1648 DEFINE_PSEUDO_GPR_IDX(24, w24), 1649 DEFINE_PSEUDO_GPR_IDX(25, w25), 1650 DEFINE_PSEUDO_GPR_IDX(26, w26), 1651 DEFINE_PSEUDO_GPR_IDX(27, w27), 1652 DEFINE_PSEUDO_GPR_IDX(28, w28)}; 1653 1654 const char *g_contained_v0[]{"v0", NULL}; 1655 const char *g_contained_v1[]{"v1", NULL}; 1656 const char *g_contained_v2[]{"v2", NULL}; 1657 const char *g_contained_v3[]{"v3", NULL}; 1658 const char *g_contained_v4[]{"v4", NULL}; 1659 const char *g_contained_v5[]{"v5", NULL}; 1660 const char *g_contained_v6[]{"v6", NULL}; 1661 const char *g_contained_v7[]{"v7", NULL}; 1662 const char *g_contained_v8[]{"v8", NULL}; 1663 const char *g_contained_v9[]{"v9", NULL}; 1664 const char *g_contained_v10[]{"v10", NULL}; 1665 const char *g_contained_v11[]{"v11", NULL}; 1666 const char *g_contained_v12[]{"v12", NULL}; 1667 const char *g_contained_v13[]{"v13", NULL}; 1668 const char *g_contained_v14[]{"v14", NULL}; 1669 const char *g_contained_v15[]{"v15", NULL}; 1670 const char *g_contained_v16[]{"v16", NULL}; 1671 const char *g_contained_v17[]{"v17", NULL}; 1672 const char *g_contained_v18[]{"v18", NULL}; 1673 const char *g_contained_v19[]{"v19", NULL}; 1674 const char *g_contained_v20[]{"v20", NULL}; 1675 const char *g_contained_v21[]{"v21", NULL}; 1676 const char *g_contained_v22[]{"v22", NULL}; 1677 const char *g_contained_v23[]{"v23", NULL}; 1678 const char *g_contained_v24[]{"v24", NULL}; 1679 const char *g_contained_v25[]{"v25", NULL}; 1680 const char *g_contained_v26[]{"v26", NULL}; 1681 const char *g_contained_v27[]{"v27", NULL}; 1682 const char *g_contained_v28[]{"v28", NULL}; 1683 const char *g_contained_v29[]{"v29", NULL}; 1684 const char *g_contained_v30[]{"v30", NULL}; 1685 const char *g_contained_v31[]{"v31", NULL}; 1686 1687 const char *g_invalidate_v0[]{"v0", "d0", "s0", NULL}; 1688 const char *g_invalidate_v1[]{"v1", "d1", "s1", NULL}; 1689 const char *g_invalidate_v2[]{"v2", "d2", "s2", NULL}; 1690 const char *g_invalidate_v3[]{"v3", "d3", "s3", NULL}; 1691 const char *g_invalidate_v4[]{"v4", "d4", "s4", NULL}; 1692 const char *g_invalidate_v5[]{"v5", "d5", "s5", NULL}; 1693 const char *g_invalidate_v6[]{"v6", "d6", "s6", NULL}; 1694 const char *g_invalidate_v7[]{"v7", "d7", "s7", NULL}; 1695 const char *g_invalidate_v8[]{"v8", "d8", "s8", NULL}; 1696 const char *g_invalidate_v9[]{"v9", "d9", "s9", NULL}; 1697 const char *g_invalidate_v10[]{"v10", "d10", "s10", NULL}; 1698 const char *g_invalidate_v11[]{"v11", "d11", "s11", NULL}; 1699 const char *g_invalidate_v12[]{"v12", "d12", "s12", NULL}; 1700 const char *g_invalidate_v13[]{"v13", "d13", "s13", NULL}; 1701 const char *g_invalidate_v14[]{"v14", "d14", "s14", NULL}; 1702 const char *g_invalidate_v15[]{"v15", "d15", "s15", NULL}; 1703 const char *g_invalidate_v16[]{"v16", "d16", "s16", NULL}; 1704 const char *g_invalidate_v17[]{"v17", "d17", "s17", NULL}; 1705 const char *g_invalidate_v18[]{"v18", "d18", "s18", NULL}; 1706 const char *g_invalidate_v19[]{"v19", "d19", "s19", NULL}; 1707 const char *g_invalidate_v20[]{"v20", "d20", "s20", NULL}; 1708 const char *g_invalidate_v21[]{"v21", "d21", "s21", NULL}; 1709 const char *g_invalidate_v22[]{"v22", "d22", "s22", NULL}; 1710 const char *g_invalidate_v23[]{"v23", "d23", "s23", NULL}; 1711 const char *g_invalidate_v24[]{"v24", "d24", "s24", NULL}; 1712 const char *g_invalidate_v25[]{"v25", "d25", "s25", NULL}; 1713 const char *g_invalidate_v26[]{"v26", "d26", "s26", NULL}; 1714 const char *g_invalidate_v27[]{"v27", "d27", "s27", NULL}; 1715 const char *g_invalidate_v28[]{"v28", "d28", "s28", NULL}; 1716 const char *g_invalidate_v29[]{"v29", "d29", "s29", NULL}; 1717 const char *g_invalidate_v30[]{"v30", "d30", "s30", NULL}; 1718 const char *g_invalidate_v31[]{"v31", "d31", "s31", NULL}; 1719 1720 #if defined(__arm64__) || defined(__aarch64__) 1721 #define VFP_V_OFFSET_IDX(idx) \ 1722 (offsetof(DNBArchMachARM64::FPU, __v) + (idx * 16) + \ 1723 offsetof(DNBArchMachARM64::Context, vfp)) 1724 #else 1725 #define VFP_V_OFFSET_IDX(idx) \ 1726 (offsetof(DNBArchMachARM64::FPU, opaque) + (idx * 16) + \ 1727 offsetof(DNBArchMachARM64::Context, vfp)) 1728 #endif 1729 #define VFP_OFFSET_NAME(reg) \ 1730 (offsetof(DNBArchMachARM64::FPU, reg) + \ 1731 offsetof(DNBArchMachARM64::Context, vfp)) 1732 #define EXC_OFFSET(reg) \ 1733 (offsetof(DNBArchMachARM64::EXC, reg) + \ 1734 offsetof(DNBArchMachARM64::Context, exc)) 1735 1736 //#define FLOAT_FORMAT Float 1737 #define DEFINE_VFP_V_IDX(idx) \ 1738 { \ 1739 e_regSetVFP, vfp_v##idx, "v" #idx, "q" #idx, Vector, VectorOfUInt8, 16, \ 1740 VFP_V_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_v##idx, \ 1741 INVALID_NUB_REGNUM, debugserver_vfp_v##idx, NULL, g_invalidate_v##idx \ 1742 } 1743 #define DEFINE_PSEUDO_VFP_S_IDX(idx) \ 1744 { \ 1745 e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, Float, 4, 0, \ 1746 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1747 INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \ 1748 } 1749 #define DEFINE_PSEUDO_VFP_D_IDX(idx) \ 1750 { \ 1751 e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, Float, 8, 0, \ 1752 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1753 INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \ 1754 } 1755 1756 // Floating point registers 1757 const DNBRegisterInfo DNBArchMachARM64::g_vfp_registers[] = { 1758 DEFINE_VFP_V_IDX(0), 1759 DEFINE_VFP_V_IDX(1), 1760 DEFINE_VFP_V_IDX(2), 1761 DEFINE_VFP_V_IDX(3), 1762 DEFINE_VFP_V_IDX(4), 1763 DEFINE_VFP_V_IDX(5), 1764 DEFINE_VFP_V_IDX(6), 1765 DEFINE_VFP_V_IDX(7), 1766 DEFINE_VFP_V_IDX(8), 1767 DEFINE_VFP_V_IDX(9), 1768 DEFINE_VFP_V_IDX(10), 1769 DEFINE_VFP_V_IDX(11), 1770 DEFINE_VFP_V_IDX(12), 1771 DEFINE_VFP_V_IDX(13), 1772 DEFINE_VFP_V_IDX(14), 1773 DEFINE_VFP_V_IDX(15), 1774 DEFINE_VFP_V_IDX(16), 1775 DEFINE_VFP_V_IDX(17), 1776 DEFINE_VFP_V_IDX(18), 1777 DEFINE_VFP_V_IDX(19), 1778 DEFINE_VFP_V_IDX(20), 1779 DEFINE_VFP_V_IDX(21), 1780 DEFINE_VFP_V_IDX(22), 1781 DEFINE_VFP_V_IDX(23), 1782 DEFINE_VFP_V_IDX(24), 1783 DEFINE_VFP_V_IDX(25), 1784 DEFINE_VFP_V_IDX(26), 1785 DEFINE_VFP_V_IDX(27), 1786 DEFINE_VFP_V_IDX(28), 1787 DEFINE_VFP_V_IDX(29), 1788 DEFINE_VFP_V_IDX(30), 1789 DEFINE_VFP_V_IDX(31), 1790 {e_regSetVFP, vfp_fpsr, "fpsr", NULL, Uint, Hex, 4, 1791 VFP_V_OFFSET_IDX(32) + 0, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1792 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}, 1793 {e_regSetVFP, vfp_fpcr, "fpcr", NULL, Uint, Hex, 4, 1794 VFP_V_OFFSET_IDX(32) + 4, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1795 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}, 1796 1797 DEFINE_PSEUDO_VFP_S_IDX(0), 1798 DEFINE_PSEUDO_VFP_S_IDX(1), 1799 DEFINE_PSEUDO_VFP_S_IDX(2), 1800 DEFINE_PSEUDO_VFP_S_IDX(3), 1801 DEFINE_PSEUDO_VFP_S_IDX(4), 1802 DEFINE_PSEUDO_VFP_S_IDX(5), 1803 DEFINE_PSEUDO_VFP_S_IDX(6), 1804 DEFINE_PSEUDO_VFP_S_IDX(7), 1805 DEFINE_PSEUDO_VFP_S_IDX(8), 1806 DEFINE_PSEUDO_VFP_S_IDX(9), 1807 DEFINE_PSEUDO_VFP_S_IDX(10), 1808 DEFINE_PSEUDO_VFP_S_IDX(11), 1809 DEFINE_PSEUDO_VFP_S_IDX(12), 1810 DEFINE_PSEUDO_VFP_S_IDX(13), 1811 DEFINE_PSEUDO_VFP_S_IDX(14), 1812 DEFINE_PSEUDO_VFP_S_IDX(15), 1813 DEFINE_PSEUDO_VFP_S_IDX(16), 1814 DEFINE_PSEUDO_VFP_S_IDX(17), 1815 DEFINE_PSEUDO_VFP_S_IDX(18), 1816 DEFINE_PSEUDO_VFP_S_IDX(19), 1817 DEFINE_PSEUDO_VFP_S_IDX(20), 1818 DEFINE_PSEUDO_VFP_S_IDX(21), 1819 DEFINE_PSEUDO_VFP_S_IDX(22), 1820 DEFINE_PSEUDO_VFP_S_IDX(23), 1821 DEFINE_PSEUDO_VFP_S_IDX(24), 1822 DEFINE_PSEUDO_VFP_S_IDX(25), 1823 DEFINE_PSEUDO_VFP_S_IDX(26), 1824 DEFINE_PSEUDO_VFP_S_IDX(27), 1825 DEFINE_PSEUDO_VFP_S_IDX(28), 1826 DEFINE_PSEUDO_VFP_S_IDX(29), 1827 DEFINE_PSEUDO_VFP_S_IDX(30), 1828 DEFINE_PSEUDO_VFP_S_IDX(31), 1829 1830 DEFINE_PSEUDO_VFP_D_IDX(0), 1831 DEFINE_PSEUDO_VFP_D_IDX(1), 1832 DEFINE_PSEUDO_VFP_D_IDX(2), 1833 DEFINE_PSEUDO_VFP_D_IDX(3), 1834 DEFINE_PSEUDO_VFP_D_IDX(4), 1835 DEFINE_PSEUDO_VFP_D_IDX(5), 1836 DEFINE_PSEUDO_VFP_D_IDX(6), 1837 DEFINE_PSEUDO_VFP_D_IDX(7), 1838 DEFINE_PSEUDO_VFP_D_IDX(8), 1839 DEFINE_PSEUDO_VFP_D_IDX(9), 1840 DEFINE_PSEUDO_VFP_D_IDX(10), 1841 DEFINE_PSEUDO_VFP_D_IDX(11), 1842 DEFINE_PSEUDO_VFP_D_IDX(12), 1843 DEFINE_PSEUDO_VFP_D_IDX(13), 1844 DEFINE_PSEUDO_VFP_D_IDX(14), 1845 DEFINE_PSEUDO_VFP_D_IDX(15), 1846 DEFINE_PSEUDO_VFP_D_IDX(16), 1847 DEFINE_PSEUDO_VFP_D_IDX(17), 1848 DEFINE_PSEUDO_VFP_D_IDX(18), 1849 DEFINE_PSEUDO_VFP_D_IDX(19), 1850 DEFINE_PSEUDO_VFP_D_IDX(20), 1851 DEFINE_PSEUDO_VFP_D_IDX(21), 1852 DEFINE_PSEUDO_VFP_D_IDX(22), 1853 DEFINE_PSEUDO_VFP_D_IDX(23), 1854 DEFINE_PSEUDO_VFP_D_IDX(24), 1855 DEFINE_PSEUDO_VFP_D_IDX(25), 1856 DEFINE_PSEUDO_VFP_D_IDX(26), 1857 DEFINE_PSEUDO_VFP_D_IDX(27), 1858 DEFINE_PSEUDO_VFP_D_IDX(28), 1859 DEFINE_PSEUDO_VFP_D_IDX(29), 1860 DEFINE_PSEUDO_VFP_D_IDX(30), 1861 DEFINE_PSEUDO_VFP_D_IDX(31) 1862 1863 }; 1864 1865 //_STRUCT_ARM_EXCEPTION_STATE64 1866 //{ 1867 // uint64_t far; /* Virtual Fault Address */ 1868 // uint32_t esr; /* Exception syndrome */ 1869 // uint32_t exception; /* number of arm exception taken */ 1870 //}; 1871 1872 // Exception registers 1873 const DNBRegisterInfo DNBArchMachARM64::g_exc_registers[] = { 1874 {e_regSetEXC, exc_far, "far", NULL, Uint, Hex, 8, EXC_OFFSET(__far), 1875 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1876 INVALID_NUB_REGNUM, NULL, NULL}, 1877 {e_regSetEXC, exc_esr, "esr", NULL, Uint, Hex, 4, EXC_OFFSET(__esr), 1878 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1879 INVALID_NUB_REGNUM, NULL, NULL}, 1880 {e_regSetEXC, exc_exception, "exception", NULL, Uint, Hex, 4, 1881 EXC_OFFSET(__exception), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1882 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}}; 1883 1884 // Number of registers in each register set 1885 const size_t DNBArchMachARM64::k_num_gpr_registers = 1886 sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo); 1887 const size_t DNBArchMachARM64::k_num_vfp_registers = 1888 sizeof(g_vfp_registers) / sizeof(DNBRegisterInfo); 1889 const size_t DNBArchMachARM64::k_num_exc_registers = 1890 sizeof(g_exc_registers) / sizeof(DNBRegisterInfo); 1891 const size_t DNBArchMachARM64::k_num_all_registers = 1892 k_num_gpr_registers + k_num_vfp_registers + k_num_exc_registers; 1893 1894 // Register set definitions. The first definitions at register set index 1895 // of zero is for all registers, followed by other registers sets. The 1896 // register information for the all register set need not be filled in. 1897 const DNBRegisterSetInfo DNBArchMachARM64::g_reg_sets[] = { 1898 {"ARM64 Registers", NULL, k_num_all_registers}, 1899 {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers}, 1900 {"Floating Point Registers", g_vfp_registers, k_num_vfp_registers}, 1901 {"Exception State Registers", g_exc_registers, k_num_exc_registers}}; 1902 // Total number of register sets for this architecture 1903 const size_t DNBArchMachARM64::k_num_register_sets = 1904 sizeof(g_reg_sets) / sizeof(DNBRegisterSetInfo); 1905 1906 const DNBRegisterSetInfo * 1907 DNBArchMachARM64::GetRegisterSetInfo(nub_size_t *num_reg_sets) { 1908 *num_reg_sets = k_num_register_sets; 1909 return g_reg_sets; 1910 } 1911 1912 bool DNBArchMachARM64::FixGenericRegisterNumber(uint32_t &set, uint32_t ®) { 1913 if (set == REGISTER_SET_GENERIC) { 1914 switch (reg) { 1915 case GENERIC_REGNUM_PC: // Program Counter 1916 set = e_regSetGPR; 1917 reg = gpr_pc; 1918 break; 1919 1920 case GENERIC_REGNUM_SP: // Stack Pointer 1921 set = e_regSetGPR; 1922 reg = gpr_sp; 1923 break; 1924 1925 case GENERIC_REGNUM_FP: // Frame Pointer 1926 set = e_regSetGPR; 1927 reg = gpr_fp; 1928 break; 1929 1930 case GENERIC_REGNUM_RA: // Return Address 1931 set = e_regSetGPR; 1932 reg = gpr_lr; 1933 break; 1934 1935 case GENERIC_REGNUM_FLAGS: // Processor flags register 1936 set = e_regSetGPR; 1937 reg = gpr_cpsr; 1938 break; 1939 1940 case GENERIC_REGNUM_ARG1: 1941 case GENERIC_REGNUM_ARG2: 1942 case GENERIC_REGNUM_ARG3: 1943 case GENERIC_REGNUM_ARG4: 1944 case GENERIC_REGNUM_ARG5: 1945 case GENERIC_REGNUM_ARG6: 1946 set = e_regSetGPR; 1947 reg = gpr_x0 + reg - GENERIC_REGNUM_ARG1; 1948 break; 1949 1950 default: 1951 return false; 1952 } 1953 } 1954 return true; 1955 } 1956 bool DNBArchMachARM64::GetRegisterValue(uint32_t set, uint32_t reg, 1957 DNBRegisterValue *value) { 1958 if (!FixGenericRegisterNumber(set, reg)) 1959 return false; 1960 1961 if (GetRegisterState(set, false) != KERN_SUCCESS) 1962 return false; 1963 1964 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1965 if (regInfo) { 1966 value->info = *regInfo; 1967 switch (set) { 1968 case e_regSetGPR: 1969 if (reg <= gpr_pc) { 1970 #if defined(__LP64__) 1971 if (reg == gpr_pc) 1972 value->value.uint64 = arm_thread_state64_get_pc (m_state.context.gpr); 1973 else if (reg == gpr_lr) 1974 value->value.uint64 = arm_thread_state64_get_lr (m_state.context.gpr); 1975 else if (reg == gpr_sp) 1976 value->value.uint64 = arm_thread_state64_get_sp (m_state.context.gpr); 1977 else if (reg == gpr_fp) 1978 value->value.uint64 = arm_thread_state64_get_fp (m_state.context.gpr); 1979 else 1980 value->value.uint64 = m_state.context.gpr.__x[reg]; 1981 #else 1982 value->value.uint64 = m_state.context.gpr.__x[reg]; 1983 #endif 1984 return true; 1985 } else if (reg == gpr_cpsr) { 1986 value->value.uint32 = m_state.context.gpr.__cpsr; 1987 return true; 1988 } 1989 break; 1990 1991 case e_regSetVFP: 1992 1993 if (reg >= vfp_v0 && reg <= vfp_v31) { 1994 #if defined(__arm64__) || defined(__aarch64__) 1995 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_v0], 1996 16); 1997 #else 1998 memcpy(&value->value.v_uint8, 1999 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), 2000 16); 2001 #endif 2002 return true; 2003 } else if (reg == vfp_fpsr) { 2004 #if defined(__arm64__) || defined(__aarch64__) 2005 memcpy(&value->value.uint32, &m_state.context.vfp.__fpsr, 4); 2006 #else 2007 memcpy(&value->value.uint32, 2008 ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0, 4); 2009 #endif 2010 return true; 2011 } else if (reg == vfp_fpcr) { 2012 #if defined(__arm64__) || defined(__aarch64__) 2013 memcpy(&value->value.uint32, &m_state.context.vfp.__fpcr, 4); 2014 #else 2015 memcpy(&value->value.uint32, 2016 ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 4, 4); 2017 #endif 2018 return true; 2019 } else if (reg >= vfp_s0 && reg <= vfp_s31) { 2020 #if defined(__arm64__) || defined(__aarch64__) 2021 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_s0], 2022 4); 2023 #else 2024 memcpy(&value->value.v_uint8, 2025 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), 2026 4); 2027 #endif 2028 return true; 2029 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 2030 #if defined(__arm64__) || defined(__aarch64__) 2031 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_d0], 2032 8); 2033 #else 2034 memcpy(&value->value.v_uint8, 2035 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), 2036 8); 2037 #endif 2038 return true; 2039 } 2040 break; 2041 2042 case e_regSetEXC: 2043 if (reg == exc_far) { 2044 value->value.uint64 = m_state.context.exc.__far; 2045 return true; 2046 } else if (reg == exc_esr) { 2047 value->value.uint32 = m_state.context.exc.__esr; 2048 return true; 2049 } else if (reg == exc_exception) { 2050 value->value.uint32 = m_state.context.exc.__exception; 2051 return true; 2052 } 2053 break; 2054 } 2055 } 2056 return false; 2057 } 2058 2059 bool DNBArchMachARM64::SetRegisterValue(uint32_t set, uint32_t reg, 2060 const DNBRegisterValue *value) { 2061 if (!FixGenericRegisterNumber(set, reg)) 2062 return false; 2063 2064 if (GetRegisterState(set, false) != KERN_SUCCESS) 2065 return false; 2066 2067 bool success = false; 2068 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 2069 if (regInfo) { 2070 switch (set) { 2071 case e_regSetGPR: 2072 if (reg <= gpr_pc) { 2073 #if defined(__LP64__) 2074 uint64_t signed_value = value->value.uint64; 2075 #if __has_feature(ptrauth_calls) 2076 // The incoming value could be garbage. Strip it to avoid 2077 // trapping when it gets resigned in the thread state. 2078 signed_value = (uint64_t) ptrauth_strip((void*) signed_value, ptrauth_key_function_pointer); 2079 signed_value = (uint64_t) ptrauth_sign_unauthenticated((void*) signed_value, ptrauth_key_function_pointer, 0); 2080 #endif 2081 if (reg == gpr_pc) 2082 arm_thread_state64_set_pc_fptr (m_state.context.gpr, (void*) signed_value); 2083 else if (reg == gpr_lr) 2084 arm_thread_state64_set_lr_fptr (m_state.context.gpr, (void*) signed_value); 2085 else if (reg == gpr_sp) 2086 arm_thread_state64_set_sp (m_state.context.gpr, value->value.uint64); 2087 else if (reg == gpr_fp) 2088 arm_thread_state64_set_fp (m_state.context.gpr, value->value.uint64); 2089 else 2090 m_state.context.gpr.__x[reg] = value->value.uint64; 2091 #else 2092 m_state.context.gpr.__x[reg] = value->value.uint64; 2093 #endif 2094 success = true; 2095 } else if (reg == gpr_cpsr) { 2096 m_state.context.gpr.__cpsr = value->value.uint32; 2097 success = true; 2098 } 2099 break; 2100 2101 case e_regSetVFP: 2102 if (reg >= vfp_v0 && reg <= vfp_v31) { 2103 #if defined(__arm64__) || defined(__aarch64__) 2104 memcpy(&m_state.context.vfp.__v[reg - vfp_v0], &value->value.v_uint8, 2105 16); 2106 #else 2107 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), 2108 &value->value.v_uint8, 16); 2109 #endif 2110 success = true; 2111 } else if (reg == vfp_fpsr) { 2112 #if defined(__arm64__) || defined(__aarch64__) 2113 memcpy(&m_state.context.vfp.__fpsr, &value->value.uint32, 4); 2114 #else 2115 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0, 2116 &value->value.uint32, 4); 2117 #endif 2118 success = true; 2119 } else if (reg == vfp_fpcr) { 2120 #if defined(__arm64__) || defined(__aarch64__) 2121 memcpy(&m_state.context.vfp.__fpcr, &value->value.uint32, 4); 2122 #else 2123 memcpy(((uint8_t *)m_state.context.vfp.opaque) + (32 * 16) + 4, 2124 &value->value.uint32, 4); 2125 #endif 2126 success = true; 2127 } else if (reg >= vfp_s0 && reg <= vfp_s31) { 2128 #if defined(__arm64__) || defined(__aarch64__) 2129 memcpy(&m_state.context.vfp.__v[reg - vfp_s0], &value->value.v_uint8, 2130 4); 2131 #else 2132 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), 2133 &value->value.v_uint8, 4); 2134 #endif 2135 success = true; 2136 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 2137 #if defined(__arm64__) || defined(__aarch64__) 2138 memcpy(&m_state.context.vfp.__v[reg - vfp_d0], &value->value.v_uint8, 2139 8); 2140 #else 2141 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), 2142 &value->value.v_uint8, 8); 2143 #endif 2144 success = true; 2145 } 2146 break; 2147 2148 case e_regSetEXC: 2149 if (reg == exc_far) { 2150 m_state.context.exc.__far = value->value.uint64; 2151 success = true; 2152 } else if (reg == exc_esr) { 2153 m_state.context.exc.__esr = value->value.uint32; 2154 success = true; 2155 } else if (reg == exc_exception) { 2156 m_state.context.exc.__exception = value->value.uint32; 2157 success = true; 2158 } 2159 break; 2160 } 2161 } 2162 if (success) 2163 return SetRegisterState(set) == KERN_SUCCESS; 2164 return false; 2165 } 2166 2167 kern_return_t DNBArchMachARM64::GetRegisterState(int set, bool force) { 2168 switch (set) { 2169 case e_regSetALL: 2170 return GetGPRState(force) | GetVFPState(force) | GetEXCState(force) | 2171 GetDBGState(force); 2172 case e_regSetGPR: 2173 return GetGPRState(force); 2174 case e_regSetVFP: 2175 return GetVFPState(force); 2176 case e_regSetEXC: 2177 return GetEXCState(force); 2178 case e_regSetDBG: 2179 return GetDBGState(force); 2180 default: 2181 break; 2182 } 2183 return KERN_INVALID_ARGUMENT; 2184 } 2185 2186 kern_return_t DNBArchMachARM64::SetRegisterState(int set) { 2187 // Make sure we have a valid context to set. 2188 kern_return_t err = GetRegisterState(set, false); 2189 if (err != KERN_SUCCESS) 2190 return err; 2191 2192 switch (set) { 2193 case e_regSetALL: 2194 return SetGPRState() | SetVFPState() | SetEXCState() | SetDBGState(false); 2195 case e_regSetGPR: 2196 return SetGPRState(); 2197 case e_regSetVFP: 2198 return SetVFPState(); 2199 case e_regSetEXC: 2200 return SetEXCState(); 2201 case e_regSetDBG: 2202 return SetDBGState(false); 2203 default: 2204 break; 2205 } 2206 return KERN_INVALID_ARGUMENT; 2207 } 2208 2209 bool DNBArchMachARM64::RegisterSetStateIsValid(int set) const { 2210 return m_state.RegsAreValid(set); 2211 } 2212 2213 nub_size_t DNBArchMachARM64::GetRegisterContext(void *buf, nub_size_t buf_len) { 2214 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 2215 sizeof(m_state.context.exc); 2216 2217 if (buf && buf_len) { 2218 if (size > buf_len) 2219 size = buf_len; 2220 2221 bool force = false; 2222 if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force)) 2223 return 0; 2224 2225 // Copy each struct individually to avoid any padding that might be between 2226 // the structs in m_state.context 2227 uint8_t *p = (uint8_t *)buf; 2228 ::memcpy(p, &m_state.context.gpr, sizeof(m_state.context.gpr)); 2229 p += sizeof(m_state.context.gpr); 2230 ::memcpy(p, &m_state.context.vfp, sizeof(m_state.context.vfp)); 2231 p += sizeof(m_state.context.vfp); 2232 ::memcpy(p, &m_state.context.exc, sizeof(m_state.context.exc)); 2233 p += sizeof(m_state.context.exc); 2234 2235 size_t bytes_written = p - (uint8_t *)buf; 2236 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2237 assert(bytes_written == size); 2238 } 2239 DNBLogThreadedIf( 2240 LOG_THREAD, 2241 "DNBArchMachARM64::GetRegisterContext (buf = %p, len = %zu) => %zu", buf, 2242 buf_len, size); 2243 // Return the size of the register context even if NULL was passed in 2244 return size; 2245 } 2246 2247 nub_size_t DNBArchMachARM64::SetRegisterContext(const void *buf, 2248 nub_size_t buf_len) { 2249 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 2250 sizeof(m_state.context.exc); 2251 2252 if (buf == NULL || buf_len == 0) 2253 size = 0; 2254 2255 if (size) { 2256 if (size > buf_len) 2257 size = buf_len; 2258 2259 // Copy each struct individually to avoid any padding that might be between 2260 // the structs in m_state.context 2261 uint8_t *p = (uint8_t *)buf; 2262 ::memcpy(&m_state.context.gpr, p, sizeof(m_state.context.gpr)); 2263 p += sizeof(m_state.context.gpr); 2264 ::memcpy(&m_state.context.vfp, p, sizeof(m_state.context.vfp)); 2265 p += sizeof(m_state.context.vfp); 2266 ::memcpy(&m_state.context.exc, p, sizeof(m_state.context.exc)); 2267 p += sizeof(m_state.context.exc); 2268 2269 size_t bytes_written = p - (uint8_t *)buf; 2270 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2271 assert(bytes_written == size); 2272 SetGPRState(); 2273 SetVFPState(); 2274 SetEXCState(); 2275 } 2276 DNBLogThreadedIf( 2277 LOG_THREAD, 2278 "DNBArchMachARM64::SetRegisterContext (buf = %p, len = %zu) => %zu", buf, 2279 buf_len, size); 2280 return size; 2281 } 2282 2283 uint32_t DNBArchMachARM64::SaveRegisterState() { 2284 kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber()); 2285 DNBLogThreadedIf( 2286 LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u " 2287 "(SetGPRState() for stop_count = %u)", 2288 m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount()); 2289 2290 // Always re-read the registers because above we call thread_abort_safely(); 2291 bool force = true; 2292 2293 if ((kret = GetGPRState(force)) != KERN_SUCCESS) { 2294 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () " 2295 "error: GPR regs failed to read: %u ", 2296 kret); 2297 } else if ((kret = GetVFPState(force)) != KERN_SUCCESS) { 2298 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () " 2299 "error: %s regs failed to read: %u", 2300 "VFP", kret); 2301 } else { 2302 const uint32_t save_id = GetNextRegisterStateSaveID(); 2303 m_saved_register_states[save_id] = m_state.context; 2304 return save_id; 2305 } 2306 return UINT32_MAX; 2307 } 2308 2309 bool DNBArchMachARM64::RestoreRegisterState(uint32_t save_id) { 2310 SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id); 2311 if (pos != m_saved_register_states.end()) { 2312 m_state.context.gpr = pos->second.gpr; 2313 m_state.context.vfp = pos->second.vfp; 2314 kern_return_t kret; 2315 bool success = true; 2316 if ((kret = SetGPRState()) != KERN_SUCCESS) { 2317 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState " 2318 "(save_id = %u) error: GPR regs failed to " 2319 "write: %u", 2320 save_id, kret); 2321 success = false; 2322 } else if ((kret = SetVFPState()) != KERN_SUCCESS) { 2323 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState " 2324 "(save_id = %u) error: %s regs failed to " 2325 "write: %u", 2326 save_id, "VFP", kret); 2327 success = false; 2328 } 2329 m_saved_register_states.erase(pos); 2330 return success; 2331 } 2332 return false; 2333 } 2334 2335 #endif // #if defined (ARM_THREAD_STATE64_COUNT) 2336 #endif // #if defined (__arm__) || defined (__arm64__) || defined (__aarch64__) 2337