1 //===-- DNBArchMachARM64.cpp ------------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Created by Greg Clayton on 6/25/07. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #if defined(__arm__) || defined(__arm64__) || defined(__aarch64__) 15 16 #include "MacOSX/arm64/DNBArchImplARM64.h" 17 18 #if defined(ARM_THREAD_STATE64_COUNT) 19 20 #include "DNB.h" 21 #include "DNBBreakpoint.h" 22 #include "DNBLog.h" 23 #include "DNBRegisterInfo.h" 24 #include "MacOSX/MachProcess.h" 25 #include "MacOSX/MachThread.h" 26 27 #include <inttypes.h> 28 #include <sys/sysctl.h> 29 30 // Break only in privileged or user mode 31 // (PAC bits in the DBGWVRn_EL1 watchpoint control register) 32 #define S_USER ((uint32_t)(2u << 1)) 33 34 #define BCR_ENABLE ((uint32_t)(1u)) 35 #define WCR_ENABLE ((uint32_t)(1u)) 36 37 // Watchpoint load/store 38 // (LSC bits in the DBGWVRn_EL1 watchpoint control register) 39 #define WCR_LOAD ((uint32_t)(1u << 3)) 40 #define WCR_STORE ((uint32_t)(1u << 4)) 41 42 // Enable breakpoint, watchpoint, and vector catch debug exceptions. 43 // (MDE bit in the MDSCR_EL1 register. Equivalent to the MDBGen bit in 44 // DBGDSCRext in Aarch32) 45 #define MDE_ENABLE ((uint32_t)(1u << 15)) 46 47 // Single instruction step 48 // (SS bit in the MDSCR_EL1 register) 49 #define SS_ENABLE ((uint32_t)(1u)) 50 51 static const uint8_t g_arm64_breakpoint_opcode[] = { 52 0x00, 0x00, 0x20, 0xD4}; // "brk #0", 0xd4200000 in BE byte order 53 static const uint8_t g_arm_breakpoint_opcode[] = { 54 0xFE, 0xDE, 0xFF, 0xE7}; // this armv7 insn also works in arm64 55 56 // If we need to set one logical watchpoint by using 57 // two hardware watchpoint registers, the watchpoint 58 // will be split into a "high" and "low" watchpoint. 59 // Record both of them in the LoHi array. 60 61 // It's safe to initialize to all 0's since 62 // hi > lo and therefore LoHi[i] cannot be 0. 63 static uint32_t LoHi[16] = {0}; 64 65 void DNBArchMachARM64::Initialize() { 66 DNBArchPluginInfo arch_plugin_info = { 67 CPU_TYPE_ARM64, DNBArchMachARM64::Create, 68 DNBArchMachARM64::GetRegisterSetInfo, 69 DNBArchMachARM64::SoftwareBreakpointOpcode}; 70 71 // Register this arch plug-in with the main protocol class 72 DNBArchProtocol::RegisterArchPlugin(arch_plugin_info); 73 } 74 75 DNBArchProtocol *DNBArchMachARM64::Create(MachThread *thread) { 76 DNBArchMachARM64 *obj = new DNBArchMachARM64(thread); 77 78 return obj; 79 } 80 81 const uint8_t * 82 DNBArchMachARM64::SoftwareBreakpointOpcode(nub_size_t byte_size) { 83 return g_arm_breakpoint_opcode; 84 } 85 86 uint32_t DNBArchMachARM64::GetCPUType() { return CPU_TYPE_ARM64; } 87 88 uint64_t DNBArchMachARM64::GetPC(uint64_t failValue) { 89 // Get program counter 90 if (GetGPRState(false) == KERN_SUCCESS) 91 return m_state.context.gpr.__pc; 92 return failValue; 93 } 94 95 kern_return_t DNBArchMachARM64::SetPC(uint64_t value) { 96 // Get program counter 97 kern_return_t err = GetGPRState(false); 98 if (err == KERN_SUCCESS) { 99 m_state.context.gpr.__pc = value; 100 err = SetGPRState(); 101 } 102 return err == KERN_SUCCESS; 103 } 104 105 uint64_t DNBArchMachARM64::GetSP(uint64_t failValue) { 106 // Get stack pointer 107 if (GetGPRState(false) == KERN_SUCCESS) 108 return m_state.context.gpr.__sp; 109 return failValue; 110 } 111 112 kern_return_t DNBArchMachARM64::GetGPRState(bool force) { 113 int set = e_regSetGPR; 114 // Check if we have valid cached registers 115 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 116 return KERN_SUCCESS; 117 118 // Read the registers from our thread 119 mach_msg_type_number_t count = e_regSetGPRCount; 120 kern_return_t kret = 121 ::thread_get_state(m_thread->MachPortNumber(), ARM_THREAD_STATE64, 122 (thread_state_t)&m_state.context.gpr, &count); 123 if (DNBLogEnabledForAny(LOG_THREAD)) { 124 uint64_t *x = &m_state.context.gpr.__x[0]; 125 DNBLogThreaded( 126 "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count = %u) regs" 127 "\n x0=%16.16llx" 128 "\n x1=%16.16llx" 129 "\n x2=%16.16llx" 130 "\n x3=%16.16llx" 131 "\n x4=%16.16llx" 132 "\n x5=%16.16llx" 133 "\n x6=%16.16llx" 134 "\n x7=%16.16llx" 135 "\n x8=%16.16llx" 136 "\n x9=%16.16llx" 137 "\n x10=%16.16llx" 138 "\n x11=%16.16llx" 139 "\n x12=%16.16llx" 140 "\n x13=%16.16llx" 141 "\n x14=%16.16llx" 142 "\n x15=%16.16llx" 143 "\n x16=%16.16llx" 144 "\n x17=%16.16llx" 145 "\n x18=%16.16llx" 146 "\n x19=%16.16llx" 147 "\n x20=%16.16llx" 148 "\n x21=%16.16llx" 149 "\n x22=%16.16llx" 150 "\n x23=%16.16llx" 151 "\n x24=%16.16llx" 152 "\n x25=%16.16llx" 153 "\n x26=%16.16llx" 154 "\n x27=%16.16llx" 155 "\n x28=%16.16llx" 156 "\n fp=%16.16llx" 157 "\n lr=%16.16llx" 158 "\n sp=%16.16llx" 159 "\n pc=%16.16llx" 160 "\n cpsr=%8.8x", 161 m_thread->MachPortNumber(), e_regSetGPR, e_regSetGPRCount, kret, count, 162 x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[0], x[11], 163 x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], x[20], x[21], 164 x[22], x[23], x[24], x[25], x[26], x[27], x[28], 165 m_state.context.gpr.__fp, m_state.context.gpr.__lr, 166 m_state.context.gpr.__sp, m_state.context.gpr.__pc, 167 m_state.context.gpr.__cpsr); 168 } 169 m_state.SetError(set, Read, kret); 170 return kret; 171 } 172 173 kern_return_t DNBArchMachARM64::GetVFPState(bool force) { 174 int set = e_regSetVFP; 175 // Check if we have valid cached registers 176 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 177 return KERN_SUCCESS; 178 179 // Read the registers from our thread 180 mach_msg_type_number_t count = e_regSetVFPCount; 181 kern_return_t kret = 182 ::thread_get_state(m_thread->MachPortNumber(), ARM_NEON_STATE64, 183 (thread_state_t)&m_state.context.vfp, &count); 184 if (DNBLogEnabledForAny(LOG_THREAD)) { 185 #if defined(__arm64__) || defined(__aarch64__) 186 DNBLogThreaded( 187 "thread_get_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs" 188 "\n q0 = 0x%16.16llx%16.16llx" 189 "\n q1 = 0x%16.16llx%16.16llx" 190 "\n q2 = 0x%16.16llx%16.16llx" 191 "\n q3 = 0x%16.16llx%16.16llx" 192 "\n q4 = 0x%16.16llx%16.16llx" 193 "\n q5 = 0x%16.16llx%16.16llx" 194 "\n q6 = 0x%16.16llx%16.16llx" 195 "\n q7 = 0x%16.16llx%16.16llx" 196 "\n q8 = 0x%16.16llx%16.16llx" 197 "\n q9 = 0x%16.16llx%16.16llx" 198 "\n q10 = 0x%16.16llx%16.16llx" 199 "\n q11 = 0x%16.16llx%16.16llx" 200 "\n q12 = 0x%16.16llx%16.16llx" 201 "\n q13 = 0x%16.16llx%16.16llx" 202 "\n q14 = 0x%16.16llx%16.16llx" 203 "\n q15 = 0x%16.16llx%16.16llx" 204 "\n q16 = 0x%16.16llx%16.16llx" 205 "\n q17 = 0x%16.16llx%16.16llx" 206 "\n q18 = 0x%16.16llx%16.16llx" 207 "\n q19 = 0x%16.16llx%16.16llx" 208 "\n q20 = 0x%16.16llx%16.16llx" 209 "\n q21 = 0x%16.16llx%16.16llx" 210 "\n q22 = 0x%16.16llx%16.16llx" 211 "\n q23 = 0x%16.16llx%16.16llx" 212 "\n q24 = 0x%16.16llx%16.16llx" 213 "\n q25 = 0x%16.16llx%16.16llx" 214 "\n q26 = 0x%16.16llx%16.16llx" 215 "\n q27 = 0x%16.16llx%16.16llx" 216 "\n q28 = 0x%16.16llx%16.16llx" 217 "\n q29 = 0x%16.16llx%16.16llx" 218 "\n q30 = 0x%16.16llx%16.16llx" 219 "\n q31 = 0x%16.16llx%16.16llx" 220 "\n fpsr = 0x%8.8x" 221 "\n fpcr = 0x%8.8x\n\n", 222 m_thread->MachPortNumber(), e_regSetVFP, e_regSetVFPCount, kret, count, 223 ((uint64_t *)&m_state.context.vfp.__v[0])[0], 224 ((uint64_t *)&m_state.context.vfp.__v[0])[1], 225 ((uint64_t *)&m_state.context.vfp.__v[1])[0], 226 ((uint64_t *)&m_state.context.vfp.__v[1])[1], 227 ((uint64_t *)&m_state.context.vfp.__v[2])[0], 228 ((uint64_t *)&m_state.context.vfp.__v[2])[1], 229 ((uint64_t *)&m_state.context.vfp.__v[3])[0], 230 ((uint64_t *)&m_state.context.vfp.__v[3])[1], 231 ((uint64_t *)&m_state.context.vfp.__v[4])[0], 232 ((uint64_t *)&m_state.context.vfp.__v[4])[1], 233 ((uint64_t *)&m_state.context.vfp.__v[5])[0], 234 ((uint64_t *)&m_state.context.vfp.__v[5])[1], 235 ((uint64_t *)&m_state.context.vfp.__v[6])[0], 236 ((uint64_t *)&m_state.context.vfp.__v[6])[1], 237 ((uint64_t *)&m_state.context.vfp.__v[7])[0], 238 ((uint64_t *)&m_state.context.vfp.__v[7])[1], 239 ((uint64_t *)&m_state.context.vfp.__v[8])[0], 240 ((uint64_t *)&m_state.context.vfp.__v[8])[1], 241 ((uint64_t *)&m_state.context.vfp.__v[9])[0], 242 ((uint64_t *)&m_state.context.vfp.__v[9])[1], 243 ((uint64_t *)&m_state.context.vfp.__v[10])[0], 244 ((uint64_t *)&m_state.context.vfp.__v[10])[1], 245 ((uint64_t *)&m_state.context.vfp.__v[11])[0], 246 ((uint64_t *)&m_state.context.vfp.__v[11])[1], 247 ((uint64_t *)&m_state.context.vfp.__v[12])[0], 248 ((uint64_t *)&m_state.context.vfp.__v[12])[1], 249 ((uint64_t *)&m_state.context.vfp.__v[13])[0], 250 ((uint64_t *)&m_state.context.vfp.__v[13])[1], 251 ((uint64_t *)&m_state.context.vfp.__v[14])[0], 252 ((uint64_t *)&m_state.context.vfp.__v[14])[1], 253 ((uint64_t *)&m_state.context.vfp.__v[15])[0], 254 ((uint64_t *)&m_state.context.vfp.__v[15])[1], 255 ((uint64_t *)&m_state.context.vfp.__v[16])[0], 256 ((uint64_t *)&m_state.context.vfp.__v[16])[1], 257 ((uint64_t *)&m_state.context.vfp.__v[17])[0], 258 ((uint64_t *)&m_state.context.vfp.__v[17])[1], 259 ((uint64_t *)&m_state.context.vfp.__v[18])[0], 260 ((uint64_t *)&m_state.context.vfp.__v[18])[1], 261 ((uint64_t *)&m_state.context.vfp.__v[19])[0], 262 ((uint64_t *)&m_state.context.vfp.__v[19])[1], 263 ((uint64_t *)&m_state.context.vfp.__v[20])[0], 264 ((uint64_t *)&m_state.context.vfp.__v[20])[1], 265 ((uint64_t *)&m_state.context.vfp.__v[21])[0], 266 ((uint64_t *)&m_state.context.vfp.__v[21])[1], 267 ((uint64_t *)&m_state.context.vfp.__v[22])[0], 268 ((uint64_t *)&m_state.context.vfp.__v[22])[1], 269 ((uint64_t *)&m_state.context.vfp.__v[23])[0], 270 ((uint64_t *)&m_state.context.vfp.__v[23])[1], 271 ((uint64_t *)&m_state.context.vfp.__v[24])[0], 272 ((uint64_t *)&m_state.context.vfp.__v[24])[1], 273 ((uint64_t *)&m_state.context.vfp.__v[25])[0], 274 ((uint64_t *)&m_state.context.vfp.__v[25])[1], 275 ((uint64_t *)&m_state.context.vfp.__v[26])[0], 276 ((uint64_t *)&m_state.context.vfp.__v[26])[1], 277 ((uint64_t *)&m_state.context.vfp.__v[27])[0], 278 ((uint64_t *)&m_state.context.vfp.__v[27])[1], 279 ((uint64_t *)&m_state.context.vfp.__v[28])[0], 280 ((uint64_t *)&m_state.context.vfp.__v[28])[1], 281 ((uint64_t *)&m_state.context.vfp.__v[29])[0], 282 ((uint64_t *)&m_state.context.vfp.__v[29])[1], 283 ((uint64_t *)&m_state.context.vfp.__v[30])[0], 284 ((uint64_t *)&m_state.context.vfp.__v[30])[1], 285 ((uint64_t *)&m_state.context.vfp.__v[31])[0], 286 ((uint64_t *)&m_state.context.vfp.__v[31])[1], 287 m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr); 288 #endif 289 } 290 m_state.SetError(set, Read, kret); 291 return kret; 292 } 293 294 kern_return_t DNBArchMachARM64::GetEXCState(bool force) { 295 int set = e_regSetEXC; 296 // Check if we have valid cached registers 297 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 298 return KERN_SUCCESS; 299 300 // Read the registers from our thread 301 mach_msg_type_number_t count = e_regSetEXCCount; 302 kern_return_t kret = 303 ::thread_get_state(m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, 304 (thread_state_t)&m_state.context.exc, &count); 305 m_state.SetError(set, Read, kret); 306 return kret; 307 } 308 309 static void DumpDBGState(const arm_debug_state_t &dbg) { 310 uint32_t i = 0; 311 for (i = 0; i < 16; i++) 312 DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } " 313 "WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }", 314 i, i, dbg.__bvr[i], dbg.__bcr[i], i, i, dbg.__wvr[i], 315 dbg.__wcr[i]); 316 } 317 318 kern_return_t DNBArchMachARM64::GetDBGState(bool force) { 319 int set = e_regSetDBG; 320 321 // Check if we have valid cached registers 322 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 323 return KERN_SUCCESS; 324 325 // Read the registers from our thread 326 mach_msg_type_number_t count = e_regSetDBGCount; 327 kern_return_t kret = 328 ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64, 329 (thread_state_t)&m_state.dbg, &count); 330 m_state.SetError(set, Read, kret); 331 332 return kret; 333 } 334 335 kern_return_t DNBArchMachARM64::SetGPRState() { 336 int set = e_regSetGPR; 337 kern_return_t kret = ::thread_set_state( 338 m_thread->MachPortNumber(), ARM_THREAD_STATE64, 339 (thread_state_t)&m_state.context.gpr, e_regSetGPRCount); 340 m_state.SetError(set, Write, 341 kret); // Set the current write error for this register set 342 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 343 // state in case registers are read 344 // back differently 345 return kret; // Return the error code 346 } 347 348 kern_return_t DNBArchMachARM64::SetVFPState() { 349 int set = e_regSetVFP; 350 kern_return_t kret = ::thread_set_state( 351 m_thread->MachPortNumber(), ARM_NEON_STATE64, 352 (thread_state_t)&m_state.context.vfp, e_regSetVFPCount); 353 m_state.SetError(set, Write, 354 kret); // Set the current write error for this register set 355 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 356 // state in case registers are read 357 // back differently 358 return kret; // Return the error code 359 } 360 361 kern_return_t DNBArchMachARM64::SetEXCState() { 362 int set = e_regSetEXC; 363 kern_return_t kret = ::thread_set_state( 364 m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, 365 (thread_state_t)&m_state.context.exc, e_regSetEXCCount); 366 m_state.SetError(set, Write, 367 kret); // Set the current write error for this register set 368 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 369 // state in case registers are read 370 // back differently 371 return kret; // Return the error code 372 } 373 374 kern_return_t DNBArchMachARM64::SetDBGState(bool also_set_on_task) { 375 int set = e_regSetDBG; 376 kern_return_t kret = 377 ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64, 378 (thread_state_t)&m_state.dbg, e_regSetDBGCount); 379 if (also_set_on_task) { 380 kern_return_t task_kret = task_set_state( 381 m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE64, 382 (thread_state_t)&m_state.dbg, e_regSetDBGCount); 383 if (task_kret != KERN_SUCCESS) 384 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::SetDBGState failed " 385 "to set debug control register state: " 386 "0x%8.8x.", 387 task_kret); 388 } 389 m_state.SetError(set, Write, 390 kret); // Set the current write error for this register set 391 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 392 // state in case registers are read 393 // back differently 394 395 return kret; // Return the error code 396 } 397 398 void DNBArchMachARM64::ThreadWillResume() { 399 // Do we need to step this thread? If so, let the mach thread tell us so. 400 if (m_thread->IsStepping()) { 401 EnableHardwareSingleStep(true); 402 } 403 404 // Disable the triggered watchpoint temporarily before we resume. 405 // Plus, we try to enable hardware single step to execute past the instruction 406 // which triggered our watchpoint. 407 if (m_watchpoint_did_occur) { 408 if (m_watchpoint_hw_index >= 0) { 409 kern_return_t kret = GetDBGState(false); 410 if (kret == KERN_SUCCESS && 411 !IsWatchpointEnabled(m_state.dbg, m_watchpoint_hw_index)) { 412 // The watchpoint might have been disabled by the user. We don't need 413 // to do anything at all 414 // to enable hardware single stepping. 415 m_watchpoint_did_occur = false; 416 m_watchpoint_hw_index = -1; 417 return; 418 } 419 420 DisableHardwareWatchpoint(m_watchpoint_hw_index, false); 421 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 422 "DisableHardwareWatchpoint(%d) called", 423 m_watchpoint_hw_index); 424 425 // Enable hardware single step to move past the watchpoint-triggering 426 // instruction. 427 m_watchpoint_resume_single_step_enabled = 428 (EnableHardwareSingleStep(true) == KERN_SUCCESS); 429 430 // If we are not able to enable single step to move past the 431 // watchpoint-triggering instruction, 432 // at least we should reset the two watchpoint member variables so that 433 // the next time around 434 // this callback function is invoked, the enclosing logical branch is 435 // skipped. 436 if (!m_watchpoint_resume_single_step_enabled) { 437 // Reset the two watchpoint member variables. 438 m_watchpoint_did_occur = false; 439 m_watchpoint_hw_index = -1; 440 DNBLogThreadedIf( 441 LOG_WATCHPOINTS, 442 "DNBArchMachARM::ThreadWillResume() failed to enable single step"); 443 } else 444 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 445 "succeeded to enable single step"); 446 } 447 } 448 } 449 450 bool DNBArchMachARM64::NotifyException(MachException::Data &exc) { 451 452 switch (exc.exc_type) { 453 default: 454 break; 455 case EXC_BREAKPOINT: 456 if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_DA_DEBUG) { 457 // The data break address is passed as exc_data[1]. 458 nub_addr_t addr = exc.exc_data[1]; 459 // Find the hardware index with the side effect of possibly massaging the 460 // addr to return the starting address as seen from the debugger side. 461 uint32_t hw_index = GetHardwareWatchpointHit(addr); 462 463 // One logical watchpoint was split into two watchpoint locations because 464 // it was too big. If the watchpoint exception is indicating the 2nd half 465 // of the two-parter, find the address of the 1st half and report that -- 466 // that's what lldb is going to expect to see. 467 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 468 "watchpoint %d was hit on address " 469 "0x%llx", 470 hw_index, (uint64_t)addr); 471 const int num_watchpoints = NumSupportedHardwareWatchpoints(); 472 for (int i = 0; i < num_watchpoints; i++) { 473 if (LoHi[i] != 0 && LoHi[i] == hw_index && LoHi[i] != i && 474 GetWatchpointAddressByIndex(i) != INVALID_NUB_ADDRESS) { 475 addr = GetWatchpointAddressByIndex(i); 476 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 477 "It is a linked watchpoint; " 478 "rewritten to index %d addr 0x%llx", 479 LoHi[i], (uint64_t)addr); 480 } 481 } 482 483 if (hw_index != INVALID_NUB_HW_INDEX) { 484 m_watchpoint_did_occur = true; 485 m_watchpoint_hw_index = hw_index; 486 exc.exc_data[1] = addr; 487 // Piggyback the hw_index in the exc.data. 488 exc.exc_data.push_back(hw_index); 489 } 490 491 return true; 492 } 493 break; 494 } 495 return false; 496 } 497 498 bool DNBArchMachARM64::ThreadDidStop() { 499 bool success = true; 500 501 m_state.InvalidateAllRegisterStates(); 502 503 if (m_watchpoint_resume_single_step_enabled) { 504 // Great! We now disable the hardware single step as well as re-enable the 505 // hardware watchpoint. 506 // See also ThreadWillResume(). 507 if (EnableHardwareSingleStep(false) == KERN_SUCCESS) { 508 if (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0) { 509 ReenableHardwareWatchpoint(m_watchpoint_hw_index); 510 m_watchpoint_resume_single_step_enabled = false; 511 m_watchpoint_did_occur = false; 512 m_watchpoint_hw_index = -1; 513 } else { 514 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 515 "is true but (m_watchpoint_did_occur && " 516 "m_watchpoint_hw_index >= 0) does not hold!"); 517 } 518 } else { 519 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 520 "is true but unable to disable single step!"); 521 } 522 } 523 524 // Are we stepping a single instruction? 525 if (GetGPRState(true) == KERN_SUCCESS) { 526 // We are single stepping, was this the primary thread? 527 if (m_thread->IsStepping()) { 528 // This was the primary thread, we need to clear the trace 529 // bit if so. 530 success = EnableHardwareSingleStep(false) == KERN_SUCCESS; 531 } else { 532 // The MachThread will automatically restore the suspend count 533 // in ThreadDidStop(), so we don't need to do anything here if 534 // we weren't the primary thread the last time 535 } 536 } 537 return success; 538 } 539 540 // Set the single step bit in the processor status register. 541 kern_return_t DNBArchMachARM64::EnableHardwareSingleStep(bool enable) { 542 DNBError err; 543 DNBLogThreadedIf(LOG_STEP, "%s( enable = %d )", __FUNCTION__, enable); 544 545 err = GetGPRState(false); 546 547 if (err.Fail()) { 548 err.LogThreaded("%s: failed to read the GPR registers", __FUNCTION__); 549 return err.Error(); 550 } 551 552 err = GetDBGState(false); 553 554 if (err.Fail()) { 555 err.LogThreaded("%s: failed to read the DBG registers", __FUNCTION__); 556 return err.Error(); 557 } 558 559 if (enable) { 560 DNBLogThreadedIf(LOG_STEP, 561 "%s: Setting MDSCR_EL1 Single Step bit at pc 0x%llx", 562 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc); 563 m_state.dbg.__mdscr_el1 |= SS_ENABLE; 564 } else { 565 DNBLogThreadedIf(LOG_STEP, 566 "%s: Clearing MDSCR_EL1 Single Step bit at pc 0x%llx", 567 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc); 568 m_state.dbg.__mdscr_el1 &= ~(SS_ENABLE); 569 } 570 571 return SetDBGState(false); 572 } 573 574 // return 1 if bit "BIT" is set in "value" 575 static inline uint32_t bit(uint32_t value, uint32_t bit) { 576 return (value >> bit) & 1u; 577 } 578 579 // return the bitfield "value[msbit:lsbit]". 580 static inline uint64_t bits(uint64_t value, uint32_t msbit, uint32_t lsbit) { 581 assert(msbit >= lsbit); 582 uint64_t shift_left = sizeof(value) * 8 - 1 - msbit; 583 value <<= 584 shift_left; // shift anything above the msbit off of the unsigned edge 585 value >>= shift_left + lsbit; // shift it back again down to the lsbit 586 // (including undoing any shift from above) 587 return value; // return our result 588 } 589 590 uint32_t DNBArchMachARM64::NumSupportedHardwareWatchpoints() { 591 // Set the init value to something that will let us know that we need to 592 // autodetect how many watchpoints are supported dynamically... 593 static uint32_t g_num_supported_hw_watchpoints = UINT_MAX; 594 if (g_num_supported_hw_watchpoints == UINT_MAX) { 595 // Set this to zero in case we can't tell if there are any HW breakpoints 596 g_num_supported_hw_watchpoints = 0; 597 598 size_t len; 599 uint32_t n = 0; 600 len = sizeof(n); 601 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) { 602 g_num_supported_hw_watchpoints = n; 603 DNBLogThreadedIf(LOG_THREAD, "hw.optional.watchpoint=%u", n); 604 } else { 605 // For AArch64 we would need to look at ID_AA64DFR0_EL1 but debugserver runs in 606 // EL0 so it can't 607 // access that reg. The kernel should have filled in the sysctls based on it 608 // though. 609 #if defined(__arm__) 610 uint32_t register_DBGDIDR; 611 612 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 613 uint32_t numWRPs = bits(register_DBGDIDR, 31, 28); 614 // Zero is reserved for the WRP count, so don't increment it if it is zero 615 if (numWRPs > 0) 616 numWRPs++; 617 g_num_supported_hw_watchpoints = numWRPs; 618 DNBLogThreadedIf(LOG_THREAD, 619 "Number of supported hw watchpoints via asm(): %d", 620 g_num_supported_hw_watchpoints); 621 #endif 622 } 623 } 624 return g_num_supported_hw_watchpoints; 625 } 626 627 uint32_t DNBArchMachARM64::EnableHardwareWatchpoint(nub_addr_t addr, 628 nub_size_t size, bool read, 629 bool write, 630 bool also_set_on_task) { 631 DNBLogThreadedIf(LOG_WATCHPOINTS, 632 "DNBArchMachARM64::EnableHardwareWatchpoint(addr = " 633 "0x%8.8llx, size = %zu, read = %u, write = %u)", 634 (uint64_t)addr, size, read, write); 635 636 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 637 638 // Can't watch zero bytes 639 if (size == 0) 640 return INVALID_NUB_HW_INDEX; 641 642 // We must watch for either read or write 643 if (read == false && write == false) 644 return INVALID_NUB_HW_INDEX; 645 646 // Otherwise, can't watch more than 8 bytes per WVR/WCR pair 647 if (size > 8) 648 return INVALID_NUB_HW_INDEX; 649 650 // arm64 watchpoints really have an 8-byte alignment requirement. You can put 651 // a watchpoint on a 4-byte 652 // offset address but you can only watch 4 bytes with that watchpoint. 653 654 // arm64 watchpoints on an 8-byte (double word) aligned addr can watch any 655 // bytes in that 656 // 8-byte long region of memory. They can watch the 1st byte, the 2nd byte, 657 // 3rd byte, etc, or any 658 // combination therein by setting the bits in the BAS [12:5] (Byte Address 659 // Select) field of 660 // the DBGWCRn_EL1 reg for the watchpoint. 661 662 // If the MASK [28:24] bits in the DBGWCRn_EL1 allow a single watchpoint to 663 // monitor a larger region 664 // of memory (16 bytes, 32 bytes, or 2GB) but the Byte Address Select bitfield 665 // then selects a larger 666 // range of bytes, instead of individual bytes. See the ARMv8 Debug 667 // Architecture manual for details. 668 // This implementation does not currently use the MASK bits; the largest 669 // single region watched by a single 670 // watchpoint right now is 8-bytes. 671 672 nub_addr_t aligned_wp_address = addr & ~0x7; 673 uint32_t addr_dword_offset = addr & 0x7; 674 675 // Do we need to split up this logical watchpoint into two hardware watchpoint 676 // registers? 677 // e.g. a watchpoint of length 4 on address 6. We need do this with 678 // one watchpoint on address 0 with bytes 6 & 7 being monitored 679 // one watchpoint on address 8 with bytes 0, 1, 2, 3 being monitored 680 681 if (addr_dword_offset + size > 8) { 682 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 683 "EnableHardwareWatchpoint(addr = " 684 "0x%8.8llx, size = %zu) needs two " 685 "hardware watchpoints slots to monitor", 686 (uint64_t)addr, size); 687 int low_watchpoint_size = 8 - addr_dword_offset; 688 int high_watchpoint_size = addr_dword_offset + size - 8; 689 690 uint32_t lo = EnableHardwareWatchpoint(addr, low_watchpoint_size, read, 691 write, also_set_on_task); 692 if (lo == INVALID_NUB_HW_INDEX) 693 return INVALID_NUB_HW_INDEX; 694 uint32_t hi = 695 EnableHardwareWatchpoint(aligned_wp_address + 8, high_watchpoint_size, 696 read, write, also_set_on_task); 697 if (hi == INVALID_NUB_HW_INDEX) { 698 DisableHardwareWatchpoint(lo, also_set_on_task); 699 return INVALID_NUB_HW_INDEX; 700 } 701 // Tag this lo->hi mapping in our database. 702 LoHi[lo] = hi; 703 return lo; 704 } 705 706 // At this point 707 // 1 aligned_wp_address is the requested address rounded down to 8-byte 708 // alignment 709 // 2 addr_dword_offset is the offset into that double word (8-byte) region 710 // that we are watching 711 // 3 size is the number of bytes within that 8-byte region that we are 712 // watching 713 714 // Set the Byte Address Selects bits DBGWCRn_EL1 bits [12:5] based on the 715 // above. 716 // The bit shift and negation operation will give us 0b11 for 2, 0b1111 for 4, 717 // etc, up to 0b11111111 for 8. 718 // then we shift those bits left by the offset into this dword that we are 719 // interested in. 720 // e.g. if we are watching bytes 4,5,6,7 in a dword we want a BAS of 721 // 0b11110000. 722 uint32_t byte_address_select = ((1 << size) - 1) << addr_dword_offset; 723 724 // Read the debug state 725 kern_return_t kret = GetDBGState(false); 726 727 if (kret == KERN_SUCCESS) { 728 // Check to make sure we have the needed hardware support 729 uint32_t i = 0; 730 731 for (i = 0; i < num_hw_watchpoints; ++i) { 732 if ((m_state.dbg.__wcr[i] & WCR_ENABLE) == 0) 733 break; // We found an available hw watchpoint slot (in i) 734 } 735 736 // See if we found an available hw watchpoint slot above 737 if (i < num_hw_watchpoints) { 738 // DumpDBGState(m_state.dbg); 739 740 // Clear any previous LoHi joined-watchpoint that may have been in use 741 LoHi[i] = 0; 742 743 // shift our Byte Address Select bits up to the correct bit range for the 744 // DBGWCRn_EL1 745 byte_address_select = byte_address_select << 5; 746 747 // Make sure bits 1:0 are clear in our address 748 m_state.dbg.__wvr[i] = aligned_wp_address; // DVA (Data Virtual Address) 749 m_state.dbg.__wcr[i] = byte_address_select | // Which bytes that follow 750 // the DVA that we will watch 751 S_USER | // Stop only in user mode 752 (read ? WCR_LOAD : 0) | // Stop on read access? 753 (write ? WCR_STORE : 0) | // Stop on write access? 754 WCR_ENABLE; // Enable this watchpoint; 755 756 DNBLogThreadedIf( 757 LOG_WATCHPOINTS, "DNBArchMachARM64::EnableHardwareWatchpoint() " 758 "adding watchpoint on address 0x%llx with control " 759 "register value 0x%x", 760 (uint64_t)m_state.dbg.__wvr[i], (uint32_t)m_state.dbg.__wcr[i]); 761 762 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 763 // automatically, don't need to do it here. 764 765 kret = SetDBGState(also_set_on_task); 766 // DumpDBGState(m_state.dbg); 767 768 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 769 "EnableHardwareWatchpoint() " 770 "SetDBGState() => 0x%8.8x.", 771 kret); 772 773 if (kret == KERN_SUCCESS) 774 return i; 775 } else { 776 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 777 "EnableHardwareWatchpoint(): All " 778 "hardware resources (%u) are in use.", 779 num_hw_watchpoints); 780 } 781 } 782 return INVALID_NUB_HW_INDEX; 783 } 784 785 bool DNBArchMachARM64::ReenableHardwareWatchpoint(uint32_t hw_index) { 786 // If this logical watchpoint # is actually implemented using 787 // two hardware watchpoint registers, re-enable both of them. 788 789 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 790 return ReenableHardwareWatchpoint_helper(hw_index) && 791 ReenableHardwareWatchpoint_helper(LoHi[hw_index]); 792 } else { 793 return ReenableHardwareWatchpoint_helper(hw_index); 794 } 795 } 796 797 bool DNBArchMachARM64::ReenableHardwareWatchpoint_helper(uint32_t hw_index) { 798 kern_return_t kret = GetDBGState(false); 799 if (kret != KERN_SUCCESS) 800 return false; 801 802 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 803 if (hw_index >= num_hw_points) 804 return false; 805 806 m_state.dbg.__wvr[hw_index] = m_disabled_watchpoints[hw_index].addr; 807 m_state.dbg.__wcr[hw_index] = m_disabled_watchpoints[hw_index].control; 808 809 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 810 "EnableHardwareWatchpoint( %u ) - WVR%u = " 811 "0x%8.8llx WCR%u = 0x%8.8llx", 812 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 813 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 814 815 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 816 // automatically, don't need to do it here. 817 818 kret = SetDBGState(false); 819 820 return (kret == KERN_SUCCESS); 821 } 822 823 bool DNBArchMachARM64::DisableHardwareWatchpoint(uint32_t hw_index, 824 bool also_set_on_task) { 825 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 826 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task) && 827 DisableHardwareWatchpoint_helper(LoHi[hw_index], also_set_on_task); 828 } else { 829 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task); 830 } 831 } 832 833 bool DNBArchMachARM64::DisableHardwareWatchpoint_helper(uint32_t hw_index, 834 bool also_set_on_task) { 835 kern_return_t kret = GetDBGState(false); 836 if (kret != KERN_SUCCESS) 837 return false; 838 839 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 840 if (hw_index >= num_hw_points) 841 return false; 842 843 m_disabled_watchpoints[hw_index].addr = m_state.dbg.__wvr[hw_index]; 844 m_disabled_watchpoints[hw_index].control = m_state.dbg.__wcr[hw_index]; 845 846 m_state.dbg.__wcr[hw_index] &= ~((nub_addr_t)WCR_ENABLE); 847 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 848 "DisableHardwareWatchpoint( %u ) - WVR%u = " 849 "0x%8.8llx WCR%u = 0x%8.8llx", 850 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 851 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 852 853 kret = SetDBGState(also_set_on_task); 854 855 return (kret == KERN_SUCCESS); 856 } 857 858 // This is for checking the Byte Address Select bits in the DBRWCRn_EL1 control 859 // register. 860 // Returns -1 if the trailing bit patterns are not one of: 861 // { 0b???????1, 0b??????10, 0b?????100, 0b????1000, 0b???10000, 0b??100000, 862 // 0b?1000000, 0b10000000 }. 863 static inline int32_t LowestBitSet(uint32_t val) { 864 for (unsigned i = 0; i < 8; ++i) { 865 if (bit(val, i)) 866 return i; 867 } 868 return -1; 869 } 870 871 // Iterate through the debug registers; return the index of the first watchpoint 872 // whose address matches. 873 // As a side effect, the starting address as understood by the debugger is 874 // returned which could be 875 // different from 'addr' passed as an in/out argument. 876 uint32_t DNBArchMachARM64::GetHardwareWatchpointHit(nub_addr_t &addr) { 877 // Read the debug state 878 kern_return_t kret = GetDBGState(true); 879 // DumpDBGState(m_state.dbg); 880 DNBLogThreadedIf( 881 LOG_WATCHPOINTS, 882 "DNBArchMachARM64::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", 883 kret); 884 DNBLogThreadedIf(LOG_WATCHPOINTS, 885 "DNBArchMachARM64::GetHardwareWatchpointHit() addr = 0x%llx", 886 (uint64_t)addr); 887 888 // This is the watchpoint value to match against, i.e., word address. 889 nub_addr_t wp_val = addr & ~((nub_addr_t)3); 890 if (kret == KERN_SUCCESS) { 891 DBG &debug_state = m_state.dbg; 892 uint32_t i, num = NumSupportedHardwareWatchpoints(); 893 for (i = 0; i < num; ++i) { 894 nub_addr_t wp_addr = GetWatchAddress(debug_state, i); 895 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 896 "GetHardwareWatchpointHit() slot: %u " 897 "(addr = 0x%llx).", 898 i, (uint64_t)wp_addr); 899 if (wp_val == wp_addr) { 900 uint32_t byte_mask = bits(debug_state.__wcr[i], 12, 5); 901 902 // Sanity check the byte_mask, first. 903 if (LowestBitSet(byte_mask) < 0) 904 continue; 905 906 // Check that the watchpoint is enabled. 907 if (!IsWatchpointEnabled(debug_state, i)) 908 continue; 909 910 // Compute the starting address (from the point of view of the 911 // debugger). 912 addr = wp_addr + LowestBitSet(byte_mask); 913 return i; 914 } 915 } 916 } 917 return INVALID_NUB_HW_INDEX; 918 } 919 920 nub_addr_t DNBArchMachARM64::GetWatchpointAddressByIndex(uint32_t hw_index) { 921 kern_return_t kret = GetDBGState(true); 922 if (kret != KERN_SUCCESS) 923 return INVALID_NUB_ADDRESS; 924 const uint32_t num = NumSupportedHardwareWatchpoints(); 925 if (hw_index >= num) 926 return INVALID_NUB_ADDRESS; 927 if (IsWatchpointEnabled(m_state.dbg, hw_index)) 928 return GetWatchAddress(m_state.dbg, hw_index); 929 return INVALID_NUB_ADDRESS; 930 } 931 932 bool DNBArchMachARM64::IsWatchpointEnabled(const DBG &debug_state, 933 uint32_t hw_index) { 934 // Watchpoint Control Registers, bitfield definitions 935 // ... 936 // Bits Value Description 937 // [0] 0 Watchpoint disabled 938 // 1 Watchpoint enabled. 939 return (debug_state.__wcr[hw_index] & 1u); 940 } 941 942 nub_addr_t DNBArchMachARM64::GetWatchAddress(const DBG &debug_state, 943 uint32_t hw_index) { 944 // Watchpoint Value Registers, bitfield definitions 945 // Bits Description 946 // [31:2] Watchpoint value (word address, i.e., 4-byte aligned) 947 // [1:0] RAZ/SBZP 948 return bits(debug_state.__wvr[hw_index], 63, 0); 949 } 950 951 //---------------------------------------------------------------------- 952 // Register information definitions for 64 bit ARMv8. 953 //---------------------------------------------------------------------- 954 enum gpr_regnums { 955 gpr_x0 = 0, 956 gpr_x1, 957 gpr_x2, 958 gpr_x3, 959 gpr_x4, 960 gpr_x5, 961 gpr_x6, 962 gpr_x7, 963 gpr_x8, 964 gpr_x9, 965 gpr_x10, 966 gpr_x11, 967 gpr_x12, 968 gpr_x13, 969 gpr_x14, 970 gpr_x15, 971 gpr_x16, 972 gpr_x17, 973 gpr_x18, 974 gpr_x19, 975 gpr_x20, 976 gpr_x21, 977 gpr_x22, 978 gpr_x23, 979 gpr_x24, 980 gpr_x25, 981 gpr_x26, 982 gpr_x27, 983 gpr_x28, 984 gpr_fp, 985 gpr_x29 = gpr_fp, 986 gpr_lr, 987 gpr_x30 = gpr_lr, 988 gpr_sp, 989 gpr_x31 = gpr_sp, 990 gpr_pc, 991 gpr_cpsr, 992 gpr_w0, 993 gpr_w1, 994 gpr_w2, 995 gpr_w3, 996 gpr_w4, 997 gpr_w5, 998 gpr_w6, 999 gpr_w7, 1000 gpr_w8, 1001 gpr_w9, 1002 gpr_w10, 1003 gpr_w11, 1004 gpr_w12, 1005 gpr_w13, 1006 gpr_w14, 1007 gpr_w15, 1008 gpr_w16, 1009 gpr_w17, 1010 gpr_w18, 1011 gpr_w19, 1012 gpr_w20, 1013 gpr_w21, 1014 gpr_w22, 1015 gpr_w23, 1016 gpr_w24, 1017 gpr_w25, 1018 gpr_w26, 1019 gpr_w27, 1020 gpr_w28 1021 1022 }; 1023 1024 enum { 1025 vfp_v0 = 0, 1026 vfp_v1, 1027 vfp_v2, 1028 vfp_v3, 1029 vfp_v4, 1030 vfp_v5, 1031 vfp_v6, 1032 vfp_v7, 1033 vfp_v8, 1034 vfp_v9, 1035 vfp_v10, 1036 vfp_v11, 1037 vfp_v12, 1038 vfp_v13, 1039 vfp_v14, 1040 vfp_v15, 1041 vfp_v16, 1042 vfp_v17, 1043 vfp_v18, 1044 vfp_v19, 1045 vfp_v20, 1046 vfp_v21, 1047 vfp_v22, 1048 vfp_v23, 1049 vfp_v24, 1050 vfp_v25, 1051 vfp_v26, 1052 vfp_v27, 1053 vfp_v28, 1054 vfp_v29, 1055 vfp_v30, 1056 vfp_v31, 1057 vfp_fpsr, 1058 vfp_fpcr, 1059 1060 // lower 32 bits of the corresponding vfp_v<n> reg. 1061 vfp_s0, 1062 vfp_s1, 1063 vfp_s2, 1064 vfp_s3, 1065 vfp_s4, 1066 vfp_s5, 1067 vfp_s6, 1068 vfp_s7, 1069 vfp_s8, 1070 vfp_s9, 1071 vfp_s10, 1072 vfp_s11, 1073 vfp_s12, 1074 vfp_s13, 1075 vfp_s14, 1076 vfp_s15, 1077 vfp_s16, 1078 vfp_s17, 1079 vfp_s18, 1080 vfp_s19, 1081 vfp_s20, 1082 vfp_s21, 1083 vfp_s22, 1084 vfp_s23, 1085 vfp_s24, 1086 vfp_s25, 1087 vfp_s26, 1088 vfp_s27, 1089 vfp_s28, 1090 vfp_s29, 1091 vfp_s30, 1092 vfp_s31, 1093 1094 // lower 64 bits of the corresponding vfp_v<n> reg. 1095 vfp_d0, 1096 vfp_d1, 1097 vfp_d2, 1098 vfp_d3, 1099 vfp_d4, 1100 vfp_d5, 1101 vfp_d6, 1102 vfp_d7, 1103 vfp_d8, 1104 vfp_d9, 1105 vfp_d10, 1106 vfp_d11, 1107 vfp_d12, 1108 vfp_d13, 1109 vfp_d14, 1110 vfp_d15, 1111 vfp_d16, 1112 vfp_d17, 1113 vfp_d18, 1114 vfp_d19, 1115 vfp_d20, 1116 vfp_d21, 1117 vfp_d22, 1118 vfp_d23, 1119 vfp_d24, 1120 vfp_d25, 1121 vfp_d26, 1122 vfp_d27, 1123 vfp_d28, 1124 vfp_d29, 1125 vfp_d30, 1126 vfp_d31 1127 }; 1128 1129 enum { exc_far = 0, exc_esr, exc_exception }; 1130 1131 // These numbers from the "DWARF for the ARM 64-bit Architecture (AArch64)" 1132 // document. 1133 1134 enum { 1135 dwarf_x0 = 0, 1136 dwarf_x1, 1137 dwarf_x2, 1138 dwarf_x3, 1139 dwarf_x4, 1140 dwarf_x5, 1141 dwarf_x6, 1142 dwarf_x7, 1143 dwarf_x8, 1144 dwarf_x9, 1145 dwarf_x10, 1146 dwarf_x11, 1147 dwarf_x12, 1148 dwarf_x13, 1149 dwarf_x14, 1150 dwarf_x15, 1151 dwarf_x16, 1152 dwarf_x17, 1153 dwarf_x18, 1154 dwarf_x19, 1155 dwarf_x20, 1156 dwarf_x21, 1157 dwarf_x22, 1158 dwarf_x23, 1159 dwarf_x24, 1160 dwarf_x25, 1161 dwarf_x26, 1162 dwarf_x27, 1163 dwarf_x28, 1164 dwarf_x29, 1165 dwarf_x30, 1166 dwarf_x31, 1167 dwarf_pc = 32, 1168 dwarf_elr_mode = 33, 1169 dwarf_fp = dwarf_x29, 1170 dwarf_lr = dwarf_x30, 1171 dwarf_sp = dwarf_x31, 1172 // 34-63 reserved 1173 1174 // V0-V31 (128 bit vector registers) 1175 dwarf_v0 = 64, 1176 dwarf_v1, 1177 dwarf_v2, 1178 dwarf_v3, 1179 dwarf_v4, 1180 dwarf_v5, 1181 dwarf_v6, 1182 dwarf_v7, 1183 dwarf_v8, 1184 dwarf_v9, 1185 dwarf_v10, 1186 dwarf_v11, 1187 dwarf_v12, 1188 dwarf_v13, 1189 dwarf_v14, 1190 dwarf_v15, 1191 dwarf_v16, 1192 dwarf_v17, 1193 dwarf_v18, 1194 dwarf_v19, 1195 dwarf_v20, 1196 dwarf_v21, 1197 dwarf_v22, 1198 dwarf_v23, 1199 dwarf_v24, 1200 dwarf_v25, 1201 dwarf_v26, 1202 dwarf_v27, 1203 dwarf_v28, 1204 dwarf_v29, 1205 dwarf_v30, 1206 dwarf_v31 1207 1208 // 96-127 reserved 1209 }; 1210 1211 enum { 1212 debugserver_gpr_x0 = 0, 1213 debugserver_gpr_x1, 1214 debugserver_gpr_x2, 1215 debugserver_gpr_x3, 1216 debugserver_gpr_x4, 1217 debugserver_gpr_x5, 1218 debugserver_gpr_x6, 1219 debugserver_gpr_x7, 1220 debugserver_gpr_x8, 1221 debugserver_gpr_x9, 1222 debugserver_gpr_x10, 1223 debugserver_gpr_x11, 1224 debugserver_gpr_x12, 1225 debugserver_gpr_x13, 1226 debugserver_gpr_x14, 1227 debugserver_gpr_x15, 1228 debugserver_gpr_x16, 1229 debugserver_gpr_x17, 1230 debugserver_gpr_x18, 1231 debugserver_gpr_x19, 1232 debugserver_gpr_x20, 1233 debugserver_gpr_x21, 1234 debugserver_gpr_x22, 1235 debugserver_gpr_x23, 1236 debugserver_gpr_x24, 1237 debugserver_gpr_x25, 1238 debugserver_gpr_x26, 1239 debugserver_gpr_x27, 1240 debugserver_gpr_x28, 1241 debugserver_gpr_fp, // x29 1242 debugserver_gpr_lr, // x30 1243 debugserver_gpr_sp, // sp aka xsp 1244 debugserver_gpr_pc, 1245 debugserver_gpr_cpsr, 1246 debugserver_vfp_v0, 1247 debugserver_vfp_v1, 1248 debugserver_vfp_v2, 1249 debugserver_vfp_v3, 1250 debugserver_vfp_v4, 1251 debugserver_vfp_v5, 1252 debugserver_vfp_v6, 1253 debugserver_vfp_v7, 1254 debugserver_vfp_v8, 1255 debugserver_vfp_v9, 1256 debugserver_vfp_v10, 1257 debugserver_vfp_v11, 1258 debugserver_vfp_v12, 1259 debugserver_vfp_v13, 1260 debugserver_vfp_v14, 1261 debugserver_vfp_v15, 1262 debugserver_vfp_v16, 1263 debugserver_vfp_v17, 1264 debugserver_vfp_v18, 1265 debugserver_vfp_v19, 1266 debugserver_vfp_v20, 1267 debugserver_vfp_v21, 1268 debugserver_vfp_v22, 1269 debugserver_vfp_v23, 1270 debugserver_vfp_v24, 1271 debugserver_vfp_v25, 1272 debugserver_vfp_v26, 1273 debugserver_vfp_v27, 1274 debugserver_vfp_v28, 1275 debugserver_vfp_v29, 1276 debugserver_vfp_v30, 1277 debugserver_vfp_v31, 1278 debugserver_vfp_fpsr, 1279 debugserver_vfp_fpcr 1280 }; 1281 1282 const char *g_contained_x0[]{"x0", NULL}; 1283 const char *g_contained_x1[]{"x1", NULL}; 1284 const char *g_contained_x2[]{"x2", NULL}; 1285 const char *g_contained_x3[]{"x3", NULL}; 1286 const char *g_contained_x4[]{"x4", NULL}; 1287 const char *g_contained_x5[]{"x5", NULL}; 1288 const char *g_contained_x6[]{"x6", NULL}; 1289 const char *g_contained_x7[]{"x7", NULL}; 1290 const char *g_contained_x8[]{"x8", NULL}; 1291 const char *g_contained_x9[]{"x9", NULL}; 1292 const char *g_contained_x10[]{"x10", NULL}; 1293 const char *g_contained_x11[]{"x11", NULL}; 1294 const char *g_contained_x12[]{"x12", NULL}; 1295 const char *g_contained_x13[]{"x13", NULL}; 1296 const char *g_contained_x14[]{"x14", NULL}; 1297 const char *g_contained_x15[]{"x15", NULL}; 1298 const char *g_contained_x16[]{"x16", NULL}; 1299 const char *g_contained_x17[]{"x17", NULL}; 1300 const char *g_contained_x18[]{"x18", NULL}; 1301 const char *g_contained_x19[]{"x19", NULL}; 1302 const char *g_contained_x20[]{"x20", NULL}; 1303 const char *g_contained_x21[]{"x21", NULL}; 1304 const char *g_contained_x22[]{"x22", NULL}; 1305 const char *g_contained_x23[]{"x23", NULL}; 1306 const char *g_contained_x24[]{"x24", NULL}; 1307 const char *g_contained_x25[]{"x25", NULL}; 1308 const char *g_contained_x26[]{"x26", NULL}; 1309 const char *g_contained_x27[]{"x27", NULL}; 1310 const char *g_contained_x28[]{"x28", NULL}; 1311 1312 const char *g_invalidate_x0[]{"x0", "w0", NULL}; 1313 const char *g_invalidate_x1[]{"x1", "w1", NULL}; 1314 const char *g_invalidate_x2[]{"x2", "w2", NULL}; 1315 const char *g_invalidate_x3[]{"x3", "w3", NULL}; 1316 const char *g_invalidate_x4[]{"x4", "w4", NULL}; 1317 const char *g_invalidate_x5[]{"x5", "w5", NULL}; 1318 const char *g_invalidate_x6[]{"x6", "w6", NULL}; 1319 const char *g_invalidate_x7[]{"x7", "w7", NULL}; 1320 const char *g_invalidate_x8[]{"x8", "w8", NULL}; 1321 const char *g_invalidate_x9[]{"x9", "w9", NULL}; 1322 const char *g_invalidate_x10[]{"x10", "w10", NULL}; 1323 const char *g_invalidate_x11[]{"x11", "w11", NULL}; 1324 const char *g_invalidate_x12[]{"x12", "w12", NULL}; 1325 const char *g_invalidate_x13[]{"x13", "w13", NULL}; 1326 const char *g_invalidate_x14[]{"x14", "w14", NULL}; 1327 const char *g_invalidate_x15[]{"x15", "w15", NULL}; 1328 const char *g_invalidate_x16[]{"x16", "w16", NULL}; 1329 const char *g_invalidate_x17[]{"x17", "w17", NULL}; 1330 const char *g_invalidate_x18[]{"x18", "w18", NULL}; 1331 const char *g_invalidate_x19[]{"x19", "w19", NULL}; 1332 const char *g_invalidate_x20[]{"x20", "w20", NULL}; 1333 const char *g_invalidate_x21[]{"x21", "w21", NULL}; 1334 const char *g_invalidate_x22[]{"x22", "w22", NULL}; 1335 const char *g_invalidate_x23[]{"x23", "w23", NULL}; 1336 const char *g_invalidate_x24[]{"x24", "w24", NULL}; 1337 const char *g_invalidate_x25[]{"x25", "w25", NULL}; 1338 const char *g_invalidate_x26[]{"x26", "w26", NULL}; 1339 const char *g_invalidate_x27[]{"x27", "w27", NULL}; 1340 const char *g_invalidate_x28[]{"x28", "w28", NULL}; 1341 1342 #define GPR_OFFSET_IDX(idx) (offsetof(DNBArchMachARM64::GPR, __x[idx])) 1343 1344 #define GPR_OFFSET_NAME(reg) (offsetof(DNBArchMachARM64::GPR, __##reg)) 1345 1346 // These macros will auto define the register name, alt name, register size, 1347 // register offset, encoding, format and native register. This ensures that 1348 // the register state structures are defined correctly and have the correct 1349 // sizes and offsets. 1350 #define DEFINE_GPR_IDX(idx, reg, alt, gen) \ 1351 { \ 1352 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_IDX(idx), \ 1353 dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, \ 1354 g_invalidate_x##idx \ 1355 } 1356 #define DEFINE_GPR_NAME(reg, alt, gen) \ 1357 { \ 1358 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_NAME(reg), \ 1359 dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, NULL \ 1360 } 1361 #define DEFINE_PSEUDO_GPR_IDX(idx, reg) \ 1362 { \ 1363 e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, 4, 0, INVALID_NUB_REGNUM, \ 1364 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1365 g_contained_x##idx, g_invalidate_x##idx \ 1366 } 1367 1368 //_STRUCT_ARM_THREAD_STATE64 1369 //{ 1370 // uint64_t x[29]; /* General purpose registers x0-x28 */ 1371 // uint64_t fp; /* Frame pointer x29 */ 1372 // uint64_t lr; /* Link register x30 */ 1373 // uint64_t sp; /* Stack pointer x31 */ 1374 // uint64_t pc; /* Program counter */ 1375 // uint32_t cpsr; /* Current program status register */ 1376 //}; 1377 1378 // General purpose registers 1379 const DNBRegisterInfo DNBArchMachARM64::g_gpr_registers[] = { 1380 DEFINE_GPR_IDX(0, x0, "arg1", GENERIC_REGNUM_ARG1), 1381 DEFINE_GPR_IDX(1, x1, "arg2", GENERIC_REGNUM_ARG2), 1382 DEFINE_GPR_IDX(2, x2, "arg3", GENERIC_REGNUM_ARG3), 1383 DEFINE_GPR_IDX(3, x3, "arg4", GENERIC_REGNUM_ARG4), 1384 DEFINE_GPR_IDX(4, x4, "arg5", GENERIC_REGNUM_ARG5), 1385 DEFINE_GPR_IDX(5, x5, "arg6", GENERIC_REGNUM_ARG6), 1386 DEFINE_GPR_IDX(6, x6, "arg7", GENERIC_REGNUM_ARG7), 1387 DEFINE_GPR_IDX(7, x7, "arg8", GENERIC_REGNUM_ARG8), 1388 DEFINE_GPR_IDX(8, x8, NULL, INVALID_NUB_REGNUM), 1389 DEFINE_GPR_IDX(9, x9, NULL, INVALID_NUB_REGNUM), 1390 DEFINE_GPR_IDX(10, x10, NULL, INVALID_NUB_REGNUM), 1391 DEFINE_GPR_IDX(11, x11, NULL, INVALID_NUB_REGNUM), 1392 DEFINE_GPR_IDX(12, x12, NULL, INVALID_NUB_REGNUM), 1393 DEFINE_GPR_IDX(13, x13, NULL, INVALID_NUB_REGNUM), 1394 DEFINE_GPR_IDX(14, x14, NULL, INVALID_NUB_REGNUM), 1395 DEFINE_GPR_IDX(15, x15, NULL, INVALID_NUB_REGNUM), 1396 DEFINE_GPR_IDX(16, x16, NULL, INVALID_NUB_REGNUM), 1397 DEFINE_GPR_IDX(17, x17, NULL, INVALID_NUB_REGNUM), 1398 DEFINE_GPR_IDX(18, x18, NULL, INVALID_NUB_REGNUM), 1399 DEFINE_GPR_IDX(19, x19, NULL, INVALID_NUB_REGNUM), 1400 DEFINE_GPR_IDX(20, x20, NULL, INVALID_NUB_REGNUM), 1401 DEFINE_GPR_IDX(21, x21, NULL, INVALID_NUB_REGNUM), 1402 DEFINE_GPR_IDX(22, x22, NULL, INVALID_NUB_REGNUM), 1403 DEFINE_GPR_IDX(23, x23, NULL, INVALID_NUB_REGNUM), 1404 DEFINE_GPR_IDX(24, x24, NULL, INVALID_NUB_REGNUM), 1405 DEFINE_GPR_IDX(25, x25, NULL, INVALID_NUB_REGNUM), 1406 DEFINE_GPR_IDX(26, x26, NULL, INVALID_NUB_REGNUM), 1407 DEFINE_GPR_IDX(27, x27, NULL, INVALID_NUB_REGNUM), 1408 DEFINE_GPR_IDX(28, x28, NULL, INVALID_NUB_REGNUM), 1409 DEFINE_GPR_NAME(fp, "x29", GENERIC_REGNUM_FP), 1410 DEFINE_GPR_NAME(lr, "x30", GENERIC_REGNUM_RA), 1411 DEFINE_GPR_NAME(sp, "xsp", GENERIC_REGNUM_SP), 1412 DEFINE_GPR_NAME(pc, NULL, GENERIC_REGNUM_PC), 1413 1414 // in armv7 we specify that writing to the CPSR should invalidate r8-12, sp, 1415 // lr. 1416 // this should be specified for arm64 too even though debugserver is only 1417 // used for 1418 // userland debugging. 1419 {e_regSetGPR, gpr_cpsr, "cpsr", "flags", Uint, Hex, 4, 1420 GPR_OFFSET_NAME(cpsr), dwarf_elr_mode, dwarf_elr_mode, INVALID_NUB_REGNUM, 1421 debugserver_gpr_cpsr, NULL, NULL}, 1422 1423 DEFINE_PSEUDO_GPR_IDX(0, w0), 1424 DEFINE_PSEUDO_GPR_IDX(1, w1), 1425 DEFINE_PSEUDO_GPR_IDX(2, w2), 1426 DEFINE_PSEUDO_GPR_IDX(3, w3), 1427 DEFINE_PSEUDO_GPR_IDX(4, w4), 1428 DEFINE_PSEUDO_GPR_IDX(5, w5), 1429 DEFINE_PSEUDO_GPR_IDX(6, w6), 1430 DEFINE_PSEUDO_GPR_IDX(7, w7), 1431 DEFINE_PSEUDO_GPR_IDX(8, w8), 1432 DEFINE_PSEUDO_GPR_IDX(9, w9), 1433 DEFINE_PSEUDO_GPR_IDX(10, w10), 1434 DEFINE_PSEUDO_GPR_IDX(11, w11), 1435 DEFINE_PSEUDO_GPR_IDX(12, w12), 1436 DEFINE_PSEUDO_GPR_IDX(13, w13), 1437 DEFINE_PSEUDO_GPR_IDX(14, w14), 1438 DEFINE_PSEUDO_GPR_IDX(15, w15), 1439 DEFINE_PSEUDO_GPR_IDX(16, w16), 1440 DEFINE_PSEUDO_GPR_IDX(17, w17), 1441 DEFINE_PSEUDO_GPR_IDX(18, w18), 1442 DEFINE_PSEUDO_GPR_IDX(19, w19), 1443 DEFINE_PSEUDO_GPR_IDX(20, w20), 1444 DEFINE_PSEUDO_GPR_IDX(21, w21), 1445 DEFINE_PSEUDO_GPR_IDX(22, w22), 1446 DEFINE_PSEUDO_GPR_IDX(23, w23), 1447 DEFINE_PSEUDO_GPR_IDX(24, w24), 1448 DEFINE_PSEUDO_GPR_IDX(25, w25), 1449 DEFINE_PSEUDO_GPR_IDX(26, w26), 1450 DEFINE_PSEUDO_GPR_IDX(27, w27), 1451 DEFINE_PSEUDO_GPR_IDX(28, w28)}; 1452 1453 const char *g_contained_v0[]{"v0", NULL}; 1454 const char *g_contained_v1[]{"v1", NULL}; 1455 const char *g_contained_v2[]{"v2", NULL}; 1456 const char *g_contained_v3[]{"v3", NULL}; 1457 const char *g_contained_v4[]{"v4", NULL}; 1458 const char *g_contained_v5[]{"v5", NULL}; 1459 const char *g_contained_v6[]{"v6", NULL}; 1460 const char *g_contained_v7[]{"v7", NULL}; 1461 const char *g_contained_v8[]{"v8", NULL}; 1462 const char *g_contained_v9[]{"v9", NULL}; 1463 const char *g_contained_v10[]{"v10", NULL}; 1464 const char *g_contained_v11[]{"v11", NULL}; 1465 const char *g_contained_v12[]{"v12", NULL}; 1466 const char *g_contained_v13[]{"v13", NULL}; 1467 const char *g_contained_v14[]{"v14", NULL}; 1468 const char *g_contained_v15[]{"v15", NULL}; 1469 const char *g_contained_v16[]{"v16", NULL}; 1470 const char *g_contained_v17[]{"v17", NULL}; 1471 const char *g_contained_v18[]{"v18", NULL}; 1472 const char *g_contained_v19[]{"v19", NULL}; 1473 const char *g_contained_v20[]{"v20", NULL}; 1474 const char *g_contained_v21[]{"v21", NULL}; 1475 const char *g_contained_v22[]{"v22", NULL}; 1476 const char *g_contained_v23[]{"v23", NULL}; 1477 const char *g_contained_v24[]{"v24", NULL}; 1478 const char *g_contained_v25[]{"v25", NULL}; 1479 const char *g_contained_v26[]{"v26", NULL}; 1480 const char *g_contained_v27[]{"v27", NULL}; 1481 const char *g_contained_v28[]{"v28", NULL}; 1482 const char *g_contained_v29[]{"v29", NULL}; 1483 const char *g_contained_v30[]{"v30", NULL}; 1484 const char *g_contained_v31[]{"v31", NULL}; 1485 1486 const char *g_invalidate_v0[]{"v0", "d0", "s0", NULL}; 1487 const char *g_invalidate_v1[]{"v1", "d1", "s1", NULL}; 1488 const char *g_invalidate_v2[]{"v2", "d2", "s2", NULL}; 1489 const char *g_invalidate_v3[]{"v3", "d3", "s3", NULL}; 1490 const char *g_invalidate_v4[]{"v4", "d4", "s4", NULL}; 1491 const char *g_invalidate_v5[]{"v5", "d5", "s5", NULL}; 1492 const char *g_invalidate_v6[]{"v6", "d6", "s6", NULL}; 1493 const char *g_invalidate_v7[]{"v7", "d7", "s7", NULL}; 1494 const char *g_invalidate_v8[]{"v8", "d8", "s8", NULL}; 1495 const char *g_invalidate_v9[]{"v9", "d9", "s9", NULL}; 1496 const char *g_invalidate_v10[]{"v10", "d10", "s10", NULL}; 1497 const char *g_invalidate_v11[]{"v11", "d11", "s11", NULL}; 1498 const char *g_invalidate_v12[]{"v12", "d12", "s12", NULL}; 1499 const char *g_invalidate_v13[]{"v13", "d13", "s13", NULL}; 1500 const char *g_invalidate_v14[]{"v14", "d14", "s14", NULL}; 1501 const char *g_invalidate_v15[]{"v15", "d15", "s15", NULL}; 1502 const char *g_invalidate_v16[]{"v16", "d16", "s16", NULL}; 1503 const char *g_invalidate_v17[]{"v17", "d17", "s17", NULL}; 1504 const char *g_invalidate_v18[]{"v18", "d18", "s18", NULL}; 1505 const char *g_invalidate_v19[]{"v19", "d19", "s19", NULL}; 1506 const char *g_invalidate_v20[]{"v20", "d20", "s20", NULL}; 1507 const char *g_invalidate_v21[]{"v21", "d21", "s21", NULL}; 1508 const char *g_invalidate_v22[]{"v22", "d22", "s22", NULL}; 1509 const char *g_invalidate_v23[]{"v23", "d23", "s23", NULL}; 1510 const char *g_invalidate_v24[]{"v24", "d24", "s24", NULL}; 1511 const char *g_invalidate_v25[]{"v25", "d25", "s25", NULL}; 1512 const char *g_invalidate_v26[]{"v26", "d26", "s26", NULL}; 1513 const char *g_invalidate_v27[]{"v27", "d27", "s27", NULL}; 1514 const char *g_invalidate_v28[]{"v28", "d28", "s28", NULL}; 1515 const char *g_invalidate_v29[]{"v29", "d29", "s29", NULL}; 1516 const char *g_invalidate_v30[]{"v30", "d30", "s30", NULL}; 1517 const char *g_invalidate_v31[]{"v31", "d31", "s31", NULL}; 1518 1519 #if defined(__arm64__) || defined(__aarch64__) 1520 #define VFP_V_OFFSET_IDX(idx) \ 1521 (offsetof(DNBArchMachARM64::FPU, __v) + (idx * 16) + \ 1522 offsetof(DNBArchMachARM64::Context, vfp)) 1523 #else 1524 #define VFP_V_OFFSET_IDX(idx) \ 1525 (offsetof(DNBArchMachARM64::FPU, opaque) + (idx * 16) + \ 1526 offsetof(DNBArchMachARM64::Context, vfp)) 1527 #endif 1528 #define VFP_OFFSET_NAME(reg) \ 1529 (offsetof(DNBArchMachARM64::FPU, reg) + \ 1530 offsetof(DNBArchMachARM64::Context, vfp)) 1531 #define EXC_OFFSET(reg) \ 1532 (offsetof(DNBArchMachARM64::EXC, reg) + \ 1533 offsetof(DNBArchMachARM64::Context, exc)) 1534 1535 //#define FLOAT_FORMAT Float 1536 #define DEFINE_VFP_V_IDX(idx) \ 1537 { \ 1538 e_regSetVFP, vfp_v##idx, "v" #idx, "q" #idx, Vector, VectorOfUInt8, 16, \ 1539 VFP_V_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_v##idx, \ 1540 INVALID_NUB_REGNUM, debugserver_vfp_v##idx, NULL, g_invalidate_v##idx \ 1541 } 1542 #define DEFINE_PSEUDO_VFP_S_IDX(idx) \ 1543 { \ 1544 e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, Float, 4, 0, \ 1545 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1546 INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \ 1547 } 1548 #define DEFINE_PSEUDO_VFP_D_IDX(idx) \ 1549 { \ 1550 e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, Float, 8, 0, \ 1551 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1552 INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \ 1553 } 1554 1555 // Floating point registers 1556 const DNBRegisterInfo DNBArchMachARM64::g_vfp_registers[] = { 1557 DEFINE_VFP_V_IDX(0), 1558 DEFINE_VFP_V_IDX(1), 1559 DEFINE_VFP_V_IDX(2), 1560 DEFINE_VFP_V_IDX(3), 1561 DEFINE_VFP_V_IDX(4), 1562 DEFINE_VFP_V_IDX(5), 1563 DEFINE_VFP_V_IDX(6), 1564 DEFINE_VFP_V_IDX(7), 1565 DEFINE_VFP_V_IDX(8), 1566 DEFINE_VFP_V_IDX(9), 1567 DEFINE_VFP_V_IDX(10), 1568 DEFINE_VFP_V_IDX(11), 1569 DEFINE_VFP_V_IDX(12), 1570 DEFINE_VFP_V_IDX(13), 1571 DEFINE_VFP_V_IDX(14), 1572 DEFINE_VFP_V_IDX(15), 1573 DEFINE_VFP_V_IDX(16), 1574 DEFINE_VFP_V_IDX(17), 1575 DEFINE_VFP_V_IDX(18), 1576 DEFINE_VFP_V_IDX(19), 1577 DEFINE_VFP_V_IDX(20), 1578 DEFINE_VFP_V_IDX(21), 1579 DEFINE_VFP_V_IDX(22), 1580 DEFINE_VFP_V_IDX(23), 1581 DEFINE_VFP_V_IDX(24), 1582 DEFINE_VFP_V_IDX(25), 1583 DEFINE_VFP_V_IDX(26), 1584 DEFINE_VFP_V_IDX(27), 1585 DEFINE_VFP_V_IDX(28), 1586 DEFINE_VFP_V_IDX(29), 1587 DEFINE_VFP_V_IDX(30), 1588 DEFINE_VFP_V_IDX(31), 1589 {e_regSetVFP, vfp_fpsr, "fpsr", NULL, Uint, Hex, 4, 1590 VFP_V_OFFSET_IDX(32) + 0, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1591 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}, 1592 {e_regSetVFP, vfp_fpcr, "fpcr", NULL, Uint, Hex, 4, 1593 VFP_V_OFFSET_IDX(32) + 4, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1594 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}, 1595 1596 DEFINE_PSEUDO_VFP_S_IDX(0), 1597 DEFINE_PSEUDO_VFP_S_IDX(1), 1598 DEFINE_PSEUDO_VFP_S_IDX(2), 1599 DEFINE_PSEUDO_VFP_S_IDX(3), 1600 DEFINE_PSEUDO_VFP_S_IDX(4), 1601 DEFINE_PSEUDO_VFP_S_IDX(5), 1602 DEFINE_PSEUDO_VFP_S_IDX(6), 1603 DEFINE_PSEUDO_VFP_S_IDX(7), 1604 DEFINE_PSEUDO_VFP_S_IDX(8), 1605 DEFINE_PSEUDO_VFP_S_IDX(9), 1606 DEFINE_PSEUDO_VFP_S_IDX(10), 1607 DEFINE_PSEUDO_VFP_S_IDX(11), 1608 DEFINE_PSEUDO_VFP_S_IDX(12), 1609 DEFINE_PSEUDO_VFP_S_IDX(13), 1610 DEFINE_PSEUDO_VFP_S_IDX(14), 1611 DEFINE_PSEUDO_VFP_S_IDX(15), 1612 DEFINE_PSEUDO_VFP_S_IDX(16), 1613 DEFINE_PSEUDO_VFP_S_IDX(17), 1614 DEFINE_PSEUDO_VFP_S_IDX(18), 1615 DEFINE_PSEUDO_VFP_S_IDX(19), 1616 DEFINE_PSEUDO_VFP_S_IDX(20), 1617 DEFINE_PSEUDO_VFP_S_IDX(21), 1618 DEFINE_PSEUDO_VFP_S_IDX(22), 1619 DEFINE_PSEUDO_VFP_S_IDX(23), 1620 DEFINE_PSEUDO_VFP_S_IDX(24), 1621 DEFINE_PSEUDO_VFP_S_IDX(25), 1622 DEFINE_PSEUDO_VFP_S_IDX(26), 1623 DEFINE_PSEUDO_VFP_S_IDX(27), 1624 DEFINE_PSEUDO_VFP_S_IDX(28), 1625 DEFINE_PSEUDO_VFP_S_IDX(29), 1626 DEFINE_PSEUDO_VFP_S_IDX(30), 1627 DEFINE_PSEUDO_VFP_S_IDX(31), 1628 1629 DEFINE_PSEUDO_VFP_D_IDX(0), 1630 DEFINE_PSEUDO_VFP_D_IDX(1), 1631 DEFINE_PSEUDO_VFP_D_IDX(2), 1632 DEFINE_PSEUDO_VFP_D_IDX(3), 1633 DEFINE_PSEUDO_VFP_D_IDX(4), 1634 DEFINE_PSEUDO_VFP_D_IDX(5), 1635 DEFINE_PSEUDO_VFP_D_IDX(6), 1636 DEFINE_PSEUDO_VFP_D_IDX(7), 1637 DEFINE_PSEUDO_VFP_D_IDX(8), 1638 DEFINE_PSEUDO_VFP_D_IDX(9), 1639 DEFINE_PSEUDO_VFP_D_IDX(10), 1640 DEFINE_PSEUDO_VFP_D_IDX(11), 1641 DEFINE_PSEUDO_VFP_D_IDX(12), 1642 DEFINE_PSEUDO_VFP_D_IDX(13), 1643 DEFINE_PSEUDO_VFP_D_IDX(14), 1644 DEFINE_PSEUDO_VFP_D_IDX(15), 1645 DEFINE_PSEUDO_VFP_D_IDX(16), 1646 DEFINE_PSEUDO_VFP_D_IDX(17), 1647 DEFINE_PSEUDO_VFP_D_IDX(18), 1648 DEFINE_PSEUDO_VFP_D_IDX(19), 1649 DEFINE_PSEUDO_VFP_D_IDX(20), 1650 DEFINE_PSEUDO_VFP_D_IDX(21), 1651 DEFINE_PSEUDO_VFP_D_IDX(22), 1652 DEFINE_PSEUDO_VFP_D_IDX(23), 1653 DEFINE_PSEUDO_VFP_D_IDX(24), 1654 DEFINE_PSEUDO_VFP_D_IDX(25), 1655 DEFINE_PSEUDO_VFP_D_IDX(26), 1656 DEFINE_PSEUDO_VFP_D_IDX(27), 1657 DEFINE_PSEUDO_VFP_D_IDX(28), 1658 DEFINE_PSEUDO_VFP_D_IDX(29), 1659 DEFINE_PSEUDO_VFP_D_IDX(30), 1660 DEFINE_PSEUDO_VFP_D_IDX(31) 1661 1662 }; 1663 1664 //_STRUCT_ARM_EXCEPTION_STATE64 1665 //{ 1666 // uint64_t far; /* Virtual Fault Address */ 1667 // uint32_t esr; /* Exception syndrome */ 1668 // uint32_t exception; /* number of arm exception taken */ 1669 //}; 1670 1671 // Exception registers 1672 const DNBRegisterInfo DNBArchMachARM64::g_exc_registers[] = { 1673 {e_regSetEXC, exc_far, "far", NULL, Uint, Hex, 8, EXC_OFFSET(__far), 1674 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1675 INVALID_NUB_REGNUM, NULL, NULL}, 1676 {e_regSetEXC, exc_esr, "esr", NULL, Uint, Hex, 4, EXC_OFFSET(__esr), 1677 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1678 INVALID_NUB_REGNUM, NULL, NULL}, 1679 {e_regSetEXC, exc_exception, "exception", NULL, Uint, Hex, 4, 1680 EXC_OFFSET(__exception), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1681 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}}; 1682 1683 // Number of registers in each register set 1684 const size_t DNBArchMachARM64::k_num_gpr_registers = 1685 sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo); 1686 const size_t DNBArchMachARM64::k_num_vfp_registers = 1687 sizeof(g_vfp_registers) / sizeof(DNBRegisterInfo); 1688 const size_t DNBArchMachARM64::k_num_exc_registers = 1689 sizeof(g_exc_registers) / sizeof(DNBRegisterInfo); 1690 const size_t DNBArchMachARM64::k_num_all_registers = 1691 k_num_gpr_registers + k_num_vfp_registers + k_num_exc_registers; 1692 1693 //---------------------------------------------------------------------- 1694 // Register set definitions. The first definitions at register set index 1695 // of zero is for all registers, followed by other registers sets. The 1696 // register information for the all register set need not be filled in. 1697 //---------------------------------------------------------------------- 1698 const DNBRegisterSetInfo DNBArchMachARM64::g_reg_sets[] = { 1699 {"ARM64 Registers", NULL, k_num_all_registers}, 1700 {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers}, 1701 {"Floating Point Registers", g_vfp_registers, k_num_vfp_registers}, 1702 {"Exception State Registers", g_exc_registers, k_num_exc_registers}}; 1703 // Total number of register sets for this architecture 1704 const size_t DNBArchMachARM64::k_num_register_sets = 1705 sizeof(g_reg_sets) / sizeof(DNBRegisterSetInfo); 1706 1707 const DNBRegisterSetInfo * 1708 DNBArchMachARM64::GetRegisterSetInfo(nub_size_t *num_reg_sets) { 1709 *num_reg_sets = k_num_register_sets; 1710 return g_reg_sets; 1711 } 1712 1713 bool DNBArchMachARM64::FixGenericRegisterNumber(uint32_t &set, uint32_t ®) { 1714 if (set == REGISTER_SET_GENERIC) { 1715 switch (reg) { 1716 case GENERIC_REGNUM_PC: // Program Counter 1717 set = e_regSetGPR; 1718 reg = gpr_pc; 1719 break; 1720 1721 case GENERIC_REGNUM_SP: // Stack Pointer 1722 set = e_regSetGPR; 1723 reg = gpr_sp; 1724 break; 1725 1726 case GENERIC_REGNUM_FP: // Frame Pointer 1727 set = e_regSetGPR; 1728 reg = gpr_fp; 1729 break; 1730 1731 case GENERIC_REGNUM_RA: // Return Address 1732 set = e_regSetGPR; 1733 reg = gpr_lr; 1734 break; 1735 1736 case GENERIC_REGNUM_FLAGS: // Processor flags register 1737 set = e_regSetGPR; 1738 reg = gpr_cpsr; 1739 break; 1740 1741 case GENERIC_REGNUM_ARG1: 1742 case GENERIC_REGNUM_ARG2: 1743 case GENERIC_REGNUM_ARG3: 1744 case GENERIC_REGNUM_ARG4: 1745 case GENERIC_REGNUM_ARG5: 1746 case GENERIC_REGNUM_ARG6: 1747 set = e_regSetGPR; 1748 reg = gpr_x0 + reg - GENERIC_REGNUM_ARG1; 1749 break; 1750 1751 default: 1752 return false; 1753 } 1754 } 1755 return true; 1756 } 1757 bool DNBArchMachARM64::GetRegisterValue(uint32_t set, uint32_t reg, 1758 DNBRegisterValue *value) { 1759 if (!FixGenericRegisterNumber(set, reg)) 1760 return false; 1761 1762 if (GetRegisterState(set, false) != KERN_SUCCESS) 1763 return false; 1764 1765 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1766 if (regInfo) { 1767 value->info = *regInfo; 1768 switch (set) { 1769 case e_regSetGPR: 1770 if (reg <= gpr_pc) { 1771 value->value.uint64 = m_state.context.gpr.__x[reg]; 1772 return true; 1773 } else if (reg == gpr_cpsr) { 1774 value->value.uint32 = m_state.context.gpr.__cpsr; 1775 return true; 1776 } 1777 break; 1778 1779 case e_regSetVFP: 1780 1781 if (reg >= vfp_v0 && reg <= vfp_v31) { 1782 #if defined(__arm64__) || defined(__aarch64__) 1783 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_v0], 1784 16); 1785 #else 1786 memcpy(&value->value.v_uint8, 1787 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), 1788 16); 1789 #endif 1790 return true; 1791 } else if (reg == vfp_fpsr) { 1792 #if defined(__arm64__) || defined(__aarch64__) 1793 memcpy(&value->value.uint32, &m_state.context.vfp.__fpsr, 4); 1794 #else 1795 memcpy(&value->value.uint32, 1796 ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0, 4); 1797 #endif 1798 return true; 1799 } else if (reg == vfp_fpcr) { 1800 #if defined(__arm64__) || defined(__aarch64__) 1801 memcpy(&value->value.uint32, &m_state.context.vfp.__fpcr, 4); 1802 #else 1803 memcpy(&value->value.uint32, 1804 ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 4, 4); 1805 #endif 1806 return true; 1807 } else if (reg >= vfp_s0 && reg <= vfp_s31) { 1808 #if defined(__arm64__) || defined(__aarch64__) 1809 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_s0], 1810 4); 1811 #else 1812 memcpy(&value->value.v_uint8, 1813 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), 1814 4); 1815 #endif 1816 return true; 1817 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 1818 #if defined(__arm64__) || defined(__aarch64__) 1819 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_d0], 1820 8); 1821 #else 1822 memcpy(&value->value.v_uint8, 1823 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), 1824 8); 1825 #endif 1826 return true; 1827 } 1828 break; 1829 1830 case e_regSetEXC: 1831 if (reg == exc_far) { 1832 value->value.uint64 = m_state.context.exc.__far; 1833 return true; 1834 } else if (reg == exc_esr) { 1835 value->value.uint32 = m_state.context.exc.__esr; 1836 return true; 1837 } else if (reg == exc_exception) { 1838 value->value.uint32 = m_state.context.exc.__exception; 1839 return true; 1840 } 1841 break; 1842 } 1843 } 1844 return false; 1845 } 1846 1847 bool DNBArchMachARM64::SetRegisterValue(uint32_t set, uint32_t reg, 1848 const DNBRegisterValue *value) { 1849 if (!FixGenericRegisterNumber(set, reg)) 1850 return false; 1851 1852 if (GetRegisterState(set, false) != KERN_SUCCESS) 1853 return false; 1854 1855 bool success = false; 1856 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1857 if (regInfo) { 1858 switch (set) { 1859 case e_regSetGPR: 1860 if (reg <= gpr_pc) { 1861 m_state.context.gpr.__x[reg] = value->value.uint64; 1862 success = true; 1863 } else if (reg == gpr_cpsr) { 1864 m_state.context.gpr.__cpsr = value->value.uint32; 1865 success = true; 1866 } 1867 break; 1868 1869 case e_regSetVFP: 1870 if (reg >= vfp_v0 && reg <= vfp_v31) { 1871 #if defined(__arm64__) || defined(__aarch64__) 1872 memcpy(&m_state.context.vfp.__v[reg - vfp_v0], &value->value.v_uint8, 1873 16); 1874 #else 1875 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), 1876 &value->value.v_uint8, 16); 1877 #endif 1878 success = true; 1879 } else if (reg == vfp_fpsr) { 1880 #if defined(__arm64__) || defined(__aarch64__) 1881 memcpy(&m_state.context.vfp.__fpsr, &value->value.uint32, 4); 1882 #else 1883 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0, 1884 &value->value.uint32, 4); 1885 #endif 1886 success = true; 1887 } else if (reg == vfp_fpcr) { 1888 #if defined(__arm64__) || defined(__aarch64__) 1889 memcpy(&m_state.context.vfp.__fpcr, &value->value.uint32, 4); 1890 #else 1891 memcpy(((uint8_t *)m_state.context.vfp.opaque) + (32 * 16) + 4, 1892 &value->value.uint32, 4); 1893 #endif 1894 success = true; 1895 } else if (reg >= vfp_s0 && reg <= vfp_s31) { 1896 #if defined(__arm64__) || defined(__aarch64__) 1897 memcpy(&m_state.context.vfp.__v[reg - vfp_s0], &value->value.v_uint8, 1898 4); 1899 #else 1900 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), 1901 &value->value.v_uint8, 4); 1902 #endif 1903 success = true; 1904 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 1905 #if defined(__arm64__) || defined(__aarch64__) 1906 memcpy(&m_state.context.vfp.__v[reg - vfp_d0], &value->value.v_uint8, 1907 8); 1908 #else 1909 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), 1910 &value->value.v_uint8, 8); 1911 #endif 1912 success = true; 1913 } 1914 break; 1915 1916 case e_regSetEXC: 1917 if (reg == exc_far) { 1918 m_state.context.exc.__far = value->value.uint64; 1919 success = true; 1920 } else if (reg == exc_esr) { 1921 m_state.context.exc.__esr = value->value.uint32; 1922 success = true; 1923 } else if (reg == exc_exception) { 1924 m_state.context.exc.__exception = value->value.uint32; 1925 success = true; 1926 } 1927 break; 1928 } 1929 } 1930 if (success) 1931 return SetRegisterState(set) == KERN_SUCCESS; 1932 return false; 1933 } 1934 1935 kern_return_t DNBArchMachARM64::GetRegisterState(int set, bool force) { 1936 switch (set) { 1937 case e_regSetALL: 1938 return GetGPRState(force) | GetVFPState(force) | GetEXCState(force) | 1939 GetDBGState(force); 1940 case e_regSetGPR: 1941 return GetGPRState(force); 1942 case e_regSetVFP: 1943 return GetVFPState(force); 1944 case e_regSetEXC: 1945 return GetEXCState(force); 1946 case e_regSetDBG: 1947 return GetDBGState(force); 1948 default: 1949 break; 1950 } 1951 return KERN_INVALID_ARGUMENT; 1952 } 1953 1954 kern_return_t DNBArchMachARM64::SetRegisterState(int set) { 1955 // Make sure we have a valid context to set. 1956 kern_return_t err = GetRegisterState(set, false); 1957 if (err != KERN_SUCCESS) 1958 return err; 1959 1960 switch (set) { 1961 case e_regSetALL: 1962 return SetGPRState() | SetVFPState() | SetEXCState() | SetDBGState(false); 1963 case e_regSetGPR: 1964 return SetGPRState(); 1965 case e_regSetVFP: 1966 return SetVFPState(); 1967 case e_regSetEXC: 1968 return SetEXCState(); 1969 case e_regSetDBG: 1970 return SetDBGState(false); 1971 default: 1972 break; 1973 } 1974 return KERN_INVALID_ARGUMENT; 1975 } 1976 1977 bool DNBArchMachARM64::RegisterSetStateIsValid(int set) const { 1978 return m_state.RegsAreValid(set); 1979 } 1980 1981 nub_size_t DNBArchMachARM64::GetRegisterContext(void *buf, nub_size_t buf_len) { 1982 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 1983 sizeof(m_state.context.exc); 1984 1985 if (buf && buf_len) { 1986 if (size > buf_len) 1987 size = buf_len; 1988 1989 bool force = false; 1990 if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force)) 1991 return 0; 1992 1993 // Copy each struct individually to avoid any padding that might be between 1994 // the structs in m_state.context 1995 uint8_t *p = (uint8_t *)buf; 1996 ::memcpy(p, &m_state.context.gpr, sizeof(m_state.context.gpr)); 1997 p += sizeof(m_state.context.gpr); 1998 ::memcpy(p, &m_state.context.vfp, sizeof(m_state.context.vfp)); 1999 p += sizeof(m_state.context.vfp); 2000 ::memcpy(p, &m_state.context.exc, sizeof(m_state.context.exc)); 2001 p += sizeof(m_state.context.exc); 2002 2003 size_t bytes_written = p - (uint8_t *)buf; 2004 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2005 assert(bytes_written == size); 2006 } 2007 DNBLogThreadedIf( 2008 LOG_THREAD, 2009 "DNBArchMachARM64::GetRegisterContext (buf = %p, len = %zu) => %zu", buf, 2010 buf_len, size); 2011 // Return the size of the register context even if NULL was passed in 2012 return size; 2013 } 2014 2015 nub_size_t DNBArchMachARM64::SetRegisterContext(const void *buf, 2016 nub_size_t buf_len) { 2017 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 2018 sizeof(m_state.context.exc); 2019 2020 if (buf == NULL || buf_len == 0) 2021 size = 0; 2022 2023 if (size) { 2024 if (size > buf_len) 2025 size = buf_len; 2026 2027 // Copy each struct individually to avoid any padding that might be between 2028 // the structs in m_state.context 2029 uint8_t *p = (uint8_t *)buf; 2030 ::memcpy(&m_state.context.gpr, p, sizeof(m_state.context.gpr)); 2031 p += sizeof(m_state.context.gpr); 2032 ::memcpy(&m_state.context.vfp, p, sizeof(m_state.context.vfp)); 2033 p += sizeof(m_state.context.vfp); 2034 ::memcpy(&m_state.context.exc, p, sizeof(m_state.context.exc)); 2035 p += sizeof(m_state.context.exc); 2036 2037 size_t bytes_written = p - (uint8_t *)buf; 2038 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2039 assert(bytes_written == size); 2040 SetGPRState(); 2041 SetVFPState(); 2042 SetEXCState(); 2043 } 2044 DNBLogThreadedIf( 2045 LOG_THREAD, 2046 "DNBArchMachARM64::SetRegisterContext (buf = %p, len = %zu) => %zu", buf, 2047 buf_len, size); 2048 return size; 2049 } 2050 2051 uint32_t DNBArchMachARM64::SaveRegisterState() { 2052 kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber()); 2053 DNBLogThreadedIf( 2054 LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u " 2055 "(SetGPRState() for stop_count = %u)", 2056 m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount()); 2057 2058 // Always re-read the registers because above we call thread_abort_safely(); 2059 bool force = true; 2060 2061 if ((kret = GetGPRState(force)) != KERN_SUCCESS) { 2062 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () " 2063 "error: GPR regs failed to read: %u ", 2064 kret); 2065 } else if ((kret = GetVFPState(force)) != KERN_SUCCESS) { 2066 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () " 2067 "error: %s regs failed to read: %u", 2068 "VFP", kret); 2069 } else { 2070 const uint32_t save_id = GetNextRegisterStateSaveID(); 2071 m_saved_register_states[save_id] = m_state.context; 2072 return save_id; 2073 } 2074 return UINT32_MAX; 2075 } 2076 2077 bool DNBArchMachARM64::RestoreRegisterState(uint32_t save_id) { 2078 SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id); 2079 if (pos != m_saved_register_states.end()) { 2080 m_state.context.gpr = pos->second.gpr; 2081 m_state.context.vfp = pos->second.vfp; 2082 kern_return_t kret; 2083 bool success = true; 2084 if ((kret = SetGPRState()) != KERN_SUCCESS) { 2085 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState " 2086 "(save_id = %u) error: GPR regs failed to " 2087 "write: %u", 2088 save_id, kret); 2089 success = false; 2090 } else if ((kret = SetVFPState()) != KERN_SUCCESS) { 2091 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState " 2092 "(save_id = %u) error: %s regs failed to " 2093 "write: %u", 2094 save_id, "VFP", kret); 2095 success = false; 2096 } 2097 m_saved_register_states.erase(pos); 2098 return success; 2099 } 2100 return false; 2101 } 2102 2103 #endif // #if defined (ARM_THREAD_STATE64_COUNT) 2104 #endif // #if defined (__arm__) || defined (__arm64__) || defined (__aarch64__) 2105