1 //===-- DNBArchImplARM64.cpp ------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Created by Greg Clayton on 6/25/07. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #if defined(__arm__) || defined(__arm64__) || defined(__aarch64__) 14 15 #include "MacOSX/arm64/DNBArchImplARM64.h" 16 17 #if defined(ARM_THREAD_STATE64_COUNT) 18 19 #include "DNB.h" 20 #include "DNBBreakpoint.h" 21 #include "DNBLog.h" 22 #include "DNBRegisterInfo.h" 23 #include "MacOSX/MachProcess.h" 24 #include "MacOSX/MachThread.h" 25 26 #include <inttypes.h> 27 #include <sys/sysctl.h> 28 29 #if __has_feature(ptrauth_calls) 30 #include <ptrauth.h> 31 #endif 32 33 // Break only in privileged or user mode 34 // (PAC bits in the DBGWVRn_EL1 watchpoint control register) 35 #define S_USER ((uint32_t)(2u << 1)) 36 37 #define BCR_ENABLE ((uint32_t)(1u)) 38 #define WCR_ENABLE ((uint32_t)(1u)) 39 40 // Watchpoint load/store 41 // (LSC bits in the DBGWVRn_EL1 watchpoint control register) 42 #define WCR_LOAD ((uint32_t)(1u << 3)) 43 #define WCR_STORE ((uint32_t)(1u << 4)) 44 45 // Enable breakpoint, watchpoint, and vector catch debug exceptions. 46 // (MDE bit in the MDSCR_EL1 register. Equivalent to the MDBGen bit in 47 // DBGDSCRext in Aarch32) 48 #define MDE_ENABLE ((uint32_t)(1u << 15)) 49 50 // Single instruction step 51 // (SS bit in the MDSCR_EL1 register) 52 #define SS_ENABLE ((uint32_t)(1u)) 53 54 static const uint8_t g_arm64_breakpoint_opcode[] = { 55 0x00, 0x00, 0x20, 0xD4}; // "brk #0", 0xd4200000 in BE byte order 56 57 // If we need to set one logical watchpoint by using 58 // two hardware watchpoint registers, the watchpoint 59 // will be split into a "high" and "low" watchpoint. 60 // Record both of them in the LoHi array. 61 62 // It's safe to initialize to all 0's since 63 // hi > lo and therefore LoHi[i] cannot be 0. 64 static uint32_t LoHi[16] = {0}; 65 66 void DNBArchMachARM64::Initialize() { 67 DNBArchPluginInfo arch_plugin_info = { 68 CPU_TYPE_ARM64, DNBArchMachARM64::Create, 69 DNBArchMachARM64::GetRegisterSetInfo, 70 DNBArchMachARM64::SoftwareBreakpointOpcode}; 71 72 // Register this arch plug-in with the main protocol class 73 DNBArchProtocol::RegisterArchPlugin(arch_plugin_info); 74 75 DNBArchPluginInfo arch_plugin_info_32 = { 76 CPU_TYPE_ARM64_32, DNBArchMachARM64::Create, 77 DNBArchMachARM64::GetRegisterSetInfo, 78 DNBArchMachARM64::SoftwareBreakpointOpcode}; 79 80 // Register this arch plug-in with the main protocol class 81 DNBArchProtocol::RegisterArchPlugin(arch_plugin_info_32); 82 } 83 84 DNBArchProtocol *DNBArchMachARM64::Create(MachThread *thread) { 85 DNBArchMachARM64 *obj = new DNBArchMachARM64(thread); 86 87 return obj; 88 } 89 90 const uint8_t * 91 DNBArchMachARM64::SoftwareBreakpointOpcode(nub_size_t byte_size) { 92 return g_arm64_breakpoint_opcode; 93 } 94 95 uint32_t DNBArchMachARM64::GetCPUType() { return CPU_TYPE_ARM64; } 96 97 uint64_t DNBArchMachARM64::GetPC(uint64_t failValue) { 98 // Get program counter 99 if (GetGPRState(false) == KERN_SUCCESS) 100 #if defined(__LP64__) 101 return arm_thread_state64_get_pc(m_state.context.gpr); 102 #else 103 return m_state.context.gpr.__pc; 104 #endif 105 return failValue; 106 } 107 108 kern_return_t DNBArchMachARM64::SetPC(uint64_t value) { 109 // Get program counter 110 kern_return_t err = GetGPRState(false); 111 if (err == KERN_SUCCESS) { 112 #if defined(__LP64__) 113 #if __has_feature(ptrauth_calls) 114 // The incoming value could be garbage. Strip it to avoid 115 // trapping when it gets resigned in the thread state. 116 value = (uint64_t) ptrauth_strip((void*) value, ptrauth_key_function_pointer); 117 value = (uint64_t) ptrauth_sign_unauthenticated((void*) value, ptrauth_key_function_pointer, 0); 118 #endif 119 arm_thread_state64_set_pc_fptr (m_state.context.gpr, (void*) value); 120 #else 121 m_state.context.gpr.__pc = value; 122 #endif 123 err = SetGPRState(); 124 } 125 return err == KERN_SUCCESS; 126 } 127 128 uint64_t DNBArchMachARM64::GetSP(uint64_t failValue) { 129 // Get stack pointer 130 if (GetGPRState(false) == KERN_SUCCESS) 131 #if defined(__LP64__) 132 return arm_thread_state64_get_sp(m_state.context.gpr); 133 #else 134 return m_state.context.gpr.__sp; 135 #endif 136 return failValue; 137 } 138 139 kern_return_t DNBArchMachARM64::GetGPRState(bool force) { 140 int set = e_regSetGPR; 141 // Check if we have valid cached registers 142 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 143 return KERN_SUCCESS; 144 145 // Read the registers from our thread 146 mach_msg_type_number_t count = e_regSetGPRCount; 147 kern_return_t kret = 148 ::thread_get_state(m_thread->MachPortNumber(), ARM_THREAD_STATE64, 149 (thread_state_t)&m_state.context.gpr, &count); 150 if (DNBLogEnabledForAny(LOG_THREAD)) { 151 uint64_t *x = &m_state.context.gpr.__x[0]; 152 DNBLogThreaded( 153 "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count = %u) regs" 154 "\n x0=%16.16llx" 155 "\n x1=%16.16llx" 156 "\n x2=%16.16llx" 157 "\n x3=%16.16llx" 158 "\n x4=%16.16llx" 159 "\n x5=%16.16llx" 160 "\n x6=%16.16llx" 161 "\n x7=%16.16llx" 162 "\n x8=%16.16llx" 163 "\n x9=%16.16llx" 164 "\n x10=%16.16llx" 165 "\n x11=%16.16llx" 166 "\n x12=%16.16llx" 167 "\n x13=%16.16llx" 168 "\n x14=%16.16llx" 169 "\n x15=%16.16llx" 170 "\n x16=%16.16llx" 171 "\n x17=%16.16llx" 172 "\n x18=%16.16llx" 173 "\n x19=%16.16llx" 174 "\n x20=%16.16llx" 175 "\n x21=%16.16llx" 176 "\n x22=%16.16llx" 177 "\n x23=%16.16llx" 178 "\n x24=%16.16llx" 179 "\n x25=%16.16llx" 180 "\n x26=%16.16llx" 181 "\n x27=%16.16llx" 182 "\n x28=%16.16llx" 183 "\n fp=%16.16llx" 184 "\n lr=%16.16llx" 185 "\n sp=%16.16llx" 186 "\n pc=%16.16llx" 187 "\n cpsr=%8.8x", 188 m_thread->MachPortNumber(), e_regSetGPR, e_regSetGPRCount, kret, count, 189 x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[0], x[11], 190 x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], x[20], x[21], 191 x[22], x[23], x[24], x[25], x[26], x[27], x[28], 192 #if defined(__LP64__) 193 (uint64_t) arm_thread_state64_get_fp (m_state.context.gpr), 194 (uint64_t) arm_thread_state64_get_lr (m_state.context.gpr), 195 (uint64_t) arm_thread_state64_get_sp (m_state.context.gpr), 196 (uint64_t) arm_thread_state64_get_pc (m_state.context.gpr), 197 #else 198 m_state.context.gpr.__fp, m_state.context.gpr.__lr, 199 m_state.context.gpr.__sp, m_state.context.gpr.__pc, 200 #endif 201 m_state.context.gpr.__cpsr); 202 } 203 m_state.SetError(set, Read, kret); 204 return kret; 205 } 206 207 kern_return_t DNBArchMachARM64::GetVFPState(bool force) { 208 int set = e_regSetVFP; 209 // Check if we have valid cached registers 210 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 211 return KERN_SUCCESS; 212 213 // Read the registers from our thread 214 mach_msg_type_number_t count = e_regSetVFPCount; 215 kern_return_t kret = 216 ::thread_get_state(m_thread->MachPortNumber(), ARM_NEON_STATE64, 217 (thread_state_t)&m_state.context.vfp, &count); 218 if (DNBLogEnabledForAny(LOG_THREAD)) { 219 #if defined(__arm64__) || defined(__aarch64__) 220 DNBLogThreaded( 221 "thread_get_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs" 222 "\n q0 = 0x%16.16llx%16.16llx" 223 "\n q1 = 0x%16.16llx%16.16llx" 224 "\n q2 = 0x%16.16llx%16.16llx" 225 "\n q3 = 0x%16.16llx%16.16llx" 226 "\n q4 = 0x%16.16llx%16.16llx" 227 "\n q5 = 0x%16.16llx%16.16llx" 228 "\n q6 = 0x%16.16llx%16.16llx" 229 "\n q7 = 0x%16.16llx%16.16llx" 230 "\n q8 = 0x%16.16llx%16.16llx" 231 "\n q9 = 0x%16.16llx%16.16llx" 232 "\n q10 = 0x%16.16llx%16.16llx" 233 "\n q11 = 0x%16.16llx%16.16llx" 234 "\n q12 = 0x%16.16llx%16.16llx" 235 "\n q13 = 0x%16.16llx%16.16llx" 236 "\n q14 = 0x%16.16llx%16.16llx" 237 "\n q15 = 0x%16.16llx%16.16llx" 238 "\n q16 = 0x%16.16llx%16.16llx" 239 "\n q17 = 0x%16.16llx%16.16llx" 240 "\n q18 = 0x%16.16llx%16.16llx" 241 "\n q19 = 0x%16.16llx%16.16llx" 242 "\n q20 = 0x%16.16llx%16.16llx" 243 "\n q21 = 0x%16.16llx%16.16llx" 244 "\n q22 = 0x%16.16llx%16.16llx" 245 "\n q23 = 0x%16.16llx%16.16llx" 246 "\n q24 = 0x%16.16llx%16.16llx" 247 "\n q25 = 0x%16.16llx%16.16llx" 248 "\n q26 = 0x%16.16llx%16.16llx" 249 "\n q27 = 0x%16.16llx%16.16llx" 250 "\n q28 = 0x%16.16llx%16.16llx" 251 "\n q29 = 0x%16.16llx%16.16llx" 252 "\n q30 = 0x%16.16llx%16.16llx" 253 "\n q31 = 0x%16.16llx%16.16llx" 254 "\n fpsr = 0x%8.8x" 255 "\n fpcr = 0x%8.8x\n\n", 256 m_thread->MachPortNumber(), e_regSetVFP, e_regSetVFPCount, kret, count, 257 ((uint64_t *)&m_state.context.vfp.__v[0])[0], 258 ((uint64_t *)&m_state.context.vfp.__v[0])[1], 259 ((uint64_t *)&m_state.context.vfp.__v[1])[0], 260 ((uint64_t *)&m_state.context.vfp.__v[1])[1], 261 ((uint64_t *)&m_state.context.vfp.__v[2])[0], 262 ((uint64_t *)&m_state.context.vfp.__v[2])[1], 263 ((uint64_t *)&m_state.context.vfp.__v[3])[0], 264 ((uint64_t *)&m_state.context.vfp.__v[3])[1], 265 ((uint64_t *)&m_state.context.vfp.__v[4])[0], 266 ((uint64_t *)&m_state.context.vfp.__v[4])[1], 267 ((uint64_t *)&m_state.context.vfp.__v[5])[0], 268 ((uint64_t *)&m_state.context.vfp.__v[5])[1], 269 ((uint64_t *)&m_state.context.vfp.__v[6])[0], 270 ((uint64_t *)&m_state.context.vfp.__v[6])[1], 271 ((uint64_t *)&m_state.context.vfp.__v[7])[0], 272 ((uint64_t *)&m_state.context.vfp.__v[7])[1], 273 ((uint64_t *)&m_state.context.vfp.__v[8])[0], 274 ((uint64_t *)&m_state.context.vfp.__v[8])[1], 275 ((uint64_t *)&m_state.context.vfp.__v[9])[0], 276 ((uint64_t *)&m_state.context.vfp.__v[9])[1], 277 ((uint64_t *)&m_state.context.vfp.__v[10])[0], 278 ((uint64_t *)&m_state.context.vfp.__v[10])[1], 279 ((uint64_t *)&m_state.context.vfp.__v[11])[0], 280 ((uint64_t *)&m_state.context.vfp.__v[11])[1], 281 ((uint64_t *)&m_state.context.vfp.__v[12])[0], 282 ((uint64_t *)&m_state.context.vfp.__v[12])[1], 283 ((uint64_t *)&m_state.context.vfp.__v[13])[0], 284 ((uint64_t *)&m_state.context.vfp.__v[13])[1], 285 ((uint64_t *)&m_state.context.vfp.__v[14])[0], 286 ((uint64_t *)&m_state.context.vfp.__v[14])[1], 287 ((uint64_t *)&m_state.context.vfp.__v[15])[0], 288 ((uint64_t *)&m_state.context.vfp.__v[15])[1], 289 ((uint64_t *)&m_state.context.vfp.__v[16])[0], 290 ((uint64_t *)&m_state.context.vfp.__v[16])[1], 291 ((uint64_t *)&m_state.context.vfp.__v[17])[0], 292 ((uint64_t *)&m_state.context.vfp.__v[17])[1], 293 ((uint64_t *)&m_state.context.vfp.__v[18])[0], 294 ((uint64_t *)&m_state.context.vfp.__v[18])[1], 295 ((uint64_t *)&m_state.context.vfp.__v[19])[0], 296 ((uint64_t *)&m_state.context.vfp.__v[19])[1], 297 ((uint64_t *)&m_state.context.vfp.__v[20])[0], 298 ((uint64_t *)&m_state.context.vfp.__v[20])[1], 299 ((uint64_t *)&m_state.context.vfp.__v[21])[0], 300 ((uint64_t *)&m_state.context.vfp.__v[21])[1], 301 ((uint64_t *)&m_state.context.vfp.__v[22])[0], 302 ((uint64_t *)&m_state.context.vfp.__v[22])[1], 303 ((uint64_t *)&m_state.context.vfp.__v[23])[0], 304 ((uint64_t *)&m_state.context.vfp.__v[23])[1], 305 ((uint64_t *)&m_state.context.vfp.__v[24])[0], 306 ((uint64_t *)&m_state.context.vfp.__v[24])[1], 307 ((uint64_t *)&m_state.context.vfp.__v[25])[0], 308 ((uint64_t *)&m_state.context.vfp.__v[25])[1], 309 ((uint64_t *)&m_state.context.vfp.__v[26])[0], 310 ((uint64_t *)&m_state.context.vfp.__v[26])[1], 311 ((uint64_t *)&m_state.context.vfp.__v[27])[0], 312 ((uint64_t *)&m_state.context.vfp.__v[27])[1], 313 ((uint64_t *)&m_state.context.vfp.__v[28])[0], 314 ((uint64_t *)&m_state.context.vfp.__v[28])[1], 315 ((uint64_t *)&m_state.context.vfp.__v[29])[0], 316 ((uint64_t *)&m_state.context.vfp.__v[29])[1], 317 ((uint64_t *)&m_state.context.vfp.__v[30])[0], 318 ((uint64_t *)&m_state.context.vfp.__v[30])[1], 319 ((uint64_t *)&m_state.context.vfp.__v[31])[0], 320 ((uint64_t *)&m_state.context.vfp.__v[31])[1], 321 m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr); 322 #endif 323 } 324 m_state.SetError(set, Read, kret); 325 return kret; 326 } 327 328 kern_return_t DNBArchMachARM64::GetEXCState(bool force) { 329 int set = e_regSetEXC; 330 // Check if we have valid cached registers 331 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 332 return KERN_SUCCESS; 333 334 // Read the registers from our thread 335 mach_msg_type_number_t count = e_regSetEXCCount; 336 kern_return_t kret = 337 ::thread_get_state(m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, 338 (thread_state_t)&m_state.context.exc, &count); 339 m_state.SetError(set, Read, kret); 340 return kret; 341 } 342 343 #if 0 344 static void DumpDBGState(const arm_debug_state_t &dbg) { 345 uint32_t i = 0; 346 for (i = 0; i < 16; i++) 347 DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } " 348 "WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }", 349 i, i, dbg.__bvr[i], dbg.__bcr[i], i, i, dbg.__wvr[i], 350 dbg.__wcr[i]); 351 } 352 #endif 353 354 kern_return_t DNBArchMachARM64::GetDBGState(bool force) { 355 int set = e_regSetDBG; 356 357 // Check if we have valid cached registers 358 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 359 return KERN_SUCCESS; 360 361 // Read the registers from our thread 362 mach_msg_type_number_t count = e_regSetDBGCount; 363 kern_return_t kret = 364 ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64, 365 (thread_state_t)&m_state.dbg, &count); 366 m_state.SetError(set, Read, kret); 367 368 return kret; 369 } 370 371 kern_return_t DNBArchMachARM64::SetGPRState() { 372 int set = e_regSetGPR; 373 kern_return_t kret = ::thread_set_state( 374 m_thread->MachPortNumber(), ARM_THREAD_STATE64, 375 (thread_state_t)&m_state.context.gpr, e_regSetGPRCount); 376 m_state.SetError(set, Write, 377 kret); // Set the current write error for this register set 378 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 379 // state in case registers are read 380 // back differently 381 return kret; // Return the error code 382 } 383 384 kern_return_t DNBArchMachARM64::SetVFPState() { 385 int set = e_regSetVFP; 386 kern_return_t kret = ::thread_set_state( 387 m_thread->MachPortNumber(), ARM_NEON_STATE64, 388 (thread_state_t)&m_state.context.vfp, e_regSetVFPCount); 389 m_state.SetError(set, Write, 390 kret); // Set the current write error for this register set 391 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 392 // state in case registers are read 393 // back differently 394 return kret; // Return the error code 395 } 396 397 kern_return_t DNBArchMachARM64::SetEXCState() { 398 int set = e_regSetEXC; 399 kern_return_t kret = ::thread_set_state( 400 m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, 401 (thread_state_t)&m_state.context.exc, e_regSetEXCCount); 402 m_state.SetError(set, Write, 403 kret); // Set the current write error for this register set 404 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 405 // state in case registers are read 406 // back differently 407 return kret; // Return the error code 408 } 409 410 kern_return_t DNBArchMachARM64::SetDBGState(bool also_set_on_task) { 411 int set = e_regSetDBG; 412 kern_return_t kret = 413 ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64, 414 (thread_state_t)&m_state.dbg, e_regSetDBGCount); 415 if (also_set_on_task) { 416 kern_return_t task_kret = task_set_state( 417 m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE64, 418 (thread_state_t)&m_state.dbg, e_regSetDBGCount); 419 if (task_kret != KERN_SUCCESS) 420 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::SetDBGState failed " 421 "to set debug control register state: " 422 "0x%8.8x.", 423 task_kret); 424 } 425 m_state.SetError(set, Write, 426 kret); // Set the current write error for this register set 427 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 428 // state in case registers are read 429 // back differently 430 431 return kret; // Return the error code 432 } 433 434 void DNBArchMachARM64::ThreadWillResume() { 435 // Do we need to step this thread? If so, let the mach thread tell us so. 436 if (m_thread->IsStepping()) { 437 EnableHardwareSingleStep(true); 438 } 439 440 // Disable the triggered watchpoint temporarily before we resume. 441 // Plus, we try to enable hardware single step to execute past the instruction 442 // which triggered our watchpoint. 443 if (m_watchpoint_did_occur) { 444 if (m_watchpoint_hw_index >= 0) { 445 kern_return_t kret = GetDBGState(false); 446 if (kret == KERN_SUCCESS && 447 !IsWatchpointEnabled(m_state.dbg, m_watchpoint_hw_index)) { 448 // The watchpoint might have been disabled by the user. We don't need 449 // to do anything at all 450 // to enable hardware single stepping. 451 m_watchpoint_did_occur = false; 452 m_watchpoint_hw_index = -1; 453 return; 454 } 455 456 DisableHardwareWatchpoint(m_watchpoint_hw_index, false); 457 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 458 "DisableHardwareWatchpoint(%d) called", 459 m_watchpoint_hw_index); 460 461 // Enable hardware single step to move past the watchpoint-triggering 462 // instruction. 463 m_watchpoint_resume_single_step_enabled = 464 (EnableHardwareSingleStep(true) == KERN_SUCCESS); 465 466 // If we are not able to enable single step to move past the 467 // watchpoint-triggering instruction, 468 // at least we should reset the two watchpoint member variables so that 469 // the next time around 470 // this callback function is invoked, the enclosing logical branch is 471 // skipped. 472 if (!m_watchpoint_resume_single_step_enabled) { 473 // Reset the two watchpoint member variables. 474 m_watchpoint_did_occur = false; 475 m_watchpoint_hw_index = -1; 476 DNBLogThreadedIf( 477 LOG_WATCHPOINTS, 478 "DNBArchMachARM::ThreadWillResume() failed to enable single step"); 479 } else 480 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 481 "succeeded to enable single step"); 482 } 483 } 484 } 485 486 bool DNBArchMachARM64::NotifyException(MachException::Data &exc) { 487 488 switch (exc.exc_type) { 489 default: 490 break; 491 case EXC_BREAKPOINT: 492 if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_DA_DEBUG) { 493 // The data break address is passed as exc_data[1]. 494 nub_addr_t addr = exc.exc_data[1]; 495 // Find the hardware index with the side effect of possibly massaging the 496 // addr to return the starting address as seen from the debugger side. 497 uint32_t hw_index = GetHardwareWatchpointHit(addr); 498 499 // One logical watchpoint was split into two watchpoint locations because 500 // it was too big. If the watchpoint exception is indicating the 2nd half 501 // of the two-parter, find the address of the 1st half and report that -- 502 // that's what lldb is going to expect to see. 503 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 504 "watchpoint %d was hit on address " 505 "0x%llx", 506 hw_index, (uint64_t)addr); 507 const uint32_t num_watchpoints = NumSupportedHardwareWatchpoints(); 508 for (uint32_t i = 0; i < num_watchpoints; i++) { 509 if (LoHi[i] != 0 && LoHi[i] == hw_index && LoHi[i] != i && 510 GetWatchpointAddressByIndex(i) != INVALID_NUB_ADDRESS) { 511 addr = GetWatchpointAddressByIndex(i); 512 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 513 "It is a linked watchpoint; " 514 "rewritten to index %d addr 0x%llx", 515 LoHi[i], (uint64_t)addr); 516 } 517 } 518 519 if (hw_index != INVALID_NUB_HW_INDEX) { 520 m_watchpoint_did_occur = true; 521 m_watchpoint_hw_index = hw_index; 522 exc.exc_data[1] = addr; 523 // Piggyback the hw_index in the exc.data. 524 exc.exc_data.push_back(hw_index); 525 } 526 527 return true; 528 } 529 // detect a __builtin_debugtrap instruction pattern ("brk #0xf000") 530 // and advance the $pc past it, so that the user can continue execution. 531 // Generally speaking, this knowledge should be centralized in lldb, 532 // recognizing the builtin_trap instruction and knowing how to advance 533 // the pc past it, so that continue etc work. 534 if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_BREAKPOINT) { 535 nub_addr_t pc = GetPC(INVALID_NUB_ADDRESS); 536 if (pc != INVALID_NUB_ADDRESS && pc > 0) { 537 DNBBreakpoint *bp = 538 m_thread->Process()->Breakpoints().FindByAddress(pc); 539 if (bp == nullptr) { 540 uint8_t insnbuf[4]; 541 if (m_thread->Process()->ReadMemory(pc, 4, insnbuf) == 4) { 542 uint8_t builtin_debugtrap_insn[4] = {0x00, 0x00, 0x3e, 543 0xd4}; // brk #0xf000 544 if (memcmp(insnbuf, builtin_debugtrap_insn, 4) == 0) { 545 SetPC(pc + 4); 546 } 547 } 548 } 549 } 550 } 551 break; 552 } 553 return false; 554 } 555 556 bool DNBArchMachARM64::ThreadDidStop() { 557 bool success = true; 558 559 m_state.InvalidateAllRegisterStates(); 560 561 if (m_watchpoint_resume_single_step_enabled) { 562 // Great! We now disable the hardware single step as well as re-enable the 563 // hardware watchpoint. 564 // See also ThreadWillResume(). 565 if (EnableHardwareSingleStep(false) == KERN_SUCCESS) { 566 if (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0) { 567 ReenableHardwareWatchpoint(m_watchpoint_hw_index); 568 m_watchpoint_resume_single_step_enabled = false; 569 m_watchpoint_did_occur = false; 570 m_watchpoint_hw_index = -1; 571 } else { 572 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 573 "is true but (m_watchpoint_did_occur && " 574 "m_watchpoint_hw_index >= 0) does not hold!"); 575 } 576 } else { 577 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 578 "is true but unable to disable single step!"); 579 } 580 } 581 582 // Are we stepping a single instruction? 583 if (GetGPRState(true) == KERN_SUCCESS) { 584 // We are single stepping, was this the primary thread? 585 if (m_thread->IsStepping()) { 586 // This was the primary thread, we need to clear the trace 587 // bit if so. 588 success = EnableHardwareSingleStep(false) == KERN_SUCCESS; 589 } else { 590 // The MachThread will automatically restore the suspend count 591 // in ThreadDidStop(), so we don't need to do anything here if 592 // we weren't the primary thread the last time 593 } 594 } 595 return success; 596 } 597 598 // Set the single step bit in the processor status register. 599 kern_return_t DNBArchMachARM64::EnableHardwareSingleStep(bool enable) { 600 DNBError err; 601 DNBLogThreadedIf(LOG_STEP, "%s( enable = %d )", __FUNCTION__, enable); 602 603 err = GetGPRState(false); 604 605 if (err.Fail()) { 606 err.LogThreaded("%s: failed to read the GPR registers", __FUNCTION__); 607 return err.Status(); 608 } 609 610 err = GetDBGState(false); 611 612 if (err.Fail()) { 613 err.LogThreaded("%s: failed to read the DBG registers", __FUNCTION__); 614 return err.Status(); 615 } 616 617 #if defined(__LP64__) 618 uint64_t pc = arm_thread_state64_get_pc (m_state.context.gpr); 619 #else 620 uint64_t pc = m_state.context.gpr.__pc; 621 #endif 622 623 if (enable) { 624 DNBLogThreadedIf(LOG_STEP, 625 "%s: Setting MDSCR_EL1 Single Step bit at pc 0x%llx", 626 __FUNCTION__, pc); 627 m_state.dbg.__mdscr_el1 |= SS_ENABLE; 628 } else { 629 DNBLogThreadedIf(LOG_STEP, 630 "%s: Clearing MDSCR_EL1 Single Step bit at pc 0x%llx", 631 __FUNCTION__, pc); 632 m_state.dbg.__mdscr_el1 &= ~(SS_ENABLE); 633 } 634 635 return SetDBGState(false); 636 } 637 638 // return 1 if bit "BIT" is set in "value" 639 static inline uint32_t bit(uint32_t value, uint32_t bit) { 640 return (value >> bit) & 1u; 641 } 642 643 // return the bitfield "value[msbit:lsbit]". 644 static inline uint64_t bits(uint64_t value, uint32_t msbit, uint32_t lsbit) { 645 assert(msbit >= lsbit); 646 uint64_t shift_left = sizeof(value) * 8 - 1 - msbit; 647 value <<= 648 shift_left; // shift anything above the msbit off of the unsigned edge 649 value >>= shift_left + lsbit; // shift it back again down to the lsbit 650 // (including undoing any shift from above) 651 return value; // return our result 652 } 653 654 uint32_t DNBArchMachARM64::NumSupportedHardwareWatchpoints() { 655 // Set the init value to something that will let us know that we need to 656 // autodetect how many watchpoints are supported dynamically... 657 static uint32_t g_num_supported_hw_watchpoints = UINT_MAX; 658 if (g_num_supported_hw_watchpoints == UINT_MAX) { 659 // Set this to zero in case we can't tell if there are any HW breakpoints 660 g_num_supported_hw_watchpoints = 0; 661 662 size_t len; 663 uint32_t n = 0; 664 len = sizeof(n); 665 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) { 666 g_num_supported_hw_watchpoints = n; 667 DNBLogThreadedIf(LOG_THREAD, "hw.optional.watchpoint=%u", n); 668 } else { 669 // For AArch64 we would need to look at ID_AA64DFR0_EL1 but debugserver runs in 670 // EL0 so it can't 671 // access that reg. The kernel should have filled in the sysctls based on it 672 // though. 673 #if defined(__arm__) 674 uint32_t register_DBGDIDR; 675 676 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 677 uint32_t numWRPs = bits(register_DBGDIDR, 31, 28); 678 // Zero is reserved for the WRP count, so don't increment it if it is zero 679 if (numWRPs > 0) 680 numWRPs++; 681 g_num_supported_hw_watchpoints = numWRPs; 682 DNBLogThreadedIf(LOG_THREAD, 683 "Number of supported hw watchpoints via asm(): %d", 684 g_num_supported_hw_watchpoints); 685 #endif 686 } 687 } 688 return g_num_supported_hw_watchpoints; 689 } 690 691 uint32_t DNBArchMachARM64::NumSupportedHardwareBreakpoints() { 692 // Set the init value to something that will let us know that we need to 693 // autodetect how many breakpoints are supported dynamically... 694 static uint32_t g_num_supported_hw_breakpoints = UINT_MAX; 695 if (g_num_supported_hw_breakpoints == UINT_MAX) { 696 // Set this to zero in case we can't tell if there are any HW breakpoints 697 g_num_supported_hw_breakpoints = 0; 698 699 size_t len; 700 uint32_t n = 0; 701 len = sizeof(n); 702 if (::sysctlbyname("hw.optional.breakpoint", &n, &len, NULL, 0) == 0) { 703 g_num_supported_hw_breakpoints = n; 704 DNBLogThreadedIf(LOG_THREAD, "hw.optional.breakpoint=%u", n); 705 } else { 706 // For AArch64 we would need to look at ID_AA64DFR0_EL1 but debugserver runs in 707 // EL0 so it can't access that reg. The kernel should have filled in the 708 // sysctls based on it though. 709 #if defined(__arm__) 710 uint32_t register_DBGDIDR; 711 712 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 713 uint32_t numWRPs = bits(register_DBGDIDR, 31, 28); 714 // Zero is reserved for the WRP count, so don't increment it if it is zero 715 if (numWRPs > 0) 716 numWRPs++; 717 g_num_supported_hw_breakpoints = numWRPs; 718 DNBLogThreadedIf(LOG_THREAD, 719 "Number of supported hw breakpoint via asm(): %d", 720 g_num_supported_hw_breakpoints); 721 #endif 722 } 723 } 724 return g_num_supported_hw_breakpoints; 725 } 726 727 uint32_t DNBArchMachARM64::EnableHardwareBreakpoint(nub_addr_t addr, 728 nub_size_t size, 729 bool also_set_on_task) { 730 DNBLogThreadedIf(LOG_WATCHPOINTS, 731 "DNBArchMachARM64::EnableHardwareBreakpoint(addr = " 732 "0x%8.8llx, size = %zu)", 733 (uint64_t)addr, size); 734 735 const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints(); 736 737 nub_addr_t aligned_bp_address = addr; 738 uint32_t control_value = 0; 739 740 switch (size) { 741 case 2: 742 control_value = (0x3 << 5) | 7; 743 aligned_bp_address &= ~1; 744 break; 745 case 4: 746 control_value = (0xfu << 5) | 7; 747 aligned_bp_address &= ~3; 748 break; 749 }; 750 751 // Read the debug state 752 kern_return_t kret = GetDBGState(false); 753 if (kret == KERN_SUCCESS) { 754 // Check to make sure we have the needed hardware support 755 uint32_t i = 0; 756 757 for (i = 0; i < num_hw_breakpoints; ++i) { 758 if ((m_state.dbg.__bcr[i] & BCR_ENABLE) == 0) 759 break; // We found an available hw breakpoint slot (in i) 760 } 761 762 // See if we found an available hw breakpoint slot above 763 if (i < num_hw_breakpoints) { 764 m_state.dbg.__bvr[i] = aligned_bp_address; 765 m_state.dbg.__bcr[i] = control_value; 766 767 DNBLogThreadedIf(LOG_WATCHPOINTS, 768 "DNBArchMachARM64::EnableHardwareBreakpoint() " 769 "adding breakpoint on address 0x%llx with control " 770 "register value 0x%x", 771 (uint64_t)m_state.dbg.__bvr[i], 772 (uint32_t)m_state.dbg.__bcr[i]); 773 774 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 775 // automatically, don't need to do it here. 776 kret = SetDBGState(also_set_on_task); 777 778 DNBLogThreadedIf(LOG_WATCHPOINTS, 779 "DNBArchMachARM64::" 780 "EnableHardwareBreakpoint() " 781 "SetDBGState() => 0x%8.8x.", 782 kret); 783 784 if (kret == KERN_SUCCESS) 785 return i; 786 } else { 787 DNBLogThreadedIf(LOG_WATCHPOINTS, 788 "DNBArchMachARM64::" 789 "EnableHardwareBreakpoint(): All " 790 "hardware resources (%u) are in use.", 791 num_hw_breakpoints); 792 } 793 } 794 return INVALID_NUB_HW_INDEX; 795 } 796 797 uint32_t DNBArchMachARM64::EnableHardwareWatchpoint(nub_addr_t addr, 798 nub_size_t size, bool read, 799 bool write, 800 bool also_set_on_task) { 801 DNBLogThreadedIf(LOG_WATCHPOINTS, 802 "DNBArchMachARM64::EnableHardwareWatchpoint(addr = " 803 "0x%8.8llx, size = %zu, read = %u, write = %u)", 804 (uint64_t)addr, size, read, write); 805 806 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 807 808 // Can't watch zero bytes 809 if (size == 0) 810 return INVALID_NUB_HW_INDEX; 811 812 // We must watch for either read or write 813 if (read == false && write == false) 814 return INVALID_NUB_HW_INDEX; 815 816 // Otherwise, can't watch more than 8 bytes per WVR/WCR pair 817 if (size > 8) 818 return INVALID_NUB_HW_INDEX; 819 820 // Aarch64 watchpoints are in one of two forms: (1) 1-8 bytes, aligned to 821 // an 8 byte address, or (2) a power-of-two size region of memory; minimum 822 // 8 bytes, maximum 2GB; the starting address must be aligned to that power 823 // of two. 824 // 825 // For (1), 1-8 byte watchpoints, using the Byte Address Selector field in 826 // DBGWCR<n>.BAS. Any of the bytes may be watched, but if multiple bytes 827 // are watched, the bytes selected must be contiguous. The start address 828 // watched must be doubleword (8-byte) aligned; if the start address is 829 // word (4-byte) aligned, only 4 bytes can be watched. 830 // 831 // For (2), the MASK field in DBGWCR<n>.MASK is used. 832 // 833 // See the ARM ARM, section "Watchpoint exceptions", and more specifically, 834 // "Watchpoint data address comparisons". 835 // 836 // debugserver today only supports (1) - the Byte Address Selector 1-8 byte 837 // watchpoints that are 8-byte aligned. To support larger watchpoints, 838 // debugserver would need to interpret the mach exception when the watched 839 // region was hit, see if the address accessed lies within the subset 840 // of the power-of-two region that lldb asked us to watch (v. ARM ARM, 841 // "Determining the memory location that caused a Watchpoint exception"), 842 // and silently resume the inferior (disable watchpoint, stepi, re-enable 843 // watchpoint) if the address lies outside the region that lldb asked us 844 // to watch. 845 // 846 // Alternatively, lldb would need to be prepared for a larger region 847 // being watched than it requested, and silently resume the inferior if 848 // the accessed address is outside the region lldb wants to watch. 849 850 nub_addr_t aligned_wp_address = addr & ~0x7; 851 uint32_t addr_dword_offset = addr & 0x7; 852 853 // Do we need to split up this logical watchpoint into two hardware watchpoint 854 // registers? 855 // e.g. a watchpoint of length 4 on address 6. We need do this with 856 // one watchpoint on address 0 with bytes 6 & 7 being monitored 857 // one watchpoint on address 8 with bytes 0, 1, 2, 3 being monitored 858 859 if (addr_dword_offset + size > 8) { 860 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 861 "EnableHardwareWatchpoint(addr = " 862 "0x%8.8llx, size = %zu) needs two " 863 "hardware watchpoints slots to monitor", 864 (uint64_t)addr, size); 865 int low_watchpoint_size = 8 - addr_dword_offset; 866 int high_watchpoint_size = addr_dword_offset + size - 8; 867 868 uint32_t lo = EnableHardwareWatchpoint(addr, low_watchpoint_size, read, 869 write, also_set_on_task); 870 if (lo == INVALID_NUB_HW_INDEX) 871 return INVALID_NUB_HW_INDEX; 872 uint32_t hi = 873 EnableHardwareWatchpoint(aligned_wp_address + 8, high_watchpoint_size, 874 read, write, also_set_on_task); 875 if (hi == INVALID_NUB_HW_INDEX) { 876 DisableHardwareWatchpoint(lo, also_set_on_task); 877 return INVALID_NUB_HW_INDEX; 878 } 879 // Tag this lo->hi mapping in our database. 880 LoHi[lo] = hi; 881 return lo; 882 } 883 884 // At this point 885 // 1 aligned_wp_address is the requested address rounded down to 8-byte 886 // alignment 887 // 2 addr_dword_offset is the offset into that double word (8-byte) region 888 // that we are watching 889 // 3 size is the number of bytes within that 8-byte region that we are 890 // watching 891 892 // Set the Byte Address Selects bits DBGWCRn_EL1 bits [12:5] based on the 893 // above. 894 // The bit shift and negation operation will give us 0b11 for 2, 0b1111 for 4, 895 // etc, up to 0b11111111 for 8. 896 // then we shift those bits left by the offset into this dword that we are 897 // interested in. 898 // e.g. if we are watching bytes 4,5,6,7 in a dword we want a BAS of 899 // 0b11110000. 900 uint32_t byte_address_select = ((1 << size) - 1) << addr_dword_offset; 901 902 // Read the debug state 903 kern_return_t kret = GetDBGState(false); 904 905 if (kret == KERN_SUCCESS) { 906 // Check to make sure we have the needed hardware support 907 uint32_t i = 0; 908 909 for (i = 0; i < num_hw_watchpoints; ++i) { 910 if ((m_state.dbg.__wcr[i] & WCR_ENABLE) == 0) 911 break; // We found an available hw watchpoint slot (in i) 912 } 913 914 // See if we found an available hw watchpoint slot above 915 if (i < num_hw_watchpoints) { 916 // DumpDBGState(m_state.dbg); 917 918 // Clear any previous LoHi joined-watchpoint that may have been in use 919 LoHi[i] = 0; 920 921 // shift our Byte Address Select bits up to the correct bit range for the 922 // DBGWCRn_EL1 923 byte_address_select = byte_address_select << 5; 924 925 // Make sure bits 1:0 are clear in our address 926 m_state.dbg.__wvr[i] = aligned_wp_address; // DVA (Data Virtual Address) 927 m_state.dbg.__wcr[i] = byte_address_select | // Which bytes that follow 928 // the DVA that we will watch 929 S_USER | // Stop only in user mode 930 (read ? WCR_LOAD : 0) | // Stop on read access? 931 (write ? WCR_STORE : 0) | // Stop on write access? 932 WCR_ENABLE; // Enable this watchpoint; 933 934 DNBLogThreadedIf( 935 LOG_WATCHPOINTS, "DNBArchMachARM64::EnableHardwareWatchpoint() " 936 "adding watchpoint on address 0x%llx with control " 937 "register value 0x%x", 938 (uint64_t)m_state.dbg.__wvr[i], (uint32_t)m_state.dbg.__wcr[i]); 939 940 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 941 // automatically, don't need to do it here. 942 943 kret = SetDBGState(also_set_on_task); 944 // DumpDBGState(m_state.dbg); 945 946 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 947 "EnableHardwareWatchpoint() " 948 "SetDBGState() => 0x%8.8x.", 949 kret); 950 951 if (kret == KERN_SUCCESS) 952 return i; 953 } else { 954 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 955 "EnableHardwareWatchpoint(): All " 956 "hardware resources (%u) are in use.", 957 num_hw_watchpoints); 958 } 959 } 960 return INVALID_NUB_HW_INDEX; 961 } 962 963 bool DNBArchMachARM64::ReenableHardwareWatchpoint(uint32_t hw_index) { 964 // If this logical watchpoint # is actually implemented using 965 // two hardware watchpoint registers, re-enable both of them. 966 967 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 968 return ReenableHardwareWatchpoint_helper(hw_index) && 969 ReenableHardwareWatchpoint_helper(LoHi[hw_index]); 970 } else { 971 return ReenableHardwareWatchpoint_helper(hw_index); 972 } 973 } 974 975 bool DNBArchMachARM64::ReenableHardwareWatchpoint_helper(uint32_t hw_index) { 976 kern_return_t kret = GetDBGState(false); 977 if (kret != KERN_SUCCESS) 978 return false; 979 980 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 981 if (hw_index >= num_hw_points) 982 return false; 983 984 m_state.dbg.__wvr[hw_index] = m_disabled_watchpoints[hw_index].addr; 985 m_state.dbg.__wcr[hw_index] = m_disabled_watchpoints[hw_index].control; 986 987 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 988 "EnableHardwareWatchpoint( %u ) - WVR%u = " 989 "0x%8.8llx WCR%u = 0x%8.8llx", 990 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 991 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 992 993 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 994 // automatically, don't need to do it here. 995 996 kret = SetDBGState(false); 997 998 return (kret == KERN_SUCCESS); 999 } 1000 1001 bool DNBArchMachARM64::DisableHardwareWatchpoint(uint32_t hw_index, 1002 bool also_set_on_task) { 1003 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 1004 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task) && 1005 DisableHardwareWatchpoint_helper(LoHi[hw_index], also_set_on_task); 1006 } else { 1007 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task); 1008 } 1009 } 1010 1011 bool DNBArchMachARM64::DisableHardwareWatchpoint_helper(uint32_t hw_index, 1012 bool also_set_on_task) { 1013 kern_return_t kret = GetDBGState(false); 1014 if (kret != KERN_SUCCESS) 1015 return false; 1016 1017 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 1018 if (hw_index >= num_hw_points) 1019 return false; 1020 1021 m_disabled_watchpoints[hw_index].addr = m_state.dbg.__wvr[hw_index]; 1022 m_disabled_watchpoints[hw_index].control = m_state.dbg.__wcr[hw_index]; 1023 1024 m_state.dbg.__wcr[hw_index] &= ~((nub_addr_t)WCR_ENABLE); 1025 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 1026 "DisableHardwareWatchpoint( %u ) - WVR%u = " 1027 "0x%8.8llx WCR%u = 0x%8.8llx", 1028 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 1029 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 1030 1031 kret = SetDBGState(also_set_on_task); 1032 1033 return (kret == KERN_SUCCESS); 1034 } 1035 1036 bool DNBArchMachARM64::DisableHardwareBreakpoint(uint32_t hw_index, 1037 bool also_set_on_task) { 1038 kern_return_t kret = GetDBGState(false); 1039 if (kret != KERN_SUCCESS) 1040 return false; 1041 1042 const uint32_t num_hw_points = NumSupportedHardwareBreakpoints(); 1043 if (hw_index >= num_hw_points) 1044 return false; 1045 1046 m_disabled_breakpoints[hw_index].addr = m_state.dbg.__bvr[hw_index]; 1047 m_disabled_breakpoints[hw_index].control = m_state.dbg.__bcr[hw_index]; 1048 1049 m_state.dbg.__bcr[hw_index] = 0; 1050 DNBLogThreadedIf(LOG_WATCHPOINTS, 1051 "DNBArchMachARM64::" 1052 "DisableHardwareBreakpoint( %u ) - WVR%u = " 1053 "0x%8.8llx BCR%u = 0x%8.8llx", 1054 hw_index, hw_index, (uint64_t)m_state.dbg.__bvr[hw_index], 1055 hw_index, (uint64_t)m_state.dbg.__bcr[hw_index]); 1056 1057 kret = SetDBGState(also_set_on_task); 1058 1059 return (kret == KERN_SUCCESS); 1060 } 1061 1062 // This is for checking the Byte Address Select bits in the DBRWCRn_EL1 control 1063 // register. 1064 // Returns -1 if the trailing bit patterns are not one of: 1065 // { 0b???????1, 0b??????10, 0b?????100, 0b????1000, 0b???10000, 0b??100000, 1066 // 0b?1000000, 0b10000000 }. 1067 static inline int32_t LowestBitSet(uint32_t val) { 1068 for (unsigned i = 0; i < 8; ++i) { 1069 if (bit(val, i)) 1070 return i; 1071 } 1072 return -1; 1073 } 1074 1075 // Iterate through the debug registers; return the index of the first watchpoint 1076 // whose address matches. 1077 // As a side effect, the starting address as understood by the debugger is 1078 // returned which could be 1079 // different from 'addr' passed as an in/out argument. 1080 uint32_t DNBArchMachARM64::GetHardwareWatchpointHit(nub_addr_t &addr) { 1081 // Read the debug state 1082 kern_return_t kret = GetDBGState(true); 1083 // DumpDBGState(m_state.dbg); 1084 DNBLogThreadedIf( 1085 LOG_WATCHPOINTS, 1086 "DNBArchMachARM64::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", 1087 kret); 1088 DNBLogThreadedIf(LOG_WATCHPOINTS, 1089 "DNBArchMachARM64::GetHardwareWatchpointHit() addr = 0x%llx", 1090 (uint64_t)addr); 1091 1092 if (kret == KERN_SUCCESS) { 1093 DBG &debug_state = m_state.dbg; 1094 uint32_t i, num = NumSupportedHardwareWatchpoints(); 1095 for (i = 0; i < num; ++i) { 1096 nub_addr_t wp_addr = GetWatchAddress(debug_state, i); 1097 uint32_t byte_mask = bits(debug_state.__wcr[i], 12, 5); 1098 1099 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::" 1100 "GetHardwareWatchpointHit() slot: %u " 1101 "(addr = 0x%llx; byte_mask = 0x%x)", 1102 i, static_cast<uint64_t>(wp_addr), 1103 byte_mask); 1104 1105 if (!IsWatchpointEnabled(debug_state, i)) 1106 continue; 1107 1108 if (bits(wp_addr, 48, 3) != bits(addr, 48, 3)) 1109 continue; 1110 1111 // Sanity check the byte_mask 1112 uint32_t lsb = LowestBitSet(byte_mask); 1113 if (lsb < 0) 1114 continue; 1115 1116 uint64_t byte_to_match = bits(addr, 2, 0); 1117 1118 if (byte_mask & (1 << byte_to_match)) { 1119 addr = wp_addr + lsb; 1120 return i; 1121 } 1122 } 1123 } 1124 return INVALID_NUB_HW_INDEX; 1125 } 1126 1127 nub_addr_t DNBArchMachARM64::GetWatchpointAddressByIndex(uint32_t hw_index) { 1128 kern_return_t kret = GetDBGState(true); 1129 if (kret != KERN_SUCCESS) 1130 return INVALID_NUB_ADDRESS; 1131 const uint32_t num = NumSupportedHardwareWatchpoints(); 1132 if (hw_index >= num) 1133 return INVALID_NUB_ADDRESS; 1134 if (IsWatchpointEnabled(m_state.dbg, hw_index)) 1135 return GetWatchAddress(m_state.dbg, hw_index); 1136 return INVALID_NUB_ADDRESS; 1137 } 1138 1139 bool DNBArchMachARM64::IsWatchpointEnabled(const DBG &debug_state, 1140 uint32_t hw_index) { 1141 // Watchpoint Control Registers, bitfield definitions 1142 // ... 1143 // Bits Value Description 1144 // [0] 0 Watchpoint disabled 1145 // 1 Watchpoint enabled. 1146 return (debug_state.__wcr[hw_index] & 1u); 1147 } 1148 1149 nub_addr_t DNBArchMachARM64::GetWatchAddress(const DBG &debug_state, 1150 uint32_t hw_index) { 1151 // Watchpoint Value Registers, bitfield definitions 1152 // Bits Description 1153 // [31:2] Watchpoint value (word address, i.e., 4-byte aligned) 1154 // [1:0] RAZ/SBZP 1155 return bits(debug_state.__wvr[hw_index], 63, 0); 1156 } 1157 1158 // Register information definitions for 64 bit ARMv8. 1159 enum gpr_regnums { 1160 gpr_x0 = 0, 1161 gpr_x1, 1162 gpr_x2, 1163 gpr_x3, 1164 gpr_x4, 1165 gpr_x5, 1166 gpr_x6, 1167 gpr_x7, 1168 gpr_x8, 1169 gpr_x9, 1170 gpr_x10, 1171 gpr_x11, 1172 gpr_x12, 1173 gpr_x13, 1174 gpr_x14, 1175 gpr_x15, 1176 gpr_x16, 1177 gpr_x17, 1178 gpr_x18, 1179 gpr_x19, 1180 gpr_x20, 1181 gpr_x21, 1182 gpr_x22, 1183 gpr_x23, 1184 gpr_x24, 1185 gpr_x25, 1186 gpr_x26, 1187 gpr_x27, 1188 gpr_x28, 1189 gpr_fp, 1190 gpr_x29 = gpr_fp, 1191 gpr_lr, 1192 gpr_x30 = gpr_lr, 1193 gpr_sp, 1194 gpr_x31 = gpr_sp, 1195 gpr_pc, 1196 gpr_cpsr, 1197 gpr_w0, 1198 gpr_w1, 1199 gpr_w2, 1200 gpr_w3, 1201 gpr_w4, 1202 gpr_w5, 1203 gpr_w6, 1204 gpr_w7, 1205 gpr_w8, 1206 gpr_w9, 1207 gpr_w10, 1208 gpr_w11, 1209 gpr_w12, 1210 gpr_w13, 1211 gpr_w14, 1212 gpr_w15, 1213 gpr_w16, 1214 gpr_w17, 1215 gpr_w18, 1216 gpr_w19, 1217 gpr_w20, 1218 gpr_w21, 1219 gpr_w22, 1220 gpr_w23, 1221 gpr_w24, 1222 gpr_w25, 1223 gpr_w26, 1224 gpr_w27, 1225 gpr_w28 1226 1227 }; 1228 1229 enum { 1230 vfp_v0 = 0, 1231 vfp_v1, 1232 vfp_v2, 1233 vfp_v3, 1234 vfp_v4, 1235 vfp_v5, 1236 vfp_v6, 1237 vfp_v7, 1238 vfp_v8, 1239 vfp_v9, 1240 vfp_v10, 1241 vfp_v11, 1242 vfp_v12, 1243 vfp_v13, 1244 vfp_v14, 1245 vfp_v15, 1246 vfp_v16, 1247 vfp_v17, 1248 vfp_v18, 1249 vfp_v19, 1250 vfp_v20, 1251 vfp_v21, 1252 vfp_v22, 1253 vfp_v23, 1254 vfp_v24, 1255 vfp_v25, 1256 vfp_v26, 1257 vfp_v27, 1258 vfp_v28, 1259 vfp_v29, 1260 vfp_v30, 1261 vfp_v31, 1262 vfp_fpsr, 1263 vfp_fpcr, 1264 1265 // lower 32 bits of the corresponding vfp_v<n> reg. 1266 vfp_s0, 1267 vfp_s1, 1268 vfp_s2, 1269 vfp_s3, 1270 vfp_s4, 1271 vfp_s5, 1272 vfp_s6, 1273 vfp_s7, 1274 vfp_s8, 1275 vfp_s9, 1276 vfp_s10, 1277 vfp_s11, 1278 vfp_s12, 1279 vfp_s13, 1280 vfp_s14, 1281 vfp_s15, 1282 vfp_s16, 1283 vfp_s17, 1284 vfp_s18, 1285 vfp_s19, 1286 vfp_s20, 1287 vfp_s21, 1288 vfp_s22, 1289 vfp_s23, 1290 vfp_s24, 1291 vfp_s25, 1292 vfp_s26, 1293 vfp_s27, 1294 vfp_s28, 1295 vfp_s29, 1296 vfp_s30, 1297 vfp_s31, 1298 1299 // lower 64 bits of the corresponding vfp_v<n> reg. 1300 vfp_d0, 1301 vfp_d1, 1302 vfp_d2, 1303 vfp_d3, 1304 vfp_d4, 1305 vfp_d5, 1306 vfp_d6, 1307 vfp_d7, 1308 vfp_d8, 1309 vfp_d9, 1310 vfp_d10, 1311 vfp_d11, 1312 vfp_d12, 1313 vfp_d13, 1314 vfp_d14, 1315 vfp_d15, 1316 vfp_d16, 1317 vfp_d17, 1318 vfp_d18, 1319 vfp_d19, 1320 vfp_d20, 1321 vfp_d21, 1322 vfp_d22, 1323 vfp_d23, 1324 vfp_d24, 1325 vfp_d25, 1326 vfp_d26, 1327 vfp_d27, 1328 vfp_d28, 1329 vfp_d29, 1330 vfp_d30, 1331 vfp_d31 1332 }; 1333 1334 enum { exc_far = 0, exc_esr, exc_exception }; 1335 1336 // These numbers from the "DWARF for the ARM 64-bit Architecture (AArch64)" 1337 // document. 1338 1339 enum { 1340 dwarf_x0 = 0, 1341 dwarf_x1, 1342 dwarf_x2, 1343 dwarf_x3, 1344 dwarf_x4, 1345 dwarf_x5, 1346 dwarf_x6, 1347 dwarf_x7, 1348 dwarf_x8, 1349 dwarf_x9, 1350 dwarf_x10, 1351 dwarf_x11, 1352 dwarf_x12, 1353 dwarf_x13, 1354 dwarf_x14, 1355 dwarf_x15, 1356 dwarf_x16, 1357 dwarf_x17, 1358 dwarf_x18, 1359 dwarf_x19, 1360 dwarf_x20, 1361 dwarf_x21, 1362 dwarf_x22, 1363 dwarf_x23, 1364 dwarf_x24, 1365 dwarf_x25, 1366 dwarf_x26, 1367 dwarf_x27, 1368 dwarf_x28, 1369 dwarf_x29, 1370 dwarf_x30, 1371 dwarf_x31, 1372 dwarf_pc = 32, 1373 dwarf_elr_mode = 33, 1374 dwarf_fp = dwarf_x29, 1375 dwarf_lr = dwarf_x30, 1376 dwarf_sp = dwarf_x31, 1377 // 34-63 reserved 1378 1379 // V0-V31 (128 bit vector registers) 1380 dwarf_v0 = 64, 1381 dwarf_v1, 1382 dwarf_v2, 1383 dwarf_v3, 1384 dwarf_v4, 1385 dwarf_v5, 1386 dwarf_v6, 1387 dwarf_v7, 1388 dwarf_v8, 1389 dwarf_v9, 1390 dwarf_v10, 1391 dwarf_v11, 1392 dwarf_v12, 1393 dwarf_v13, 1394 dwarf_v14, 1395 dwarf_v15, 1396 dwarf_v16, 1397 dwarf_v17, 1398 dwarf_v18, 1399 dwarf_v19, 1400 dwarf_v20, 1401 dwarf_v21, 1402 dwarf_v22, 1403 dwarf_v23, 1404 dwarf_v24, 1405 dwarf_v25, 1406 dwarf_v26, 1407 dwarf_v27, 1408 dwarf_v28, 1409 dwarf_v29, 1410 dwarf_v30, 1411 dwarf_v31 1412 1413 // 96-127 reserved 1414 }; 1415 1416 enum { 1417 debugserver_gpr_x0 = 0, 1418 debugserver_gpr_x1, 1419 debugserver_gpr_x2, 1420 debugserver_gpr_x3, 1421 debugserver_gpr_x4, 1422 debugserver_gpr_x5, 1423 debugserver_gpr_x6, 1424 debugserver_gpr_x7, 1425 debugserver_gpr_x8, 1426 debugserver_gpr_x9, 1427 debugserver_gpr_x10, 1428 debugserver_gpr_x11, 1429 debugserver_gpr_x12, 1430 debugserver_gpr_x13, 1431 debugserver_gpr_x14, 1432 debugserver_gpr_x15, 1433 debugserver_gpr_x16, 1434 debugserver_gpr_x17, 1435 debugserver_gpr_x18, 1436 debugserver_gpr_x19, 1437 debugserver_gpr_x20, 1438 debugserver_gpr_x21, 1439 debugserver_gpr_x22, 1440 debugserver_gpr_x23, 1441 debugserver_gpr_x24, 1442 debugserver_gpr_x25, 1443 debugserver_gpr_x26, 1444 debugserver_gpr_x27, 1445 debugserver_gpr_x28, 1446 debugserver_gpr_fp, // x29 1447 debugserver_gpr_lr, // x30 1448 debugserver_gpr_sp, // sp aka xsp 1449 debugserver_gpr_pc, 1450 debugserver_gpr_cpsr, 1451 debugserver_vfp_v0, 1452 debugserver_vfp_v1, 1453 debugserver_vfp_v2, 1454 debugserver_vfp_v3, 1455 debugserver_vfp_v4, 1456 debugserver_vfp_v5, 1457 debugserver_vfp_v6, 1458 debugserver_vfp_v7, 1459 debugserver_vfp_v8, 1460 debugserver_vfp_v9, 1461 debugserver_vfp_v10, 1462 debugserver_vfp_v11, 1463 debugserver_vfp_v12, 1464 debugserver_vfp_v13, 1465 debugserver_vfp_v14, 1466 debugserver_vfp_v15, 1467 debugserver_vfp_v16, 1468 debugserver_vfp_v17, 1469 debugserver_vfp_v18, 1470 debugserver_vfp_v19, 1471 debugserver_vfp_v20, 1472 debugserver_vfp_v21, 1473 debugserver_vfp_v22, 1474 debugserver_vfp_v23, 1475 debugserver_vfp_v24, 1476 debugserver_vfp_v25, 1477 debugserver_vfp_v26, 1478 debugserver_vfp_v27, 1479 debugserver_vfp_v28, 1480 debugserver_vfp_v29, 1481 debugserver_vfp_v30, 1482 debugserver_vfp_v31, 1483 debugserver_vfp_fpsr, 1484 debugserver_vfp_fpcr 1485 }; 1486 1487 const char *g_contained_x0[]{"x0", NULL}; 1488 const char *g_contained_x1[]{"x1", NULL}; 1489 const char *g_contained_x2[]{"x2", NULL}; 1490 const char *g_contained_x3[]{"x3", NULL}; 1491 const char *g_contained_x4[]{"x4", NULL}; 1492 const char *g_contained_x5[]{"x5", NULL}; 1493 const char *g_contained_x6[]{"x6", NULL}; 1494 const char *g_contained_x7[]{"x7", NULL}; 1495 const char *g_contained_x8[]{"x8", NULL}; 1496 const char *g_contained_x9[]{"x9", NULL}; 1497 const char *g_contained_x10[]{"x10", NULL}; 1498 const char *g_contained_x11[]{"x11", NULL}; 1499 const char *g_contained_x12[]{"x12", NULL}; 1500 const char *g_contained_x13[]{"x13", NULL}; 1501 const char *g_contained_x14[]{"x14", NULL}; 1502 const char *g_contained_x15[]{"x15", NULL}; 1503 const char *g_contained_x16[]{"x16", NULL}; 1504 const char *g_contained_x17[]{"x17", NULL}; 1505 const char *g_contained_x18[]{"x18", NULL}; 1506 const char *g_contained_x19[]{"x19", NULL}; 1507 const char *g_contained_x20[]{"x20", NULL}; 1508 const char *g_contained_x21[]{"x21", NULL}; 1509 const char *g_contained_x22[]{"x22", NULL}; 1510 const char *g_contained_x23[]{"x23", NULL}; 1511 const char *g_contained_x24[]{"x24", NULL}; 1512 const char *g_contained_x25[]{"x25", NULL}; 1513 const char *g_contained_x26[]{"x26", NULL}; 1514 const char *g_contained_x27[]{"x27", NULL}; 1515 const char *g_contained_x28[]{"x28", NULL}; 1516 1517 const char *g_invalidate_x0[]{"x0", "w0", NULL}; 1518 const char *g_invalidate_x1[]{"x1", "w1", NULL}; 1519 const char *g_invalidate_x2[]{"x2", "w2", NULL}; 1520 const char *g_invalidate_x3[]{"x3", "w3", NULL}; 1521 const char *g_invalidate_x4[]{"x4", "w4", NULL}; 1522 const char *g_invalidate_x5[]{"x5", "w5", NULL}; 1523 const char *g_invalidate_x6[]{"x6", "w6", NULL}; 1524 const char *g_invalidate_x7[]{"x7", "w7", NULL}; 1525 const char *g_invalidate_x8[]{"x8", "w8", NULL}; 1526 const char *g_invalidate_x9[]{"x9", "w9", NULL}; 1527 const char *g_invalidate_x10[]{"x10", "w10", NULL}; 1528 const char *g_invalidate_x11[]{"x11", "w11", NULL}; 1529 const char *g_invalidate_x12[]{"x12", "w12", NULL}; 1530 const char *g_invalidate_x13[]{"x13", "w13", NULL}; 1531 const char *g_invalidate_x14[]{"x14", "w14", NULL}; 1532 const char *g_invalidate_x15[]{"x15", "w15", NULL}; 1533 const char *g_invalidate_x16[]{"x16", "w16", NULL}; 1534 const char *g_invalidate_x17[]{"x17", "w17", NULL}; 1535 const char *g_invalidate_x18[]{"x18", "w18", NULL}; 1536 const char *g_invalidate_x19[]{"x19", "w19", NULL}; 1537 const char *g_invalidate_x20[]{"x20", "w20", NULL}; 1538 const char *g_invalidate_x21[]{"x21", "w21", NULL}; 1539 const char *g_invalidate_x22[]{"x22", "w22", NULL}; 1540 const char *g_invalidate_x23[]{"x23", "w23", NULL}; 1541 const char *g_invalidate_x24[]{"x24", "w24", NULL}; 1542 const char *g_invalidate_x25[]{"x25", "w25", NULL}; 1543 const char *g_invalidate_x26[]{"x26", "w26", NULL}; 1544 const char *g_invalidate_x27[]{"x27", "w27", NULL}; 1545 const char *g_invalidate_x28[]{"x28", "w28", NULL}; 1546 1547 #define GPR_OFFSET_IDX(idx) (offsetof(DNBArchMachARM64::GPR, __x[idx])) 1548 1549 #define GPR_OFFSET_NAME(reg) (offsetof(DNBArchMachARM64::GPR, __##reg)) 1550 1551 // These macros will auto define the register name, alt name, register size, 1552 // register offset, encoding, format and native register. This ensures that 1553 // the register state structures are defined correctly and have the correct 1554 // sizes and offsets. 1555 #define DEFINE_GPR_IDX(idx, reg, alt, gen) \ 1556 { \ 1557 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_IDX(idx), \ 1558 dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, \ 1559 g_invalidate_x##idx \ 1560 } 1561 #define DEFINE_GPR_NAME(reg, alt, gen) \ 1562 { \ 1563 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_NAME(reg), \ 1564 dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, NULL \ 1565 } 1566 #define DEFINE_PSEUDO_GPR_IDX(idx, reg) \ 1567 { \ 1568 e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, 4, 0, INVALID_NUB_REGNUM, \ 1569 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1570 g_contained_x##idx, g_invalidate_x##idx \ 1571 } 1572 1573 //_STRUCT_ARM_THREAD_STATE64 1574 //{ 1575 // uint64_t x[29]; /* General purpose registers x0-x28 */ 1576 // uint64_t fp; /* Frame pointer x29 */ 1577 // uint64_t lr; /* Link register x30 */ 1578 // uint64_t sp; /* Stack pointer x31 */ 1579 // uint64_t pc; /* Program counter */ 1580 // uint32_t cpsr; /* Current program status register */ 1581 //}; 1582 1583 // General purpose registers 1584 const DNBRegisterInfo DNBArchMachARM64::g_gpr_registers[] = { 1585 DEFINE_GPR_IDX(0, x0, "arg1", GENERIC_REGNUM_ARG1), 1586 DEFINE_GPR_IDX(1, x1, "arg2", GENERIC_REGNUM_ARG2), 1587 DEFINE_GPR_IDX(2, x2, "arg3", GENERIC_REGNUM_ARG3), 1588 DEFINE_GPR_IDX(3, x3, "arg4", GENERIC_REGNUM_ARG4), 1589 DEFINE_GPR_IDX(4, x4, "arg5", GENERIC_REGNUM_ARG5), 1590 DEFINE_GPR_IDX(5, x5, "arg6", GENERIC_REGNUM_ARG6), 1591 DEFINE_GPR_IDX(6, x6, "arg7", GENERIC_REGNUM_ARG7), 1592 DEFINE_GPR_IDX(7, x7, "arg8", GENERIC_REGNUM_ARG8), 1593 DEFINE_GPR_IDX(8, x8, NULL, INVALID_NUB_REGNUM), 1594 DEFINE_GPR_IDX(9, x9, NULL, INVALID_NUB_REGNUM), 1595 DEFINE_GPR_IDX(10, x10, NULL, INVALID_NUB_REGNUM), 1596 DEFINE_GPR_IDX(11, x11, NULL, INVALID_NUB_REGNUM), 1597 DEFINE_GPR_IDX(12, x12, NULL, INVALID_NUB_REGNUM), 1598 DEFINE_GPR_IDX(13, x13, NULL, INVALID_NUB_REGNUM), 1599 DEFINE_GPR_IDX(14, x14, NULL, INVALID_NUB_REGNUM), 1600 DEFINE_GPR_IDX(15, x15, NULL, INVALID_NUB_REGNUM), 1601 DEFINE_GPR_IDX(16, x16, NULL, INVALID_NUB_REGNUM), 1602 DEFINE_GPR_IDX(17, x17, NULL, INVALID_NUB_REGNUM), 1603 DEFINE_GPR_IDX(18, x18, NULL, INVALID_NUB_REGNUM), 1604 DEFINE_GPR_IDX(19, x19, NULL, INVALID_NUB_REGNUM), 1605 DEFINE_GPR_IDX(20, x20, NULL, INVALID_NUB_REGNUM), 1606 DEFINE_GPR_IDX(21, x21, NULL, INVALID_NUB_REGNUM), 1607 DEFINE_GPR_IDX(22, x22, NULL, INVALID_NUB_REGNUM), 1608 DEFINE_GPR_IDX(23, x23, NULL, INVALID_NUB_REGNUM), 1609 DEFINE_GPR_IDX(24, x24, NULL, INVALID_NUB_REGNUM), 1610 DEFINE_GPR_IDX(25, x25, NULL, INVALID_NUB_REGNUM), 1611 DEFINE_GPR_IDX(26, x26, NULL, INVALID_NUB_REGNUM), 1612 DEFINE_GPR_IDX(27, x27, NULL, INVALID_NUB_REGNUM), 1613 DEFINE_GPR_IDX(28, x28, NULL, INVALID_NUB_REGNUM), 1614 // For the G/g packet we want to show where the offset into the regctx 1615 // is for fp/lr/sp/pc, but we cannot directly access them on arm64e 1616 // devices (and therefore can't offsetof() them)) - add the offset based 1617 // on the last accessible register by hand for advertising the location 1618 // in the regctx to lldb. We'll go through the accessor functions when 1619 // we read/write them here. 1620 { 1621 e_regSetGPR, gpr_fp, "fp", "x29", Uint, Hex, 8, GPR_OFFSET_IDX(28) + 8, 1622 dwarf_fp, dwarf_fp, GENERIC_REGNUM_FP, debugserver_gpr_fp, NULL, NULL 1623 }, 1624 { 1625 e_regSetGPR, gpr_lr, "lr", "x30", Uint, Hex, 8, GPR_OFFSET_IDX(28) + 16, 1626 dwarf_lr, dwarf_lr, GENERIC_REGNUM_RA, debugserver_gpr_lr, NULL, NULL 1627 }, 1628 { 1629 e_regSetGPR, gpr_sp, "sp", "xsp", Uint, Hex, 8, GPR_OFFSET_IDX(28) + 24, 1630 dwarf_sp, dwarf_sp, GENERIC_REGNUM_SP, debugserver_gpr_sp, NULL, NULL 1631 }, 1632 { 1633 e_regSetGPR, gpr_pc, "pc", NULL, Uint, Hex, 8, GPR_OFFSET_IDX(28) + 32, 1634 dwarf_pc, dwarf_pc, GENERIC_REGNUM_PC, debugserver_gpr_pc, NULL, NULL 1635 }, 1636 1637 // in armv7 we specify that writing to the CPSR should invalidate r8-12, sp, 1638 // lr. 1639 // this should be specified for arm64 too even though debugserver is only 1640 // used for 1641 // userland debugging. 1642 {e_regSetGPR, gpr_cpsr, "cpsr", "flags", Uint, Hex, 4, 1643 GPR_OFFSET_NAME(cpsr), dwarf_elr_mode, dwarf_elr_mode, INVALID_NUB_REGNUM, 1644 debugserver_gpr_cpsr, NULL, NULL}, 1645 1646 DEFINE_PSEUDO_GPR_IDX(0, w0), 1647 DEFINE_PSEUDO_GPR_IDX(1, w1), 1648 DEFINE_PSEUDO_GPR_IDX(2, w2), 1649 DEFINE_PSEUDO_GPR_IDX(3, w3), 1650 DEFINE_PSEUDO_GPR_IDX(4, w4), 1651 DEFINE_PSEUDO_GPR_IDX(5, w5), 1652 DEFINE_PSEUDO_GPR_IDX(6, w6), 1653 DEFINE_PSEUDO_GPR_IDX(7, w7), 1654 DEFINE_PSEUDO_GPR_IDX(8, w8), 1655 DEFINE_PSEUDO_GPR_IDX(9, w9), 1656 DEFINE_PSEUDO_GPR_IDX(10, w10), 1657 DEFINE_PSEUDO_GPR_IDX(11, w11), 1658 DEFINE_PSEUDO_GPR_IDX(12, w12), 1659 DEFINE_PSEUDO_GPR_IDX(13, w13), 1660 DEFINE_PSEUDO_GPR_IDX(14, w14), 1661 DEFINE_PSEUDO_GPR_IDX(15, w15), 1662 DEFINE_PSEUDO_GPR_IDX(16, w16), 1663 DEFINE_PSEUDO_GPR_IDX(17, w17), 1664 DEFINE_PSEUDO_GPR_IDX(18, w18), 1665 DEFINE_PSEUDO_GPR_IDX(19, w19), 1666 DEFINE_PSEUDO_GPR_IDX(20, w20), 1667 DEFINE_PSEUDO_GPR_IDX(21, w21), 1668 DEFINE_PSEUDO_GPR_IDX(22, w22), 1669 DEFINE_PSEUDO_GPR_IDX(23, w23), 1670 DEFINE_PSEUDO_GPR_IDX(24, w24), 1671 DEFINE_PSEUDO_GPR_IDX(25, w25), 1672 DEFINE_PSEUDO_GPR_IDX(26, w26), 1673 DEFINE_PSEUDO_GPR_IDX(27, w27), 1674 DEFINE_PSEUDO_GPR_IDX(28, w28)}; 1675 1676 const char *g_contained_v0[]{"v0", NULL}; 1677 const char *g_contained_v1[]{"v1", NULL}; 1678 const char *g_contained_v2[]{"v2", NULL}; 1679 const char *g_contained_v3[]{"v3", NULL}; 1680 const char *g_contained_v4[]{"v4", NULL}; 1681 const char *g_contained_v5[]{"v5", NULL}; 1682 const char *g_contained_v6[]{"v6", NULL}; 1683 const char *g_contained_v7[]{"v7", NULL}; 1684 const char *g_contained_v8[]{"v8", NULL}; 1685 const char *g_contained_v9[]{"v9", NULL}; 1686 const char *g_contained_v10[]{"v10", NULL}; 1687 const char *g_contained_v11[]{"v11", NULL}; 1688 const char *g_contained_v12[]{"v12", NULL}; 1689 const char *g_contained_v13[]{"v13", NULL}; 1690 const char *g_contained_v14[]{"v14", NULL}; 1691 const char *g_contained_v15[]{"v15", NULL}; 1692 const char *g_contained_v16[]{"v16", NULL}; 1693 const char *g_contained_v17[]{"v17", NULL}; 1694 const char *g_contained_v18[]{"v18", NULL}; 1695 const char *g_contained_v19[]{"v19", NULL}; 1696 const char *g_contained_v20[]{"v20", NULL}; 1697 const char *g_contained_v21[]{"v21", NULL}; 1698 const char *g_contained_v22[]{"v22", NULL}; 1699 const char *g_contained_v23[]{"v23", NULL}; 1700 const char *g_contained_v24[]{"v24", NULL}; 1701 const char *g_contained_v25[]{"v25", NULL}; 1702 const char *g_contained_v26[]{"v26", NULL}; 1703 const char *g_contained_v27[]{"v27", NULL}; 1704 const char *g_contained_v28[]{"v28", NULL}; 1705 const char *g_contained_v29[]{"v29", NULL}; 1706 const char *g_contained_v30[]{"v30", NULL}; 1707 const char *g_contained_v31[]{"v31", NULL}; 1708 1709 const char *g_invalidate_v0[]{"v0", "d0", "s0", NULL}; 1710 const char *g_invalidate_v1[]{"v1", "d1", "s1", NULL}; 1711 const char *g_invalidate_v2[]{"v2", "d2", "s2", NULL}; 1712 const char *g_invalidate_v3[]{"v3", "d3", "s3", NULL}; 1713 const char *g_invalidate_v4[]{"v4", "d4", "s4", NULL}; 1714 const char *g_invalidate_v5[]{"v5", "d5", "s5", NULL}; 1715 const char *g_invalidate_v6[]{"v6", "d6", "s6", NULL}; 1716 const char *g_invalidate_v7[]{"v7", "d7", "s7", NULL}; 1717 const char *g_invalidate_v8[]{"v8", "d8", "s8", NULL}; 1718 const char *g_invalidate_v9[]{"v9", "d9", "s9", NULL}; 1719 const char *g_invalidate_v10[]{"v10", "d10", "s10", NULL}; 1720 const char *g_invalidate_v11[]{"v11", "d11", "s11", NULL}; 1721 const char *g_invalidate_v12[]{"v12", "d12", "s12", NULL}; 1722 const char *g_invalidate_v13[]{"v13", "d13", "s13", NULL}; 1723 const char *g_invalidate_v14[]{"v14", "d14", "s14", NULL}; 1724 const char *g_invalidate_v15[]{"v15", "d15", "s15", NULL}; 1725 const char *g_invalidate_v16[]{"v16", "d16", "s16", NULL}; 1726 const char *g_invalidate_v17[]{"v17", "d17", "s17", NULL}; 1727 const char *g_invalidate_v18[]{"v18", "d18", "s18", NULL}; 1728 const char *g_invalidate_v19[]{"v19", "d19", "s19", NULL}; 1729 const char *g_invalidate_v20[]{"v20", "d20", "s20", NULL}; 1730 const char *g_invalidate_v21[]{"v21", "d21", "s21", NULL}; 1731 const char *g_invalidate_v22[]{"v22", "d22", "s22", NULL}; 1732 const char *g_invalidate_v23[]{"v23", "d23", "s23", NULL}; 1733 const char *g_invalidate_v24[]{"v24", "d24", "s24", NULL}; 1734 const char *g_invalidate_v25[]{"v25", "d25", "s25", NULL}; 1735 const char *g_invalidate_v26[]{"v26", "d26", "s26", NULL}; 1736 const char *g_invalidate_v27[]{"v27", "d27", "s27", NULL}; 1737 const char *g_invalidate_v28[]{"v28", "d28", "s28", NULL}; 1738 const char *g_invalidate_v29[]{"v29", "d29", "s29", NULL}; 1739 const char *g_invalidate_v30[]{"v30", "d30", "s30", NULL}; 1740 const char *g_invalidate_v31[]{"v31", "d31", "s31", NULL}; 1741 1742 #if defined(__arm64__) || defined(__aarch64__) 1743 #define VFP_V_OFFSET_IDX(idx) \ 1744 (offsetof(DNBArchMachARM64::FPU, __v) + (idx * 16) + \ 1745 offsetof(DNBArchMachARM64::Context, vfp)) 1746 #else 1747 #define VFP_V_OFFSET_IDX(idx) \ 1748 (offsetof(DNBArchMachARM64::FPU, opaque) + (idx * 16) + \ 1749 offsetof(DNBArchMachARM64::Context, vfp)) 1750 #endif 1751 #define VFP_OFFSET_NAME(reg) \ 1752 (offsetof(DNBArchMachARM64::FPU, reg) + \ 1753 offsetof(DNBArchMachARM64::Context, vfp)) 1754 #define EXC_OFFSET(reg) \ 1755 (offsetof(DNBArchMachARM64::EXC, reg) + \ 1756 offsetof(DNBArchMachARM64::Context, exc)) 1757 1758 //#define FLOAT_FORMAT Float 1759 #define DEFINE_VFP_V_IDX(idx) \ 1760 { \ 1761 e_regSetVFP, vfp_v##idx, "v" #idx, "q" #idx, Vector, VectorOfUInt8, 16, \ 1762 VFP_V_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_v##idx, \ 1763 INVALID_NUB_REGNUM, debugserver_vfp_v##idx, NULL, g_invalidate_v##idx \ 1764 } 1765 #define DEFINE_PSEUDO_VFP_S_IDX(idx) \ 1766 { \ 1767 e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, Float, 4, 0, \ 1768 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1769 INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \ 1770 } 1771 #define DEFINE_PSEUDO_VFP_D_IDX(idx) \ 1772 { \ 1773 e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, Float, 8, 0, \ 1774 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1775 INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \ 1776 } 1777 1778 // Floating point registers 1779 const DNBRegisterInfo DNBArchMachARM64::g_vfp_registers[] = { 1780 DEFINE_VFP_V_IDX(0), 1781 DEFINE_VFP_V_IDX(1), 1782 DEFINE_VFP_V_IDX(2), 1783 DEFINE_VFP_V_IDX(3), 1784 DEFINE_VFP_V_IDX(4), 1785 DEFINE_VFP_V_IDX(5), 1786 DEFINE_VFP_V_IDX(6), 1787 DEFINE_VFP_V_IDX(7), 1788 DEFINE_VFP_V_IDX(8), 1789 DEFINE_VFP_V_IDX(9), 1790 DEFINE_VFP_V_IDX(10), 1791 DEFINE_VFP_V_IDX(11), 1792 DEFINE_VFP_V_IDX(12), 1793 DEFINE_VFP_V_IDX(13), 1794 DEFINE_VFP_V_IDX(14), 1795 DEFINE_VFP_V_IDX(15), 1796 DEFINE_VFP_V_IDX(16), 1797 DEFINE_VFP_V_IDX(17), 1798 DEFINE_VFP_V_IDX(18), 1799 DEFINE_VFP_V_IDX(19), 1800 DEFINE_VFP_V_IDX(20), 1801 DEFINE_VFP_V_IDX(21), 1802 DEFINE_VFP_V_IDX(22), 1803 DEFINE_VFP_V_IDX(23), 1804 DEFINE_VFP_V_IDX(24), 1805 DEFINE_VFP_V_IDX(25), 1806 DEFINE_VFP_V_IDX(26), 1807 DEFINE_VFP_V_IDX(27), 1808 DEFINE_VFP_V_IDX(28), 1809 DEFINE_VFP_V_IDX(29), 1810 DEFINE_VFP_V_IDX(30), 1811 DEFINE_VFP_V_IDX(31), 1812 {e_regSetVFP, vfp_fpsr, "fpsr", NULL, Uint, Hex, 4, 1813 VFP_V_OFFSET_IDX(32) + 0, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1814 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}, 1815 {e_regSetVFP, vfp_fpcr, "fpcr", NULL, Uint, Hex, 4, 1816 VFP_V_OFFSET_IDX(32) + 4, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1817 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}, 1818 1819 DEFINE_PSEUDO_VFP_S_IDX(0), 1820 DEFINE_PSEUDO_VFP_S_IDX(1), 1821 DEFINE_PSEUDO_VFP_S_IDX(2), 1822 DEFINE_PSEUDO_VFP_S_IDX(3), 1823 DEFINE_PSEUDO_VFP_S_IDX(4), 1824 DEFINE_PSEUDO_VFP_S_IDX(5), 1825 DEFINE_PSEUDO_VFP_S_IDX(6), 1826 DEFINE_PSEUDO_VFP_S_IDX(7), 1827 DEFINE_PSEUDO_VFP_S_IDX(8), 1828 DEFINE_PSEUDO_VFP_S_IDX(9), 1829 DEFINE_PSEUDO_VFP_S_IDX(10), 1830 DEFINE_PSEUDO_VFP_S_IDX(11), 1831 DEFINE_PSEUDO_VFP_S_IDX(12), 1832 DEFINE_PSEUDO_VFP_S_IDX(13), 1833 DEFINE_PSEUDO_VFP_S_IDX(14), 1834 DEFINE_PSEUDO_VFP_S_IDX(15), 1835 DEFINE_PSEUDO_VFP_S_IDX(16), 1836 DEFINE_PSEUDO_VFP_S_IDX(17), 1837 DEFINE_PSEUDO_VFP_S_IDX(18), 1838 DEFINE_PSEUDO_VFP_S_IDX(19), 1839 DEFINE_PSEUDO_VFP_S_IDX(20), 1840 DEFINE_PSEUDO_VFP_S_IDX(21), 1841 DEFINE_PSEUDO_VFP_S_IDX(22), 1842 DEFINE_PSEUDO_VFP_S_IDX(23), 1843 DEFINE_PSEUDO_VFP_S_IDX(24), 1844 DEFINE_PSEUDO_VFP_S_IDX(25), 1845 DEFINE_PSEUDO_VFP_S_IDX(26), 1846 DEFINE_PSEUDO_VFP_S_IDX(27), 1847 DEFINE_PSEUDO_VFP_S_IDX(28), 1848 DEFINE_PSEUDO_VFP_S_IDX(29), 1849 DEFINE_PSEUDO_VFP_S_IDX(30), 1850 DEFINE_PSEUDO_VFP_S_IDX(31), 1851 1852 DEFINE_PSEUDO_VFP_D_IDX(0), 1853 DEFINE_PSEUDO_VFP_D_IDX(1), 1854 DEFINE_PSEUDO_VFP_D_IDX(2), 1855 DEFINE_PSEUDO_VFP_D_IDX(3), 1856 DEFINE_PSEUDO_VFP_D_IDX(4), 1857 DEFINE_PSEUDO_VFP_D_IDX(5), 1858 DEFINE_PSEUDO_VFP_D_IDX(6), 1859 DEFINE_PSEUDO_VFP_D_IDX(7), 1860 DEFINE_PSEUDO_VFP_D_IDX(8), 1861 DEFINE_PSEUDO_VFP_D_IDX(9), 1862 DEFINE_PSEUDO_VFP_D_IDX(10), 1863 DEFINE_PSEUDO_VFP_D_IDX(11), 1864 DEFINE_PSEUDO_VFP_D_IDX(12), 1865 DEFINE_PSEUDO_VFP_D_IDX(13), 1866 DEFINE_PSEUDO_VFP_D_IDX(14), 1867 DEFINE_PSEUDO_VFP_D_IDX(15), 1868 DEFINE_PSEUDO_VFP_D_IDX(16), 1869 DEFINE_PSEUDO_VFP_D_IDX(17), 1870 DEFINE_PSEUDO_VFP_D_IDX(18), 1871 DEFINE_PSEUDO_VFP_D_IDX(19), 1872 DEFINE_PSEUDO_VFP_D_IDX(20), 1873 DEFINE_PSEUDO_VFP_D_IDX(21), 1874 DEFINE_PSEUDO_VFP_D_IDX(22), 1875 DEFINE_PSEUDO_VFP_D_IDX(23), 1876 DEFINE_PSEUDO_VFP_D_IDX(24), 1877 DEFINE_PSEUDO_VFP_D_IDX(25), 1878 DEFINE_PSEUDO_VFP_D_IDX(26), 1879 DEFINE_PSEUDO_VFP_D_IDX(27), 1880 DEFINE_PSEUDO_VFP_D_IDX(28), 1881 DEFINE_PSEUDO_VFP_D_IDX(29), 1882 DEFINE_PSEUDO_VFP_D_IDX(30), 1883 DEFINE_PSEUDO_VFP_D_IDX(31) 1884 1885 }; 1886 1887 //_STRUCT_ARM_EXCEPTION_STATE64 1888 //{ 1889 // uint64_t far; /* Virtual Fault Address */ 1890 // uint32_t esr; /* Exception syndrome */ 1891 // uint32_t exception; /* number of arm exception taken */ 1892 //}; 1893 1894 // Exception registers 1895 const DNBRegisterInfo DNBArchMachARM64::g_exc_registers[] = { 1896 {e_regSetEXC, exc_far, "far", NULL, Uint, Hex, 8, EXC_OFFSET(__far), 1897 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1898 INVALID_NUB_REGNUM, NULL, NULL}, 1899 {e_regSetEXC, exc_esr, "esr", NULL, Uint, Hex, 4, EXC_OFFSET(__esr), 1900 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1901 INVALID_NUB_REGNUM, NULL, NULL}, 1902 {e_regSetEXC, exc_exception, "exception", NULL, Uint, Hex, 4, 1903 EXC_OFFSET(__exception), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1904 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}}; 1905 1906 // Number of registers in each register set 1907 const size_t DNBArchMachARM64::k_num_gpr_registers = 1908 sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo); 1909 const size_t DNBArchMachARM64::k_num_vfp_registers = 1910 sizeof(g_vfp_registers) / sizeof(DNBRegisterInfo); 1911 const size_t DNBArchMachARM64::k_num_exc_registers = 1912 sizeof(g_exc_registers) / sizeof(DNBRegisterInfo); 1913 const size_t DNBArchMachARM64::k_num_all_registers = 1914 k_num_gpr_registers + k_num_vfp_registers + k_num_exc_registers; 1915 1916 // Register set definitions. The first definitions at register set index 1917 // of zero is for all registers, followed by other registers sets. The 1918 // register information for the all register set need not be filled in. 1919 const DNBRegisterSetInfo DNBArchMachARM64::g_reg_sets[] = { 1920 {"ARM64 Registers", NULL, k_num_all_registers}, 1921 {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers}, 1922 {"Floating Point Registers", g_vfp_registers, k_num_vfp_registers}, 1923 {"Exception State Registers", g_exc_registers, k_num_exc_registers}}; 1924 // Total number of register sets for this architecture 1925 const size_t DNBArchMachARM64::k_num_register_sets = 1926 sizeof(g_reg_sets) / sizeof(DNBRegisterSetInfo); 1927 1928 const DNBRegisterSetInfo * 1929 DNBArchMachARM64::GetRegisterSetInfo(nub_size_t *num_reg_sets) { 1930 *num_reg_sets = k_num_register_sets; 1931 return g_reg_sets; 1932 } 1933 1934 bool DNBArchMachARM64::FixGenericRegisterNumber(uint32_t &set, uint32_t ®) { 1935 if (set == REGISTER_SET_GENERIC) { 1936 switch (reg) { 1937 case GENERIC_REGNUM_PC: // Program Counter 1938 set = e_regSetGPR; 1939 reg = gpr_pc; 1940 break; 1941 1942 case GENERIC_REGNUM_SP: // Stack Pointer 1943 set = e_regSetGPR; 1944 reg = gpr_sp; 1945 break; 1946 1947 case GENERIC_REGNUM_FP: // Frame Pointer 1948 set = e_regSetGPR; 1949 reg = gpr_fp; 1950 break; 1951 1952 case GENERIC_REGNUM_RA: // Return Address 1953 set = e_regSetGPR; 1954 reg = gpr_lr; 1955 break; 1956 1957 case GENERIC_REGNUM_FLAGS: // Processor flags register 1958 set = e_regSetGPR; 1959 reg = gpr_cpsr; 1960 break; 1961 1962 case GENERIC_REGNUM_ARG1: 1963 case GENERIC_REGNUM_ARG2: 1964 case GENERIC_REGNUM_ARG3: 1965 case GENERIC_REGNUM_ARG4: 1966 case GENERIC_REGNUM_ARG5: 1967 case GENERIC_REGNUM_ARG6: 1968 set = e_regSetGPR; 1969 reg = gpr_x0 + reg - GENERIC_REGNUM_ARG1; 1970 break; 1971 1972 default: 1973 return false; 1974 } 1975 } 1976 return true; 1977 } 1978 bool DNBArchMachARM64::GetRegisterValue(uint32_t set, uint32_t reg, 1979 DNBRegisterValue *value) { 1980 if (!FixGenericRegisterNumber(set, reg)) 1981 return false; 1982 1983 if (GetRegisterState(set, false) != KERN_SUCCESS) 1984 return false; 1985 1986 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1987 if (regInfo) { 1988 value->info = *regInfo; 1989 switch (set) { 1990 case e_regSetGPR: 1991 if (reg <= gpr_pc) { 1992 #if defined(__LP64__) 1993 if (reg == gpr_pc) 1994 value->value.uint64 = arm_thread_state64_get_pc (m_state.context.gpr); 1995 else if (reg == gpr_lr) 1996 value->value.uint64 = arm_thread_state64_get_lr (m_state.context.gpr); 1997 else if (reg == gpr_sp) 1998 value->value.uint64 = arm_thread_state64_get_sp (m_state.context.gpr); 1999 else if (reg == gpr_fp) 2000 value->value.uint64 = arm_thread_state64_get_fp (m_state.context.gpr); 2001 else 2002 value->value.uint64 = m_state.context.gpr.__x[reg]; 2003 #else 2004 value->value.uint64 = m_state.context.gpr.__x[reg]; 2005 #endif 2006 return true; 2007 } else if (reg == gpr_cpsr) { 2008 value->value.uint32 = m_state.context.gpr.__cpsr; 2009 return true; 2010 } 2011 break; 2012 2013 case e_regSetVFP: 2014 2015 if (reg >= vfp_v0 && reg <= vfp_v31) { 2016 #if defined(__arm64__) || defined(__aarch64__) 2017 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_v0], 2018 16); 2019 #else 2020 memcpy(&value->value.v_uint8, 2021 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), 2022 16); 2023 #endif 2024 return true; 2025 } else if (reg == vfp_fpsr) { 2026 #if defined(__arm64__) || defined(__aarch64__) 2027 memcpy(&value->value.uint32, &m_state.context.vfp.__fpsr, 4); 2028 #else 2029 memcpy(&value->value.uint32, 2030 ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0, 4); 2031 #endif 2032 return true; 2033 } else if (reg == vfp_fpcr) { 2034 #if defined(__arm64__) || defined(__aarch64__) 2035 memcpy(&value->value.uint32, &m_state.context.vfp.__fpcr, 4); 2036 #else 2037 memcpy(&value->value.uint32, 2038 ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 4, 4); 2039 #endif 2040 return true; 2041 } else if (reg >= vfp_s0 && reg <= vfp_s31) { 2042 #if defined(__arm64__) || defined(__aarch64__) 2043 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_s0], 2044 4); 2045 #else 2046 memcpy(&value->value.v_uint8, 2047 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), 2048 4); 2049 #endif 2050 return true; 2051 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 2052 #if defined(__arm64__) || defined(__aarch64__) 2053 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_d0], 2054 8); 2055 #else 2056 memcpy(&value->value.v_uint8, 2057 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), 2058 8); 2059 #endif 2060 return true; 2061 } 2062 break; 2063 2064 case e_regSetEXC: 2065 if (reg == exc_far) { 2066 value->value.uint64 = m_state.context.exc.__far; 2067 return true; 2068 } else if (reg == exc_esr) { 2069 value->value.uint32 = m_state.context.exc.__esr; 2070 return true; 2071 } else if (reg == exc_exception) { 2072 value->value.uint32 = m_state.context.exc.__exception; 2073 return true; 2074 } 2075 break; 2076 } 2077 } 2078 return false; 2079 } 2080 2081 bool DNBArchMachARM64::SetRegisterValue(uint32_t set, uint32_t reg, 2082 const DNBRegisterValue *value) { 2083 if (!FixGenericRegisterNumber(set, reg)) 2084 return false; 2085 2086 if (GetRegisterState(set, false) != KERN_SUCCESS) 2087 return false; 2088 2089 bool success = false; 2090 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 2091 if (regInfo) { 2092 switch (set) { 2093 case e_regSetGPR: 2094 if (reg <= gpr_pc) { 2095 #if defined(__LP64__) 2096 uint64_t signed_value = value->value.uint64; 2097 #if __has_feature(ptrauth_calls) 2098 // The incoming value could be garbage. Strip it to avoid 2099 // trapping when it gets resigned in the thread state. 2100 signed_value = (uint64_t) ptrauth_strip((void*) signed_value, ptrauth_key_function_pointer); 2101 signed_value = (uint64_t) ptrauth_sign_unauthenticated((void*) signed_value, ptrauth_key_function_pointer, 0); 2102 #endif 2103 if (reg == gpr_pc) 2104 arm_thread_state64_set_pc_fptr (m_state.context.gpr, (void*) signed_value); 2105 else if (reg == gpr_lr) 2106 arm_thread_state64_set_lr_fptr (m_state.context.gpr, (void*) signed_value); 2107 else if (reg == gpr_sp) 2108 arm_thread_state64_set_sp (m_state.context.gpr, value->value.uint64); 2109 else if (reg == gpr_fp) 2110 arm_thread_state64_set_fp (m_state.context.gpr, value->value.uint64); 2111 else 2112 m_state.context.gpr.__x[reg] = value->value.uint64; 2113 #else 2114 m_state.context.gpr.__x[reg] = value->value.uint64; 2115 #endif 2116 success = true; 2117 } else if (reg == gpr_cpsr) { 2118 m_state.context.gpr.__cpsr = value->value.uint32; 2119 success = true; 2120 } 2121 break; 2122 2123 case e_regSetVFP: 2124 if (reg >= vfp_v0 && reg <= vfp_v31) { 2125 #if defined(__arm64__) || defined(__aarch64__) 2126 memcpy(&m_state.context.vfp.__v[reg - vfp_v0], &value->value.v_uint8, 2127 16); 2128 #else 2129 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), 2130 &value->value.v_uint8, 16); 2131 #endif 2132 success = true; 2133 } else if (reg == vfp_fpsr) { 2134 #if defined(__arm64__) || defined(__aarch64__) 2135 memcpy(&m_state.context.vfp.__fpsr, &value->value.uint32, 4); 2136 #else 2137 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0, 2138 &value->value.uint32, 4); 2139 #endif 2140 success = true; 2141 } else if (reg == vfp_fpcr) { 2142 #if defined(__arm64__) || defined(__aarch64__) 2143 memcpy(&m_state.context.vfp.__fpcr, &value->value.uint32, 4); 2144 #else 2145 memcpy(((uint8_t *)m_state.context.vfp.opaque) + (32 * 16) + 4, 2146 &value->value.uint32, 4); 2147 #endif 2148 success = true; 2149 } else if (reg >= vfp_s0 && reg <= vfp_s31) { 2150 #if defined(__arm64__) || defined(__aarch64__) 2151 memcpy(&m_state.context.vfp.__v[reg - vfp_s0], &value->value.v_uint8, 2152 4); 2153 #else 2154 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), 2155 &value->value.v_uint8, 4); 2156 #endif 2157 success = true; 2158 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 2159 #if defined(__arm64__) || defined(__aarch64__) 2160 memcpy(&m_state.context.vfp.__v[reg - vfp_d0], &value->value.v_uint8, 2161 8); 2162 #else 2163 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), 2164 &value->value.v_uint8, 8); 2165 #endif 2166 success = true; 2167 } 2168 break; 2169 2170 case e_regSetEXC: 2171 if (reg == exc_far) { 2172 m_state.context.exc.__far = value->value.uint64; 2173 success = true; 2174 } else if (reg == exc_esr) { 2175 m_state.context.exc.__esr = value->value.uint32; 2176 success = true; 2177 } else if (reg == exc_exception) { 2178 m_state.context.exc.__exception = value->value.uint32; 2179 success = true; 2180 } 2181 break; 2182 } 2183 } 2184 if (success) 2185 return SetRegisterState(set) == KERN_SUCCESS; 2186 return false; 2187 } 2188 2189 kern_return_t DNBArchMachARM64::GetRegisterState(int set, bool force) { 2190 switch (set) { 2191 case e_regSetALL: 2192 return GetGPRState(force) | GetVFPState(force) | GetEXCState(force) | 2193 GetDBGState(force); 2194 case e_regSetGPR: 2195 return GetGPRState(force); 2196 case e_regSetVFP: 2197 return GetVFPState(force); 2198 case e_regSetEXC: 2199 return GetEXCState(force); 2200 case e_regSetDBG: 2201 return GetDBGState(force); 2202 default: 2203 break; 2204 } 2205 return KERN_INVALID_ARGUMENT; 2206 } 2207 2208 kern_return_t DNBArchMachARM64::SetRegisterState(int set) { 2209 // Make sure we have a valid context to set. 2210 kern_return_t err = GetRegisterState(set, false); 2211 if (err != KERN_SUCCESS) 2212 return err; 2213 2214 switch (set) { 2215 case e_regSetALL: 2216 return SetGPRState() | SetVFPState() | SetEXCState() | SetDBGState(false); 2217 case e_regSetGPR: 2218 return SetGPRState(); 2219 case e_regSetVFP: 2220 return SetVFPState(); 2221 case e_regSetEXC: 2222 return SetEXCState(); 2223 case e_regSetDBG: 2224 return SetDBGState(false); 2225 default: 2226 break; 2227 } 2228 return KERN_INVALID_ARGUMENT; 2229 } 2230 2231 bool DNBArchMachARM64::RegisterSetStateIsValid(int set) const { 2232 return m_state.RegsAreValid(set); 2233 } 2234 2235 nub_size_t DNBArchMachARM64::GetRegisterContext(void *buf, nub_size_t buf_len) { 2236 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 2237 sizeof(m_state.context.exc); 2238 2239 if (buf && buf_len) { 2240 if (size > buf_len) 2241 size = buf_len; 2242 2243 bool force = false; 2244 if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force)) 2245 return 0; 2246 2247 // Copy each struct individually to avoid any padding that might be between 2248 // the structs in m_state.context 2249 uint8_t *p = (uint8_t *)buf; 2250 ::memcpy(p, &m_state.context.gpr, sizeof(m_state.context.gpr)); 2251 p += sizeof(m_state.context.gpr); 2252 ::memcpy(p, &m_state.context.vfp, sizeof(m_state.context.vfp)); 2253 p += sizeof(m_state.context.vfp); 2254 ::memcpy(p, &m_state.context.exc, sizeof(m_state.context.exc)); 2255 p += sizeof(m_state.context.exc); 2256 2257 size_t bytes_written = p - (uint8_t *)buf; 2258 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2259 assert(bytes_written == size); 2260 } 2261 DNBLogThreadedIf( 2262 LOG_THREAD, 2263 "DNBArchMachARM64::GetRegisterContext (buf = %p, len = %zu) => %zu", buf, 2264 buf_len, size); 2265 // Return the size of the register context even if NULL was passed in 2266 return size; 2267 } 2268 2269 nub_size_t DNBArchMachARM64::SetRegisterContext(const void *buf, 2270 nub_size_t buf_len) { 2271 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 2272 sizeof(m_state.context.exc); 2273 2274 if (buf == NULL || buf_len == 0) 2275 size = 0; 2276 2277 if (size) { 2278 if (size > buf_len) 2279 size = buf_len; 2280 2281 // Copy each struct individually to avoid any padding that might be between 2282 // the structs in m_state.context 2283 uint8_t *p = (uint8_t *)buf; 2284 ::memcpy(&m_state.context.gpr, p, sizeof(m_state.context.gpr)); 2285 p += sizeof(m_state.context.gpr); 2286 ::memcpy(&m_state.context.vfp, p, sizeof(m_state.context.vfp)); 2287 p += sizeof(m_state.context.vfp); 2288 ::memcpy(&m_state.context.exc, p, sizeof(m_state.context.exc)); 2289 p += sizeof(m_state.context.exc); 2290 2291 size_t bytes_written = p - (uint8_t *)buf; 2292 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2293 assert(bytes_written == size); 2294 SetGPRState(); 2295 SetVFPState(); 2296 SetEXCState(); 2297 } 2298 DNBLogThreadedIf( 2299 LOG_THREAD, 2300 "DNBArchMachARM64::SetRegisterContext (buf = %p, len = %zu) => %zu", buf, 2301 buf_len, size); 2302 return size; 2303 } 2304 2305 uint32_t DNBArchMachARM64::SaveRegisterState() { 2306 kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber()); 2307 DNBLogThreadedIf( 2308 LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u " 2309 "(SetGPRState() for stop_count = %u)", 2310 m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount()); 2311 2312 // Always re-read the registers because above we call thread_abort_safely(); 2313 bool force = true; 2314 2315 if ((kret = GetGPRState(force)) != KERN_SUCCESS) { 2316 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () " 2317 "error: GPR regs failed to read: %u ", 2318 kret); 2319 } else if ((kret = GetVFPState(force)) != KERN_SUCCESS) { 2320 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () " 2321 "error: %s regs failed to read: %u", 2322 "VFP", kret); 2323 } else { 2324 const uint32_t save_id = GetNextRegisterStateSaveID(); 2325 m_saved_register_states[save_id] = m_state.context; 2326 return save_id; 2327 } 2328 return UINT32_MAX; 2329 } 2330 2331 bool DNBArchMachARM64::RestoreRegisterState(uint32_t save_id) { 2332 SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id); 2333 if (pos != m_saved_register_states.end()) { 2334 m_state.context.gpr = pos->second.gpr; 2335 m_state.context.vfp = pos->second.vfp; 2336 kern_return_t kret; 2337 bool success = true; 2338 if ((kret = SetGPRState()) != KERN_SUCCESS) { 2339 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState " 2340 "(save_id = %u) error: GPR regs failed to " 2341 "write: %u", 2342 save_id, kret); 2343 success = false; 2344 } else if ((kret = SetVFPState()) != KERN_SUCCESS) { 2345 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState " 2346 "(save_id = %u) error: %s regs failed to " 2347 "write: %u", 2348 save_id, "VFP", kret); 2349 success = false; 2350 } 2351 m_saved_register_states.erase(pos); 2352 return success; 2353 } 2354 return false; 2355 } 2356 2357 #endif // #if defined (ARM_THREAD_STATE64_COUNT) 2358 #endif // #if defined (__arm__) || defined (__arm64__) || defined (__aarch64__) 2359