1 //===-- DNBArchImplARM64.cpp ------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Created by Greg Clayton on 6/25/07. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #if defined(__arm__) || defined(__arm64__) || defined(__aarch64__) 14 15 #include "MacOSX/arm64/DNBArchImplARM64.h" 16 17 #if defined(ARM_THREAD_STATE64_COUNT) 18 19 #include "DNB.h" 20 #include "DNBBreakpoint.h" 21 #include "DNBLog.h" 22 #include "DNBRegisterInfo.h" 23 #include "MacOSX/MachProcess.h" 24 #include "MacOSX/MachThread.h" 25 26 #include <inttypes.h> 27 #include <sys/sysctl.h> 28 29 // Break only in privileged or user mode 30 // (PAC bits in the DBGWVRn_EL1 watchpoint control register) 31 #define S_USER ((uint32_t)(2u << 1)) 32 33 #define BCR_ENABLE ((uint32_t)(1u)) 34 #define WCR_ENABLE ((uint32_t)(1u)) 35 36 // Watchpoint load/store 37 // (LSC bits in the DBGWVRn_EL1 watchpoint control register) 38 #define WCR_LOAD ((uint32_t)(1u << 3)) 39 #define WCR_STORE ((uint32_t)(1u << 4)) 40 41 // Enable breakpoint, watchpoint, and vector catch debug exceptions. 42 // (MDE bit in the MDSCR_EL1 register. Equivalent to the MDBGen bit in 43 // DBGDSCRext in Aarch32) 44 #define MDE_ENABLE ((uint32_t)(1u << 15)) 45 46 // Single instruction step 47 // (SS bit in the MDSCR_EL1 register) 48 #define SS_ENABLE ((uint32_t)(1u)) 49 50 static const uint8_t g_arm64_breakpoint_opcode[] = { 51 0x00, 0x00, 0x20, 0xD4}; // "brk #0", 0xd4200000 in BE byte order 52 53 // If we need to set one logical watchpoint by using 54 // two hardware watchpoint registers, the watchpoint 55 // will be split into a "high" and "low" watchpoint. 56 // Record both of them in the LoHi array. 57 58 // It's safe to initialize to all 0's since 59 // hi > lo and therefore LoHi[i] cannot be 0. 60 static uint32_t LoHi[16] = {0}; 61 62 void DNBArchMachARM64::Initialize() { 63 DNBArchPluginInfo arch_plugin_info = { 64 CPU_TYPE_ARM64, DNBArchMachARM64::Create, 65 DNBArchMachARM64::GetRegisterSetInfo, 66 DNBArchMachARM64::SoftwareBreakpointOpcode}; 67 68 // Register this arch plug-in with the main protocol class 69 DNBArchProtocol::RegisterArchPlugin(arch_plugin_info); 70 71 DNBArchPluginInfo arch_plugin_info_32 = { 72 CPU_TYPE_ARM64_32, DNBArchMachARM64::Create, 73 DNBArchMachARM64::GetRegisterSetInfo, 74 DNBArchMachARM64::SoftwareBreakpointOpcode}; 75 76 // Register this arch plug-in with the main protocol class 77 DNBArchProtocol::RegisterArchPlugin(arch_plugin_info_32); 78 } 79 80 DNBArchProtocol *DNBArchMachARM64::Create(MachThread *thread) { 81 DNBArchMachARM64 *obj = new DNBArchMachARM64(thread); 82 83 return obj; 84 } 85 86 const uint8_t * 87 DNBArchMachARM64::SoftwareBreakpointOpcode(nub_size_t byte_size) { 88 return g_arm64_breakpoint_opcode; 89 } 90 91 uint32_t DNBArchMachARM64::GetCPUType() { return CPU_TYPE_ARM64; } 92 93 uint64_t DNBArchMachARM64::GetPC(uint64_t failValue) { 94 // Get program counter 95 if (GetGPRState(false) == KERN_SUCCESS) 96 return m_state.context.gpr.__pc; 97 return failValue; 98 } 99 100 kern_return_t DNBArchMachARM64::SetPC(uint64_t value) { 101 // Get program counter 102 kern_return_t err = GetGPRState(false); 103 if (err == KERN_SUCCESS) { 104 m_state.context.gpr.__pc = value; 105 err = SetGPRState(); 106 } 107 return err == KERN_SUCCESS; 108 } 109 110 uint64_t DNBArchMachARM64::GetSP(uint64_t failValue) { 111 // Get stack pointer 112 if (GetGPRState(false) == KERN_SUCCESS) 113 return m_state.context.gpr.__sp; 114 return failValue; 115 } 116 117 kern_return_t DNBArchMachARM64::GetGPRState(bool force) { 118 int set = e_regSetGPR; 119 // Check if we have valid cached registers 120 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 121 return KERN_SUCCESS; 122 123 // Read the registers from our thread 124 mach_msg_type_number_t count = e_regSetGPRCount; 125 kern_return_t kret = 126 ::thread_get_state(m_thread->MachPortNumber(), ARM_THREAD_STATE64, 127 (thread_state_t)&m_state.context.gpr, &count); 128 if (DNBLogEnabledForAny(LOG_THREAD)) { 129 uint64_t *x = &m_state.context.gpr.__x[0]; 130 DNBLogThreaded( 131 "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count = %u) regs" 132 "\n x0=%16.16llx" 133 "\n x1=%16.16llx" 134 "\n x2=%16.16llx" 135 "\n x3=%16.16llx" 136 "\n x4=%16.16llx" 137 "\n x5=%16.16llx" 138 "\n x6=%16.16llx" 139 "\n x7=%16.16llx" 140 "\n x8=%16.16llx" 141 "\n x9=%16.16llx" 142 "\n x10=%16.16llx" 143 "\n x11=%16.16llx" 144 "\n x12=%16.16llx" 145 "\n x13=%16.16llx" 146 "\n x14=%16.16llx" 147 "\n x15=%16.16llx" 148 "\n x16=%16.16llx" 149 "\n x17=%16.16llx" 150 "\n x18=%16.16llx" 151 "\n x19=%16.16llx" 152 "\n x20=%16.16llx" 153 "\n x21=%16.16llx" 154 "\n x22=%16.16llx" 155 "\n x23=%16.16llx" 156 "\n x24=%16.16llx" 157 "\n x25=%16.16llx" 158 "\n x26=%16.16llx" 159 "\n x27=%16.16llx" 160 "\n x28=%16.16llx" 161 "\n fp=%16.16llx" 162 "\n lr=%16.16llx" 163 "\n sp=%16.16llx" 164 "\n pc=%16.16llx" 165 "\n cpsr=%8.8x", 166 m_thread->MachPortNumber(), e_regSetGPR, e_regSetGPRCount, kret, count, 167 x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[0], x[11], 168 x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], x[20], x[21], 169 x[22], x[23], x[24], x[25], x[26], x[27], x[28], 170 m_state.context.gpr.__fp, m_state.context.gpr.__lr, 171 m_state.context.gpr.__sp, m_state.context.gpr.__pc, 172 m_state.context.gpr.__cpsr); 173 } 174 m_state.SetError(set, Read, kret); 175 return kret; 176 } 177 178 kern_return_t DNBArchMachARM64::GetVFPState(bool force) { 179 int set = e_regSetVFP; 180 // Check if we have valid cached registers 181 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 182 return KERN_SUCCESS; 183 184 // Read the registers from our thread 185 mach_msg_type_number_t count = e_regSetVFPCount; 186 kern_return_t kret = 187 ::thread_get_state(m_thread->MachPortNumber(), ARM_NEON_STATE64, 188 (thread_state_t)&m_state.context.vfp, &count); 189 if (DNBLogEnabledForAny(LOG_THREAD)) { 190 #if defined(__arm64__) || defined(__aarch64__) 191 DNBLogThreaded( 192 "thread_get_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs" 193 "\n q0 = 0x%16.16llx%16.16llx" 194 "\n q1 = 0x%16.16llx%16.16llx" 195 "\n q2 = 0x%16.16llx%16.16llx" 196 "\n q3 = 0x%16.16llx%16.16llx" 197 "\n q4 = 0x%16.16llx%16.16llx" 198 "\n q5 = 0x%16.16llx%16.16llx" 199 "\n q6 = 0x%16.16llx%16.16llx" 200 "\n q7 = 0x%16.16llx%16.16llx" 201 "\n q8 = 0x%16.16llx%16.16llx" 202 "\n q9 = 0x%16.16llx%16.16llx" 203 "\n q10 = 0x%16.16llx%16.16llx" 204 "\n q11 = 0x%16.16llx%16.16llx" 205 "\n q12 = 0x%16.16llx%16.16llx" 206 "\n q13 = 0x%16.16llx%16.16llx" 207 "\n q14 = 0x%16.16llx%16.16llx" 208 "\n q15 = 0x%16.16llx%16.16llx" 209 "\n q16 = 0x%16.16llx%16.16llx" 210 "\n q17 = 0x%16.16llx%16.16llx" 211 "\n q18 = 0x%16.16llx%16.16llx" 212 "\n q19 = 0x%16.16llx%16.16llx" 213 "\n q20 = 0x%16.16llx%16.16llx" 214 "\n q21 = 0x%16.16llx%16.16llx" 215 "\n q22 = 0x%16.16llx%16.16llx" 216 "\n q23 = 0x%16.16llx%16.16llx" 217 "\n q24 = 0x%16.16llx%16.16llx" 218 "\n q25 = 0x%16.16llx%16.16llx" 219 "\n q26 = 0x%16.16llx%16.16llx" 220 "\n q27 = 0x%16.16llx%16.16llx" 221 "\n q28 = 0x%16.16llx%16.16llx" 222 "\n q29 = 0x%16.16llx%16.16llx" 223 "\n q30 = 0x%16.16llx%16.16llx" 224 "\n q31 = 0x%16.16llx%16.16llx" 225 "\n fpsr = 0x%8.8x" 226 "\n fpcr = 0x%8.8x\n\n", 227 m_thread->MachPortNumber(), e_regSetVFP, e_regSetVFPCount, kret, count, 228 ((uint64_t *)&m_state.context.vfp.__v[0])[0], 229 ((uint64_t *)&m_state.context.vfp.__v[0])[1], 230 ((uint64_t *)&m_state.context.vfp.__v[1])[0], 231 ((uint64_t *)&m_state.context.vfp.__v[1])[1], 232 ((uint64_t *)&m_state.context.vfp.__v[2])[0], 233 ((uint64_t *)&m_state.context.vfp.__v[2])[1], 234 ((uint64_t *)&m_state.context.vfp.__v[3])[0], 235 ((uint64_t *)&m_state.context.vfp.__v[3])[1], 236 ((uint64_t *)&m_state.context.vfp.__v[4])[0], 237 ((uint64_t *)&m_state.context.vfp.__v[4])[1], 238 ((uint64_t *)&m_state.context.vfp.__v[5])[0], 239 ((uint64_t *)&m_state.context.vfp.__v[5])[1], 240 ((uint64_t *)&m_state.context.vfp.__v[6])[0], 241 ((uint64_t *)&m_state.context.vfp.__v[6])[1], 242 ((uint64_t *)&m_state.context.vfp.__v[7])[0], 243 ((uint64_t *)&m_state.context.vfp.__v[7])[1], 244 ((uint64_t *)&m_state.context.vfp.__v[8])[0], 245 ((uint64_t *)&m_state.context.vfp.__v[8])[1], 246 ((uint64_t *)&m_state.context.vfp.__v[9])[0], 247 ((uint64_t *)&m_state.context.vfp.__v[9])[1], 248 ((uint64_t *)&m_state.context.vfp.__v[10])[0], 249 ((uint64_t *)&m_state.context.vfp.__v[10])[1], 250 ((uint64_t *)&m_state.context.vfp.__v[11])[0], 251 ((uint64_t *)&m_state.context.vfp.__v[11])[1], 252 ((uint64_t *)&m_state.context.vfp.__v[12])[0], 253 ((uint64_t *)&m_state.context.vfp.__v[12])[1], 254 ((uint64_t *)&m_state.context.vfp.__v[13])[0], 255 ((uint64_t *)&m_state.context.vfp.__v[13])[1], 256 ((uint64_t *)&m_state.context.vfp.__v[14])[0], 257 ((uint64_t *)&m_state.context.vfp.__v[14])[1], 258 ((uint64_t *)&m_state.context.vfp.__v[15])[0], 259 ((uint64_t *)&m_state.context.vfp.__v[15])[1], 260 ((uint64_t *)&m_state.context.vfp.__v[16])[0], 261 ((uint64_t *)&m_state.context.vfp.__v[16])[1], 262 ((uint64_t *)&m_state.context.vfp.__v[17])[0], 263 ((uint64_t *)&m_state.context.vfp.__v[17])[1], 264 ((uint64_t *)&m_state.context.vfp.__v[18])[0], 265 ((uint64_t *)&m_state.context.vfp.__v[18])[1], 266 ((uint64_t *)&m_state.context.vfp.__v[19])[0], 267 ((uint64_t *)&m_state.context.vfp.__v[19])[1], 268 ((uint64_t *)&m_state.context.vfp.__v[20])[0], 269 ((uint64_t *)&m_state.context.vfp.__v[20])[1], 270 ((uint64_t *)&m_state.context.vfp.__v[21])[0], 271 ((uint64_t *)&m_state.context.vfp.__v[21])[1], 272 ((uint64_t *)&m_state.context.vfp.__v[22])[0], 273 ((uint64_t *)&m_state.context.vfp.__v[22])[1], 274 ((uint64_t *)&m_state.context.vfp.__v[23])[0], 275 ((uint64_t *)&m_state.context.vfp.__v[23])[1], 276 ((uint64_t *)&m_state.context.vfp.__v[24])[0], 277 ((uint64_t *)&m_state.context.vfp.__v[24])[1], 278 ((uint64_t *)&m_state.context.vfp.__v[25])[0], 279 ((uint64_t *)&m_state.context.vfp.__v[25])[1], 280 ((uint64_t *)&m_state.context.vfp.__v[26])[0], 281 ((uint64_t *)&m_state.context.vfp.__v[26])[1], 282 ((uint64_t *)&m_state.context.vfp.__v[27])[0], 283 ((uint64_t *)&m_state.context.vfp.__v[27])[1], 284 ((uint64_t *)&m_state.context.vfp.__v[28])[0], 285 ((uint64_t *)&m_state.context.vfp.__v[28])[1], 286 ((uint64_t *)&m_state.context.vfp.__v[29])[0], 287 ((uint64_t *)&m_state.context.vfp.__v[29])[1], 288 ((uint64_t *)&m_state.context.vfp.__v[30])[0], 289 ((uint64_t *)&m_state.context.vfp.__v[30])[1], 290 ((uint64_t *)&m_state.context.vfp.__v[31])[0], 291 ((uint64_t *)&m_state.context.vfp.__v[31])[1], 292 m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr); 293 #endif 294 } 295 m_state.SetError(set, Read, kret); 296 return kret; 297 } 298 299 kern_return_t DNBArchMachARM64::GetEXCState(bool force) { 300 int set = e_regSetEXC; 301 // Check if we have valid cached registers 302 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 303 return KERN_SUCCESS; 304 305 // Read the registers from our thread 306 mach_msg_type_number_t count = e_regSetEXCCount; 307 kern_return_t kret = 308 ::thread_get_state(m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, 309 (thread_state_t)&m_state.context.exc, &count); 310 m_state.SetError(set, Read, kret); 311 return kret; 312 } 313 314 static void DumpDBGState(const arm_debug_state_t &dbg) { 315 uint32_t i = 0; 316 for (i = 0; i < 16; i++) 317 DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } " 318 "WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }", 319 i, i, dbg.__bvr[i], dbg.__bcr[i], i, i, dbg.__wvr[i], 320 dbg.__wcr[i]); 321 } 322 323 kern_return_t DNBArchMachARM64::GetDBGState(bool force) { 324 int set = e_regSetDBG; 325 326 // Check if we have valid cached registers 327 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 328 return KERN_SUCCESS; 329 330 // Read the registers from our thread 331 mach_msg_type_number_t count = e_regSetDBGCount; 332 kern_return_t kret = 333 ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64, 334 (thread_state_t)&m_state.dbg, &count); 335 m_state.SetError(set, Read, kret); 336 337 return kret; 338 } 339 340 kern_return_t DNBArchMachARM64::SetGPRState() { 341 int set = e_regSetGPR; 342 kern_return_t kret = ::thread_set_state( 343 m_thread->MachPortNumber(), ARM_THREAD_STATE64, 344 (thread_state_t)&m_state.context.gpr, e_regSetGPRCount); 345 m_state.SetError(set, Write, 346 kret); // Set the current write error for this register set 347 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 348 // state in case registers are read 349 // back differently 350 return kret; // Return the error code 351 } 352 353 kern_return_t DNBArchMachARM64::SetVFPState() { 354 int set = e_regSetVFP; 355 kern_return_t kret = ::thread_set_state( 356 m_thread->MachPortNumber(), ARM_NEON_STATE64, 357 (thread_state_t)&m_state.context.vfp, e_regSetVFPCount); 358 m_state.SetError(set, Write, 359 kret); // Set the current write error for this register set 360 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 361 // state in case registers are read 362 // back differently 363 return kret; // Return the error code 364 } 365 366 kern_return_t DNBArchMachARM64::SetEXCState() { 367 int set = e_regSetEXC; 368 kern_return_t kret = ::thread_set_state( 369 m_thread->MachPortNumber(), ARM_EXCEPTION_STATE64, 370 (thread_state_t)&m_state.context.exc, e_regSetEXCCount); 371 m_state.SetError(set, Write, 372 kret); // Set the current write error for this register set 373 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 374 // state in case registers are read 375 // back differently 376 return kret; // Return the error code 377 } 378 379 kern_return_t DNBArchMachARM64::SetDBGState(bool also_set_on_task) { 380 int set = e_regSetDBG; 381 kern_return_t kret = 382 ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE64, 383 (thread_state_t)&m_state.dbg, e_regSetDBGCount); 384 if (also_set_on_task) { 385 kern_return_t task_kret = task_set_state( 386 m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE64, 387 (thread_state_t)&m_state.dbg, e_regSetDBGCount); 388 if (task_kret != KERN_SUCCESS) 389 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::SetDBGState failed " 390 "to set debug control register state: " 391 "0x%8.8x.", 392 task_kret); 393 } 394 m_state.SetError(set, Write, 395 kret); // Set the current write error for this register set 396 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 397 // state in case registers are read 398 // back differently 399 400 return kret; // Return the error code 401 } 402 403 void DNBArchMachARM64::ThreadWillResume() { 404 // Do we need to step this thread? If so, let the mach thread tell us so. 405 if (m_thread->IsStepping()) { 406 EnableHardwareSingleStep(true); 407 } 408 409 // Disable the triggered watchpoint temporarily before we resume. 410 // Plus, we try to enable hardware single step to execute past the instruction 411 // which triggered our watchpoint. 412 if (m_watchpoint_did_occur) { 413 if (m_watchpoint_hw_index >= 0) { 414 kern_return_t kret = GetDBGState(false); 415 if (kret == KERN_SUCCESS && 416 !IsWatchpointEnabled(m_state.dbg, m_watchpoint_hw_index)) { 417 // The watchpoint might have been disabled by the user. We don't need 418 // to do anything at all 419 // to enable hardware single stepping. 420 m_watchpoint_did_occur = false; 421 m_watchpoint_hw_index = -1; 422 return; 423 } 424 425 DisableHardwareWatchpoint(m_watchpoint_hw_index, false); 426 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 427 "DisableHardwareWatchpoint(%d) called", 428 m_watchpoint_hw_index); 429 430 // Enable hardware single step to move past the watchpoint-triggering 431 // instruction. 432 m_watchpoint_resume_single_step_enabled = 433 (EnableHardwareSingleStep(true) == KERN_SUCCESS); 434 435 // If we are not able to enable single step to move past the 436 // watchpoint-triggering instruction, 437 // at least we should reset the two watchpoint member variables so that 438 // the next time around 439 // this callback function is invoked, the enclosing logical branch is 440 // skipped. 441 if (!m_watchpoint_resume_single_step_enabled) { 442 // Reset the two watchpoint member variables. 443 m_watchpoint_did_occur = false; 444 m_watchpoint_hw_index = -1; 445 DNBLogThreadedIf( 446 LOG_WATCHPOINTS, 447 "DNBArchMachARM::ThreadWillResume() failed to enable single step"); 448 } else 449 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 450 "succeeded to enable single step"); 451 } 452 } 453 } 454 455 bool DNBArchMachARM64::NotifyException(MachException::Data &exc) { 456 457 switch (exc.exc_type) { 458 default: 459 break; 460 case EXC_BREAKPOINT: 461 if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_DA_DEBUG) { 462 // The data break address is passed as exc_data[1]. 463 nub_addr_t addr = exc.exc_data[1]; 464 // Find the hardware index with the side effect of possibly massaging the 465 // addr to return the starting address as seen from the debugger side. 466 uint32_t hw_index = GetHardwareWatchpointHit(addr); 467 468 // One logical watchpoint was split into two watchpoint locations because 469 // it was too big. If the watchpoint exception is indicating the 2nd half 470 // of the two-parter, find the address of the 1st half and report that -- 471 // that's what lldb is going to expect to see. 472 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 473 "watchpoint %d was hit on address " 474 "0x%llx", 475 hw_index, (uint64_t)addr); 476 const int num_watchpoints = NumSupportedHardwareWatchpoints(); 477 for (int i = 0; i < num_watchpoints; i++) { 478 if (LoHi[i] != 0 && LoHi[i] == hw_index && LoHi[i] != i && 479 GetWatchpointAddressByIndex(i) != INVALID_NUB_ADDRESS) { 480 addr = GetWatchpointAddressByIndex(i); 481 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 482 "It is a linked watchpoint; " 483 "rewritten to index %d addr 0x%llx", 484 LoHi[i], (uint64_t)addr); 485 } 486 } 487 488 if (hw_index != INVALID_NUB_HW_INDEX) { 489 m_watchpoint_did_occur = true; 490 m_watchpoint_hw_index = hw_index; 491 exc.exc_data[1] = addr; 492 // Piggyback the hw_index in the exc.data. 493 exc.exc_data.push_back(hw_index); 494 } 495 496 return true; 497 } 498 break; 499 } 500 return false; 501 } 502 503 bool DNBArchMachARM64::ThreadDidStop() { 504 bool success = true; 505 506 m_state.InvalidateAllRegisterStates(); 507 508 if (m_watchpoint_resume_single_step_enabled) { 509 // Great! We now disable the hardware single step as well as re-enable the 510 // hardware watchpoint. 511 // See also ThreadWillResume(). 512 if (EnableHardwareSingleStep(false) == KERN_SUCCESS) { 513 if (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0) { 514 ReenableHardwareWatchpoint(m_watchpoint_hw_index); 515 m_watchpoint_resume_single_step_enabled = false; 516 m_watchpoint_did_occur = false; 517 m_watchpoint_hw_index = -1; 518 } else { 519 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 520 "is true but (m_watchpoint_did_occur && " 521 "m_watchpoint_hw_index >= 0) does not hold!"); 522 } 523 } else { 524 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 525 "is true but unable to disable single step!"); 526 } 527 } 528 529 // Are we stepping a single instruction? 530 if (GetGPRState(true) == KERN_SUCCESS) { 531 // We are single stepping, was this the primary thread? 532 if (m_thread->IsStepping()) { 533 // This was the primary thread, we need to clear the trace 534 // bit if so. 535 success = EnableHardwareSingleStep(false) == KERN_SUCCESS; 536 } else { 537 // The MachThread will automatically restore the suspend count 538 // in ThreadDidStop(), so we don't need to do anything here if 539 // we weren't the primary thread the last time 540 } 541 } 542 return success; 543 } 544 545 // Set the single step bit in the processor status register. 546 kern_return_t DNBArchMachARM64::EnableHardwareSingleStep(bool enable) { 547 DNBError err; 548 DNBLogThreadedIf(LOG_STEP, "%s( enable = %d )", __FUNCTION__, enable); 549 550 err = GetGPRState(false); 551 552 if (err.Fail()) { 553 err.LogThreaded("%s: failed to read the GPR registers", __FUNCTION__); 554 return err.Status(); 555 } 556 557 err = GetDBGState(false); 558 559 if (err.Fail()) { 560 err.LogThreaded("%s: failed to read the DBG registers", __FUNCTION__); 561 return err.Status(); 562 } 563 564 if (enable) { 565 DNBLogThreadedIf(LOG_STEP, 566 "%s: Setting MDSCR_EL1 Single Step bit at pc 0x%llx", 567 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc); 568 m_state.dbg.__mdscr_el1 |= SS_ENABLE; 569 } else { 570 DNBLogThreadedIf(LOG_STEP, 571 "%s: Clearing MDSCR_EL1 Single Step bit at pc 0x%llx", 572 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc); 573 m_state.dbg.__mdscr_el1 &= ~(SS_ENABLE); 574 } 575 576 return SetDBGState(false); 577 } 578 579 // return 1 if bit "BIT" is set in "value" 580 static inline uint32_t bit(uint32_t value, uint32_t bit) { 581 return (value >> bit) & 1u; 582 } 583 584 // return the bitfield "value[msbit:lsbit]". 585 static inline uint64_t bits(uint64_t value, uint32_t msbit, uint32_t lsbit) { 586 assert(msbit >= lsbit); 587 uint64_t shift_left = sizeof(value) * 8 - 1 - msbit; 588 value <<= 589 shift_left; // shift anything above the msbit off of the unsigned edge 590 value >>= shift_left + lsbit; // shift it back again down to the lsbit 591 // (including undoing any shift from above) 592 return value; // return our result 593 } 594 595 uint32_t DNBArchMachARM64::NumSupportedHardwareWatchpoints() { 596 // Set the init value to something that will let us know that we need to 597 // autodetect how many watchpoints are supported dynamically... 598 static uint32_t g_num_supported_hw_watchpoints = UINT_MAX; 599 if (g_num_supported_hw_watchpoints == UINT_MAX) { 600 // Set this to zero in case we can't tell if there are any HW breakpoints 601 g_num_supported_hw_watchpoints = 0; 602 603 size_t len; 604 uint32_t n = 0; 605 len = sizeof(n); 606 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) { 607 g_num_supported_hw_watchpoints = n; 608 DNBLogThreadedIf(LOG_THREAD, "hw.optional.watchpoint=%u", n); 609 } else { 610 // For AArch64 we would need to look at ID_AA64DFR0_EL1 but debugserver runs in 611 // EL0 so it can't 612 // access that reg. The kernel should have filled in the sysctls based on it 613 // though. 614 #if defined(__arm__) 615 uint32_t register_DBGDIDR; 616 617 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 618 uint32_t numWRPs = bits(register_DBGDIDR, 31, 28); 619 // Zero is reserved for the WRP count, so don't increment it if it is zero 620 if (numWRPs > 0) 621 numWRPs++; 622 g_num_supported_hw_watchpoints = numWRPs; 623 DNBLogThreadedIf(LOG_THREAD, 624 "Number of supported hw watchpoints via asm(): %d", 625 g_num_supported_hw_watchpoints); 626 #endif 627 } 628 } 629 return g_num_supported_hw_watchpoints; 630 } 631 632 uint32_t DNBArchMachARM64::EnableHardwareWatchpoint(nub_addr_t addr, 633 nub_size_t size, bool read, 634 bool write, 635 bool also_set_on_task) { 636 DNBLogThreadedIf(LOG_WATCHPOINTS, 637 "DNBArchMachARM64::EnableHardwareWatchpoint(addr = " 638 "0x%8.8llx, size = %zu, read = %u, write = %u)", 639 (uint64_t)addr, size, read, write); 640 641 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 642 643 // Can't watch zero bytes 644 if (size == 0) 645 return INVALID_NUB_HW_INDEX; 646 647 // We must watch for either read or write 648 if (read == false && write == false) 649 return INVALID_NUB_HW_INDEX; 650 651 // Otherwise, can't watch more than 8 bytes per WVR/WCR pair 652 if (size > 8) 653 return INVALID_NUB_HW_INDEX; 654 655 // arm64 watchpoints really have an 8-byte alignment requirement. You can put 656 // a watchpoint on a 4-byte 657 // offset address but you can only watch 4 bytes with that watchpoint. 658 659 // arm64 watchpoints on an 8-byte (double word) aligned addr can watch any 660 // bytes in that 661 // 8-byte long region of memory. They can watch the 1st byte, the 2nd byte, 662 // 3rd byte, etc, or any 663 // combination therein by setting the bits in the BAS [12:5] (Byte Address 664 // Select) field of 665 // the DBGWCRn_EL1 reg for the watchpoint. 666 667 // If the MASK [28:24] bits in the DBGWCRn_EL1 allow a single watchpoint to 668 // monitor a larger region 669 // of memory (16 bytes, 32 bytes, or 2GB) but the Byte Address Select bitfield 670 // then selects a larger 671 // range of bytes, instead of individual bytes. See the ARMv8 Debug 672 // Architecture manual for details. 673 // This implementation does not currently use the MASK bits; the largest 674 // single region watched by a single 675 // watchpoint right now is 8-bytes. 676 677 nub_addr_t aligned_wp_address = addr & ~0x7; 678 uint32_t addr_dword_offset = addr & 0x7; 679 680 // Do we need to split up this logical watchpoint into two hardware watchpoint 681 // registers? 682 // e.g. a watchpoint of length 4 on address 6. We need do this with 683 // one watchpoint on address 0 with bytes 6 & 7 being monitored 684 // one watchpoint on address 8 with bytes 0, 1, 2, 3 being monitored 685 686 if (addr_dword_offset + size > 8) { 687 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 688 "EnableHardwareWatchpoint(addr = " 689 "0x%8.8llx, size = %zu) needs two " 690 "hardware watchpoints slots to monitor", 691 (uint64_t)addr, size); 692 int low_watchpoint_size = 8 - addr_dword_offset; 693 int high_watchpoint_size = addr_dword_offset + size - 8; 694 695 uint32_t lo = EnableHardwareWatchpoint(addr, low_watchpoint_size, read, 696 write, also_set_on_task); 697 if (lo == INVALID_NUB_HW_INDEX) 698 return INVALID_NUB_HW_INDEX; 699 uint32_t hi = 700 EnableHardwareWatchpoint(aligned_wp_address + 8, high_watchpoint_size, 701 read, write, also_set_on_task); 702 if (hi == INVALID_NUB_HW_INDEX) { 703 DisableHardwareWatchpoint(lo, also_set_on_task); 704 return INVALID_NUB_HW_INDEX; 705 } 706 // Tag this lo->hi mapping in our database. 707 LoHi[lo] = hi; 708 return lo; 709 } 710 711 // At this point 712 // 1 aligned_wp_address is the requested address rounded down to 8-byte 713 // alignment 714 // 2 addr_dword_offset is the offset into that double word (8-byte) region 715 // that we are watching 716 // 3 size is the number of bytes within that 8-byte region that we are 717 // watching 718 719 // Set the Byte Address Selects bits DBGWCRn_EL1 bits [12:5] based on the 720 // above. 721 // The bit shift and negation operation will give us 0b11 for 2, 0b1111 for 4, 722 // etc, up to 0b11111111 for 8. 723 // then we shift those bits left by the offset into this dword that we are 724 // interested in. 725 // e.g. if we are watching bytes 4,5,6,7 in a dword we want a BAS of 726 // 0b11110000. 727 uint32_t byte_address_select = ((1 << size) - 1) << addr_dword_offset; 728 729 // Read the debug state 730 kern_return_t kret = GetDBGState(false); 731 732 if (kret == KERN_SUCCESS) { 733 // Check to make sure we have the needed hardware support 734 uint32_t i = 0; 735 736 for (i = 0; i < num_hw_watchpoints; ++i) { 737 if ((m_state.dbg.__wcr[i] & WCR_ENABLE) == 0) 738 break; // We found an available hw watchpoint slot (in i) 739 } 740 741 // See if we found an available hw watchpoint slot above 742 if (i < num_hw_watchpoints) { 743 // DumpDBGState(m_state.dbg); 744 745 // Clear any previous LoHi joined-watchpoint that may have been in use 746 LoHi[i] = 0; 747 748 // shift our Byte Address Select bits up to the correct bit range for the 749 // DBGWCRn_EL1 750 byte_address_select = byte_address_select << 5; 751 752 // Make sure bits 1:0 are clear in our address 753 m_state.dbg.__wvr[i] = aligned_wp_address; // DVA (Data Virtual Address) 754 m_state.dbg.__wcr[i] = byte_address_select | // Which bytes that follow 755 // the DVA that we will watch 756 S_USER | // Stop only in user mode 757 (read ? WCR_LOAD : 0) | // Stop on read access? 758 (write ? WCR_STORE : 0) | // Stop on write access? 759 WCR_ENABLE; // Enable this watchpoint; 760 761 DNBLogThreadedIf( 762 LOG_WATCHPOINTS, "DNBArchMachARM64::EnableHardwareWatchpoint() " 763 "adding watchpoint on address 0x%llx with control " 764 "register value 0x%x", 765 (uint64_t)m_state.dbg.__wvr[i], (uint32_t)m_state.dbg.__wcr[i]); 766 767 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 768 // automatically, don't need to do it here. 769 770 kret = SetDBGState(also_set_on_task); 771 // DumpDBGState(m_state.dbg); 772 773 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 774 "EnableHardwareWatchpoint() " 775 "SetDBGState() => 0x%8.8x.", 776 kret); 777 778 if (kret == KERN_SUCCESS) 779 return i; 780 } else { 781 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 782 "EnableHardwareWatchpoint(): All " 783 "hardware resources (%u) are in use.", 784 num_hw_watchpoints); 785 } 786 } 787 return INVALID_NUB_HW_INDEX; 788 } 789 790 bool DNBArchMachARM64::ReenableHardwareWatchpoint(uint32_t hw_index) { 791 // If this logical watchpoint # is actually implemented using 792 // two hardware watchpoint registers, re-enable both of them. 793 794 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 795 return ReenableHardwareWatchpoint_helper(hw_index) && 796 ReenableHardwareWatchpoint_helper(LoHi[hw_index]); 797 } else { 798 return ReenableHardwareWatchpoint_helper(hw_index); 799 } 800 } 801 802 bool DNBArchMachARM64::ReenableHardwareWatchpoint_helper(uint32_t hw_index) { 803 kern_return_t kret = GetDBGState(false); 804 if (kret != KERN_SUCCESS) 805 return false; 806 807 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 808 if (hw_index >= num_hw_points) 809 return false; 810 811 m_state.dbg.__wvr[hw_index] = m_disabled_watchpoints[hw_index].addr; 812 m_state.dbg.__wcr[hw_index] = m_disabled_watchpoints[hw_index].control; 813 814 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 815 "EnableHardwareWatchpoint( %u ) - WVR%u = " 816 "0x%8.8llx WCR%u = 0x%8.8llx", 817 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 818 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 819 820 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 821 // automatically, don't need to do it here. 822 823 kret = SetDBGState(false); 824 825 return (kret == KERN_SUCCESS); 826 } 827 828 bool DNBArchMachARM64::DisableHardwareWatchpoint(uint32_t hw_index, 829 bool also_set_on_task) { 830 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 831 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task) && 832 DisableHardwareWatchpoint_helper(LoHi[hw_index], also_set_on_task); 833 } else { 834 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task); 835 } 836 } 837 838 bool DNBArchMachARM64::DisableHardwareWatchpoint_helper(uint32_t hw_index, 839 bool also_set_on_task) { 840 kern_return_t kret = GetDBGState(false); 841 if (kret != KERN_SUCCESS) 842 return false; 843 844 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 845 if (hw_index >= num_hw_points) 846 return false; 847 848 m_disabled_watchpoints[hw_index].addr = m_state.dbg.__wvr[hw_index]; 849 m_disabled_watchpoints[hw_index].control = m_state.dbg.__wcr[hw_index]; 850 851 m_state.dbg.__wcr[hw_index] &= ~((nub_addr_t)WCR_ENABLE); 852 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 853 "DisableHardwareWatchpoint( %u ) - WVR%u = " 854 "0x%8.8llx WCR%u = 0x%8.8llx", 855 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 856 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 857 858 kret = SetDBGState(also_set_on_task); 859 860 return (kret == KERN_SUCCESS); 861 } 862 863 // This is for checking the Byte Address Select bits in the DBRWCRn_EL1 control 864 // register. 865 // Returns -1 if the trailing bit patterns are not one of: 866 // { 0b???????1, 0b??????10, 0b?????100, 0b????1000, 0b???10000, 0b??100000, 867 // 0b?1000000, 0b10000000 }. 868 static inline int32_t LowestBitSet(uint32_t val) { 869 for (unsigned i = 0; i < 8; ++i) { 870 if (bit(val, i)) 871 return i; 872 } 873 return -1; 874 } 875 876 // Iterate through the debug registers; return the index of the first watchpoint 877 // whose address matches. 878 // As a side effect, the starting address as understood by the debugger is 879 // returned which could be 880 // different from 'addr' passed as an in/out argument. 881 uint32_t DNBArchMachARM64::GetHardwareWatchpointHit(nub_addr_t &addr) { 882 // Read the debug state 883 kern_return_t kret = GetDBGState(true); 884 // DumpDBGState(m_state.dbg); 885 DNBLogThreadedIf( 886 LOG_WATCHPOINTS, 887 "DNBArchMachARM64::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", 888 kret); 889 DNBLogThreadedIf(LOG_WATCHPOINTS, 890 "DNBArchMachARM64::GetHardwareWatchpointHit() addr = 0x%llx", 891 (uint64_t)addr); 892 893 // This is the watchpoint value to match against, i.e., word address. 894 nub_addr_t wp_val = addr & ~((nub_addr_t)3); 895 if (kret == KERN_SUCCESS) { 896 DBG &debug_state = m_state.dbg; 897 uint32_t i, num = NumSupportedHardwareWatchpoints(); 898 for (i = 0; i < num; ++i) { 899 nub_addr_t wp_addr = GetWatchAddress(debug_state, i); 900 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM64::" 901 "GetHardwareWatchpointHit() slot: %u " 902 "(addr = 0x%llx).", 903 i, (uint64_t)wp_addr); 904 if (wp_val == wp_addr) { 905 uint32_t byte_mask = bits(debug_state.__wcr[i], 12, 5); 906 907 // Sanity check the byte_mask, first. 908 if (LowestBitSet(byte_mask) < 0) 909 continue; 910 911 // Check that the watchpoint is enabled. 912 if (!IsWatchpointEnabled(debug_state, i)) 913 continue; 914 915 // Compute the starting address (from the point of view of the 916 // debugger). 917 addr = wp_addr + LowestBitSet(byte_mask); 918 return i; 919 } 920 } 921 } 922 return INVALID_NUB_HW_INDEX; 923 } 924 925 nub_addr_t DNBArchMachARM64::GetWatchpointAddressByIndex(uint32_t hw_index) { 926 kern_return_t kret = GetDBGState(true); 927 if (kret != KERN_SUCCESS) 928 return INVALID_NUB_ADDRESS; 929 const uint32_t num = NumSupportedHardwareWatchpoints(); 930 if (hw_index >= num) 931 return INVALID_NUB_ADDRESS; 932 if (IsWatchpointEnabled(m_state.dbg, hw_index)) 933 return GetWatchAddress(m_state.dbg, hw_index); 934 return INVALID_NUB_ADDRESS; 935 } 936 937 bool DNBArchMachARM64::IsWatchpointEnabled(const DBG &debug_state, 938 uint32_t hw_index) { 939 // Watchpoint Control Registers, bitfield definitions 940 // ... 941 // Bits Value Description 942 // [0] 0 Watchpoint disabled 943 // 1 Watchpoint enabled. 944 return (debug_state.__wcr[hw_index] & 1u); 945 } 946 947 nub_addr_t DNBArchMachARM64::GetWatchAddress(const DBG &debug_state, 948 uint32_t hw_index) { 949 // Watchpoint Value Registers, bitfield definitions 950 // Bits Description 951 // [31:2] Watchpoint value (word address, i.e., 4-byte aligned) 952 // [1:0] RAZ/SBZP 953 return bits(debug_state.__wvr[hw_index], 63, 0); 954 } 955 956 // Register information definitions for 64 bit ARMv8. 957 enum gpr_regnums { 958 gpr_x0 = 0, 959 gpr_x1, 960 gpr_x2, 961 gpr_x3, 962 gpr_x4, 963 gpr_x5, 964 gpr_x6, 965 gpr_x7, 966 gpr_x8, 967 gpr_x9, 968 gpr_x10, 969 gpr_x11, 970 gpr_x12, 971 gpr_x13, 972 gpr_x14, 973 gpr_x15, 974 gpr_x16, 975 gpr_x17, 976 gpr_x18, 977 gpr_x19, 978 gpr_x20, 979 gpr_x21, 980 gpr_x22, 981 gpr_x23, 982 gpr_x24, 983 gpr_x25, 984 gpr_x26, 985 gpr_x27, 986 gpr_x28, 987 gpr_fp, 988 gpr_x29 = gpr_fp, 989 gpr_lr, 990 gpr_x30 = gpr_lr, 991 gpr_sp, 992 gpr_x31 = gpr_sp, 993 gpr_pc, 994 gpr_cpsr, 995 gpr_w0, 996 gpr_w1, 997 gpr_w2, 998 gpr_w3, 999 gpr_w4, 1000 gpr_w5, 1001 gpr_w6, 1002 gpr_w7, 1003 gpr_w8, 1004 gpr_w9, 1005 gpr_w10, 1006 gpr_w11, 1007 gpr_w12, 1008 gpr_w13, 1009 gpr_w14, 1010 gpr_w15, 1011 gpr_w16, 1012 gpr_w17, 1013 gpr_w18, 1014 gpr_w19, 1015 gpr_w20, 1016 gpr_w21, 1017 gpr_w22, 1018 gpr_w23, 1019 gpr_w24, 1020 gpr_w25, 1021 gpr_w26, 1022 gpr_w27, 1023 gpr_w28 1024 1025 }; 1026 1027 enum { 1028 vfp_v0 = 0, 1029 vfp_v1, 1030 vfp_v2, 1031 vfp_v3, 1032 vfp_v4, 1033 vfp_v5, 1034 vfp_v6, 1035 vfp_v7, 1036 vfp_v8, 1037 vfp_v9, 1038 vfp_v10, 1039 vfp_v11, 1040 vfp_v12, 1041 vfp_v13, 1042 vfp_v14, 1043 vfp_v15, 1044 vfp_v16, 1045 vfp_v17, 1046 vfp_v18, 1047 vfp_v19, 1048 vfp_v20, 1049 vfp_v21, 1050 vfp_v22, 1051 vfp_v23, 1052 vfp_v24, 1053 vfp_v25, 1054 vfp_v26, 1055 vfp_v27, 1056 vfp_v28, 1057 vfp_v29, 1058 vfp_v30, 1059 vfp_v31, 1060 vfp_fpsr, 1061 vfp_fpcr, 1062 1063 // lower 32 bits of the corresponding vfp_v<n> reg. 1064 vfp_s0, 1065 vfp_s1, 1066 vfp_s2, 1067 vfp_s3, 1068 vfp_s4, 1069 vfp_s5, 1070 vfp_s6, 1071 vfp_s7, 1072 vfp_s8, 1073 vfp_s9, 1074 vfp_s10, 1075 vfp_s11, 1076 vfp_s12, 1077 vfp_s13, 1078 vfp_s14, 1079 vfp_s15, 1080 vfp_s16, 1081 vfp_s17, 1082 vfp_s18, 1083 vfp_s19, 1084 vfp_s20, 1085 vfp_s21, 1086 vfp_s22, 1087 vfp_s23, 1088 vfp_s24, 1089 vfp_s25, 1090 vfp_s26, 1091 vfp_s27, 1092 vfp_s28, 1093 vfp_s29, 1094 vfp_s30, 1095 vfp_s31, 1096 1097 // lower 64 bits of the corresponding vfp_v<n> reg. 1098 vfp_d0, 1099 vfp_d1, 1100 vfp_d2, 1101 vfp_d3, 1102 vfp_d4, 1103 vfp_d5, 1104 vfp_d6, 1105 vfp_d7, 1106 vfp_d8, 1107 vfp_d9, 1108 vfp_d10, 1109 vfp_d11, 1110 vfp_d12, 1111 vfp_d13, 1112 vfp_d14, 1113 vfp_d15, 1114 vfp_d16, 1115 vfp_d17, 1116 vfp_d18, 1117 vfp_d19, 1118 vfp_d20, 1119 vfp_d21, 1120 vfp_d22, 1121 vfp_d23, 1122 vfp_d24, 1123 vfp_d25, 1124 vfp_d26, 1125 vfp_d27, 1126 vfp_d28, 1127 vfp_d29, 1128 vfp_d30, 1129 vfp_d31 1130 }; 1131 1132 enum { exc_far = 0, exc_esr, exc_exception }; 1133 1134 // These numbers from the "DWARF for the ARM 64-bit Architecture (AArch64)" 1135 // document. 1136 1137 enum { 1138 dwarf_x0 = 0, 1139 dwarf_x1, 1140 dwarf_x2, 1141 dwarf_x3, 1142 dwarf_x4, 1143 dwarf_x5, 1144 dwarf_x6, 1145 dwarf_x7, 1146 dwarf_x8, 1147 dwarf_x9, 1148 dwarf_x10, 1149 dwarf_x11, 1150 dwarf_x12, 1151 dwarf_x13, 1152 dwarf_x14, 1153 dwarf_x15, 1154 dwarf_x16, 1155 dwarf_x17, 1156 dwarf_x18, 1157 dwarf_x19, 1158 dwarf_x20, 1159 dwarf_x21, 1160 dwarf_x22, 1161 dwarf_x23, 1162 dwarf_x24, 1163 dwarf_x25, 1164 dwarf_x26, 1165 dwarf_x27, 1166 dwarf_x28, 1167 dwarf_x29, 1168 dwarf_x30, 1169 dwarf_x31, 1170 dwarf_pc = 32, 1171 dwarf_elr_mode = 33, 1172 dwarf_fp = dwarf_x29, 1173 dwarf_lr = dwarf_x30, 1174 dwarf_sp = dwarf_x31, 1175 // 34-63 reserved 1176 1177 // V0-V31 (128 bit vector registers) 1178 dwarf_v0 = 64, 1179 dwarf_v1, 1180 dwarf_v2, 1181 dwarf_v3, 1182 dwarf_v4, 1183 dwarf_v5, 1184 dwarf_v6, 1185 dwarf_v7, 1186 dwarf_v8, 1187 dwarf_v9, 1188 dwarf_v10, 1189 dwarf_v11, 1190 dwarf_v12, 1191 dwarf_v13, 1192 dwarf_v14, 1193 dwarf_v15, 1194 dwarf_v16, 1195 dwarf_v17, 1196 dwarf_v18, 1197 dwarf_v19, 1198 dwarf_v20, 1199 dwarf_v21, 1200 dwarf_v22, 1201 dwarf_v23, 1202 dwarf_v24, 1203 dwarf_v25, 1204 dwarf_v26, 1205 dwarf_v27, 1206 dwarf_v28, 1207 dwarf_v29, 1208 dwarf_v30, 1209 dwarf_v31 1210 1211 // 96-127 reserved 1212 }; 1213 1214 enum { 1215 debugserver_gpr_x0 = 0, 1216 debugserver_gpr_x1, 1217 debugserver_gpr_x2, 1218 debugserver_gpr_x3, 1219 debugserver_gpr_x4, 1220 debugserver_gpr_x5, 1221 debugserver_gpr_x6, 1222 debugserver_gpr_x7, 1223 debugserver_gpr_x8, 1224 debugserver_gpr_x9, 1225 debugserver_gpr_x10, 1226 debugserver_gpr_x11, 1227 debugserver_gpr_x12, 1228 debugserver_gpr_x13, 1229 debugserver_gpr_x14, 1230 debugserver_gpr_x15, 1231 debugserver_gpr_x16, 1232 debugserver_gpr_x17, 1233 debugserver_gpr_x18, 1234 debugserver_gpr_x19, 1235 debugserver_gpr_x20, 1236 debugserver_gpr_x21, 1237 debugserver_gpr_x22, 1238 debugserver_gpr_x23, 1239 debugserver_gpr_x24, 1240 debugserver_gpr_x25, 1241 debugserver_gpr_x26, 1242 debugserver_gpr_x27, 1243 debugserver_gpr_x28, 1244 debugserver_gpr_fp, // x29 1245 debugserver_gpr_lr, // x30 1246 debugserver_gpr_sp, // sp aka xsp 1247 debugserver_gpr_pc, 1248 debugserver_gpr_cpsr, 1249 debugserver_vfp_v0, 1250 debugserver_vfp_v1, 1251 debugserver_vfp_v2, 1252 debugserver_vfp_v3, 1253 debugserver_vfp_v4, 1254 debugserver_vfp_v5, 1255 debugserver_vfp_v6, 1256 debugserver_vfp_v7, 1257 debugserver_vfp_v8, 1258 debugserver_vfp_v9, 1259 debugserver_vfp_v10, 1260 debugserver_vfp_v11, 1261 debugserver_vfp_v12, 1262 debugserver_vfp_v13, 1263 debugserver_vfp_v14, 1264 debugserver_vfp_v15, 1265 debugserver_vfp_v16, 1266 debugserver_vfp_v17, 1267 debugserver_vfp_v18, 1268 debugserver_vfp_v19, 1269 debugserver_vfp_v20, 1270 debugserver_vfp_v21, 1271 debugserver_vfp_v22, 1272 debugserver_vfp_v23, 1273 debugserver_vfp_v24, 1274 debugserver_vfp_v25, 1275 debugserver_vfp_v26, 1276 debugserver_vfp_v27, 1277 debugserver_vfp_v28, 1278 debugserver_vfp_v29, 1279 debugserver_vfp_v30, 1280 debugserver_vfp_v31, 1281 debugserver_vfp_fpsr, 1282 debugserver_vfp_fpcr 1283 }; 1284 1285 const char *g_contained_x0[]{"x0", NULL}; 1286 const char *g_contained_x1[]{"x1", NULL}; 1287 const char *g_contained_x2[]{"x2", NULL}; 1288 const char *g_contained_x3[]{"x3", NULL}; 1289 const char *g_contained_x4[]{"x4", NULL}; 1290 const char *g_contained_x5[]{"x5", NULL}; 1291 const char *g_contained_x6[]{"x6", NULL}; 1292 const char *g_contained_x7[]{"x7", NULL}; 1293 const char *g_contained_x8[]{"x8", NULL}; 1294 const char *g_contained_x9[]{"x9", NULL}; 1295 const char *g_contained_x10[]{"x10", NULL}; 1296 const char *g_contained_x11[]{"x11", NULL}; 1297 const char *g_contained_x12[]{"x12", NULL}; 1298 const char *g_contained_x13[]{"x13", NULL}; 1299 const char *g_contained_x14[]{"x14", NULL}; 1300 const char *g_contained_x15[]{"x15", NULL}; 1301 const char *g_contained_x16[]{"x16", NULL}; 1302 const char *g_contained_x17[]{"x17", NULL}; 1303 const char *g_contained_x18[]{"x18", NULL}; 1304 const char *g_contained_x19[]{"x19", NULL}; 1305 const char *g_contained_x20[]{"x20", NULL}; 1306 const char *g_contained_x21[]{"x21", NULL}; 1307 const char *g_contained_x22[]{"x22", NULL}; 1308 const char *g_contained_x23[]{"x23", NULL}; 1309 const char *g_contained_x24[]{"x24", NULL}; 1310 const char *g_contained_x25[]{"x25", NULL}; 1311 const char *g_contained_x26[]{"x26", NULL}; 1312 const char *g_contained_x27[]{"x27", NULL}; 1313 const char *g_contained_x28[]{"x28", NULL}; 1314 1315 const char *g_invalidate_x0[]{"x0", "w0", NULL}; 1316 const char *g_invalidate_x1[]{"x1", "w1", NULL}; 1317 const char *g_invalidate_x2[]{"x2", "w2", NULL}; 1318 const char *g_invalidate_x3[]{"x3", "w3", NULL}; 1319 const char *g_invalidate_x4[]{"x4", "w4", NULL}; 1320 const char *g_invalidate_x5[]{"x5", "w5", NULL}; 1321 const char *g_invalidate_x6[]{"x6", "w6", NULL}; 1322 const char *g_invalidate_x7[]{"x7", "w7", NULL}; 1323 const char *g_invalidate_x8[]{"x8", "w8", NULL}; 1324 const char *g_invalidate_x9[]{"x9", "w9", NULL}; 1325 const char *g_invalidate_x10[]{"x10", "w10", NULL}; 1326 const char *g_invalidate_x11[]{"x11", "w11", NULL}; 1327 const char *g_invalidate_x12[]{"x12", "w12", NULL}; 1328 const char *g_invalidate_x13[]{"x13", "w13", NULL}; 1329 const char *g_invalidate_x14[]{"x14", "w14", NULL}; 1330 const char *g_invalidate_x15[]{"x15", "w15", NULL}; 1331 const char *g_invalidate_x16[]{"x16", "w16", NULL}; 1332 const char *g_invalidate_x17[]{"x17", "w17", NULL}; 1333 const char *g_invalidate_x18[]{"x18", "w18", NULL}; 1334 const char *g_invalidate_x19[]{"x19", "w19", NULL}; 1335 const char *g_invalidate_x20[]{"x20", "w20", NULL}; 1336 const char *g_invalidate_x21[]{"x21", "w21", NULL}; 1337 const char *g_invalidate_x22[]{"x22", "w22", NULL}; 1338 const char *g_invalidate_x23[]{"x23", "w23", NULL}; 1339 const char *g_invalidate_x24[]{"x24", "w24", NULL}; 1340 const char *g_invalidate_x25[]{"x25", "w25", NULL}; 1341 const char *g_invalidate_x26[]{"x26", "w26", NULL}; 1342 const char *g_invalidate_x27[]{"x27", "w27", NULL}; 1343 const char *g_invalidate_x28[]{"x28", "w28", NULL}; 1344 1345 #define GPR_OFFSET_IDX(idx) (offsetof(DNBArchMachARM64::GPR, __x[idx])) 1346 1347 #define GPR_OFFSET_NAME(reg) (offsetof(DNBArchMachARM64::GPR, __##reg)) 1348 1349 // These macros will auto define the register name, alt name, register size, 1350 // register offset, encoding, format and native register. This ensures that 1351 // the register state structures are defined correctly and have the correct 1352 // sizes and offsets. 1353 #define DEFINE_GPR_IDX(idx, reg, alt, gen) \ 1354 { \ 1355 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_IDX(idx), \ 1356 dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, \ 1357 g_invalidate_x##idx \ 1358 } 1359 #define DEFINE_GPR_NAME(reg, alt, gen) \ 1360 { \ 1361 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 8, GPR_OFFSET_NAME(reg), \ 1362 dwarf_##reg, dwarf_##reg, gen, debugserver_gpr_##reg, NULL, NULL \ 1363 } 1364 #define DEFINE_PSEUDO_GPR_IDX(idx, reg) \ 1365 { \ 1366 e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, 4, 0, INVALID_NUB_REGNUM, \ 1367 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1368 g_contained_x##idx, g_invalidate_x##idx \ 1369 } 1370 1371 //_STRUCT_ARM_THREAD_STATE64 1372 //{ 1373 // uint64_t x[29]; /* General purpose registers x0-x28 */ 1374 // uint64_t fp; /* Frame pointer x29 */ 1375 // uint64_t lr; /* Link register x30 */ 1376 // uint64_t sp; /* Stack pointer x31 */ 1377 // uint64_t pc; /* Program counter */ 1378 // uint32_t cpsr; /* Current program status register */ 1379 //}; 1380 1381 // General purpose registers 1382 const DNBRegisterInfo DNBArchMachARM64::g_gpr_registers[] = { 1383 DEFINE_GPR_IDX(0, x0, "arg1", GENERIC_REGNUM_ARG1), 1384 DEFINE_GPR_IDX(1, x1, "arg2", GENERIC_REGNUM_ARG2), 1385 DEFINE_GPR_IDX(2, x2, "arg3", GENERIC_REGNUM_ARG3), 1386 DEFINE_GPR_IDX(3, x3, "arg4", GENERIC_REGNUM_ARG4), 1387 DEFINE_GPR_IDX(4, x4, "arg5", GENERIC_REGNUM_ARG5), 1388 DEFINE_GPR_IDX(5, x5, "arg6", GENERIC_REGNUM_ARG6), 1389 DEFINE_GPR_IDX(6, x6, "arg7", GENERIC_REGNUM_ARG7), 1390 DEFINE_GPR_IDX(7, x7, "arg8", GENERIC_REGNUM_ARG8), 1391 DEFINE_GPR_IDX(8, x8, NULL, INVALID_NUB_REGNUM), 1392 DEFINE_GPR_IDX(9, x9, NULL, INVALID_NUB_REGNUM), 1393 DEFINE_GPR_IDX(10, x10, NULL, INVALID_NUB_REGNUM), 1394 DEFINE_GPR_IDX(11, x11, NULL, INVALID_NUB_REGNUM), 1395 DEFINE_GPR_IDX(12, x12, NULL, INVALID_NUB_REGNUM), 1396 DEFINE_GPR_IDX(13, x13, NULL, INVALID_NUB_REGNUM), 1397 DEFINE_GPR_IDX(14, x14, NULL, INVALID_NUB_REGNUM), 1398 DEFINE_GPR_IDX(15, x15, NULL, INVALID_NUB_REGNUM), 1399 DEFINE_GPR_IDX(16, x16, NULL, INVALID_NUB_REGNUM), 1400 DEFINE_GPR_IDX(17, x17, NULL, INVALID_NUB_REGNUM), 1401 DEFINE_GPR_IDX(18, x18, NULL, INVALID_NUB_REGNUM), 1402 DEFINE_GPR_IDX(19, x19, NULL, INVALID_NUB_REGNUM), 1403 DEFINE_GPR_IDX(20, x20, NULL, INVALID_NUB_REGNUM), 1404 DEFINE_GPR_IDX(21, x21, NULL, INVALID_NUB_REGNUM), 1405 DEFINE_GPR_IDX(22, x22, NULL, INVALID_NUB_REGNUM), 1406 DEFINE_GPR_IDX(23, x23, NULL, INVALID_NUB_REGNUM), 1407 DEFINE_GPR_IDX(24, x24, NULL, INVALID_NUB_REGNUM), 1408 DEFINE_GPR_IDX(25, x25, NULL, INVALID_NUB_REGNUM), 1409 DEFINE_GPR_IDX(26, x26, NULL, INVALID_NUB_REGNUM), 1410 DEFINE_GPR_IDX(27, x27, NULL, INVALID_NUB_REGNUM), 1411 DEFINE_GPR_IDX(28, x28, NULL, INVALID_NUB_REGNUM), 1412 DEFINE_GPR_NAME(fp, "x29", GENERIC_REGNUM_FP), 1413 DEFINE_GPR_NAME(lr, "x30", GENERIC_REGNUM_RA), 1414 DEFINE_GPR_NAME(sp, "xsp", GENERIC_REGNUM_SP), 1415 DEFINE_GPR_NAME(pc, NULL, GENERIC_REGNUM_PC), 1416 1417 // in armv7 we specify that writing to the CPSR should invalidate r8-12, sp, 1418 // lr. 1419 // this should be specified for arm64 too even though debugserver is only 1420 // used for 1421 // userland debugging. 1422 {e_regSetGPR, gpr_cpsr, "cpsr", "flags", Uint, Hex, 4, 1423 GPR_OFFSET_NAME(cpsr), dwarf_elr_mode, dwarf_elr_mode, INVALID_NUB_REGNUM, 1424 debugserver_gpr_cpsr, NULL, NULL}, 1425 1426 DEFINE_PSEUDO_GPR_IDX(0, w0), 1427 DEFINE_PSEUDO_GPR_IDX(1, w1), 1428 DEFINE_PSEUDO_GPR_IDX(2, w2), 1429 DEFINE_PSEUDO_GPR_IDX(3, w3), 1430 DEFINE_PSEUDO_GPR_IDX(4, w4), 1431 DEFINE_PSEUDO_GPR_IDX(5, w5), 1432 DEFINE_PSEUDO_GPR_IDX(6, w6), 1433 DEFINE_PSEUDO_GPR_IDX(7, w7), 1434 DEFINE_PSEUDO_GPR_IDX(8, w8), 1435 DEFINE_PSEUDO_GPR_IDX(9, w9), 1436 DEFINE_PSEUDO_GPR_IDX(10, w10), 1437 DEFINE_PSEUDO_GPR_IDX(11, w11), 1438 DEFINE_PSEUDO_GPR_IDX(12, w12), 1439 DEFINE_PSEUDO_GPR_IDX(13, w13), 1440 DEFINE_PSEUDO_GPR_IDX(14, w14), 1441 DEFINE_PSEUDO_GPR_IDX(15, w15), 1442 DEFINE_PSEUDO_GPR_IDX(16, w16), 1443 DEFINE_PSEUDO_GPR_IDX(17, w17), 1444 DEFINE_PSEUDO_GPR_IDX(18, w18), 1445 DEFINE_PSEUDO_GPR_IDX(19, w19), 1446 DEFINE_PSEUDO_GPR_IDX(20, w20), 1447 DEFINE_PSEUDO_GPR_IDX(21, w21), 1448 DEFINE_PSEUDO_GPR_IDX(22, w22), 1449 DEFINE_PSEUDO_GPR_IDX(23, w23), 1450 DEFINE_PSEUDO_GPR_IDX(24, w24), 1451 DEFINE_PSEUDO_GPR_IDX(25, w25), 1452 DEFINE_PSEUDO_GPR_IDX(26, w26), 1453 DEFINE_PSEUDO_GPR_IDX(27, w27), 1454 DEFINE_PSEUDO_GPR_IDX(28, w28)}; 1455 1456 const char *g_contained_v0[]{"v0", NULL}; 1457 const char *g_contained_v1[]{"v1", NULL}; 1458 const char *g_contained_v2[]{"v2", NULL}; 1459 const char *g_contained_v3[]{"v3", NULL}; 1460 const char *g_contained_v4[]{"v4", NULL}; 1461 const char *g_contained_v5[]{"v5", NULL}; 1462 const char *g_contained_v6[]{"v6", NULL}; 1463 const char *g_contained_v7[]{"v7", NULL}; 1464 const char *g_contained_v8[]{"v8", NULL}; 1465 const char *g_contained_v9[]{"v9", NULL}; 1466 const char *g_contained_v10[]{"v10", NULL}; 1467 const char *g_contained_v11[]{"v11", NULL}; 1468 const char *g_contained_v12[]{"v12", NULL}; 1469 const char *g_contained_v13[]{"v13", NULL}; 1470 const char *g_contained_v14[]{"v14", NULL}; 1471 const char *g_contained_v15[]{"v15", NULL}; 1472 const char *g_contained_v16[]{"v16", NULL}; 1473 const char *g_contained_v17[]{"v17", NULL}; 1474 const char *g_contained_v18[]{"v18", NULL}; 1475 const char *g_contained_v19[]{"v19", NULL}; 1476 const char *g_contained_v20[]{"v20", NULL}; 1477 const char *g_contained_v21[]{"v21", NULL}; 1478 const char *g_contained_v22[]{"v22", NULL}; 1479 const char *g_contained_v23[]{"v23", NULL}; 1480 const char *g_contained_v24[]{"v24", NULL}; 1481 const char *g_contained_v25[]{"v25", NULL}; 1482 const char *g_contained_v26[]{"v26", NULL}; 1483 const char *g_contained_v27[]{"v27", NULL}; 1484 const char *g_contained_v28[]{"v28", NULL}; 1485 const char *g_contained_v29[]{"v29", NULL}; 1486 const char *g_contained_v30[]{"v30", NULL}; 1487 const char *g_contained_v31[]{"v31", NULL}; 1488 1489 const char *g_invalidate_v0[]{"v0", "d0", "s0", NULL}; 1490 const char *g_invalidate_v1[]{"v1", "d1", "s1", NULL}; 1491 const char *g_invalidate_v2[]{"v2", "d2", "s2", NULL}; 1492 const char *g_invalidate_v3[]{"v3", "d3", "s3", NULL}; 1493 const char *g_invalidate_v4[]{"v4", "d4", "s4", NULL}; 1494 const char *g_invalidate_v5[]{"v5", "d5", "s5", NULL}; 1495 const char *g_invalidate_v6[]{"v6", "d6", "s6", NULL}; 1496 const char *g_invalidate_v7[]{"v7", "d7", "s7", NULL}; 1497 const char *g_invalidate_v8[]{"v8", "d8", "s8", NULL}; 1498 const char *g_invalidate_v9[]{"v9", "d9", "s9", NULL}; 1499 const char *g_invalidate_v10[]{"v10", "d10", "s10", NULL}; 1500 const char *g_invalidate_v11[]{"v11", "d11", "s11", NULL}; 1501 const char *g_invalidate_v12[]{"v12", "d12", "s12", NULL}; 1502 const char *g_invalidate_v13[]{"v13", "d13", "s13", NULL}; 1503 const char *g_invalidate_v14[]{"v14", "d14", "s14", NULL}; 1504 const char *g_invalidate_v15[]{"v15", "d15", "s15", NULL}; 1505 const char *g_invalidate_v16[]{"v16", "d16", "s16", NULL}; 1506 const char *g_invalidate_v17[]{"v17", "d17", "s17", NULL}; 1507 const char *g_invalidate_v18[]{"v18", "d18", "s18", NULL}; 1508 const char *g_invalidate_v19[]{"v19", "d19", "s19", NULL}; 1509 const char *g_invalidate_v20[]{"v20", "d20", "s20", NULL}; 1510 const char *g_invalidate_v21[]{"v21", "d21", "s21", NULL}; 1511 const char *g_invalidate_v22[]{"v22", "d22", "s22", NULL}; 1512 const char *g_invalidate_v23[]{"v23", "d23", "s23", NULL}; 1513 const char *g_invalidate_v24[]{"v24", "d24", "s24", NULL}; 1514 const char *g_invalidate_v25[]{"v25", "d25", "s25", NULL}; 1515 const char *g_invalidate_v26[]{"v26", "d26", "s26", NULL}; 1516 const char *g_invalidate_v27[]{"v27", "d27", "s27", NULL}; 1517 const char *g_invalidate_v28[]{"v28", "d28", "s28", NULL}; 1518 const char *g_invalidate_v29[]{"v29", "d29", "s29", NULL}; 1519 const char *g_invalidate_v30[]{"v30", "d30", "s30", NULL}; 1520 const char *g_invalidate_v31[]{"v31", "d31", "s31", NULL}; 1521 1522 #if defined(__arm64__) || defined(__aarch64__) 1523 #define VFP_V_OFFSET_IDX(idx) \ 1524 (offsetof(DNBArchMachARM64::FPU, __v) + (idx * 16) + \ 1525 offsetof(DNBArchMachARM64::Context, vfp)) 1526 #else 1527 #define VFP_V_OFFSET_IDX(idx) \ 1528 (offsetof(DNBArchMachARM64::FPU, opaque) + (idx * 16) + \ 1529 offsetof(DNBArchMachARM64::Context, vfp)) 1530 #endif 1531 #define VFP_OFFSET_NAME(reg) \ 1532 (offsetof(DNBArchMachARM64::FPU, reg) + \ 1533 offsetof(DNBArchMachARM64::Context, vfp)) 1534 #define EXC_OFFSET(reg) \ 1535 (offsetof(DNBArchMachARM64::EXC, reg) + \ 1536 offsetof(DNBArchMachARM64::Context, exc)) 1537 1538 //#define FLOAT_FORMAT Float 1539 #define DEFINE_VFP_V_IDX(idx) \ 1540 { \ 1541 e_regSetVFP, vfp_v##idx, "v" #idx, "q" #idx, Vector, VectorOfUInt8, 16, \ 1542 VFP_V_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_v##idx, \ 1543 INVALID_NUB_REGNUM, debugserver_vfp_v##idx, NULL, g_invalidate_v##idx \ 1544 } 1545 #define DEFINE_PSEUDO_VFP_S_IDX(idx) \ 1546 { \ 1547 e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, Float, 4, 0, \ 1548 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1549 INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \ 1550 } 1551 #define DEFINE_PSEUDO_VFP_D_IDX(idx) \ 1552 { \ 1553 e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, Float, 8, 0, \ 1554 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, \ 1555 INVALID_NUB_REGNUM, g_contained_v##idx, g_invalidate_v##idx \ 1556 } 1557 1558 // Floating point registers 1559 const DNBRegisterInfo DNBArchMachARM64::g_vfp_registers[] = { 1560 DEFINE_VFP_V_IDX(0), 1561 DEFINE_VFP_V_IDX(1), 1562 DEFINE_VFP_V_IDX(2), 1563 DEFINE_VFP_V_IDX(3), 1564 DEFINE_VFP_V_IDX(4), 1565 DEFINE_VFP_V_IDX(5), 1566 DEFINE_VFP_V_IDX(6), 1567 DEFINE_VFP_V_IDX(7), 1568 DEFINE_VFP_V_IDX(8), 1569 DEFINE_VFP_V_IDX(9), 1570 DEFINE_VFP_V_IDX(10), 1571 DEFINE_VFP_V_IDX(11), 1572 DEFINE_VFP_V_IDX(12), 1573 DEFINE_VFP_V_IDX(13), 1574 DEFINE_VFP_V_IDX(14), 1575 DEFINE_VFP_V_IDX(15), 1576 DEFINE_VFP_V_IDX(16), 1577 DEFINE_VFP_V_IDX(17), 1578 DEFINE_VFP_V_IDX(18), 1579 DEFINE_VFP_V_IDX(19), 1580 DEFINE_VFP_V_IDX(20), 1581 DEFINE_VFP_V_IDX(21), 1582 DEFINE_VFP_V_IDX(22), 1583 DEFINE_VFP_V_IDX(23), 1584 DEFINE_VFP_V_IDX(24), 1585 DEFINE_VFP_V_IDX(25), 1586 DEFINE_VFP_V_IDX(26), 1587 DEFINE_VFP_V_IDX(27), 1588 DEFINE_VFP_V_IDX(28), 1589 DEFINE_VFP_V_IDX(29), 1590 DEFINE_VFP_V_IDX(30), 1591 DEFINE_VFP_V_IDX(31), 1592 {e_regSetVFP, vfp_fpsr, "fpsr", NULL, Uint, Hex, 4, 1593 VFP_V_OFFSET_IDX(32) + 0, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1594 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}, 1595 {e_regSetVFP, vfp_fpcr, "fpcr", NULL, Uint, Hex, 4, 1596 VFP_V_OFFSET_IDX(32) + 4, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1597 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}, 1598 1599 DEFINE_PSEUDO_VFP_S_IDX(0), 1600 DEFINE_PSEUDO_VFP_S_IDX(1), 1601 DEFINE_PSEUDO_VFP_S_IDX(2), 1602 DEFINE_PSEUDO_VFP_S_IDX(3), 1603 DEFINE_PSEUDO_VFP_S_IDX(4), 1604 DEFINE_PSEUDO_VFP_S_IDX(5), 1605 DEFINE_PSEUDO_VFP_S_IDX(6), 1606 DEFINE_PSEUDO_VFP_S_IDX(7), 1607 DEFINE_PSEUDO_VFP_S_IDX(8), 1608 DEFINE_PSEUDO_VFP_S_IDX(9), 1609 DEFINE_PSEUDO_VFP_S_IDX(10), 1610 DEFINE_PSEUDO_VFP_S_IDX(11), 1611 DEFINE_PSEUDO_VFP_S_IDX(12), 1612 DEFINE_PSEUDO_VFP_S_IDX(13), 1613 DEFINE_PSEUDO_VFP_S_IDX(14), 1614 DEFINE_PSEUDO_VFP_S_IDX(15), 1615 DEFINE_PSEUDO_VFP_S_IDX(16), 1616 DEFINE_PSEUDO_VFP_S_IDX(17), 1617 DEFINE_PSEUDO_VFP_S_IDX(18), 1618 DEFINE_PSEUDO_VFP_S_IDX(19), 1619 DEFINE_PSEUDO_VFP_S_IDX(20), 1620 DEFINE_PSEUDO_VFP_S_IDX(21), 1621 DEFINE_PSEUDO_VFP_S_IDX(22), 1622 DEFINE_PSEUDO_VFP_S_IDX(23), 1623 DEFINE_PSEUDO_VFP_S_IDX(24), 1624 DEFINE_PSEUDO_VFP_S_IDX(25), 1625 DEFINE_PSEUDO_VFP_S_IDX(26), 1626 DEFINE_PSEUDO_VFP_S_IDX(27), 1627 DEFINE_PSEUDO_VFP_S_IDX(28), 1628 DEFINE_PSEUDO_VFP_S_IDX(29), 1629 DEFINE_PSEUDO_VFP_S_IDX(30), 1630 DEFINE_PSEUDO_VFP_S_IDX(31), 1631 1632 DEFINE_PSEUDO_VFP_D_IDX(0), 1633 DEFINE_PSEUDO_VFP_D_IDX(1), 1634 DEFINE_PSEUDO_VFP_D_IDX(2), 1635 DEFINE_PSEUDO_VFP_D_IDX(3), 1636 DEFINE_PSEUDO_VFP_D_IDX(4), 1637 DEFINE_PSEUDO_VFP_D_IDX(5), 1638 DEFINE_PSEUDO_VFP_D_IDX(6), 1639 DEFINE_PSEUDO_VFP_D_IDX(7), 1640 DEFINE_PSEUDO_VFP_D_IDX(8), 1641 DEFINE_PSEUDO_VFP_D_IDX(9), 1642 DEFINE_PSEUDO_VFP_D_IDX(10), 1643 DEFINE_PSEUDO_VFP_D_IDX(11), 1644 DEFINE_PSEUDO_VFP_D_IDX(12), 1645 DEFINE_PSEUDO_VFP_D_IDX(13), 1646 DEFINE_PSEUDO_VFP_D_IDX(14), 1647 DEFINE_PSEUDO_VFP_D_IDX(15), 1648 DEFINE_PSEUDO_VFP_D_IDX(16), 1649 DEFINE_PSEUDO_VFP_D_IDX(17), 1650 DEFINE_PSEUDO_VFP_D_IDX(18), 1651 DEFINE_PSEUDO_VFP_D_IDX(19), 1652 DEFINE_PSEUDO_VFP_D_IDX(20), 1653 DEFINE_PSEUDO_VFP_D_IDX(21), 1654 DEFINE_PSEUDO_VFP_D_IDX(22), 1655 DEFINE_PSEUDO_VFP_D_IDX(23), 1656 DEFINE_PSEUDO_VFP_D_IDX(24), 1657 DEFINE_PSEUDO_VFP_D_IDX(25), 1658 DEFINE_PSEUDO_VFP_D_IDX(26), 1659 DEFINE_PSEUDO_VFP_D_IDX(27), 1660 DEFINE_PSEUDO_VFP_D_IDX(28), 1661 DEFINE_PSEUDO_VFP_D_IDX(29), 1662 DEFINE_PSEUDO_VFP_D_IDX(30), 1663 DEFINE_PSEUDO_VFP_D_IDX(31) 1664 1665 }; 1666 1667 //_STRUCT_ARM_EXCEPTION_STATE64 1668 //{ 1669 // uint64_t far; /* Virtual Fault Address */ 1670 // uint32_t esr; /* Exception syndrome */ 1671 // uint32_t exception; /* number of arm exception taken */ 1672 //}; 1673 1674 // Exception registers 1675 const DNBRegisterInfo DNBArchMachARM64::g_exc_registers[] = { 1676 {e_regSetEXC, exc_far, "far", NULL, Uint, Hex, 8, EXC_OFFSET(__far), 1677 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1678 INVALID_NUB_REGNUM, NULL, NULL}, 1679 {e_regSetEXC, exc_esr, "esr", NULL, Uint, Hex, 4, EXC_OFFSET(__esr), 1680 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1681 INVALID_NUB_REGNUM, NULL, NULL}, 1682 {e_regSetEXC, exc_exception, "exception", NULL, Uint, Hex, 4, 1683 EXC_OFFSET(__exception), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1684 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}}; 1685 1686 // Number of registers in each register set 1687 const size_t DNBArchMachARM64::k_num_gpr_registers = 1688 sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo); 1689 const size_t DNBArchMachARM64::k_num_vfp_registers = 1690 sizeof(g_vfp_registers) / sizeof(DNBRegisterInfo); 1691 const size_t DNBArchMachARM64::k_num_exc_registers = 1692 sizeof(g_exc_registers) / sizeof(DNBRegisterInfo); 1693 const size_t DNBArchMachARM64::k_num_all_registers = 1694 k_num_gpr_registers + k_num_vfp_registers + k_num_exc_registers; 1695 1696 // Register set definitions. The first definitions at register set index 1697 // of zero is for all registers, followed by other registers sets. The 1698 // register information for the all register set need not be filled in. 1699 const DNBRegisterSetInfo DNBArchMachARM64::g_reg_sets[] = { 1700 {"ARM64 Registers", NULL, k_num_all_registers}, 1701 {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers}, 1702 {"Floating Point Registers", g_vfp_registers, k_num_vfp_registers}, 1703 {"Exception State Registers", g_exc_registers, k_num_exc_registers}}; 1704 // Total number of register sets for this architecture 1705 const size_t DNBArchMachARM64::k_num_register_sets = 1706 sizeof(g_reg_sets) / sizeof(DNBRegisterSetInfo); 1707 1708 const DNBRegisterSetInfo * 1709 DNBArchMachARM64::GetRegisterSetInfo(nub_size_t *num_reg_sets) { 1710 *num_reg_sets = k_num_register_sets; 1711 return g_reg_sets; 1712 } 1713 1714 bool DNBArchMachARM64::FixGenericRegisterNumber(uint32_t &set, uint32_t ®) { 1715 if (set == REGISTER_SET_GENERIC) { 1716 switch (reg) { 1717 case GENERIC_REGNUM_PC: // Program Counter 1718 set = e_regSetGPR; 1719 reg = gpr_pc; 1720 break; 1721 1722 case GENERIC_REGNUM_SP: // Stack Pointer 1723 set = e_regSetGPR; 1724 reg = gpr_sp; 1725 break; 1726 1727 case GENERIC_REGNUM_FP: // Frame Pointer 1728 set = e_regSetGPR; 1729 reg = gpr_fp; 1730 break; 1731 1732 case GENERIC_REGNUM_RA: // Return Address 1733 set = e_regSetGPR; 1734 reg = gpr_lr; 1735 break; 1736 1737 case GENERIC_REGNUM_FLAGS: // Processor flags register 1738 set = e_regSetGPR; 1739 reg = gpr_cpsr; 1740 break; 1741 1742 case GENERIC_REGNUM_ARG1: 1743 case GENERIC_REGNUM_ARG2: 1744 case GENERIC_REGNUM_ARG3: 1745 case GENERIC_REGNUM_ARG4: 1746 case GENERIC_REGNUM_ARG5: 1747 case GENERIC_REGNUM_ARG6: 1748 set = e_regSetGPR; 1749 reg = gpr_x0 + reg - GENERIC_REGNUM_ARG1; 1750 break; 1751 1752 default: 1753 return false; 1754 } 1755 } 1756 return true; 1757 } 1758 bool DNBArchMachARM64::GetRegisterValue(uint32_t set, uint32_t reg, 1759 DNBRegisterValue *value) { 1760 if (!FixGenericRegisterNumber(set, reg)) 1761 return false; 1762 1763 if (GetRegisterState(set, false) != KERN_SUCCESS) 1764 return false; 1765 1766 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1767 if (regInfo) { 1768 value->info = *regInfo; 1769 switch (set) { 1770 case e_regSetGPR: 1771 if (reg <= gpr_pc) { 1772 value->value.uint64 = m_state.context.gpr.__x[reg]; 1773 return true; 1774 } else if (reg == gpr_cpsr) { 1775 value->value.uint32 = m_state.context.gpr.__cpsr; 1776 return true; 1777 } 1778 break; 1779 1780 case e_regSetVFP: 1781 1782 if (reg >= vfp_v0 && reg <= vfp_v31) { 1783 #if defined(__arm64__) || defined(__aarch64__) 1784 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_v0], 1785 16); 1786 #else 1787 memcpy(&value->value.v_uint8, 1788 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), 1789 16); 1790 #endif 1791 return true; 1792 } else if (reg == vfp_fpsr) { 1793 #if defined(__arm64__) || defined(__aarch64__) 1794 memcpy(&value->value.uint32, &m_state.context.vfp.__fpsr, 4); 1795 #else 1796 memcpy(&value->value.uint32, 1797 ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0, 4); 1798 #endif 1799 return true; 1800 } else if (reg == vfp_fpcr) { 1801 #if defined(__arm64__) || defined(__aarch64__) 1802 memcpy(&value->value.uint32, &m_state.context.vfp.__fpcr, 4); 1803 #else 1804 memcpy(&value->value.uint32, 1805 ((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 4, 4); 1806 #endif 1807 return true; 1808 } else if (reg >= vfp_s0 && reg <= vfp_s31) { 1809 #if defined(__arm64__) || defined(__aarch64__) 1810 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_s0], 1811 4); 1812 #else 1813 memcpy(&value->value.v_uint8, 1814 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), 1815 4); 1816 #endif 1817 return true; 1818 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 1819 #if defined(__arm64__) || defined(__aarch64__) 1820 memcpy(&value->value.v_uint8, &m_state.context.vfp.__v[reg - vfp_d0], 1821 8); 1822 #else 1823 memcpy(&value->value.v_uint8, 1824 ((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), 1825 8); 1826 #endif 1827 return true; 1828 } 1829 break; 1830 1831 case e_regSetEXC: 1832 if (reg == exc_far) { 1833 value->value.uint64 = m_state.context.exc.__far; 1834 return true; 1835 } else if (reg == exc_esr) { 1836 value->value.uint32 = m_state.context.exc.__esr; 1837 return true; 1838 } else if (reg == exc_exception) { 1839 value->value.uint32 = m_state.context.exc.__exception; 1840 return true; 1841 } 1842 break; 1843 } 1844 } 1845 return false; 1846 } 1847 1848 bool DNBArchMachARM64::SetRegisterValue(uint32_t set, uint32_t reg, 1849 const DNBRegisterValue *value) { 1850 if (!FixGenericRegisterNumber(set, reg)) 1851 return false; 1852 1853 if (GetRegisterState(set, false) != KERN_SUCCESS) 1854 return false; 1855 1856 bool success = false; 1857 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1858 if (regInfo) { 1859 switch (set) { 1860 case e_regSetGPR: 1861 if (reg <= gpr_pc) { 1862 m_state.context.gpr.__x[reg] = value->value.uint64; 1863 success = true; 1864 } else if (reg == gpr_cpsr) { 1865 m_state.context.gpr.__cpsr = value->value.uint32; 1866 success = true; 1867 } 1868 break; 1869 1870 case e_regSetVFP: 1871 if (reg >= vfp_v0 && reg <= vfp_v31) { 1872 #if defined(__arm64__) || defined(__aarch64__) 1873 memcpy(&m_state.context.vfp.__v[reg - vfp_v0], &value->value.v_uint8, 1874 16); 1875 #else 1876 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_v0) * 16), 1877 &value->value.v_uint8, 16); 1878 #endif 1879 success = true; 1880 } else if (reg == vfp_fpsr) { 1881 #if defined(__arm64__) || defined(__aarch64__) 1882 memcpy(&m_state.context.vfp.__fpsr, &value->value.uint32, 4); 1883 #else 1884 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + (32 * 16) + 0, 1885 &value->value.uint32, 4); 1886 #endif 1887 success = true; 1888 } else if (reg == vfp_fpcr) { 1889 #if defined(__arm64__) || defined(__aarch64__) 1890 memcpy(&m_state.context.vfp.__fpcr, &value->value.uint32, 4); 1891 #else 1892 memcpy(((uint8_t *)m_state.context.vfp.opaque) + (32 * 16) + 4, 1893 &value->value.uint32, 4); 1894 #endif 1895 success = true; 1896 } else if (reg >= vfp_s0 && reg <= vfp_s31) { 1897 #if defined(__arm64__) || defined(__aarch64__) 1898 memcpy(&m_state.context.vfp.__v[reg - vfp_s0], &value->value.v_uint8, 1899 4); 1900 #else 1901 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_s0) * 16), 1902 &value->value.v_uint8, 4); 1903 #endif 1904 success = true; 1905 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 1906 #if defined(__arm64__) || defined(__aarch64__) 1907 memcpy(&m_state.context.vfp.__v[reg - vfp_d0], &value->value.v_uint8, 1908 8); 1909 #else 1910 memcpy(((uint8_t *)&m_state.context.vfp.opaque) + ((reg - vfp_d0) * 16), 1911 &value->value.v_uint8, 8); 1912 #endif 1913 success = true; 1914 } 1915 break; 1916 1917 case e_regSetEXC: 1918 if (reg == exc_far) { 1919 m_state.context.exc.__far = value->value.uint64; 1920 success = true; 1921 } else if (reg == exc_esr) { 1922 m_state.context.exc.__esr = value->value.uint32; 1923 success = true; 1924 } else if (reg == exc_exception) { 1925 m_state.context.exc.__exception = value->value.uint32; 1926 success = true; 1927 } 1928 break; 1929 } 1930 } 1931 if (success) 1932 return SetRegisterState(set) == KERN_SUCCESS; 1933 return false; 1934 } 1935 1936 kern_return_t DNBArchMachARM64::GetRegisterState(int set, bool force) { 1937 switch (set) { 1938 case e_regSetALL: 1939 return GetGPRState(force) | GetVFPState(force) | GetEXCState(force) | 1940 GetDBGState(force); 1941 case e_regSetGPR: 1942 return GetGPRState(force); 1943 case e_regSetVFP: 1944 return GetVFPState(force); 1945 case e_regSetEXC: 1946 return GetEXCState(force); 1947 case e_regSetDBG: 1948 return GetDBGState(force); 1949 default: 1950 break; 1951 } 1952 return KERN_INVALID_ARGUMENT; 1953 } 1954 1955 kern_return_t DNBArchMachARM64::SetRegisterState(int set) { 1956 // Make sure we have a valid context to set. 1957 kern_return_t err = GetRegisterState(set, false); 1958 if (err != KERN_SUCCESS) 1959 return err; 1960 1961 switch (set) { 1962 case e_regSetALL: 1963 return SetGPRState() | SetVFPState() | SetEXCState() | SetDBGState(false); 1964 case e_regSetGPR: 1965 return SetGPRState(); 1966 case e_regSetVFP: 1967 return SetVFPState(); 1968 case e_regSetEXC: 1969 return SetEXCState(); 1970 case e_regSetDBG: 1971 return SetDBGState(false); 1972 default: 1973 break; 1974 } 1975 return KERN_INVALID_ARGUMENT; 1976 } 1977 1978 bool DNBArchMachARM64::RegisterSetStateIsValid(int set) const { 1979 return m_state.RegsAreValid(set); 1980 } 1981 1982 nub_size_t DNBArchMachARM64::GetRegisterContext(void *buf, nub_size_t buf_len) { 1983 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 1984 sizeof(m_state.context.exc); 1985 1986 if (buf && buf_len) { 1987 if (size > buf_len) 1988 size = buf_len; 1989 1990 bool force = false; 1991 if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force)) 1992 return 0; 1993 1994 // Copy each struct individually to avoid any padding that might be between 1995 // the structs in m_state.context 1996 uint8_t *p = (uint8_t *)buf; 1997 ::memcpy(p, &m_state.context.gpr, sizeof(m_state.context.gpr)); 1998 p += sizeof(m_state.context.gpr); 1999 ::memcpy(p, &m_state.context.vfp, sizeof(m_state.context.vfp)); 2000 p += sizeof(m_state.context.vfp); 2001 ::memcpy(p, &m_state.context.exc, sizeof(m_state.context.exc)); 2002 p += sizeof(m_state.context.exc); 2003 2004 size_t bytes_written = p - (uint8_t *)buf; 2005 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2006 assert(bytes_written == size); 2007 } 2008 DNBLogThreadedIf( 2009 LOG_THREAD, 2010 "DNBArchMachARM64::GetRegisterContext (buf = %p, len = %zu) => %zu", buf, 2011 buf_len, size); 2012 // Return the size of the register context even if NULL was passed in 2013 return size; 2014 } 2015 2016 nub_size_t DNBArchMachARM64::SetRegisterContext(const void *buf, 2017 nub_size_t buf_len) { 2018 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 2019 sizeof(m_state.context.exc); 2020 2021 if (buf == NULL || buf_len == 0) 2022 size = 0; 2023 2024 if (size) { 2025 if (size > buf_len) 2026 size = buf_len; 2027 2028 // Copy each struct individually to avoid any padding that might be between 2029 // the structs in m_state.context 2030 uint8_t *p = (uint8_t *)buf; 2031 ::memcpy(&m_state.context.gpr, p, sizeof(m_state.context.gpr)); 2032 p += sizeof(m_state.context.gpr); 2033 ::memcpy(&m_state.context.vfp, p, sizeof(m_state.context.vfp)); 2034 p += sizeof(m_state.context.vfp); 2035 ::memcpy(&m_state.context.exc, p, sizeof(m_state.context.exc)); 2036 p += sizeof(m_state.context.exc); 2037 2038 size_t bytes_written = p - (uint8_t *)buf; 2039 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2040 assert(bytes_written == size); 2041 SetGPRState(); 2042 SetVFPState(); 2043 SetEXCState(); 2044 } 2045 DNBLogThreadedIf( 2046 LOG_THREAD, 2047 "DNBArchMachARM64::SetRegisterContext (buf = %p, len = %zu) => %zu", buf, 2048 buf_len, size); 2049 return size; 2050 } 2051 2052 uint32_t DNBArchMachARM64::SaveRegisterState() { 2053 kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber()); 2054 DNBLogThreadedIf( 2055 LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u " 2056 "(SetGPRState() for stop_count = %u)", 2057 m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount()); 2058 2059 // Always re-read the registers because above we call thread_abort_safely(); 2060 bool force = true; 2061 2062 if ((kret = GetGPRState(force)) != KERN_SUCCESS) { 2063 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () " 2064 "error: GPR regs failed to read: %u ", 2065 kret); 2066 } else if ((kret = GetVFPState(force)) != KERN_SUCCESS) { 2067 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::SaveRegisterState () " 2068 "error: %s regs failed to read: %u", 2069 "VFP", kret); 2070 } else { 2071 const uint32_t save_id = GetNextRegisterStateSaveID(); 2072 m_saved_register_states[save_id] = m_state.context; 2073 return save_id; 2074 } 2075 return UINT32_MAX; 2076 } 2077 2078 bool DNBArchMachARM64::RestoreRegisterState(uint32_t save_id) { 2079 SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id); 2080 if (pos != m_saved_register_states.end()) { 2081 m_state.context.gpr = pos->second.gpr; 2082 m_state.context.vfp = pos->second.vfp; 2083 kern_return_t kret; 2084 bool success = true; 2085 if ((kret = SetGPRState()) != KERN_SUCCESS) { 2086 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState " 2087 "(save_id = %u) error: GPR regs failed to " 2088 "write: %u", 2089 save_id, kret); 2090 success = false; 2091 } else if ((kret = SetVFPState()) != KERN_SUCCESS) { 2092 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM64::RestoreRegisterState " 2093 "(save_id = %u) error: %s regs failed to " 2094 "write: %u", 2095 save_id, "VFP", kret); 2096 success = false; 2097 } 2098 m_saved_register_states.erase(pos); 2099 return success; 2100 } 2101 return false; 2102 } 2103 2104 #endif // #if defined (ARM_THREAD_STATE64_COUNT) 2105 #endif // #if defined (__arm__) || defined (__arm64__) || defined (__aarch64__) 2106