1 //===-- DNBArchImpl.cpp -----------------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Created by Greg Clayton on 6/25/07. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #if defined(__arm__) || defined(__arm64__) || defined(__aarch64__) 15 16 #include "MacOSX/arm/DNBArchImpl.h" 17 #include "ARM_DWARF_Registers.h" 18 #include "ARM_ehframe_Registers.h" 19 #include "DNB.h" 20 #include "DNBBreakpoint.h" 21 #include "DNBLog.h" 22 #include "DNBRegisterInfo.h" 23 #include "MacOSX/MachProcess.h" 24 #include "MacOSX/MachThread.h" 25 26 #include <inttypes.h> 27 #include <sys/sysctl.h> 28 29 // BCR address match type 30 #define BCR_M_IMVA_MATCH ((uint32_t)(0u << 21)) 31 #define BCR_M_CONTEXT_ID_MATCH ((uint32_t)(1u << 21)) 32 #define BCR_M_IMVA_MISMATCH ((uint32_t)(2u << 21)) 33 #define BCR_M_RESERVED ((uint32_t)(3u << 21)) 34 35 // Link a BVR/BCR or WVR/WCR pair to another 36 #define E_ENABLE_LINKING ((uint32_t)(1u << 20)) 37 38 // Byte Address Select 39 #define BAS_IMVA_PLUS_0 ((uint32_t)(1u << 5)) 40 #define BAS_IMVA_PLUS_1 ((uint32_t)(1u << 6)) 41 #define BAS_IMVA_PLUS_2 ((uint32_t)(1u << 7)) 42 #define BAS_IMVA_PLUS_3 ((uint32_t)(1u << 8)) 43 #define BAS_IMVA_0_1 ((uint32_t)(3u << 5)) 44 #define BAS_IMVA_2_3 ((uint32_t)(3u << 7)) 45 #define BAS_IMVA_ALL ((uint32_t)(0xfu << 5)) 46 47 // Break only in privileged or user mode 48 #define S_RSVD ((uint32_t)(0u << 1)) 49 #define S_PRIV ((uint32_t)(1u << 1)) 50 #define S_USER ((uint32_t)(2u << 1)) 51 #define S_PRIV_USER ((S_PRIV) | (S_USER)) 52 53 #define BCR_ENABLE ((uint32_t)(1u)) 54 #define WCR_ENABLE ((uint32_t)(1u)) 55 56 // Watchpoint load/store 57 #define WCR_LOAD ((uint32_t)(1u << 3)) 58 #define WCR_STORE ((uint32_t)(1u << 4)) 59 60 // Definitions for the Debug Status and Control Register fields: 61 // [5:2] => Method of debug entry 62 //#define WATCHPOINT_OCCURRED ((uint32_t)(2u)) 63 // I'm seeing this, instead. 64 #define WATCHPOINT_OCCURRED ((uint32_t)(10u)) 65 66 // 0xE120BE70 67 static const uint8_t g_arm_breakpoint_opcode[] = {0x70, 0xBE, 0x20, 0xE1}; 68 static const uint8_t g_thumb_breakpoint_opcode[] = {0x70, 0xBE}; 69 70 // A watchpoint may need to be implemented using two watchpoint registers. 71 // e.g. watching an 8-byte region when the device can only watch 4-bytes. 72 // 73 // This stores the lo->hi mappings. It's safe to initialize to all 0's 74 // since hi > lo and therefore LoHi[i] cannot be 0. 75 static uint32_t LoHi[16] = {0}; 76 77 // ARM constants used during decoding 78 #define REG_RD 0 79 #define LDM_REGLIST 1 80 #define PC_REG 15 81 #define PC_REGLIST_BIT 0x8000 82 83 // ARM conditions 84 #define COND_EQ 0x0 85 #define COND_NE 0x1 86 #define COND_CS 0x2 87 #define COND_HS 0x2 88 #define COND_CC 0x3 89 #define COND_LO 0x3 90 #define COND_MI 0x4 91 #define COND_PL 0x5 92 #define COND_VS 0x6 93 #define COND_VC 0x7 94 #define COND_HI 0x8 95 #define COND_LS 0x9 96 #define COND_GE 0xA 97 #define COND_LT 0xB 98 #define COND_GT 0xC 99 #define COND_LE 0xD 100 #define COND_AL 0xE 101 #define COND_UNCOND 0xF 102 103 #define MASK_CPSR_T (1u << 5) 104 #define MASK_CPSR_J (1u << 24) 105 106 #define MNEMONIC_STRING_SIZE 32 107 #define OPERAND_STRING_SIZE 128 108 109 // Returns true if the first 16 bit opcode of a thumb instruction indicates 110 // the instruction will be a 32 bit thumb opcode 111 static bool IsThumb32Opcode(uint16_t opcode) { 112 if (((opcode & 0xE000) == 0xE000) && (opcode & 0x1800)) 113 return true; 114 return false; 115 } 116 117 void DNBArchMachARM::Initialize() { 118 DNBArchPluginInfo arch_plugin_info = { 119 CPU_TYPE_ARM, DNBArchMachARM::Create, DNBArchMachARM::GetRegisterSetInfo, 120 DNBArchMachARM::SoftwareBreakpointOpcode}; 121 122 // Register this arch plug-in with the main protocol class 123 DNBArchProtocol::RegisterArchPlugin(arch_plugin_info); 124 } 125 126 DNBArchProtocol *DNBArchMachARM::Create(MachThread *thread) { 127 DNBArchMachARM *obj = new DNBArchMachARM(thread); 128 return obj; 129 } 130 131 const uint8_t *DNBArchMachARM::SoftwareBreakpointOpcode(nub_size_t byte_size) { 132 switch (byte_size) { 133 case 2: 134 return g_thumb_breakpoint_opcode; 135 case 4: 136 return g_arm_breakpoint_opcode; 137 } 138 return NULL; 139 } 140 141 uint32_t DNBArchMachARM::GetCPUType() { return CPU_TYPE_ARM; } 142 143 uint64_t DNBArchMachARM::GetPC(uint64_t failValue) { 144 // Get program counter 145 if (GetGPRState(false) == KERN_SUCCESS) 146 return m_state.context.gpr.__pc; 147 return failValue; 148 } 149 150 kern_return_t DNBArchMachARM::SetPC(uint64_t value) { 151 // Get program counter 152 kern_return_t err = GetGPRState(false); 153 if (err == KERN_SUCCESS) { 154 m_state.context.gpr.__pc = (uint32_t)value; 155 err = SetGPRState(); 156 } 157 return err == KERN_SUCCESS; 158 } 159 160 uint64_t DNBArchMachARM::GetSP(uint64_t failValue) { 161 // Get stack pointer 162 if (GetGPRState(false) == KERN_SUCCESS) 163 return m_state.context.gpr.__sp; 164 return failValue; 165 } 166 167 kern_return_t DNBArchMachARM::GetGPRState(bool force) { 168 int set = e_regSetGPR; 169 // Check if we have valid cached registers 170 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 171 return KERN_SUCCESS; 172 173 // Read the registers from our thread 174 mach_msg_type_number_t count = ARM_THREAD_STATE_COUNT; 175 kern_return_t kret = 176 ::thread_get_state(m_thread->MachPortNumber(), ARM_THREAD_STATE, 177 (thread_state_t)&m_state.context.gpr, &count); 178 uint32_t *r = &m_state.context.gpr.__r[0]; 179 DNBLogThreadedIf( 180 LOG_THREAD, "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count = " 181 "%u) regs r0=%8.8x r1=%8.8x r2=%8.8x r3=%8.8x r4=%8.8x " 182 "r5=%8.8x r6=%8.8x r7=%8.8x r8=%8.8x r9=%8.8x r10=%8.8x " 183 "r11=%8.8x s12=%8.8x sp=%8.8x lr=%8.8x pc=%8.8x cpsr=%8.8x", 184 m_thread->MachPortNumber(), ARM_THREAD_STATE, ARM_THREAD_STATE_COUNT, 185 kret, count, r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7], r[8], r[9], 186 r[10], r[11], r[12], r[13], r[14], r[15], r[16]); 187 m_state.SetError(set, Read, kret); 188 return kret; 189 } 190 191 kern_return_t DNBArchMachARM::GetVFPState(bool force) { 192 int set = e_regSetVFP; 193 // Check if we have valid cached registers 194 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 195 return KERN_SUCCESS; 196 197 kern_return_t kret; 198 199 #if defined(__arm64__) || defined(__aarch64__) 200 // Read the registers from our thread 201 mach_msg_type_number_t count = ARM_NEON_STATE_COUNT; 202 kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_NEON_STATE, 203 (thread_state_t)&m_state.context.vfp, &count); 204 if (DNBLogEnabledForAny(LOG_THREAD)) { 205 DNBLogThreaded( 206 "thread_get_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs" 207 "\n q0 = 0x%16.16llx%16.16llx" 208 "\n q1 = 0x%16.16llx%16.16llx" 209 "\n q2 = 0x%16.16llx%16.16llx" 210 "\n q3 = 0x%16.16llx%16.16llx" 211 "\n q4 = 0x%16.16llx%16.16llx" 212 "\n q5 = 0x%16.16llx%16.16llx" 213 "\n q6 = 0x%16.16llx%16.16llx" 214 "\n q7 = 0x%16.16llx%16.16llx" 215 "\n q8 = 0x%16.16llx%16.16llx" 216 "\n q9 = 0x%16.16llx%16.16llx" 217 "\n q10 = 0x%16.16llx%16.16llx" 218 "\n q11 = 0x%16.16llx%16.16llx" 219 "\n q12 = 0x%16.16llx%16.16llx" 220 "\n q13 = 0x%16.16llx%16.16llx" 221 "\n q14 = 0x%16.16llx%16.16llx" 222 "\n q15 = 0x%16.16llx%16.16llx" 223 "\n fpsr = 0x%8.8x" 224 "\n fpcr = 0x%8.8x\n\n", 225 m_thread->MachPortNumber(), ARM_NEON_STATE, ARM_NEON_STATE_COUNT, kret, 226 count, ((uint64_t *)&m_state.context.vfp.__v[0])[0], 227 ((uint64_t *)&m_state.context.vfp.__v[0])[1], 228 ((uint64_t *)&m_state.context.vfp.__v[1])[0], 229 ((uint64_t *)&m_state.context.vfp.__v[1])[1], 230 ((uint64_t *)&m_state.context.vfp.__v[2])[0], 231 ((uint64_t *)&m_state.context.vfp.__v[2])[1], 232 ((uint64_t *)&m_state.context.vfp.__v[3])[0], 233 ((uint64_t *)&m_state.context.vfp.__v[3])[1], 234 ((uint64_t *)&m_state.context.vfp.__v[4])[0], 235 ((uint64_t *)&m_state.context.vfp.__v[4])[1], 236 ((uint64_t *)&m_state.context.vfp.__v[5])[0], 237 ((uint64_t *)&m_state.context.vfp.__v[5])[1], 238 ((uint64_t *)&m_state.context.vfp.__v[6])[0], 239 ((uint64_t *)&m_state.context.vfp.__v[6])[1], 240 ((uint64_t *)&m_state.context.vfp.__v[7])[0], 241 ((uint64_t *)&m_state.context.vfp.__v[7])[1], 242 ((uint64_t *)&m_state.context.vfp.__v[8])[0], 243 ((uint64_t *)&m_state.context.vfp.__v[8])[1], 244 ((uint64_t *)&m_state.context.vfp.__v[9])[0], 245 ((uint64_t *)&m_state.context.vfp.__v[9])[1], 246 ((uint64_t *)&m_state.context.vfp.__v[10])[0], 247 ((uint64_t *)&m_state.context.vfp.__v[10])[1], 248 ((uint64_t *)&m_state.context.vfp.__v[11])[0], 249 ((uint64_t *)&m_state.context.vfp.__v[11])[1], 250 ((uint64_t *)&m_state.context.vfp.__v[12])[0], 251 ((uint64_t *)&m_state.context.vfp.__v[12])[1], 252 ((uint64_t *)&m_state.context.vfp.__v[13])[0], 253 ((uint64_t *)&m_state.context.vfp.__v[13])[1], 254 ((uint64_t *)&m_state.context.vfp.__v[14])[0], 255 ((uint64_t *)&m_state.context.vfp.__v[14])[1], 256 ((uint64_t *)&m_state.context.vfp.__v[15])[0], 257 ((uint64_t *)&m_state.context.vfp.__v[15])[1], 258 m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr); 259 } 260 #else 261 // Read the registers from our thread 262 mach_msg_type_number_t count = ARM_VFP_STATE_COUNT; 263 kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_VFP_STATE, 264 (thread_state_t)&m_state.context.vfp, &count); 265 266 if (DNBLogEnabledForAny(LOG_THREAD)) { 267 uint32_t *r = &m_state.context.vfp.__r[0]; 268 DNBLogThreaded( 269 "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count => %u)", 270 m_thread->MachPortNumber(), ARM_THREAD_STATE, ARM_THREAD_STATE_COUNT, 271 kret, count); 272 DNBLogThreaded(" s0=%8.8x s1=%8.8x s2=%8.8x s3=%8.8x s4=%8.8x " 273 "s5=%8.8x s6=%8.8x s7=%8.8x", 274 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]); 275 DNBLogThreaded(" s8=%8.8x s9=%8.8x s10=%8.8x s11=%8.8x s12=%8.8x " 276 "s13=%8.8x s14=%8.8x s15=%8.8x", 277 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]); 278 DNBLogThreaded(" s16=%8.8x s17=%8.8x s18=%8.8x s19=%8.8x s20=%8.8x " 279 "s21=%8.8x s22=%8.8x s23=%8.8x", 280 r[16], r[17], r[18], r[19], r[20], r[21], r[22], r[23]); 281 DNBLogThreaded(" s24=%8.8x s25=%8.8x s26=%8.8x s27=%8.8x s28=%8.8x " 282 "s29=%8.8x s30=%8.8x s31=%8.8x", 283 r[24], r[25], r[26], r[27], r[28], r[29], r[30], r[31]); 284 DNBLogThreaded(" s32=%8.8x s33=%8.8x s34=%8.8x s35=%8.8x s36=%8.8x " 285 "s37=%8.8x s38=%8.8x s39=%8.8x", 286 r[32], r[33], r[34], r[35], r[36], r[37], r[38], r[39]); 287 DNBLogThreaded(" s40=%8.8x s41=%8.8x s42=%8.8x s43=%8.8x s44=%8.8x " 288 "s45=%8.8x s46=%8.8x s47=%8.8x", 289 r[40], r[41], r[42], r[43], r[44], r[45], r[46], r[47]); 290 DNBLogThreaded(" s48=%8.8x s49=%8.8x s50=%8.8x s51=%8.8x s52=%8.8x " 291 "s53=%8.8x s54=%8.8x s55=%8.8x", 292 r[48], r[49], r[50], r[51], r[52], r[53], r[54], r[55]); 293 DNBLogThreaded(" s56=%8.8x s57=%8.8x s58=%8.8x s59=%8.8x s60=%8.8x " 294 "s61=%8.8x s62=%8.8x s63=%8.8x fpscr=%8.8x", 295 r[56], r[57], r[58], r[59], r[60], r[61], r[62], r[63], 296 r[64]); 297 } 298 299 #endif 300 m_state.SetError(set, Read, kret); 301 return kret; 302 } 303 304 kern_return_t DNBArchMachARM::GetEXCState(bool force) { 305 int set = e_regSetEXC; 306 // Check if we have valid cached registers 307 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 308 return KERN_SUCCESS; 309 310 // Read the registers from our thread 311 mach_msg_type_number_t count = ARM_EXCEPTION_STATE_COUNT; 312 kern_return_t kret = 313 ::thread_get_state(m_thread->MachPortNumber(), ARM_EXCEPTION_STATE, 314 (thread_state_t)&m_state.context.exc, &count); 315 m_state.SetError(set, Read, kret); 316 return kret; 317 } 318 319 static void DumpDBGState(const DNBArchMachARM::DBG &dbg) { 320 uint32_t i = 0; 321 for (i = 0; i < 16; i++) { 322 DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } " 323 "WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }", 324 i, i, dbg.__bvr[i], dbg.__bcr[i], i, i, dbg.__wvr[i], 325 dbg.__wcr[i]); 326 } 327 } 328 329 kern_return_t DNBArchMachARM::GetDBGState(bool force) { 330 int set = e_regSetDBG; 331 332 // Check if we have valid cached registers 333 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS) 334 return KERN_SUCCESS; 335 336 // Read the registers from our thread 337 #if defined(ARM_DEBUG_STATE32) && (defined(__arm64__) || defined(__aarch64__)) 338 mach_msg_type_number_t count = ARM_DEBUG_STATE32_COUNT; 339 kern_return_t kret = 340 ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE32, 341 (thread_state_t)&m_state.dbg, &count); 342 #else 343 mach_msg_type_number_t count = ARM_DEBUG_STATE_COUNT; 344 kern_return_t kret = 345 ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE, 346 (thread_state_t)&m_state.dbg, &count); 347 #endif 348 m_state.SetError(set, Read, kret); 349 350 return kret; 351 } 352 353 kern_return_t DNBArchMachARM::SetGPRState() { 354 int set = e_regSetGPR; 355 kern_return_t kret = ::thread_set_state( 356 m_thread->MachPortNumber(), ARM_THREAD_STATE, 357 (thread_state_t)&m_state.context.gpr, ARM_THREAD_STATE_COUNT); 358 m_state.SetError(set, Write, 359 kret); // Set the current write error for this register set 360 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 361 // state in case registers are read 362 // back differently 363 return kret; // Return the error code 364 } 365 366 kern_return_t DNBArchMachARM::SetVFPState() { 367 int set = e_regSetVFP; 368 kern_return_t kret; 369 mach_msg_type_number_t count; 370 371 #if defined(__arm64__) || defined(__aarch64__) 372 count = ARM_NEON_STATE_COUNT; 373 kret = ::thread_set_state(m_thread->MachPortNumber(), ARM_NEON_STATE, 374 (thread_state_t)&m_state.context.vfp, count); 375 #else 376 count = ARM_VFP_STATE_COUNT; 377 kret = ::thread_set_state(m_thread->MachPortNumber(), ARM_VFP_STATE, 378 (thread_state_t)&m_state.context.vfp, count); 379 #endif 380 381 #if defined(__arm64__) || defined(__aarch64__) 382 if (DNBLogEnabledForAny(LOG_THREAD)) { 383 DNBLogThreaded( 384 "thread_set_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs" 385 "\n q0 = 0x%16.16llx%16.16llx" 386 "\n q1 = 0x%16.16llx%16.16llx" 387 "\n q2 = 0x%16.16llx%16.16llx" 388 "\n q3 = 0x%16.16llx%16.16llx" 389 "\n q4 = 0x%16.16llx%16.16llx" 390 "\n q5 = 0x%16.16llx%16.16llx" 391 "\n q6 = 0x%16.16llx%16.16llx" 392 "\n q7 = 0x%16.16llx%16.16llx" 393 "\n q8 = 0x%16.16llx%16.16llx" 394 "\n q9 = 0x%16.16llx%16.16llx" 395 "\n q10 = 0x%16.16llx%16.16llx" 396 "\n q11 = 0x%16.16llx%16.16llx" 397 "\n q12 = 0x%16.16llx%16.16llx" 398 "\n q13 = 0x%16.16llx%16.16llx" 399 "\n q14 = 0x%16.16llx%16.16llx" 400 "\n q15 = 0x%16.16llx%16.16llx" 401 "\n fpsr = 0x%8.8x" 402 "\n fpcr = 0x%8.8x\n\n", 403 m_thread->MachPortNumber(), ARM_NEON_STATE, ARM_NEON_STATE_COUNT, kret, 404 count, ((uint64_t *)&m_state.context.vfp.__v[0])[0], 405 ((uint64_t *)&m_state.context.vfp.__v[0])[1], 406 ((uint64_t *)&m_state.context.vfp.__v[1])[0], 407 ((uint64_t *)&m_state.context.vfp.__v[1])[1], 408 ((uint64_t *)&m_state.context.vfp.__v[2])[0], 409 ((uint64_t *)&m_state.context.vfp.__v[2])[1], 410 ((uint64_t *)&m_state.context.vfp.__v[3])[0], 411 ((uint64_t *)&m_state.context.vfp.__v[3])[1], 412 ((uint64_t *)&m_state.context.vfp.__v[4])[0], 413 ((uint64_t *)&m_state.context.vfp.__v[4])[1], 414 ((uint64_t *)&m_state.context.vfp.__v[5])[0], 415 ((uint64_t *)&m_state.context.vfp.__v[5])[1], 416 ((uint64_t *)&m_state.context.vfp.__v[6])[0], 417 ((uint64_t *)&m_state.context.vfp.__v[6])[1], 418 ((uint64_t *)&m_state.context.vfp.__v[7])[0], 419 ((uint64_t *)&m_state.context.vfp.__v[7])[1], 420 ((uint64_t *)&m_state.context.vfp.__v[8])[0], 421 ((uint64_t *)&m_state.context.vfp.__v[8])[1], 422 ((uint64_t *)&m_state.context.vfp.__v[9])[0], 423 ((uint64_t *)&m_state.context.vfp.__v[9])[1], 424 ((uint64_t *)&m_state.context.vfp.__v[10])[0], 425 ((uint64_t *)&m_state.context.vfp.__v[10])[1], 426 ((uint64_t *)&m_state.context.vfp.__v[11])[0], 427 ((uint64_t *)&m_state.context.vfp.__v[11])[1], 428 ((uint64_t *)&m_state.context.vfp.__v[12])[0], 429 ((uint64_t *)&m_state.context.vfp.__v[12])[1], 430 ((uint64_t *)&m_state.context.vfp.__v[13])[0], 431 ((uint64_t *)&m_state.context.vfp.__v[13])[1], 432 ((uint64_t *)&m_state.context.vfp.__v[14])[0], 433 ((uint64_t *)&m_state.context.vfp.__v[14])[1], 434 ((uint64_t *)&m_state.context.vfp.__v[15])[0], 435 ((uint64_t *)&m_state.context.vfp.__v[15])[1], 436 m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr); 437 } 438 #else 439 if (DNBLogEnabledForAny(LOG_THREAD)) { 440 uint32_t *r = &m_state.context.vfp.__r[0]; 441 DNBLogThreaded( 442 "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count => %u)", 443 m_thread->MachPortNumber(), ARM_THREAD_STATE, ARM_THREAD_STATE_COUNT, 444 kret, count); 445 DNBLogThreaded(" s0=%8.8x s1=%8.8x s2=%8.8x s3=%8.8x s4=%8.8x " 446 "s5=%8.8x s6=%8.8x s7=%8.8x", 447 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]); 448 DNBLogThreaded(" s8=%8.8x s9=%8.8x s10=%8.8x s11=%8.8x s12=%8.8x " 449 "s13=%8.8x s14=%8.8x s15=%8.8x", 450 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]); 451 DNBLogThreaded(" s16=%8.8x s17=%8.8x s18=%8.8x s19=%8.8x s20=%8.8x " 452 "s21=%8.8x s22=%8.8x s23=%8.8x", 453 r[16], r[17], r[18], r[19], r[20], r[21], r[22], r[23]); 454 DNBLogThreaded(" s24=%8.8x s25=%8.8x s26=%8.8x s27=%8.8x s28=%8.8x " 455 "s29=%8.8x s30=%8.8x s31=%8.8x", 456 r[24], r[25], r[26], r[27], r[28], r[29], r[30], r[31]); 457 DNBLogThreaded(" s32=%8.8x s33=%8.8x s34=%8.8x s35=%8.8x s36=%8.8x " 458 "s37=%8.8x s38=%8.8x s39=%8.8x", 459 r[32], r[33], r[34], r[35], r[36], r[37], r[38], r[39]); 460 DNBLogThreaded(" s40=%8.8x s41=%8.8x s42=%8.8x s43=%8.8x s44=%8.8x " 461 "s45=%8.8x s46=%8.8x s47=%8.8x", 462 r[40], r[41], r[42], r[43], r[44], r[45], r[46], r[47]); 463 DNBLogThreaded(" s48=%8.8x s49=%8.8x s50=%8.8x s51=%8.8x s52=%8.8x " 464 "s53=%8.8x s54=%8.8x s55=%8.8x", 465 r[48], r[49], r[50], r[51], r[52], r[53], r[54], r[55]); 466 DNBLogThreaded(" s56=%8.8x s57=%8.8x s58=%8.8x s59=%8.8x s60=%8.8x " 467 "s61=%8.8x s62=%8.8x s63=%8.8x fpscr=%8.8x", 468 r[56], r[57], r[58], r[59], r[60], r[61], r[62], r[63], 469 r[64]); 470 } 471 #endif 472 473 m_state.SetError(set, Write, 474 kret); // Set the current write error for this register set 475 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 476 // state in case registers are read 477 // back differently 478 return kret; // Return the error code 479 } 480 481 kern_return_t DNBArchMachARM::SetEXCState() { 482 int set = e_regSetEXC; 483 kern_return_t kret = ::thread_set_state( 484 m_thread->MachPortNumber(), ARM_EXCEPTION_STATE, 485 (thread_state_t)&m_state.context.exc, ARM_EXCEPTION_STATE_COUNT); 486 m_state.SetError(set, Write, 487 kret); // Set the current write error for this register set 488 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 489 // state in case registers are read 490 // back differently 491 return kret; // Return the error code 492 } 493 494 kern_return_t DNBArchMachARM::SetDBGState(bool also_set_on_task) { 495 int set = e_regSetDBG; 496 #if defined(ARM_DEBUG_STATE32) && (defined(__arm64__) || defined(__aarch64__)) 497 kern_return_t kret = 498 ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE32, 499 (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE32_COUNT); 500 if (also_set_on_task) { 501 kern_return_t task_kret = ::task_set_state( 502 m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE32, 503 (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE32_COUNT); 504 if (task_kret != KERN_SUCCESS) 505 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::SetDBGState failed to " 506 "set debug control register state: " 507 "0x%8.8x.", 508 kret); 509 } 510 #else 511 kern_return_t kret = 512 ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE, 513 (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE_COUNT); 514 if (also_set_on_task) { 515 kern_return_t task_kret = ::task_set_state( 516 m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE, 517 (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE_COUNT); 518 if (task_kret != KERN_SUCCESS) 519 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::SetDBGState failed to " 520 "set debug control register state: " 521 "0x%8.8x.", 522 kret); 523 } 524 #endif 525 526 m_state.SetError(set, Write, 527 kret); // Set the current write error for this register set 528 m_state.InvalidateRegisterSetState(set); // Invalidate the current register 529 // state in case registers are read 530 // back differently 531 return kret; // Return the error code 532 } 533 534 void DNBArchMachARM::ThreadWillResume() { 535 // Do we need to step this thread? If so, let the mach thread tell us so. 536 if (m_thread->IsStepping()) { 537 // This is the primary thread, let the arch do anything it needs 538 if (NumSupportedHardwareBreakpoints() > 0) { 539 if (EnableHardwareSingleStep(true) != KERN_SUCCESS) { 540 DNBLogThreaded("DNBArchMachARM::ThreadWillResume() failed to enable " 541 "hardware single step"); 542 } 543 } 544 } 545 546 // Disable the triggered watchpoint temporarily before we resume. 547 // Plus, we try to enable hardware single step to execute past the instruction 548 // which triggered our watchpoint. 549 if (m_watchpoint_did_occur) { 550 if (m_watchpoint_hw_index >= 0) { 551 kern_return_t kret = GetDBGState(false); 552 if (kret == KERN_SUCCESS && 553 !IsWatchpointEnabled(m_state.dbg, m_watchpoint_hw_index)) { 554 // The watchpoint might have been disabled by the user. We don't need 555 // to do anything at all 556 // to enable hardware single stepping. 557 m_watchpoint_did_occur = false; 558 m_watchpoint_hw_index = -1; 559 return; 560 } 561 562 DisableHardwareWatchpoint(m_watchpoint_hw_index, false); 563 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 564 "DisableHardwareWatchpoint(%d) called", 565 m_watchpoint_hw_index); 566 567 // Enable hardware single step to move past the watchpoint-triggering 568 // instruction. 569 m_watchpoint_resume_single_step_enabled = 570 (EnableHardwareSingleStep(true) == KERN_SUCCESS); 571 572 // If we are not able to enable single step to move past the 573 // watchpoint-triggering instruction, 574 // at least we should reset the two watchpoint member variables so that 575 // the next time around 576 // this callback function is invoked, the enclosing logical branch is 577 // skipped. 578 if (!m_watchpoint_resume_single_step_enabled) { 579 // Reset the two watchpoint member variables. 580 m_watchpoint_did_occur = false; 581 m_watchpoint_hw_index = -1; 582 DNBLogThreadedIf( 583 LOG_WATCHPOINTS, 584 "DNBArchMachARM::ThreadWillResume() failed to enable single step"); 585 } else 586 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() " 587 "succeeded to enable single step"); 588 } 589 } 590 } 591 592 bool DNBArchMachARM::ThreadDidStop() { 593 bool success = true; 594 595 m_state.InvalidateRegisterSetState(e_regSetALL); 596 597 if (m_watchpoint_resume_single_step_enabled) { 598 // Great! We now disable the hardware single step as well as re-enable the 599 // hardware watchpoint. 600 // See also ThreadWillResume(). 601 if (EnableHardwareSingleStep(false) == KERN_SUCCESS) { 602 if (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0) { 603 ReenableHardwareWatchpoint(m_watchpoint_hw_index); 604 m_watchpoint_resume_single_step_enabled = false; 605 m_watchpoint_did_occur = false; 606 m_watchpoint_hw_index = -1; 607 } else { 608 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 609 "is true but (m_watchpoint_did_occur && " 610 "m_watchpoint_hw_index >= 0) does not hold!"); 611 } 612 } else { 613 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled " 614 "is true but unable to disable single step!"); 615 } 616 } 617 618 // Are we stepping a single instruction? 619 if (GetGPRState(true) == KERN_SUCCESS) { 620 // We are single stepping, was this the primary thread? 621 if (m_thread->IsStepping()) { 622 success = EnableHardwareSingleStep(false) == KERN_SUCCESS; 623 } else { 624 // The MachThread will automatically restore the suspend count 625 // in ThreadDidStop(), so we don't need to do anything here if 626 // we weren't the primary thread the last time 627 } 628 } 629 return success; 630 } 631 632 bool DNBArchMachARM::NotifyException(MachException::Data &exc) { 633 switch (exc.exc_type) { 634 default: 635 break; 636 case EXC_BREAKPOINT: 637 if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_DA_DEBUG) { 638 // The data break address is passed as exc_data[1]. 639 nub_addr_t addr = exc.exc_data[1]; 640 // Find the hardware index with the side effect of possibly massaging the 641 // addr to return the starting address as seen from the debugger side. 642 uint32_t hw_index = GetHardwareWatchpointHit(addr); 643 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 644 "watchpoint %d was hit on address " 645 "0x%llx", 646 hw_index, (uint64_t)addr); 647 const int num_watchpoints = NumSupportedHardwareWatchpoints(); 648 for (int i = 0; i < num_watchpoints; i++) { 649 if (LoHi[i] != 0 && LoHi[i] == hw_index && LoHi[i] != i && 650 GetWatchpointAddressByIndex(i) != INVALID_NUB_ADDRESS) { 651 addr = GetWatchpointAddressByIndex(i); 652 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException " 653 "It is a linked watchpoint; " 654 "rewritten to index %d addr 0x%llx", 655 LoHi[i], (uint64_t)addr); 656 } 657 } 658 if (hw_index != INVALID_NUB_HW_INDEX) { 659 m_watchpoint_did_occur = true; 660 m_watchpoint_hw_index = hw_index; 661 exc.exc_data[1] = addr; 662 // Piggyback the hw_index in the exc.data. 663 exc.exc_data.push_back(hw_index); 664 } 665 666 return true; 667 } 668 break; 669 } 670 return false; 671 } 672 673 bool DNBArchMachARM::StepNotComplete() { 674 if (m_hw_single_chained_step_addr != INVALID_NUB_ADDRESS) { 675 kern_return_t kret = KERN_INVALID_ARGUMENT; 676 kret = GetGPRState(false); 677 if (kret == KERN_SUCCESS) { 678 if (m_state.context.gpr.__pc == m_hw_single_chained_step_addr) { 679 DNBLogThreadedIf(LOG_STEP, "Need to step some more at 0x%8.8llx", 680 (uint64_t)m_hw_single_chained_step_addr); 681 return true; 682 } 683 } 684 } 685 686 m_hw_single_chained_step_addr = INVALID_NUB_ADDRESS; 687 return false; 688 } 689 690 // Set the single step bit in the processor status register. 691 kern_return_t DNBArchMachARM::EnableHardwareSingleStep(bool enable) { 692 DNBError err; 693 DNBLogThreadedIf(LOG_STEP, "%s( enable = %d )", __FUNCTION__, enable); 694 695 err = GetGPRState(false); 696 697 if (err.Fail()) { 698 err.LogThreaded("%s: failed to read the GPR registers", __FUNCTION__); 699 return err.Error(); 700 } 701 702 err = GetDBGState(false); 703 704 if (err.Fail()) { 705 err.LogThreaded("%s: failed to read the DBG registers", __FUNCTION__); 706 return err.Error(); 707 } 708 709 // The use of __arm64__ here is not ideal. If debugserver is running on 710 // an armv8 device, regardless of whether it was built for arch arm or arch 711 // arm64, 712 // it needs to use the MDSCR_EL1 SS bit to single instruction step. 713 714 #if defined(__arm64__) || defined(__aarch64__) 715 if (enable) { 716 DNBLogThreadedIf(LOG_STEP, 717 "%s: Setting MDSCR_EL1 Single Step bit at pc 0x%llx", 718 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc); 719 m_state.dbg.__mdscr_el1 |= 720 1; // Set bit 0 (single step, SS) in the MDSCR_EL1. 721 } else { 722 DNBLogThreadedIf(LOG_STEP, 723 "%s: Clearing MDSCR_EL1 Single Step bit at pc 0x%llx", 724 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc); 725 m_state.dbg.__mdscr_el1 &= 726 ~(1ULL); // Clear bit 0 (single step, SS) in the MDSCR_EL1. 727 } 728 #else 729 const uint32_t i = 0; 730 if (enable) { 731 m_hw_single_chained_step_addr = INVALID_NUB_ADDRESS; 732 733 // Save our previous state 734 m_dbg_save = m_state.dbg; 735 // Set a breakpoint that will stop when the PC doesn't match the current 736 // one! 737 m_state.dbg.__bvr[i] = 738 m_state.context.gpr.__pc & 739 0xFFFFFFFCu; // Set the current PC as the breakpoint address 740 m_state.dbg.__bcr[i] = BCR_M_IMVA_MISMATCH | // Stop on address mismatch 741 S_USER | // Stop only in user mode 742 BCR_ENABLE; // Enable this breakpoint 743 if (m_state.context.gpr.__cpsr & 0x20) { 744 // Thumb breakpoint 745 if (m_state.context.gpr.__pc & 2) 746 m_state.dbg.__bcr[i] |= BAS_IMVA_2_3; 747 else 748 m_state.dbg.__bcr[i] |= BAS_IMVA_0_1; 749 750 uint16_t opcode; 751 if (sizeof(opcode) == 752 m_thread->Process()->Task().ReadMemory(m_state.context.gpr.__pc, 753 sizeof(opcode), &opcode)) { 754 if (IsThumb32Opcode(opcode)) { 755 // 32 bit thumb opcode... 756 if (m_state.context.gpr.__pc & 2) { 757 // We can't take care of a 32 bit thumb instruction single step 758 // with just IVA mismatching. We will need to chain an extra 759 // hardware single step in order to complete this single step... 760 m_hw_single_chained_step_addr = m_state.context.gpr.__pc + 2; 761 } else { 762 // Extend the number of bits to ignore for the mismatch 763 m_state.dbg.__bcr[i] |= BAS_IMVA_ALL; 764 } 765 } 766 } 767 } else { 768 // ARM breakpoint 769 m_state.dbg.__bcr[i] |= BAS_IMVA_ALL; // Stop when any address bits change 770 } 771 772 DNBLogThreadedIf(LOG_STEP, "%s: BVR%u=0x%8.8x BCR%u=0x%8.8x", __FUNCTION__, 773 i, m_state.dbg.__bvr[i], i, m_state.dbg.__bcr[i]); 774 775 for (uint32_t j = i + 1; j < 16; ++j) { 776 // Disable all others 777 m_state.dbg.__bvr[j] = 0; 778 m_state.dbg.__bcr[j] = 0; 779 } 780 } else { 781 // Just restore the state we had before we did single stepping 782 m_state.dbg = m_dbg_save; 783 } 784 #endif 785 786 return SetDBGState(false); 787 } 788 789 // return 1 if bit "BIT" is set in "value" 790 static inline uint32_t bit(uint32_t value, uint32_t bit) { 791 return (value >> bit) & 1u; 792 } 793 794 // return the bitfield "value[msbit:lsbit]". 795 static inline uint32_t bits(uint32_t value, uint32_t msbit, uint32_t lsbit) { 796 assert(msbit >= lsbit); 797 uint32_t shift_left = sizeof(value) * 8 - 1 - msbit; 798 value <<= 799 shift_left; // shift anything above the msbit off of the unsigned edge 800 value >>= (shift_left + lsbit); // shift it back again down to the lsbit 801 // (including undoing any shift from above) 802 return value; // return our result 803 } 804 805 bool DNBArchMachARM::ConditionPassed(uint8_t condition, uint32_t cpsr) { 806 uint32_t cpsr_n = bit(cpsr, 31); // Negative condition code flag 807 uint32_t cpsr_z = bit(cpsr, 30); // Zero condition code flag 808 uint32_t cpsr_c = bit(cpsr, 29); // Carry condition code flag 809 uint32_t cpsr_v = bit(cpsr, 28); // Overflow condition code flag 810 811 switch (condition) { 812 case COND_EQ: // (0x0) 813 if (cpsr_z == 1) 814 return true; 815 break; 816 case COND_NE: // (0x1) 817 if (cpsr_z == 0) 818 return true; 819 break; 820 case COND_CS: // (0x2) 821 if (cpsr_c == 1) 822 return true; 823 break; 824 case COND_CC: // (0x3) 825 if (cpsr_c == 0) 826 return true; 827 break; 828 case COND_MI: // (0x4) 829 if (cpsr_n == 1) 830 return true; 831 break; 832 case COND_PL: // (0x5) 833 if (cpsr_n == 0) 834 return true; 835 break; 836 case COND_VS: // (0x6) 837 if (cpsr_v == 1) 838 return true; 839 break; 840 case COND_VC: // (0x7) 841 if (cpsr_v == 0) 842 return true; 843 break; 844 case COND_HI: // (0x8) 845 if ((cpsr_c == 1) && (cpsr_z == 0)) 846 return true; 847 break; 848 case COND_LS: // (0x9) 849 if ((cpsr_c == 0) || (cpsr_z == 1)) 850 return true; 851 break; 852 case COND_GE: // (0xA) 853 if (cpsr_n == cpsr_v) 854 return true; 855 break; 856 case COND_LT: // (0xB) 857 if (cpsr_n != cpsr_v) 858 return true; 859 break; 860 case COND_GT: // (0xC) 861 if ((cpsr_z == 0) && (cpsr_n == cpsr_v)) 862 return true; 863 break; 864 case COND_LE: // (0xD) 865 if ((cpsr_z == 1) || (cpsr_n != cpsr_v)) 866 return true; 867 break; 868 default: 869 return true; 870 break; 871 } 872 873 return false; 874 } 875 876 uint32_t DNBArchMachARM::NumSupportedHardwareBreakpoints() { 877 // Set the init value to something that will let us know that we need to 878 // autodetect how many breakpoints are supported dynamically... 879 static uint32_t g_num_supported_hw_breakpoints = UINT_MAX; 880 if (g_num_supported_hw_breakpoints == UINT_MAX) { 881 // Set this to zero in case we can't tell if there are any HW breakpoints 882 g_num_supported_hw_breakpoints = 0; 883 884 size_t len; 885 uint32_t n = 0; 886 len = sizeof(n); 887 if (::sysctlbyname("hw.optional.breakpoint", &n, &len, NULL, 0) == 0) { 888 g_num_supported_hw_breakpoints = n; 889 DNBLogThreadedIf(LOG_THREAD, "hw.optional.breakpoint=%u", n); 890 } else { 891 #if !defined(__arm64__) && !defined(__aarch64__) 892 // Read the DBGDIDR to get the number of available hardware breakpoints 893 // However, in some of our current armv7 processors, hardware 894 // breakpoints/watchpoints were not properly connected. So detect those 895 // cases using a field in a sysctl. For now we are using "hw.cpusubtype" 896 // field to distinguish CPU architectures. This is a hack until we can 897 // get <rdar://problem/6372672> fixed, at which point we will switch to 898 // using a different sysctl string that will tell us how many BRPs 899 // are available to us directly without having to read DBGDIDR. 900 uint32_t register_DBGDIDR; 901 902 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 903 uint32_t numBRPs = bits(register_DBGDIDR, 27, 24); 904 // Zero is reserved for the BRP count, so don't increment it if it is zero 905 if (numBRPs > 0) 906 numBRPs++; 907 DNBLogThreadedIf(LOG_THREAD, "DBGDIDR=0x%8.8x (number BRP pairs = %u)", 908 register_DBGDIDR, numBRPs); 909 910 if (numBRPs > 0) { 911 uint32_t cpusubtype; 912 len = sizeof(cpusubtype); 913 // TODO: remove this hack and change to using hw.optional.xx when 914 // implmented 915 if (::sysctlbyname("hw.cpusubtype", &cpusubtype, &len, NULL, 0) == 0) { 916 DNBLogThreadedIf(LOG_THREAD, "hw.cpusubtype=%d", cpusubtype); 917 if (cpusubtype == CPU_SUBTYPE_ARM_V7) 918 DNBLogThreadedIf(LOG_THREAD, "Hardware breakpoints disabled for " 919 "armv7 (rdar://problem/6372672)"); 920 else 921 g_num_supported_hw_breakpoints = numBRPs; 922 } 923 } 924 #endif 925 } 926 } 927 return g_num_supported_hw_breakpoints; 928 } 929 930 uint32_t DNBArchMachARM::NumSupportedHardwareWatchpoints() { 931 // Set the init value to something that will let us know that we need to 932 // autodetect how many watchpoints are supported dynamically... 933 static uint32_t g_num_supported_hw_watchpoints = UINT_MAX; 934 if (g_num_supported_hw_watchpoints == UINT_MAX) { 935 // Set this to zero in case we can't tell if there are any HW breakpoints 936 g_num_supported_hw_watchpoints = 0; 937 938 size_t len; 939 uint32_t n = 0; 940 len = sizeof(n); 941 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) { 942 g_num_supported_hw_watchpoints = n; 943 DNBLogThreadedIf(LOG_THREAD, "hw.optional.watchpoint=%u", n); 944 } else { 945 #if !defined(__arm64__) && !defined(__aarch64__) 946 // Read the DBGDIDR to get the number of available hardware breakpoints 947 // However, in some of our current armv7 processors, hardware 948 // breakpoints/watchpoints were not properly connected. So detect those 949 // cases using a field in a sysctl. For now we are using "hw.cpusubtype" 950 // field to distinguish CPU architectures. This is a hack until we can 951 // get <rdar://problem/6372672> fixed, at which point we will switch to 952 // using a different sysctl string that will tell us how many WRPs 953 // are available to us directly without having to read DBGDIDR. 954 955 uint32_t register_DBGDIDR; 956 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 957 uint32_t numWRPs = bits(register_DBGDIDR, 31, 28) + 1; 958 DNBLogThreadedIf(LOG_THREAD, "DBGDIDR=0x%8.8x (number WRP pairs = %u)", 959 register_DBGDIDR, numWRPs); 960 961 if (numWRPs > 0) { 962 uint32_t cpusubtype; 963 size_t len; 964 len = sizeof(cpusubtype); 965 // TODO: remove this hack and change to using hw.optional.xx when 966 // implmented 967 if (::sysctlbyname("hw.cpusubtype", &cpusubtype, &len, NULL, 0) == 0) { 968 DNBLogThreadedIf(LOG_THREAD, "hw.cpusubtype=0x%d", cpusubtype); 969 970 if (cpusubtype == CPU_SUBTYPE_ARM_V7) 971 DNBLogThreadedIf(LOG_THREAD, "Hardware watchpoints disabled for " 972 "armv7 (rdar://problem/6372672)"); 973 else 974 g_num_supported_hw_watchpoints = numWRPs; 975 } 976 } 977 #endif 978 } 979 } 980 return g_num_supported_hw_watchpoints; 981 } 982 983 uint32_t DNBArchMachARM::EnableHardwareBreakpoint(nub_addr_t addr, 984 nub_size_t size) { 985 // Make sure our address isn't bogus 986 if (addr & 1) 987 return INVALID_NUB_HW_INDEX; 988 989 kern_return_t kret = GetDBGState(false); 990 991 if (kret == KERN_SUCCESS) { 992 const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints(); 993 uint32_t i; 994 for (i = 0; i < num_hw_breakpoints; ++i) { 995 if ((m_state.dbg.__bcr[i] & BCR_ENABLE) == 0) 996 break; // We found an available hw breakpoint slot (in i) 997 } 998 999 // See if we found an available hw breakpoint slot above 1000 if (i < num_hw_breakpoints) { 1001 // Make sure bits 1:0 are clear in our address 1002 m_state.dbg.__bvr[i] = addr & ~((nub_addr_t)3); 1003 1004 if (size == 2 || addr & 2) { 1005 uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1; 1006 1007 // We have a thumb breakpoint 1008 // We have an ARM breakpoint 1009 m_state.dbg.__bcr[i] = 1010 BCR_M_IMVA_MATCH | // Stop on address mismatch 1011 byte_addr_select | // Set the correct byte address select so we only 1012 // trigger on the correct opcode 1013 S_USER | // Which modes should this breakpoint stop in? 1014 BCR_ENABLE; // Enable this hardware breakpoint 1015 DNBLogThreadedIf(LOG_BREAKPOINTS, 1016 "DNBArchMachARM::EnableHardwareBreakpoint( addr = " 1017 "0x%8.8llx, size = %llu ) - BVR%u/BCR%u = 0x%8.8x / " 1018 "0x%8.8x (Thumb)", 1019 (uint64_t)addr, (uint64_t)size, i, i, 1020 m_state.dbg.__bvr[i], m_state.dbg.__bcr[i]); 1021 } else if (size == 4) { 1022 // We have an ARM breakpoint 1023 m_state.dbg.__bcr[i] = 1024 BCR_M_IMVA_MATCH | // Stop on address mismatch 1025 BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA 1026 S_USER | // Which modes should this breakpoint stop in? 1027 BCR_ENABLE; // Enable this hardware breakpoint 1028 DNBLogThreadedIf(LOG_BREAKPOINTS, 1029 "DNBArchMachARM::EnableHardwareBreakpoint( addr = " 1030 "0x%8.8llx, size = %llu ) - BVR%u/BCR%u = 0x%8.8x / " 1031 "0x%8.8x (ARM)", 1032 (uint64_t)addr, (uint64_t)size, i, i, 1033 m_state.dbg.__bvr[i], m_state.dbg.__bcr[i]); 1034 } 1035 1036 kret = SetDBGState(false); 1037 DNBLogThreadedIf(LOG_BREAKPOINTS, "DNBArchMachARM::" 1038 "EnableHardwareBreakpoint() " 1039 "SetDBGState() => 0x%8.8x.", 1040 kret); 1041 1042 if (kret == KERN_SUCCESS) 1043 return i; 1044 } else { 1045 DNBLogThreadedIf(LOG_BREAKPOINTS, 1046 "DNBArchMachARM::EnableHardwareBreakpoint(addr = " 1047 "0x%8.8llx, size = %llu) => all hardware breakpoint " 1048 "resources are being used.", 1049 (uint64_t)addr, (uint64_t)size); 1050 } 1051 } 1052 1053 return INVALID_NUB_HW_INDEX; 1054 } 1055 1056 bool DNBArchMachARM::DisableHardwareBreakpoint(uint32_t hw_index) { 1057 kern_return_t kret = GetDBGState(false); 1058 1059 const uint32_t num_hw_points = NumSupportedHardwareBreakpoints(); 1060 if (kret == KERN_SUCCESS) { 1061 if (hw_index < num_hw_points) { 1062 m_state.dbg.__bcr[hw_index] = 0; 1063 DNBLogThreadedIf(LOG_BREAKPOINTS, "DNBArchMachARM::SetHardwareBreakpoint(" 1064 " %u ) - BVR%u = 0x%8.8x BCR%u = " 1065 "0x%8.8x", 1066 hw_index, hw_index, m_state.dbg.__bvr[hw_index], 1067 hw_index, m_state.dbg.__bcr[hw_index]); 1068 1069 kret = SetDBGState(false); 1070 1071 if (kret == KERN_SUCCESS) 1072 return true; 1073 } 1074 } 1075 return false; 1076 } 1077 1078 // ARM v7 watchpoints may be either word-size or double-word-size. 1079 // It's implementation defined which they can handle. It looks like on an 1080 // armv8 device, armv7 processes can watch dwords. But on a genuine armv7 1081 // device I tried, only word watchpoints are supported. 1082 1083 #if defined(__arm64__) || defined(__aarch64__) 1084 #define WATCHPOINTS_ARE_DWORD 1 1085 #else 1086 #undef WATCHPOINTS_ARE_DWORD 1087 #endif 1088 1089 uint32_t DNBArchMachARM::EnableHardwareWatchpoint(nub_addr_t addr, 1090 nub_size_t size, bool read, 1091 bool write, 1092 bool also_set_on_task) { 1093 1094 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint(" 1095 "addr = 0x%8.8llx, size = %zu, read = %u, " 1096 "write = %u)", 1097 (uint64_t)addr, size, read, write); 1098 1099 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 1100 1101 // Can't watch zero bytes 1102 if (size == 0) 1103 return INVALID_NUB_HW_INDEX; 1104 1105 // We must watch for either read or write 1106 if (read == false && write == false) 1107 return INVALID_NUB_HW_INDEX; 1108 1109 // Otherwise, can't watch more than 8 bytes per WVR/WCR pair 1110 if (size > 8) 1111 return INVALID_NUB_HW_INDEX; 1112 1113 // Treat arm watchpoints as having an 8-byte alignment requirement. You can put 1114 // a watchpoint on a 4-byte 1115 // offset address but you can only watch 4 bytes with that watchpoint. 1116 1117 // arm watchpoints on an 8-byte (double word) aligned addr can watch any bytes 1118 // in that 1119 // 8-byte long region of memory. They can watch the 1st byte, the 2nd byte, 3rd 1120 // byte, etc, or any 1121 // combination therein by setting the bits in the BAS [12:5] (Byte Address 1122 // Select) field of 1123 // the DBGWCRn_EL1 reg for the watchpoint. 1124 1125 // If the MASK [28:24] bits in the DBGWCRn_EL1 allow a single watchpoint to 1126 // monitor a larger region 1127 // of memory (16 bytes, 32 bytes, or 2GB) but the Byte Address Select bitfield 1128 // then selects a larger 1129 // range of bytes, instead of individual bytes. See the ARMv8 Debug 1130 // Architecture manual for details. 1131 // This implementation does not currently use the MASK bits; the largest single 1132 // region watched by a single 1133 // watchpoint right now is 8-bytes. 1134 1135 #if defined(WATCHPOINTS_ARE_DWORD) 1136 nub_addr_t aligned_wp_address = addr & ~0x7; 1137 uint32_t addr_dword_offset = addr & 0x7; 1138 const int max_watchpoint_size = 8; 1139 #else 1140 nub_addr_t aligned_wp_address = addr & ~0x3; 1141 uint32_t addr_dword_offset = addr & 0x3; 1142 const int max_watchpoint_size = 4; 1143 #endif 1144 1145 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint " 1146 "aligned_wp_address is 0x%llx and " 1147 "addr_dword_offset is 0x%x", 1148 (uint64_t)aligned_wp_address, addr_dword_offset); 1149 1150 // Do we need to split up this logical watchpoint into two hardware watchpoint 1151 // registers? 1152 // e.g. a watchpoint of length 4 on address 6. We need do this with 1153 // one watchpoint on address 0 with bytes 6 & 7 being monitored 1154 // one watchpoint on address 8 with bytes 0, 1, 2, 3 being monitored 1155 1156 if (addr_dword_offset + size > max_watchpoint_size) { 1157 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::" 1158 "EnableHardwareWatchpoint(addr = " 1159 "0x%8.8llx, size = %zu) needs two " 1160 "hardware watchpoints slots to monitor", 1161 (uint64_t)addr, size); 1162 int low_watchpoint_size = max_watchpoint_size - addr_dword_offset; 1163 int high_watchpoint_size = addr_dword_offset + size - max_watchpoint_size; 1164 1165 uint32_t lo = EnableHardwareWatchpoint(addr, low_watchpoint_size, read, 1166 write, also_set_on_task); 1167 if (lo == INVALID_NUB_HW_INDEX) 1168 return INVALID_NUB_HW_INDEX; 1169 uint32_t hi = EnableHardwareWatchpoint( 1170 aligned_wp_address + max_watchpoint_size, high_watchpoint_size, read, 1171 write, also_set_on_task); 1172 if (hi == INVALID_NUB_HW_INDEX) { 1173 DisableHardwareWatchpoint(lo, also_set_on_task); 1174 return INVALID_NUB_HW_INDEX; 1175 } 1176 // Tag this lo->hi mapping in our database. 1177 LoHi[lo] = hi; 1178 return lo; 1179 } 1180 1181 // At this point 1182 // 1 aligned_wp_address is the requested address rounded down to 8-byte 1183 // alignment 1184 // 2 addr_dword_offset is the offset into that double word (8-byte) region 1185 // that we are watching 1186 // 3 size is the number of bytes within that 8-byte region that we are 1187 // watching 1188 1189 // Set the Byte Address Selects bits DBGWCRn_EL1 bits [12:5] based on the 1190 // above. 1191 // The bit shift and negation operation will give us 0b11 for 2, 0b1111 for 4, 1192 // etc, up to 0b11111111 for 8. 1193 // then we shift those bits left by the offset into this dword that we are 1194 // interested in. 1195 // e.g. if we are watching bytes 4,5,6,7 in a dword we want a BAS of 1196 // 0b11110000. 1197 uint32_t byte_address_select = ((1 << size) - 1) << addr_dword_offset; 1198 1199 // Read the debug state 1200 kern_return_t kret = GetDBGState(true); 1201 1202 if (kret == KERN_SUCCESS) { 1203 // Check to make sure we have the needed hardware support 1204 uint32_t i = 0; 1205 1206 for (i = 0; i < num_hw_watchpoints; ++i) { 1207 if ((m_state.dbg.__wcr[i] & WCR_ENABLE) == 0) 1208 break; // We found an available hw watchpoint slot (in i) 1209 } 1210 1211 // See if we found an available hw watchpoint slot above 1212 if (i < num_hw_watchpoints) { 1213 // DumpDBGState(m_state.dbg); 1214 1215 // Clear any previous LoHi joined-watchpoint that may have been in use 1216 LoHi[i] = 0; 1217 1218 // shift our Byte Address Select bits up to the correct bit range for the 1219 // DBGWCRn_EL1 1220 byte_address_select = byte_address_select << 5; 1221 1222 // Make sure bits 1:0 are clear in our address 1223 m_state.dbg.__wvr[i] = aligned_wp_address; // DVA (Data Virtual Address) 1224 m_state.dbg.__wcr[i] = byte_address_select | // Which bytes that follow 1225 // the DVA that we will watch 1226 S_USER | // Stop only in user mode 1227 (read ? WCR_LOAD : 0) | // Stop on read access? 1228 (write ? WCR_STORE : 0) | // Stop on write access? 1229 WCR_ENABLE; // Enable this watchpoint; 1230 1231 DNBLogThreadedIf( 1232 LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint() adding " 1233 "watchpoint on address 0x%llx with control register " 1234 "value 0x%x", 1235 (uint64_t)m_state.dbg.__wvr[i], (uint32_t)m_state.dbg.__wcr[i]); 1236 1237 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 1238 // automatically, don't need to do it here. 1239 1240 kret = SetDBGState(also_set_on_task); 1241 // DumpDBGState(m_state.dbg); 1242 1243 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::" 1244 "EnableHardwareWatchpoint() " 1245 "SetDBGState() => 0x%8.8x.", 1246 kret); 1247 1248 if (kret == KERN_SUCCESS) 1249 return i; 1250 } else { 1251 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::" 1252 "EnableHardwareWatchpoint(): All " 1253 "hardware resources (%u) are in use.", 1254 num_hw_watchpoints); 1255 } 1256 } 1257 return INVALID_NUB_HW_INDEX; 1258 } 1259 1260 bool DNBArchMachARM::ReenableHardwareWatchpoint(uint32_t hw_index) { 1261 // If this logical watchpoint # is actually implemented using 1262 // two hardware watchpoint registers, re-enable both of them. 1263 1264 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 1265 return ReenableHardwareWatchpoint_helper(hw_index) && 1266 ReenableHardwareWatchpoint_helper(LoHi[hw_index]); 1267 } else { 1268 return ReenableHardwareWatchpoint_helper(hw_index); 1269 } 1270 } 1271 1272 bool DNBArchMachARM::ReenableHardwareWatchpoint_helper(uint32_t hw_index) { 1273 kern_return_t kret = GetDBGState(false); 1274 if (kret != KERN_SUCCESS) 1275 return false; 1276 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 1277 if (hw_index >= num_hw_points) 1278 return false; 1279 1280 m_state.dbg.__wvr[hw_index] = m_disabled_watchpoints[hw_index].addr; 1281 m_state.dbg.__wcr[hw_index] = m_disabled_watchpoints[hw_index].control; 1282 1283 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint( " 1284 "%u ) - WVR%u = 0x%8.8llx WCR%u = " 1285 "0x%8.8llx", 1286 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 1287 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 1288 1289 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us 1290 // automatically, don't need to do it here. 1291 1292 kret = SetDBGState(false); 1293 1294 return (kret == KERN_SUCCESS); 1295 } 1296 1297 bool DNBArchMachARM::DisableHardwareWatchpoint(uint32_t hw_index, 1298 bool also_set_on_task) { 1299 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) { 1300 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task) && 1301 DisableHardwareWatchpoint_helper(LoHi[hw_index], also_set_on_task); 1302 } else { 1303 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task); 1304 } 1305 } 1306 1307 bool DNBArchMachARM::DisableHardwareWatchpoint_helper(uint32_t hw_index, 1308 bool also_set_on_task) { 1309 kern_return_t kret = GetDBGState(false); 1310 if (kret != KERN_SUCCESS) 1311 return false; 1312 1313 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 1314 if (hw_index >= num_hw_points) 1315 return false; 1316 1317 m_disabled_watchpoints[hw_index].addr = m_state.dbg.__wvr[hw_index]; 1318 m_disabled_watchpoints[hw_index].control = m_state.dbg.__wcr[hw_index]; 1319 1320 m_state.dbg.__wvr[hw_index] = 0; 1321 m_state.dbg.__wcr[hw_index] = 0; 1322 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::DisableHardwareWatchpoint(" 1323 " %u ) - WVR%u = 0x%8.8llx WCR%u = " 1324 "0x%8.8llx", 1325 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index], 1326 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]); 1327 1328 kret = SetDBGState(also_set_on_task); 1329 1330 return (kret == KERN_SUCCESS); 1331 } 1332 1333 // Returns -1 if the trailing bit patterns are not one of: 1334 // { 0b???1, 0b??10, 0b?100, 0b1000 }. 1335 static inline int32_t LowestBitSet(uint32_t val) { 1336 for (unsigned i = 0; i < 4; ++i) { 1337 if (bit(val, i)) 1338 return i; 1339 } 1340 return -1; 1341 } 1342 1343 // Iterate through the debug registers; return the index of the first watchpoint 1344 // whose address matches. 1345 // As a side effect, the starting address as understood by the debugger is 1346 // returned which could be 1347 // different from 'addr' passed as an in/out argument. 1348 uint32_t DNBArchMachARM::GetHardwareWatchpointHit(nub_addr_t &addr) { 1349 // Read the debug state 1350 kern_return_t kret = GetDBGState(true); 1351 // DumpDBGState(m_state.dbg); 1352 DNBLogThreadedIf( 1353 LOG_WATCHPOINTS, 1354 "DNBArchMachARM::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", 1355 kret); 1356 DNBLogThreadedIf(LOG_WATCHPOINTS, 1357 "DNBArchMachARM::GetHardwareWatchpointHit() addr = 0x%llx", 1358 (uint64_t)addr); 1359 1360 // This is the watchpoint value to match against, i.e., word address. 1361 #if defined(WATCHPOINTS_ARE_DWORD) 1362 nub_addr_t wp_val = addr & ~((nub_addr_t)7); 1363 #else 1364 nub_addr_t wp_val = addr & ~((nub_addr_t)3); 1365 #endif 1366 if (kret == KERN_SUCCESS) { 1367 DBG &debug_state = m_state.dbg; 1368 uint32_t i, num = NumSupportedHardwareWatchpoints(); 1369 for (i = 0; i < num; ++i) { 1370 nub_addr_t wp_addr = GetWatchAddress(debug_state, i); 1371 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::" 1372 "GetHardwareWatchpointHit() slot: %u " 1373 "(addr = 0x%llx).", 1374 i, (uint64_t)wp_addr); 1375 if (wp_val == wp_addr) { 1376 #if defined(WATCHPOINTS_ARE_DWORD) 1377 uint32_t byte_mask = bits(debug_state.__wcr[i], 12, 5); 1378 #else 1379 uint32_t byte_mask = bits(debug_state.__wcr[i], 8, 5); 1380 #endif 1381 1382 // Sanity check the byte_mask, first. 1383 if (LowestBitSet(byte_mask) < 0) 1384 continue; 1385 1386 // Compute the starting address (from the point of view of the 1387 // debugger). 1388 addr = wp_addr + LowestBitSet(byte_mask); 1389 return i; 1390 } 1391 } 1392 } 1393 return INVALID_NUB_HW_INDEX; 1394 } 1395 1396 nub_addr_t DNBArchMachARM::GetWatchpointAddressByIndex(uint32_t hw_index) { 1397 kern_return_t kret = GetDBGState(true); 1398 if (kret != KERN_SUCCESS) 1399 return INVALID_NUB_ADDRESS; 1400 const uint32_t num = NumSupportedHardwareWatchpoints(); 1401 if (hw_index >= num) 1402 return INVALID_NUB_ADDRESS; 1403 if (IsWatchpointEnabled(m_state.dbg, hw_index)) 1404 return GetWatchAddress(m_state.dbg, hw_index); 1405 return INVALID_NUB_ADDRESS; 1406 } 1407 1408 bool DNBArchMachARM::IsWatchpointEnabled(const DBG &debug_state, 1409 uint32_t hw_index) { 1410 // Watchpoint Control Registers, bitfield definitions 1411 // ... 1412 // Bits Value Description 1413 // [0] 0 Watchpoint disabled 1414 // 1 Watchpoint enabled. 1415 return (debug_state.__wcr[hw_index] & 1u); 1416 } 1417 1418 nub_addr_t DNBArchMachARM::GetWatchAddress(const DBG &debug_state, 1419 uint32_t hw_index) { 1420 // Watchpoint Value Registers, bitfield definitions 1421 // Bits Description 1422 // [31:2] Watchpoint value (word address, i.e., 4-byte aligned) 1423 // [1:0] RAZ/SBZP 1424 return bits(debug_state.__wvr[hw_index], 31, 0); 1425 } 1426 1427 //---------------------------------------------------------------------- 1428 // Register information definitions for 32 bit ARMV7. 1429 //---------------------------------------------------------------------- 1430 enum gpr_regnums { 1431 gpr_r0 = 0, 1432 gpr_r1, 1433 gpr_r2, 1434 gpr_r3, 1435 gpr_r4, 1436 gpr_r5, 1437 gpr_r6, 1438 gpr_r7, 1439 gpr_r8, 1440 gpr_r9, 1441 gpr_r10, 1442 gpr_r11, 1443 gpr_r12, 1444 gpr_sp, 1445 gpr_lr, 1446 gpr_pc, 1447 gpr_cpsr 1448 }; 1449 1450 enum { 1451 vfp_s0 = 0, 1452 vfp_s1, 1453 vfp_s2, 1454 vfp_s3, 1455 vfp_s4, 1456 vfp_s5, 1457 vfp_s6, 1458 vfp_s7, 1459 vfp_s8, 1460 vfp_s9, 1461 vfp_s10, 1462 vfp_s11, 1463 vfp_s12, 1464 vfp_s13, 1465 vfp_s14, 1466 vfp_s15, 1467 vfp_s16, 1468 vfp_s17, 1469 vfp_s18, 1470 vfp_s19, 1471 vfp_s20, 1472 vfp_s21, 1473 vfp_s22, 1474 vfp_s23, 1475 vfp_s24, 1476 vfp_s25, 1477 vfp_s26, 1478 vfp_s27, 1479 vfp_s28, 1480 vfp_s29, 1481 vfp_s30, 1482 vfp_s31, 1483 vfp_d0, 1484 vfp_d1, 1485 vfp_d2, 1486 vfp_d3, 1487 vfp_d4, 1488 vfp_d5, 1489 vfp_d6, 1490 vfp_d7, 1491 vfp_d8, 1492 vfp_d9, 1493 vfp_d10, 1494 vfp_d11, 1495 vfp_d12, 1496 vfp_d13, 1497 vfp_d14, 1498 vfp_d15, 1499 vfp_d16, 1500 vfp_d17, 1501 vfp_d18, 1502 vfp_d19, 1503 vfp_d20, 1504 vfp_d21, 1505 vfp_d22, 1506 vfp_d23, 1507 vfp_d24, 1508 vfp_d25, 1509 vfp_d26, 1510 vfp_d27, 1511 vfp_d28, 1512 vfp_d29, 1513 vfp_d30, 1514 vfp_d31, 1515 vfp_q0, 1516 vfp_q1, 1517 vfp_q2, 1518 vfp_q3, 1519 vfp_q4, 1520 vfp_q5, 1521 vfp_q6, 1522 vfp_q7, 1523 vfp_q8, 1524 vfp_q9, 1525 vfp_q10, 1526 vfp_q11, 1527 vfp_q12, 1528 vfp_q13, 1529 vfp_q14, 1530 vfp_q15, 1531 #if defined(__arm64__) || defined(__aarch64__) 1532 vfp_fpsr, 1533 vfp_fpcr, 1534 #else 1535 vfp_fpscr 1536 #endif 1537 }; 1538 1539 enum { 1540 exc_exception, 1541 exc_fsr, 1542 exc_far, 1543 }; 1544 1545 #define GPR_OFFSET_IDX(idx) (offsetof(DNBArchMachARM::GPR, __r[idx])) 1546 #define GPR_OFFSET_NAME(reg) (offsetof(DNBArchMachARM::GPR, __##reg)) 1547 1548 #define EXC_OFFSET(reg) \ 1549 (offsetof(DNBArchMachARM::EXC, __##reg) + \ 1550 offsetof(DNBArchMachARM::Context, exc)) 1551 1552 // These macros will auto define the register name, alt name, register size, 1553 // register offset, encoding, format and native register. This ensures that 1554 // the register state structures are defined correctly and have the correct 1555 // sizes and offsets. 1556 #define DEFINE_GPR_IDX(idx, reg, alt, gen) \ 1557 { \ 1558 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_IDX(idx), \ 1559 ehframe_##reg, dwarf_##reg, gen, INVALID_NUB_REGNUM, NULL, NULL \ 1560 } 1561 #define DEFINE_GPR_NAME(reg, alt, gen, inval) \ 1562 { \ 1563 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_NAME(reg), \ 1564 ehframe_##reg, dwarf_##reg, gen, INVALID_NUB_REGNUM, NULL, inval \ 1565 } 1566 1567 // In case we are debugging to a debug target that the ability to 1568 // change into the protected modes with folded registers (ABT, IRQ, 1569 // FIQ, SYS, USR, etc..), we should invalidate r8-r14 if the CPSR 1570 // gets modified. 1571 1572 const char *g_invalidate_cpsr[] = {"r8", "r9", "r10", "r11", 1573 "r12", "sp", "lr", NULL}; 1574 1575 // General purpose registers 1576 const DNBRegisterInfo DNBArchMachARM::g_gpr_registers[] = { 1577 DEFINE_GPR_IDX(0, r0, "arg1", GENERIC_REGNUM_ARG1), 1578 DEFINE_GPR_IDX(1, r1, "arg2", GENERIC_REGNUM_ARG2), 1579 DEFINE_GPR_IDX(2, r2, "arg3", GENERIC_REGNUM_ARG3), 1580 DEFINE_GPR_IDX(3, r3, "arg4", GENERIC_REGNUM_ARG4), 1581 DEFINE_GPR_IDX(4, r4, NULL, INVALID_NUB_REGNUM), 1582 DEFINE_GPR_IDX(5, r5, NULL, INVALID_NUB_REGNUM), 1583 DEFINE_GPR_IDX(6, r6, NULL, INVALID_NUB_REGNUM), 1584 DEFINE_GPR_IDX(7, r7, "fp", GENERIC_REGNUM_FP), 1585 DEFINE_GPR_IDX(8, r8, NULL, INVALID_NUB_REGNUM), 1586 DEFINE_GPR_IDX(9, r9, NULL, INVALID_NUB_REGNUM), 1587 DEFINE_GPR_IDX(10, r10, NULL, INVALID_NUB_REGNUM), 1588 DEFINE_GPR_IDX(11, r11, NULL, INVALID_NUB_REGNUM), 1589 DEFINE_GPR_IDX(12, r12, NULL, INVALID_NUB_REGNUM), 1590 DEFINE_GPR_NAME(sp, "r13", GENERIC_REGNUM_SP, NULL), 1591 DEFINE_GPR_NAME(lr, "r14", GENERIC_REGNUM_RA, NULL), 1592 DEFINE_GPR_NAME(pc, "r15", GENERIC_REGNUM_PC, NULL), 1593 DEFINE_GPR_NAME(cpsr, "flags", GENERIC_REGNUM_FLAGS, g_invalidate_cpsr)}; 1594 1595 const char *g_contained_q0[]{"q0", NULL}; 1596 const char *g_contained_q1[]{"q1", NULL}; 1597 const char *g_contained_q2[]{"q2", NULL}; 1598 const char *g_contained_q3[]{"q3", NULL}; 1599 const char *g_contained_q4[]{"q4", NULL}; 1600 const char *g_contained_q5[]{"q5", NULL}; 1601 const char *g_contained_q6[]{"q6", NULL}; 1602 const char *g_contained_q7[]{"q7", NULL}; 1603 const char *g_contained_q8[]{"q8", NULL}; 1604 const char *g_contained_q9[]{"q9", NULL}; 1605 const char *g_contained_q10[]{"q10", NULL}; 1606 const char *g_contained_q11[]{"q11", NULL}; 1607 const char *g_contained_q12[]{"q12", NULL}; 1608 const char *g_contained_q13[]{"q13", NULL}; 1609 const char *g_contained_q14[]{"q14", NULL}; 1610 const char *g_contained_q15[]{"q15", NULL}; 1611 1612 const char *g_invalidate_q0[]{"q0", "d0", "d1", "s0", "s1", "s2", "s3", NULL}; 1613 const char *g_invalidate_q1[]{"q1", "d2", "d3", "s4", "s5", "s6", "s7", NULL}; 1614 const char *g_invalidate_q2[]{"q2", "d4", "d5", "s8", "s9", "s10", "s11", NULL}; 1615 const char *g_invalidate_q3[]{"q3", "d6", "d7", "s12", 1616 "s13", "s14", "s15", NULL}; 1617 const char *g_invalidate_q4[]{"q4", "d8", "d9", "s16", 1618 "s17", "s18", "s19", NULL}; 1619 const char *g_invalidate_q5[]{"q5", "d10", "d11", "s20", 1620 "s21", "s22", "s23", NULL}; 1621 const char *g_invalidate_q6[]{"q6", "d12", "d13", "s24", 1622 "s25", "s26", "s27", NULL}; 1623 const char *g_invalidate_q7[]{"q7", "d14", "d15", "s28", 1624 "s29", "s30", "s31", NULL}; 1625 const char *g_invalidate_q8[]{"q8", "d16", "d17", NULL}; 1626 const char *g_invalidate_q9[]{"q9", "d18", "d19", NULL}; 1627 const char *g_invalidate_q10[]{"q10", "d20", "d21", NULL}; 1628 const char *g_invalidate_q11[]{"q11", "d22", "d23", NULL}; 1629 const char *g_invalidate_q12[]{"q12", "d24", "d25", NULL}; 1630 const char *g_invalidate_q13[]{"q13", "d26", "d27", NULL}; 1631 const char *g_invalidate_q14[]{"q14", "d28", "d29", NULL}; 1632 const char *g_invalidate_q15[]{"q15", "d30", "d31", NULL}; 1633 1634 #define VFP_S_OFFSET_IDX(idx) \ 1635 (((idx) % 4) * 4) // offset into q reg: 0, 4, 8, 12 1636 #define VFP_D_OFFSET_IDX(idx) (((idx) % 2) * 8) // offset into q reg: 0, 8 1637 #define VFP_Q_OFFSET_IDX(idx) (VFP_S_OFFSET_IDX((idx)*4)) 1638 1639 #define VFP_OFFSET_NAME(reg) \ 1640 (offsetof(DNBArchMachARM::FPU, __##reg) + \ 1641 offsetof(DNBArchMachARM::Context, vfp)) 1642 1643 #define FLOAT_FORMAT Float 1644 1645 #define DEFINE_VFP_S_IDX(idx) \ 1646 e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, FLOAT_FORMAT, 4, \ 1647 VFP_S_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_s##idx, \ 1648 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM 1649 #define DEFINE_VFP_D_IDX(idx) \ 1650 e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, FLOAT_FORMAT, 8, \ 1651 VFP_D_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_d##idx, \ 1652 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM 1653 #define DEFINE_VFP_Q_IDX(idx) \ 1654 e_regSetVFP, vfp_q##idx, "q" #idx, NULL, Vector, VectorOfUInt8, 16, \ 1655 VFP_Q_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_q##idx, \ 1656 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM 1657 1658 // Floating point registers 1659 const DNBRegisterInfo DNBArchMachARM::g_vfp_registers[] = { 1660 {DEFINE_VFP_S_IDX(0), g_contained_q0, g_invalidate_q0}, 1661 {DEFINE_VFP_S_IDX(1), g_contained_q0, g_invalidate_q0}, 1662 {DEFINE_VFP_S_IDX(2), g_contained_q0, g_invalidate_q0}, 1663 {DEFINE_VFP_S_IDX(3), g_contained_q0, g_invalidate_q0}, 1664 {DEFINE_VFP_S_IDX(4), g_contained_q1, g_invalidate_q1}, 1665 {DEFINE_VFP_S_IDX(5), g_contained_q1, g_invalidate_q1}, 1666 {DEFINE_VFP_S_IDX(6), g_contained_q1, g_invalidate_q1}, 1667 {DEFINE_VFP_S_IDX(7), g_contained_q1, g_invalidate_q1}, 1668 {DEFINE_VFP_S_IDX(8), g_contained_q2, g_invalidate_q2}, 1669 {DEFINE_VFP_S_IDX(9), g_contained_q2, g_invalidate_q2}, 1670 {DEFINE_VFP_S_IDX(10), g_contained_q2, g_invalidate_q2}, 1671 {DEFINE_VFP_S_IDX(11), g_contained_q2, g_invalidate_q2}, 1672 {DEFINE_VFP_S_IDX(12), g_contained_q3, g_invalidate_q3}, 1673 {DEFINE_VFP_S_IDX(13), g_contained_q3, g_invalidate_q3}, 1674 {DEFINE_VFP_S_IDX(14), g_contained_q3, g_invalidate_q3}, 1675 {DEFINE_VFP_S_IDX(15), g_contained_q3, g_invalidate_q3}, 1676 {DEFINE_VFP_S_IDX(16), g_contained_q4, g_invalidate_q4}, 1677 {DEFINE_VFP_S_IDX(17), g_contained_q4, g_invalidate_q4}, 1678 {DEFINE_VFP_S_IDX(18), g_contained_q4, g_invalidate_q4}, 1679 {DEFINE_VFP_S_IDX(19), g_contained_q4, g_invalidate_q4}, 1680 {DEFINE_VFP_S_IDX(20), g_contained_q5, g_invalidate_q5}, 1681 {DEFINE_VFP_S_IDX(21), g_contained_q5, g_invalidate_q5}, 1682 {DEFINE_VFP_S_IDX(22), g_contained_q5, g_invalidate_q5}, 1683 {DEFINE_VFP_S_IDX(23), g_contained_q5, g_invalidate_q5}, 1684 {DEFINE_VFP_S_IDX(24), g_contained_q6, g_invalidate_q6}, 1685 {DEFINE_VFP_S_IDX(25), g_contained_q6, g_invalidate_q6}, 1686 {DEFINE_VFP_S_IDX(26), g_contained_q6, g_invalidate_q6}, 1687 {DEFINE_VFP_S_IDX(27), g_contained_q6, g_invalidate_q6}, 1688 {DEFINE_VFP_S_IDX(28), g_contained_q7, g_invalidate_q7}, 1689 {DEFINE_VFP_S_IDX(29), g_contained_q7, g_invalidate_q7}, 1690 {DEFINE_VFP_S_IDX(30), g_contained_q7, g_invalidate_q7}, 1691 {DEFINE_VFP_S_IDX(31), g_contained_q7, g_invalidate_q7}, 1692 1693 {DEFINE_VFP_D_IDX(0), g_contained_q0, g_invalidate_q0}, 1694 {DEFINE_VFP_D_IDX(1), g_contained_q0, g_invalidate_q0}, 1695 {DEFINE_VFP_D_IDX(2), g_contained_q1, g_invalidate_q1}, 1696 {DEFINE_VFP_D_IDX(3), g_contained_q1, g_invalidate_q1}, 1697 {DEFINE_VFP_D_IDX(4), g_contained_q2, g_invalidate_q2}, 1698 {DEFINE_VFP_D_IDX(5), g_contained_q2, g_invalidate_q2}, 1699 {DEFINE_VFP_D_IDX(6), g_contained_q3, g_invalidate_q3}, 1700 {DEFINE_VFP_D_IDX(7), g_contained_q3, g_invalidate_q3}, 1701 {DEFINE_VFP_D_IDX(8), g_contained_q4, g_invalidate_q4}, 1702 {DEFINE_VFP_D_IDX(9), g_contained_q4, g_invalidate_q4}, 1703 {DEFINE_VFP_D_IDX(10), g_contained_q5, g_invalidate_q5}, 1704 {DEFINE_VFP_D_IDX(11), g_contained_q5, g_invalidate_q5}, 1705 {DEFINE_VFP_D_IDX(12), g_contained_q6, g_invalidate_q6}, 1706 {DEFINE_VFP_D_IDX(13), g_contained_q6, g_invalidate_q6}, 1707 {DEFINE_VFP_D_IDX(14), g_contained_q7, g_invalidate_q7}, 1708 {DEFINE_VFP_D_IDX(15), g_contained_q7, g_invalidate_q7}, 1709 {DEFINE_VFP_D_IDX(16), g_contained_q8, g_invalidate_q8}, 1710 {DEFINE_VFP_D_IDX(17), g_contained_q8, g_invalidate_q8}, 1711 {DEFINE_VFP_D_IDX(18), g_contained_q9, g_invalidate_q9}, 1712 {DEFINE_VFP_D_IDX(19), g_contained_q9, g_invalidate_q9}, 1713 {DEFINE_VFP_D_IDX(20), g_contained_q10, g_invalidate_q10}, 1714 {DEFINE_VFP_D_IDX(21), g_contained_q10, g_invalidate_q10}, 1715 {DEFINE_VFP_D_IDX(22), g_contained_q11, g_invalidate_q11}, 1716 {DEFINE_VFP_D_IDX(23), g_contained_q11, g_invalidate_q11}, 1717 {DEFINE_VFP_D_IDX(24), g_contained_q12, g_invalidate_q12}, 1718 {DEFINE_VFP_D_IDX(25), g_contained_q12, g_invalidate_q12}, 1719 {DEFINE_VFP_D_IDX(26), g_contained_q13, g_invalidate_q13}, 1720 {DEFINE_VFP_D_IDX(27), g_contained_q13, g_invalidate_q13}, 1721 {DEFINE_VFP_D_IDX(28), g_contained_q14, g_invalidate_q14}, 1722 {DEFINE_VFP_D_IDX(29), g_contained_q14, g_invalidate_q14}, 1723 {DEFINE_VFP_D_IDX(30), g_contained_q15, g_invalidate_q15}, 1724 {DEFINE_VFP_D_IDX(31), g_contained_q15, g_invalidate_q15}, 1725 1726 {DEFINE_VFP_Q_IDX(0), NULL, g_invalidate_q0}, 1727 {DEFINE_VFP_Q_IDX(1), NULL, g_invalidate_q1}, 1728 {DEFINE_VFP_Q_IDX(2), NULL, g_invalidate_q2}, 1729 {DEFINE_VFP_Q_IDX(3), NULL, g_invalidate_q3}, 1730 {DEFINE_VFP_Q_IDX(4), NULL, g_invalidate_q4}, 1731 {DEFINE_VFP_Q_IDX(5), NULL, g_invalidate_q5}, 1732 {DEFINE_VFP_Q_IDX(6), NULL, g_invalidate_q6}, 1733 {DEFINE_VFP_Q_IDX(7), NULL, g_invalidate_q7}, 1734 {DEFINE_VFP_Q_IDX(8), NULL, g_invalidate_q8}, 1735 {DEFINE_VFP_Q_IDX(9), NULL, g_invalidate_q9}, 1736 {DEFINE_VFP_Q_IDX(10), NULL, g_invalidate_q10}, 1737 {DEFINE_VFP_Q_IDX(11), NULL, g_invalidate_q11}, 1738 {DEFINE_VFP_Q_IDX(12), NULL, g_invalidate_q12}, 1739 {DEFINE_VFP_Q_IDX(13), NULL, g_invalidate_q13}, 1740 {DEFINE_VFP_Q_IDX(14), NULL, g_invalidate_q14}, 1741 {DEFINE_VFP_Q_IDX(15), NULL, g_invalidate_q15}, 1742 1743 #if defined(__arm64__) || defined(__aarch64__) 1744 {e_regSetVFP, vfp_fpsr, "fpsr", NULL, Uint, Hex, 4, VFP_OFFSET_NAME(fpsr), 1745 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1746 INVALID_NUB_REGNUM, NULL, NULL}, 1747 {e_regSetVFP, vfp_fpcr, "fpcr", NULL, Uint, Hex, 4, VFP_OFFSET_NAME(fpcr), 1748 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1749 INVALID_NUB_REGNUM, NULL, NULL} 1750 #else 1751 {e_regSetVFP, vfp_fpscr, "fpscr", NULL, Uint, Hex, 4, 1752 VFP_OFFSET_NAME(fpscr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1753 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL} 1754 #endif 1755 }; 1756 1757 // Exception registers 1758 1759 const DNBRegisterInfo DNBArchMachARM::g_exc_registers[] = { 1760 {e_regSetVFP, exc_exception, "exception", NULL, Uint, Hex, 4, 1761 EXC_OFFSET(exception), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1762 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM}, 1763 {e_regSetVFP, exc_fsr, "fsr", NULL, Uint, Hex, 4, EXC_OFFSET(fsr), 1764 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1765 INVALID_NUB_REGNUM}, 1766 {e_regSetVFP, exc_far, "far", NULL, Uint, Hex, 4, EXC_OFFSET(far), 1767 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, 1768 INVALID_NUB_REGNUM}}; 1769 1770 // Number of registers in each register set 1771 const size_t DNBArchMachARM::k_num_gpr_registers = 1772 sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo); 1773 const size_t DNBArchMachARM::k_num_vfp_registers = 1774 sizeof(g_vfp_registers) / sizeof(DNBRegisterInfo); 1775 const size_t DNBArchMachARM::k_num_exc_registers = 1776 sizeof(g_exc_registers) / sizeof(DNBRegisterInfo); 1777 const size_t DNBArchMachARM::k_num_all_registers = 1778 k_num_gpr_registers + k_num_vfp_registers + k_num_exc_registers; 1779 1780 //---------------------------------------------------------------------- 1781 // Register set definitions. The first definitions at register set index 1782 // of zero is for all registers, followed by other registers sets. The 1783 // register information for the all register set need not be filled in. 1784 //---------------------------------------------------------------------- 1785 const DNBRegisterSetInfo DNBArchMachARM::g_reg_sets[] = { 1786 {"ARM Registers", NULL, k_num_all_registers}, 1787 {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers}, 1788 {"Floating Point Registers", g_vfp_registers, k_num_vfp_registers}, 1789 {"Exception State Registers", g_exc_registers, k_num_exc_registers}}; 1790 // Total number of register sets for this architecture 1791 const size_t DNBArchMachARM::k_num_register_sets = 1792 sizeof(g_reg_sets) / sizeof(DNBRegisterSetInfo); 1793 1794 const DNBRegisterSetInfo * 1795 DNBArchMachARM::GetRegisterSetInfo(nub_size_t *num_reg_sets) { 1796 *num_reg_sets = k_num_register_sets; 1797 return g_reg_sets; 1798 } 1799 1800 bool DNBArchMachARM::GetRegisterValue(uint32_t set, uint32_t reg, 1801 DNBRegisterValue *value) { 1802 if (set == REGISTER_SET_GENERIC) { 1803 switch (reg) { 1804 case GENERIC_REGNUM_PC: // Program Counter 1805 set = e_regSetGPR; 1806 reg = gpr_pc; 1807 break; 1808 1809 case GENERIC_REGNUM_SP: // Stack Pointer 1810 set = e_regSetGPR; 1811 reg = gpr_sp; 1812 break; 1813 1814 case GENERIC_REGNUM_FP: // Frame Pointer 1815 set = e_regSetGPR; 1816 reg = gpr_r7; // is this the right reg? 1817 break; 1818 1819 case GENERIC_REGNUM_RA: // Return Address 1820 set = e_regSetGPR; 1821 reg = gpr_lr; 1822 break; 1823 1824 case GENERIC_REGNUM_FLAGS: // Processor flags register 1825 set = e_regSetGPR; 1826 reg = gpr_cpsr; 1827 break; 1828 1829 default: 1830 return false; 1831 } 1832 } 1833 1834 if (GetRegisterState(set, false) != KERN_SUCCESS) 1835 return false; 1836 1837 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1838 if (regInfo) { 1839 value->info = *regInfo; 1840 switch (set) { 1841 case e_regSetGPR: 1842 if (reg < k_num_gpr_registers) { 1843 value->value.uint32 = m_state.context.gpr.__r[reg]; 1844 return true; 1845 } 1846 break; 1847 1848 case e_regSetVFP: 1849 // "reg" is an index into the floating point register set at this point. 1850 // We need to translate it up so entry 0 in the fp reg set is the same as 1851 // vfp_s0 1852 // in the enumerated values for case statement below. 1853 if (reg >= vfp_s0 && reg <= vfp_s31) { 1854 #if defined(__arm64__) || defined(__aarch64__) 1855 uint32_t *s_reg = 1856 ((uint32_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_s0); 1857 memcpy(&value->value.v_uint8, s_reg, 4); 1858 #else 1859 value->value.uint32 = m_state.context.vfp.__r[reg]; 1860 #endif 1861 return true; 1862 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 1863 #if defined(__arm64__) || defined(__aarch64__) 1864 uint64_t *d_reg = 1865 ((uint64_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_d0); 1866 memcpy(&value->value.v_uint8, d_reg, 8); 1867 #else 1868 uint32_t d_reg_idx = reg - vfp_d0; 1869 uint32_t s_reg_idx = d_reg_idx * 2; 1870 value->value.v_sint32[0] = m_state.context.vfp.__r[s_reg_idx + 0]; 1871 value->value.v_sint32[1] = m_state.context.vfp.__r[s_reg_idx + 1]; 1872 #endif 1873 return true; 1874 } else if (reg >= vfp_q0 && reg <= vfp_q15) { 1875 #if defined(__arm64__) || defined(__aarch64__) 1876 memcpy(&value->value.v_uint8, 1877 (uint8_t *)&m_state.context.vfp.__v[reg - vfp_q0], 16); 1878 #else 1879 uint32_t s_reg_idx = (reg - vfp_q0) * 4; 1880 memcpy(&value->value.v_uint8, 1881 (uint8_t *)&m_state.context.vfp.__r[s_reg_idx], 16); 1882 #endif 1883 return true; 1884 } 1885 #if defined(__arm64__) || defined(__aarch64__) 1886 else if (reg == vfp_fpsr) { 1887 value->value.uint32 = m_state.context.vfp.__fpsr; 1888 return true; 1889 } else if (reg == vfp_fpcr) { 1890 value->value.uint32 = m_state.context.vfp.__fpcr; 1891 return true; 1892 } 1893 #else 1894 else if (reg == vfp_fpscr) { 1895 value->value.uint32 = m_state.context.vfp.__fpscr; 1896 return true; 1897 } 1898 #endif 1899 break; 1900 1901 case e_regSetEXC: 1902 if (reg < k_num_exc_registers) { 1903 value->value.uint32 = (&m_state.context.exc.__exception)[reg]; 1904 return true; 1905 } 1906 break; 1907 } 1908 } 1909 return false; 1910 } 1911 1912 bool DNBArchMachARM::SetRegisterValue(uint32_t set, uint32_t reg, 1913 const DNBRegisterValue *value) { 1914 if (set == REGISTER_SET_GENERIC) { 1915 switch (reg) { 1916 case GENERIC_REGNUM_PC: // Program Counter 1917 set = e_regSetGPR; 1918 reg = gpr_pc; 1919 break; 1920 1921 case GENERIC_REGNUM_SP: // Stack Pointer 1922 set = e_regSetGPR; 1923 reg = gpr_sp; 1924 break; 1925 1926 case GENERIC_REGNUM_FP: // Frame Pointer 1927 set = e_regSetGPR; 1928 reg = gpr_r7; 1929 break; 1930 1931 case GENERIC_REGNUM_RA: // Return Address 1932 set = e_regSetGPR; 1933 reg = gpr_lr; 1934 break; 1935 1936 case GENERIC_REGNUM_FLAGS: // Processor flags register 1937 set = e_regSetGPR; 1938 reg = gpr_cpsr; 1939 break; 1940 1941 default: 1942 return false; 1943 } 1944 } 1945 1946 if (GetRegisterState(set, false) != KERN_SUCCESS) 1947 return false; 1948 1949 bool success = false; 1950 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1951 if (regInfo) { 1952 switch (set) { 1953 case e_regSetGPR: 1954 if (reg < k_num_gpr_registers) { 1955 m_state.context.gpr.__r[reg] = value->value.uint32; 1956 success = true; 1957 } 1958 break; 1959 1960 case e_regSetVFP: 1961 // "reg" is an index into the floating point register set at this point. 1962 // We need to translate it up so entry 0 in the fp reg set is the same as 1963 // vfp_s0 1964 // in the enumerated values for case statement below. 1965 if (reg >= vfp_s0 && reg <= vfp_s31) { 1966 #if defined(__arm64__) || defined(__aarch64__) 1967 uint32_t *s_reg = 1968 ((uint32_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_s0); 1969 memcpy(s_reg, &value->value.v_uint8, 4); 1970 #else 1971 m_state.context.vfp.__r[reg] = value->value.uint32; 1972 #endif 1973 success = true; 1974 } else if (reg >= vfp_d0 && reg <= vfp_d31) { 1975 #if defined(__arm64__) || defined(__aarch64__) 1976 uint64_t *d_reg = 1977 ((uint64_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_d0); 1978 memcpy(d_reg, &value->value.v_uint8, 8); 1979 #else 1980 uint32_t d_reg_idx = reg - vfp_d0; 1981 uint32_t s_reg_idx = d_reg_idx * 2; 1982 m_state.context.vfp.__r[s_reg_idx + 0] = value->value.v_sint32[0]; 1983 m_state.context.vfp.__r[s_reg_idx + 1] = value->value.v_sint32[1]; 1984 #endif 1985 success = true; 1986 } else if (reg >= vfp_q0 && reg <= vfp_q15) { 1987 #if defined(__arm64__) || defined(__aarch64__) 1988 memcpy((uint8_t *)&m_state.context.vfp.__v[reg - vfp_q0], 1989 &value->value.v_uint8, 16); 1990 #else 1991 uint32_t s_reg_idx = (reg - vfp_q0) * 4; 1992 memcpy((uint8_t *)&m_state.context.vfp.__r[s_reg_idx], 1993 &value->value.v_uint8, 16); 1994 #endif 1995 success = true; 1996 } 1997 #if defined(__arm64__) || defined(__aarch64__) 1998 else if (reg == vfp_fpsr) { 1999 m_state.context.vfp.__fpsr = value->value.uint32; 2000 success = true; 2001 } else if (reg == vfp_fpcr) { 2002 m_state.context.vfp.__fpcr = value->value.uint32; 2003 success = true; 2004 } 2005 #else 2006 else if (reg == vfp_fpscr) { 2007 m_state.context.vfp.__fpscr = value->value.uint32; 2008 success = true; 2009 } 2010 #endif 2011 break; 2012 2013 case e_regSetEXC: 2014 if (reg < k_num_exc_registers) { 2015 (&m_state.context.exc.__exception)[reg] = value->value.uint32; 2016 success = true; 2017 } 2018 break; 2019 } 2020 } 2021 if (success) 2022 return SetRegisterState(set) == KERN_SUCCESS; 2023 return false; 2024 } 2025 2026 kern_return_t DNBArchMachARM::GetRegisterState(int set, bool force) { 2027 switch (set) { 2028 case e_regSetALL: 2029 return GetGPRState(force) | GetVFPState(force) | GetEXCState(force) | 2030 GetDBGState(force); 2031 case e_regSetGPR: 2032 return GetGPRState(force); 2033 case e_regSetVFP: 2034 return GetVFPState(force); 2035 case e_regSetEXC: 2036 return GetEXCState(force); 2037 case e_regSetDBG: 2038 return GetDBGState(force); 2039 default: 2040 break; 2041 } 2042 return KERN_INVALID_ARGUMENT; 2043 } 2044 2045 kern_return_t DNBArchMachARM::SetRegisterState(int set) { 2046 // Make sure we have a valid context to set. 2047 kern_return_t err = GetRegisterState(set, false); 2048 if (err != KERN_SUCCESS) 2049 return err; 2050 2051 switch (set) { 2052 case e_regSetALL: 2053 return SetGPRState() | SetVFPState() | SetEXCState() | SetDBGState(false); 2054 case e_regSetGPR: 2055 return SetGPRState(); 2056 case e_regSetVFP: 2057 return SetVFPState(); 2058 case e_regSetEXC: 2059 return SetEXCState(); 2060 case e_regSetDBG: 2061 return SetDBGState(false); 2062 default: 2063 break; 2064 } 2065 return KERN_INVALID_ARGUMENT; 2066 } 2067 2068 bool DNBArchMachARM::RegisterSetStateIsValid(int set) const { 2069 return m_state.RegsAreValid(set); 2070 } 2071 2072 nub_size_t DNBArchMachARM::GetRegisterContext(void *buf, nub_size_t buf_len) { 2073 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 2074 sizeof(m_state.context.exc); 2075 2076 if (buf && buf_len) { 2077 if (size > buf_len) 2078 size = buf_len; 2079 2080 bool force = false; 2081 if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force)) 2082 return 0; 2083 2084 // Copy each struct individually to avoid any padding that might be between 2085 // the structs in m_state.context 2086 uint8_t *p = (uint8_t *)buf; 2087 ::memcpy(p, &m_state.context.gpr, sizeof(m_state.context.gpr)); 2088 p += sizeof(m_state.context.gpr); 2089 ::memcpy(p, &m_state.context.vfp, sizeof(m_state.context.vfp)); 2090 p += sizeof(m_state.context.vfp); 2091 ::memcpy(p, &m_state.context.exc, sizeof(m_state.context.exc)); 2092 p += sizeof(m_state.context.exc); 2093 2094 size_t bytes_written = p - (uint8_t *)buf; 2095 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2096 assert(bytes_written == size); 2097 } 2098 DNBLogThreadedIf( 2099 LOG_THREAD, 2100 "DNBArchMachARM::GetRegisterContext (buf = %p, len = %llu) => %llu", buf, 2101 (uint64_t)buf_len, (uint64_t)size); 2102 // Return the size of the register context even if NULL was passed in 2103 return size; 2104 } 2105 2106 nub_size_t DNBArchMachARM::SetRegisterContext(const void *buf, 2107 nub_size_t buf_len) { 2108 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) + 2109 sizeof(m_state.context.exc); 2110 2111 if (buf == NULL || buf_len == 0) 2112 size = 0; 2113 2114 if (size) { 2115 if (size > buf_len) 2116 size = buf_len; 2117 2118 // Copy each struct individually to avoid any padding that might be between 2119 // the structs in m_state.context 2120 uint8_t *p = (uint8_t *)buf; 2121 ::memcpy(&m_state.context.gpr, p, sizeof(m_state.context.gpr)); 2122 p += sizeof(m_state.context.gpr); 2123 ::memcpy(&m_state.context.vfp, p, sizeof(m_state.context.vfp)); 2124 p += sizeof(m_state.context.vfp); 2125 ::memcpy(&m_state.context.exc, p, sizeof(m_state.context.exc)); 2126 p += sizeof(m_state.context.exc); 2127 2128 size_t bytes_written = p - (uint8_t *)buf; 2129 UNUSED_IF_ASSERT_DISABLED(bytes_written); 2130 assert(bytes_written == size); 2131 2132 if (SetGPRState() | SetVFPState() | SetEXCState()) 2133 return 0; 2134 } 2135 DNBLogThreadedIf( 2136 LOG_THREAD, 2137 "DNBArchMachARM::SetRegisterContext (buf = %p, len = %llu) => %llu", buf, 2138 (uint64_t)buf_len, (uint64_t)size); 2139 return size; 2140 } 2141 2142 uint32_t DNBArchMachARM::SaveRegisterState() { 2143 kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber()); 2144 DNBLogThreadedIf( 2145 LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u " 2146 "(SetGPRState() for stop_count = %u)", 2147 m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount()); 2148 2149 // Always re-read the registers because above we call thread_abort_safely(); 2150 bool force = true; 2151 2152 if ((kret = GetGPRState(force)) != KERN_SUCCESS) { 2153 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::SaveRegisterState () error: " 2154 "GPR regs failed to read: %u ", 2155 kret); 2156 } else if ((kret = GetVFPState(force)) != KERN_SUCCESS) { 2157 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::SaveRegisterState () error: " 2158 "%s regs failed to read: %u", 2159 "VFP", kret); 2160 } else { 2161 const uint32_t save_id = GetNextRegisterStateSaveID(); 2162 m_saved_register_states[save_id] = m_state.context; 2163 return save_id; 2164 } 2165 return UINT32_MAX; 2166 } 2167 2168 bool DNBArchMachARM::RestoreRegisterState(uint32_t save_id) { 2169 SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id); 2170 if (pos != m_saved_register_states.end()) { 2171 m_state.context.gpr = pos->second.gpr; 2172 m_state.context.vfp = pos->second.vfp; 2173 kern_return_t kret; 2174 bool success = true; 2175 if ((kret = SetGPRState()) != KERN_SUCCESS) { 2176 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::RestoreRegisterState " 2177 "(save_id = %u) error: GPR regs failed to " 2178 "write: %u", 2179 save_id, kret); 2180 success = false; 2181 } else if ((kret = SetVFPState()) != KERN_SUCCESS) { 2182 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::RestoreRegisterState " 2183 "(save_id = %u) error: %s regs failed to " 2184 "write: %u", 2185 save_id, "VFP", kret); 2186 success = false; 2187 } 2188 m_saved_register_states.erase(pos); 2189 return success; 2190 } 2191 return false; 2192 } 2193 2194 #endif // #if defined (__arm__) 2195