1 //===-- ARM_DWARF_Registers.h -----------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifndef ARM_DWARF_Registers_h_ 11 #define ARM_DWARF_Registers_h_ 12 13 enum { 14 dwarf_r0 = 0, 15 dwarf_r1, 16 dwarf_r2, 17 dwarf_r3, 18 dwarf_r4, 19 dwarf_r5, 20 dwarf_r6, 21 dwarf_r7, 22 dwarf_r8, 23 dwarf_r9, 24 dwarf_r10, 25 dwarf_r11, 26 dwarf_r12, 27 dwarf_sp, 28 dwarf_lr, 29 dwarf_pc, 30 dwarf_cpsr, 31 32 dwarf_s0 = 64, 33 dwarf_s1, 34 dwarf_s2, 35 dwarf_s3, 36 dwarf_s4, 37 dwarf_s5, 38 dwarf_s6, 39 dwarf_s7, 40 dwarf_s8, 41 dwarf_s9, 42 dwarf_s10, 43 dwarf_s11, 44 dwarf_s12, 45 dwarf_s13, 46 dwarf_s14, 47 dwarf_s15, 48 dwarf_s16, 49 dwarf_s17, 50 dwarf_s18, 51 dwarf_s19, 52 dwarf_s20, 53 dwarf_s21, 54 dwarf_s22, 55 dwarf_s23, 56 dwarf_s24, 57 dwarf_s25, 58 dwarf_s26, 59 dwarf_s27, 60 dwarf_s28, 61 dwarf_s29, 62 dwarf_s30, 63 dwarf_s31, 64 65 // FPA Registers 0-7 66 dwarf_f0 = 96, 67 dwarf_f1, 68 dwarf_f2, 69 dwarf_f3, 70 dwarf_f4, 71 dwarf_f5, 72 dwarf_f6, 73 dwarf_f7, 74 75 // Intel wireless MMX general purpose registers 0 - 7 76 dwarf_wCGR0 = 104, 77 dwarf_wCGR1, 78 dwarf_wCGR2, 79 dwarf_wCGR3, 80 dwarf_wCGR4, 81 dwarf_wCGR5, 82 dwarf_wCGR6, 83 dwarf_wCGR7, 84 85 // XScale accumulator register 0–7 (they do overlap with wCGR0 - wCGR7) 86 dwarf_ACC0 = 104, 87 dwarf_ACC1, 88 dwarf_ACC2, 89 dwarf_ACC3, 90 dwarf_ACC4, 91 dwarf_ACC5, 92 dwarf_ACC6, 93 dwarf_ACC7, 94 95 // Intel wireless MMX data registers 0 - 15 96 dwarf_wR0 = 112, 97 dwarf_wR1, 98 dwarf_wR2, 99 dwarf_wR3, 100 dwarf_wR4, 101 dwarf_wR5, 102 dwarf_wR6, 103 dwarf_wR7, 104 dwarf_wR8, 105 dwarf_wR9, 106 dwarf_wR10, 107 dwarf_wR11, 108 dwarf_wR12, 109 dwarf_wR13, 110 dwarf_wR14, 111 dwarf_wR15, 112 113 dwarf_spsr = 128, 114 dwarf_spsr_fiq, 115 dwarf_spsr_irq, 116 dwarf_spsr_abt, 117 dwarf_spsr_und, 118 dwarf_spsr_svc, 119 120 dwarf_r8_usr = 144, 121 dwarf_r9_usr, 122 dwarf_r10_usr, 123 dwarf_r11_usr, 124 dwarf_r12_usr, 125 dwarf_r13_usr, 126 dwarf_r14_usr, 127 dwarf_r8_fiq, 128 dwarf_r9_fiq, 129 dwarf_r10_fiq, 130 dwarf_r11_fiq, 131 dwarf_r12_fiq, 132 dwarf_r13_fiq, 133 dwarf_r14_fiq, 134 dwarf_r13_irq, 135 dwarf_r14_irq, 136 dwarf_r13_abt, 137 dwarf_r14_abt, 138 dwarf_r13_und, 139 dwarf_r14_und, 140 dwarf_r13_svc, 141 dwarf_r14_svc, 142 143 // Intel wireless MMX control register in co-processor 0 - 7 144 dwarf_wC0 = 192, 145 dwarf_wC1, 146 dwarf_wC2, 147 dwarf_wC3, 148 dwarf_wC4, 149 dwarf_wC5, 150 dwarf_wC6, 151 dwarf_wC7, 152 153 // VFP-v3/Neon 154 dwarf_d0 = 256, 155 dwarf_d1, 156 dwarf_d2, 157 dwarf_d3, 158 dwarf_d4, 159 dwarf_d5, 160 dwarf_d6, 161 dwarf_d7, 162 dwarf_d8, 163 dwarf_d9, 164 dwarf_d10, 165 dwarf_d11, 166 dwarf_d12, 167 dwarf_d13, 168 dwarf_d14, 169 dwarf_d15, 170 dwarf_d16, 171 dwarf_d17, 172 dwarf_d18, 173 dwarf_d19, 174 dwarf_d20, 175 dwarf_d21, 176 dwarf_d22, 177 dwarf_d23, 178 dwarf_d24, 179 dwarf_d25, 180 dwarf_d26, 181 dwarf_d27, 182 dwarf_d28, 183 dwarf_d29, 184 dwarf_d30, 185 dwarf_d31, 186 187 // Neon quadword registers 188 dwarf_q0 = 288, 189 dwarf_q1, 190 dwarf_q2, 191 dwarf_q3, 192 dwarf_q4, 193 dwarf_q5, 194 dwarf_q6, 195 dwarf_q7, 196 dwarf_q8, 197 dwarf_q9, 198 dwarf_q10, 199 dwarf_q11, 200 dwarf_q12, 201 dwarf_q13, 202 dwarf_q14, 203 dwarf_q15 204 }; 205 206 #endif // ARM_DWARF_Registers_h_ 207