1"""
2Test the iteration protocol for frame registers.
3"""
4
5from __future__ import print_function
6
7
8import lldb
9from lldbsuite.test.decorators import *
10from lldbsuite.test.lldbtest import *
11from lldbsuite.test import lldbutil
12
13
14class RegistersIteratorTestCase(TestBase):
15
16    mydir = TestBase.compute_mydir(__file__)
17
18    def setUp(self):
19        # Call super's setUp().
20        TestBase.setUp(self)
21        # Find the line number to break inside main().
22        self.line1 = line_number(
23            'main.cpp', '// Set break point at this line.')
24
25    @add_test_categories(['pyapi'])
26    @expectedFailureNetBSD
27    def test_iter_registers(self):
28        """Test iterator works correctly for lldbutil.iter_registers()."""
29        self.build()
30        exe = self.getBuildArtifact("a.out")
31
32        target = self.dbg.CreateTarget(exe)
33        self.assertTrue(target, VALID_TARGET)
34
35        breakpoint = target.BreakpointCreateByLocation("main.cpp", self.line1)
36        self.assertTrue(breakpoint, VALID_BREAKPOINT)
37
38        # Now launch the process, and do not stop at entry point.
39        process = target.LaunchSimple(
40            None, None, self.get_process_working_directory())
41
42        if not process:
43            self.fail("SBTarget.LaunchProcess() failed")
44
45        import lldbsuite.test.lldbutil as lldbutil
46        for thread in process:
47            if thread.GetStopReason() == lldb.eStopReasonBreakpoint:
48                for frame in thread:
49                    # Dump the registers of this frame using
50                    # lldbutil.get_GPRs() and friends.
51                    if self.TraceOn():
52                        print(frame)
53
54                    REGs = lldbutil.get_GPRs(frame)
55                    num = len(REGs)
56                    if self.TraceOn():
57                        print(
58                            "\nNumber of general purpose registers: %d" %
59                            num)
60                    for reg in REGs:
61                        self.assertTrue(reg)
62                        if self.TraceOn():
63                            print("%s => %s" % (reg.GetName(), reg.GetValue()))
64
65                    REGs = lldbutil.get_FPRs(frame)
66                    num = len(REGs)
67                    if self.TraceOn():
68                        print("\nNumber of floating point registers: %d" % num)
69                    for reg in REGs:
70                        self.assertTrue(reg)
71                        if self.TraceOn():
72                            print("%s => %s" % (reg.GetName(), reg.GetValue()))
73
74                    REGs = lldbutil.get_ESRs(frame)
75                    if self.platformIsDarwin():
76                        if self.getArchitecture() != 'armv7' and self.getArchitecture() != 'armv7k':
77                            num = len(REGs)
78                            if self.TraceOn():
79                                print(
80                                    "\nNumber of exception state registers: %d" %
81                                    num)
82                            for reg in REGs:
83                                self.assertTrue(reg)
84                                if self.TraceOn():
85                                    print(
86                                        "%s => %s" %
87                                        (reg.GetName(), reg.GetValue()))
88                    else:
89                        self.assertIsNone(REGs)
90
91                    # And these should also work.
92                    for kind in ["General Purpose Registers",
93                                 "Floating Point Registers"]:
94                        REGs = lldbutil.get_registers(frame, kind)
95                        self.assertTrue(REGs)
96
97                    REGs = lldbutil.get_registers(
98                        frame, "Exception State Registers")
99                    if self.platformIsDarwin():
100                        if self.getArchitecture() != 'armv7' and self.getArchitecture() != 'armv7k':
101                            self.assertIsNotNone(REGs)
102                    else:
103                        self.assertIsNone(REGs)
104
105                    # We've finished dumping the registers for frame #0.
106                    break
107