1"""
2Test the iteration protocol for frame registers.
3"""
4
5from __future__ import print_function
6
7
8import lldb
9from lldbsuite.test.decorators import *
10from lldbsuite.test.lldbtest import *
11from lldbsuite.test import lldbutil
12
13
14class RegistersIteratorTestCase(TestBase):
15
16    mydir = TestBase.compute_mydir(__file__)
17
18    def setUp(self):
19        # Call super's setUp().
20        TestBase.setUp(self)
21        # Find the line number to break inside main().
22        self.line1 = line_number(
23            'main.cpp', '// Set break point at this line.')
24
25    def test_iter_registers(self):
26        """Test iterator works correctly for lldbutil.iter_registers()."""
27        self.build()
28        exe = self.getBuildArtifact("a.out")
29
30        target = self.dbg.CreateTarget(exe)
31        self.assertTrue(target, VALID_TARGET)
32
33        breakpoint = target.BreakpointCreateByLocation("main.cpp", self.line1)
34        self.assertTrue(breakpoint, VALID_BREAKPOINT)
35
36        # Now launch the process, and do not stop at entry point.
37        process = target.LaunchSimple(
38            None, None, self.get_process_working_directory())
39
40        if not process:
41            self.fail("SBTarget.LaunchProcess() failed")
42
43        import lldbsuite.test.lldbutil as lldbutil
44        for thread in process:
45            if thread.GetStopReason() == lldb.eStopReasonBreakpoint:
46                for frame in thread:
47                    # Dump the registers of this frame using
48                    # lldbutil.get_GPRs() and friends.
49                    if self.TraceOn():
50                        print(frame)
51
52                    REGs = lldbutil.get_GPRs(frame)
53                    num = len(REGs)
54                    if self.TraceOn():
55                        print(
56                            "\nNumber of general purpose registers: %d" %
57                            num)
58                    for reg in REGs:
59                        self.assertTrue(reg)
60                        if self.TraceOn():
61                            print("%s => %s" % (reg.GetName(), reg.GetValue()))
62
63                    REGs = lldbutil.get_FPRs(frame)
64                    num = len(REGs)
65                    if self.TraceOn():
66                        print("\nNumber of floating point registers: %d" % num)
67                    for reg in REGs:
68                        self.assertTrue(reg)
69                        if self.TraceOn():
70                            print("%s => %s" % (reg.GetName(), reg.GetValue()))
71
72                    REGs = lldbutil.get_ESRs(frame)
73                    if self.platformIsDarwin():
74                        if self.getArchitecture() != 'armv7' and self.getArchitecture() != 'armv7k':
75                            num = len(REGs)
76                            if self.TraceOn():
77                                print(
78                                    "\nNumber of exception state registers: %d" %
79                                    num)
80                            for reg in REGs:
81                                self.assertTrue(reg)
82                                if self.TraceOn():
83                                    print(
84                                        "%s => %s" %
85                                        (reg.GetName(), reg.GetValue()))
86                    else:
87                        self.assertIsNone(REGs)
88
89                    # And these should also work.
90                    for kind in ["General Purpose Registers",
91                                 "Floating Point Registers"]:
92                        REGs = lldbutil.get_registers(frame, kind)
93                        self.assertTrue(REGs)
94
95                    REGs = lldbutil.get_registers(
96                        frame, "Exception State Registers")
97                    if self.platformIsDarwin():
98                        if self.getArchitecture() != 'armv7' and self.getArchitecture() != 'armv7k':
99                            self.assertIsNotNone(REGs)
100                    else:
101                        self.assertIsNone(REGs)
102
103                    # We've finished dumping the registers for frame #0.
104                    break
105