1"""
2Test the iteration protocol for frame registers.
3"""
4
5from __future__ import print_function
6
7
8import lldb
9from lldbsuite.test.decorators import *
10from lldbsuite.test.lldbtest import *
11from lldbsuite.test import lldbutil
12
13
14class RegistersIteratorTestCase(TestBase):
15
16    def setUp(self):
17        # Call super's setUp().
18        TestBase.setUp(self)
19        # Find the line number to break inside main().
20        self.line1 = line_number(
21            'main.cpp', '// Set break point at this line.')
22
23    def test_iter_registers(self):
24        """Test iterator works correctly for lldbutil.iter_registers()."""
25        self.build()
26        exe = self.getBuildArtifact("a.out")
27
28        target = self.dbg.CreateTarget(exe)
29        self.assertTrue(target, VALID_TARGET)
30
31        breakpoint = target.BreakpointCreateByLocation("main.cpp", self.line1)
32        self.assertTrue(breakpoint, VALID_BREAKPOINT)
33
34        # Now launch the process, and do not stop at entry point.
35        process = target.LaunchSimple(
36            None, None, self.get_process_working_directory())
37
38        if not process:
39            self.fail("SBTarget.LaunchProcess() failed")
40
41        import lldbsuite.test.lldbutil as lldbutil
42        for thread in process:
43            if thread.GetStopReason() == lldb.eStopReasonBreakpoint:
44                for frame in thread:
45                    # Dump the registers of this frame using
46                    # lldbutil.get_GPRs() and friends.
47                    if self.TraceOn():
48                        print(frame)
49
50                    REGs = lldbutil.get_GPRs(frame)
51                    num = len(REGs)
52                    if self.TraceOn():
53                        print(
54                            "\nNumber of general purpose registers: %d" %
55                            num)
56                    for reg in REGs:
57                        self.assertTrue(reg)
58                        if self.TraceOn():
59                            print("%s => %s" % (reg.GetName(), reg.GetValue()))
60
61                    REGs = lldbutil.get_FPRs(frame)
62                    num = len(REGs)
63                    if self.TraceOn():
64                        print("\nNumber of floating point registers: %d" % num)
65                    for reg in REGs:
66                        self.assertTrue(reg)
67                        if self.TraceOn():
68                            print("%s => %s" % (reg.GetName(), reg.GetValue()))
69
70                    REGs = lldbutil.get_ESRs(frame)
71                    if self.platformIsDarwin():
72                        if self.getArchitecture() != 'armv7' and self.getArchitecture() != 'armv7k':
73                            num = len(REGs)
74                            if self.TraceOn():
75                                print(
76                                    "\nNumber of exception state registers: %d" %
77                                    num)
78                            for reg in REGs:
79                                self.assertTrue(reg)
80                                if self.TraceOn():
81                                    print(
82                                        "%s => %s" %
83                                        (reg.GetName(), reg.GetValue()))
84                    else:
85                        self.assertIsNone(REGs)
86
87                    # And these should also work.
88                    for kind in ["General Purpose Registers",
89                                 "Floating Point Registers"]:
90                        REGs = lldbutil.get_registers(frame, kind)
91                        self.assertTrue(REGs)
92
93                    REGs = lldbutil.get_registers(
94                        frame, "Exception State Registers")
95                    if self.platformIsDarwin():
96                        if self.getArchitecture() != 'armv7' and self.getArchitecture() != 'armv7k':
97                            self.assertIsNotNone(REGs)
98                    else:
99                        self.assertIsNone(REGs)
100
101                    # We've finished dumping the registers for frame #0.
102                    break
103