1from __future__ import print_function
2import lldb
3from lldbsuite.test.lldbtest import *
4from lldbsuite.test.decorators import *
5from gdbclientutils import *
6
7
8# This test case is testing three things:
9#
10#  1. three register values will be provided in the ? stop packet (T11) -
11#     registers 0 ("rax"), 1 ("rbx"), and 3 ("rip")
12#  2. ReadRegister packet will provide the value of register 2 ("rsi")
13#  3. The "g" read-all-registers packet is not supported; p must be used
14#     to get the value of register 2 ("rsi")
15#
16# Forcing lldb to use the expedited registers in the stop packet and
17# marking it an error to request that register value is to prevent
18# performance regressions.
19#
20# Some gdb RSP stubs only implement p/P, they do not support g/G.
21# lldb must be able to work with either.
22
23class TestNoGPacketSupported(GDBRemoteTestBase):
24
25    @skipIfXmlSupportMissing
26    def test(self):
27        class MyResponder(MockGDBServerResponder):
28            def haltReason(self):
29                return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;00:7882773ce0ffffff;01:1122334455667788;03:00bc010001000000;"
30
31            def threadStopInfo(self, threadnum):
32                return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;00:7882773ce0ffffff;01:1122334455667788;03:00bc010001000000;"
33
34            def writeRegisters(self):
35                return "E02"
36
37            def readRegisters(self):
38                return "E01"
39
40            def readRegister(self, regnum):
41                # lldb will try sending "p0" to see if the p packet is supported,
42                # give a bogus value; in theory lldb could use this value in the
43                # register context and that would be valid behavior.
44
45                # notably, don't give values for registers 1 & 3 -- lldb should
46                # get those from the ? stop packet ("T11") and it is a pref regression
47                # if lldb is asking for these register values.
48                if regnum == 0:
49                    return "5555555555555555"
50                if regnum == 2:
51                    return "c04825ebfe7f0000" # 0x00007ffeeb2548c0
52
53                return "E03"
54
55            def writeRegister(self, regnum):
56                return "OK"
57
58            def qXferRead(self, obj, annex, offset, length):
59                if annex == "target.xml":
60                    return """<?xml version="1.0"?>
61                        <target version="1.0">
62                          <architecture>i386:x86-64</architecture>
63                          <feature name="org.gnu.gdb.i386.core">
64                            <reg name="rax" bitsize="64" regnum="0" type="code_ptr" group="general"/>
65                            <reg name="rbx" bitsize="64" regnum="1" type="code_ptr" group="general"/>
66                            <reg name="rsi" bitsize="64" regnum="2" type="code_ptr" group="general"/>
67                            <reg name="rip" bitsize="64" regnum="3" type="code_ptr" group="general" altname="pc" generic="pc"/>
68                          </feature>
69                        </target>""", False
70                else:
71                    return None, False
72
73        self.server.responder = MyResponder()
74        target = self.dbg.CreateTarget('')
75        if self.TraceOn():
76          self.runCmd("log enable gdb-remote packets")
77          self.addTearDownHook(
78                lambda: self.runCmd("log disable gdb-remote packets"))
79        process = self.connect(target)
80
81        thread = process.GetThreadAtIndex(0)
82        frame = thread.GetFrameAtIndex(0)
83        rax = frame.FindRegister("rax").GetValueAsUnsigned()
84        rbx = frame.FindRegister("rbx").GetValueAsUnsigned()
85        rsi = frame.FindRegister("rsi").GetValueAsUnsigned()
86        pc = frame.GetPC()
87        rip = frame.FindRegister("rip").GetValueAsUnsigned()
88
89        if self.TraceOn():
90            print("Register values: rax == 0x%x, rbx == 0x%x, rsi == 0x%x, pc == 0x%x, rip == 0x%x" % (rax, rbx, rsi, pc, rip))
91
92        self.assertEqual(rax, 0xffffffe03c778278)
93        self.assertEqual(rbx, 0x8877665544332211)
94        self.assertEqual(rsi, 0x00007ffeeb2548c0)
95        self.assertEqual(pc, 0x10001bc00)
96        self.assertEqual(rip, 0x10001bc00)
97