1 //===-- RegisterInfos_arm.h -------------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifdef DECLARE_REGISTER_INFOS_ARM_STRUCT 11 12 // C Includes 13 #include <stddef.h> 14 15 // C++ Includes 16 // Other libraries and framework includes 17 // Project includes 18 #include "lldb/lldb-private.h" 19 #include "lldb/lldb-defines.h" 20 #include "lldb/lldb-enumerations.h" 21 22 #include "Utility/ARM_ehframe_Registers.h" 23 #include "Utility/ARM_DWARF_Registers.h" 24 25 using namespace lldb; 26 using namespace lldb_private; 27 28 #ifndef GPR_OFFSET 29 #error GPR_OFFSET must be defined before including this header file 30 #endif 31 32 #ifndef FPU_OFFSET 33 #error FPU_OFFSET must be defined before including this header file 34 #endif 35 36 #ifndef EXC_OFFSET 37 #error EXC_OFFSET_NAME must be defined before including this header file 38 #endif 39 40 #ifndef DBG_OFFSET 41 #error DBG_OFFSET_NAME must be defined before including this header file 42 #endif 43 44 #ifndef DEFINE_DBG 45 #error DEFINE_DBG must be defined before including this header file 46 #endif 47 48 enum 49 { 50 gpr_r0 = 0, 51 gpr_r1, 52 gpr_r2, 53 gpr_r3, 54 gpr_r4, 55 gpr_r5, 56 gpr_r6, 57 gpr_r7, 58 gpr_r8, 59 gpr_r9, 60 gpr_r10, 61 gpr_r11, 62 gpr_r12, 63 gpr_r13, gpr_sp = gpr_r13, 64 gpr_r14, gpr_lr = gpr_r14, 65 gpr_r15, gpr_pc = gpr_r15, 66 gpr_cpsr, 67 68 fpu_s0, 69 fpu_s1, 70 fpu_s2, 71 fpu_s3, 72 fpu_s4, 73 fpu_s5, 74 fpu_s6, 75 fpu_s7, 76 fpu_s8, 77 fpu_s9, 78 fpu_s10, 79 fpu_s11, 80 fpu_s12, 81 fpu_s13, 82 fpu_s14, 83 fpu_s15, 84 fpu_s16, 85 fpu_s17, 86 fpu_s18, 87 fpu_s19, 88 fpu_s20, 89 fpu_s21, 90 fpu_s22, 91 fpu_s23, 92 fpu_s24, 93 fpu_s25, 94 fpu_s26, 95 fpu_s27, 96 fpu_s28, 97 fpu_s29, 98 fpu_s30, 99 fpu_s31, 100 fpu_fpscr, 101 102 exc_exception, 103 exc_fsr, 104 exc_far, 105 106 dbg_bvr0, 107 dbg_bvr1, 108 dbg_bvr2, 109 dbg_bvr3, 110 dbg_bvr4, 111 dbg_bvr5, 112 dbg_bvr6, 113 dbg_bvr7, 114 dbg_bvr8, 115 dbg_bvr9, 116 dbg_bvr10, 117 dbg_bvr11, 118 dbg_bvr12, 119 dbg_bvr13, 120 dbg_bvr14, 121 dbg_bvr15, 122 123 dbg_bcr0, 124 dbg_bcr1, 125 dbg_bcr2, 126 dbg_bcr3, 127 dbg_bcr4, 128 dbg_bcr5, 129 dbg_bcr6, 130 dbg_bcr7, 131 dbg_bcr8, 132 dbg_bcr9, 133 dbg_bcr10, 134 dbg_bcr11, 135 dbg_bcr12, 136 dbg_bcr13, 137 dbg_bcr14, 138 dbg_bcr15, 139 140 dbg_wvr0, 141 dbg_wvr1, 142 dbg_wvr2, 143 dbg_wvr3, 144 dbg_wvr4, 145 dbg_wvr5, 146 dbg_wvr6, 147 dbg_wvr7, 148 dbg_wvr8, 149 dbg_wvr9, 150 dbg_wvr10, 151 dbg_wvr11, 152 dbg_wvr12, 153 dbg_wvr13, 154 dbg_wvr14, 155 dbg_wvr15, 156 157 dbg_wcr0, 158 dbg_wcr1, 159 dbg_wcr2, 160 dbg_wcr3, 161 dbg_wcr4, 162 dbg_wcr5, 163 dbg_wcr6, 164 dbg_wcr7, 165 dbg_wcr8, 166 dbg_wcr9, 167 dbg_wcr10, 168 dbg_wcr11, 169 dbg_wcr12, 170 dbg_wcr13, 171 dbg_wcr14, 172 dbg_wcr15, 173 174 k_num_registers 175 }; 176 177 static RegisterInfo g_register_infos_arm[] = { 178 // General purpose registers 179 // NAME ALT SZ OFFSET ENCODING FORMAT EH_FRAME DWARF GENERIC PROCESS PLUGIN LLDB NATIVE VALUE REGS INVALIDATE REGS 180 // ====== ======= == ============= ============= ============ =============== =============== ========================= ===================== ============= ========== =============== 181 { "r0", nullptr, 4, GPR_OFFSET(0), eEncodingUint, eFormatHex, { ehframe_r0, dwarf_r0, LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM, gpr_r0 }, nullptr, nullptr}, 182 { "r1", nullptr, 4, GPR_OFFSET(1), eEncodingUint, eFormatHex, { ehframe_r1, dwarf_r1, LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM, gpr_r1 }, nullptr, nullptr}, 183 { "r2", nullptr, 4, GPR_OFFSET(2), eEncodingUint, eFormatHex, { ehframe_r2, dwarf_r2, LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM, gpr_r2 }, nullptr, nullptr}, 184 { "r3", nullptr, 4, GPR_OFFSET(3), eEncodingUint, eFormatHex, { ehframe_r3, dwarf_r3, LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM, gpr_r3 }, nullptr, nullptr}, 185 { "r4", nullptr, 4, GPR_OFFSET(4), eEncodingUint, eFormatHex, { ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4 }, nullptr, nullptr}, 186 { "r5", nullptr, 4, GPR_OFFSET(5), eEncodingUint, eFormatHex, { ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5 }, nullptr, nullptr}, 187 { "r6", nullptr, 4, GPR_OFFSET(6), eEncodingUint, eFormatHex, { ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6 }, nullptr, nullptr}, 188 { "r7", nullptr, 4, GPR_OFFSET(7), eEncodingUint, eFormatHex, { ehframe_r7, dwarf_r7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r7 }, nullptr, nullptr}, 189 { "r8", nullptr, 4, GPR_OFFSET(8), eEncodingUint, eFormatHex, { ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8 }, nullptr, nullptr}, 190 { "r9", nullptr, 4, GPR_OFFSET(9), eEncodingUint, eFormatHex, { ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9 }, nullptr, nullptr}, 191 { "r10", nullptr, 4, GPR_OFFSET(10), eEncodingUint, eFormatHex, { ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r10 }, nullptr, nullptr}, 192 { "r11", nullptr, 4, GPR_OFFSET(11), eEncodingUint, eFormatHex, { ehframe_r11, dwarf_r11, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, gpr_r11 }, nullptr, nullptr}, 193 { "r12", nullptr, 4, GPR_OFFSET(12), eEncodingUint, eFormatHex, { ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r12 }, nullptr, nullptr}, 194 { "sp", "r13", 4, GPR_OFFSET(13), eEncodingUint, eFormatHex, { ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, gpr_sp }, nullptr, nullptr}, 195 { "lr", "r14", 4, GPR_OFFSET(14), eEncodingUint, eFormatHex, { ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, gpr_lr }, nullptr, nullptr}, 196 { "pc", "r15", 4, GPR_OFFSET(15), eEncodingUint, eFormatHex, { ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, gpr_pc }, nullptr, nullptr}, 197 { "cpsr", "psr", 4, GPR_OFFSET(16), eEncodingUint, eFormatHex, { ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM, gpr_cpsr }, nullptr, nullptr}, 198 199 { "s0", nullptr, 4, FPU_OFFSET(0), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s0 }, nullptr, nullptr}, 200 { "s1", nullptr, 4, FPU_OFFSET(1), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s1 }, nullptr, nullptr}, 201 { "s2", nullptr, 4, FPU_OFFSET(2), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s2 }, nullptr, nullptr}, 202 { "s3", nullptr, 4, FPU_OFFSET(3), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s3 }, nullptr, nullptr}, 203 { "s4", nullptr, 4, FPU_OFFSET(4), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s4 }, nullptr, nullptr}, 204 { "s5", nullptr, 4, FPU_OFFSET(5), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s5 }, nullptr, nullptr}, 205 { "s6", nullptr, 4, FPU_OFFSET(6), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s6 }, nullptr, nullptr}, 206 { "s7", nullptr, 4, FPU_OFFSET(7), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s7 }, nullptr, nullptr}, 207 { "s8", nullptr, 4, FPU_OFFSET(8), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s8 }, nullptr, nullptr}, 208 { "s9", nullptr, 4, FPU_OFFSET(9), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s9 }, nullptr, nullptr}, 209 { "s10", nullptr, 4, FPU_OFFSET(10), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s10 }, nullptr, nullptr}, 210 { "s11", nullptr, 4, FPU_OFFSET(11), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s11 }, nullptr, nullptr}, 211 { "s12", nullptr, 4, FPU_OFFSET(12), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s12 }, nullptr, nullptr}, 212 { "s13", nullptr, 4, FPU_OFFSET(13), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s13 }, nullptr, nullptr}, 213 { "s14", nullptr, 4, FPU_OFFSET(14), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s14 }, nullptr, nullptr}, 214 { "s15", nullptr, 4, FPU_OFFSET(15), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s15 }, nullptr, nullptr}, 215 { "s16", nullptr, 4, FPU_OFFSET(16), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s16 }, nullptr, nullptr}, 216 { "s17", nullptr, 4, FPU_OFFSET(17), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s17 }, nullptr, nullptr}, 217 { "s18", nullptr, 4, FPU_OFFSET(18), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s18 }, nullptr, nullptr}, 218 { "s19", nullptr, 4, FPU_OFFSET(19), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s19 }, nullptr, nullptr}, 219 { "s20", nullptr, 4, FPU_OFFSET(20), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s20 }, nullptr, nullptr}, 220 { "s21", nullptr, 4, FPU_OFFSET(21), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s21 }, nullptr, nullptr}, 221 { "s22", nullptr, 4, FPU_OFFSET(22), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s22 }, nullptr, nullptr}, 222 { "s23", nullptr, 4, FPU_OFFSET(23), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s23 }, nullptr, nullptr}, 223 { "s24", nullptr, 4, FPU_OFFSET(24), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s24 }, nullptr, nullptr}, 224 { "s25", nullptr, 4, FPU_OFFSET(25), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s25 }, nullptr, nullptr}, 225 { "s26", nullptr, 4, FPU_OFFSET(26), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s26 }, nullptr, nullptr}, 226 { "s27", nullptr, 4, FPU_OFFSET(27), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s27 }, nullptr, nullptr}, 227 { "s28", nullptr, 4, FPU_OFFSET(28), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s28 }, nullptr, nullptr}, 228 { "s29", nullptr, 4, FPU_OFFSET(29), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s29 }, nullptr, nullptr}, 229 { "s30", nullptr, 4, FPU_OFFSET(30), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s30 }, nullptr, nullptr}, 230 { "s31", nullptr, 4, FPU_OFFSET(31), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_s31 }, nullptr, nullptr}, 231 { "fpscr", nullptr, 4, FPU_OFFSET(32), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpu_fpscr }, nullptr, nullptr}, 232 233 { "exception",nullptr, 4, EXC_OFFSET(0), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_exception }, nullptr, nullptr}, 234 { "fsr", nullptr, 4, EXC_OFFSET(1), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_fsr }, nullptr, nullptr}, 235 { "far", nullptr, 4, EXC_OFFSET(2), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_far }, nullptr, nullptr}, 236 237 { DEFINE_DBG (bvr, 0) }, 238 { DEFINE_DBG (bvr, 1) }, 239 { DEFINE_DBG (bvr, 2) }, 240 { DEFINE_DBG (bvr, 3) }, 241 { DEFINE_DBG (bvr, 4) }, 242 { DEFINE_DBG (bvr, 5) }, 243 { DEFINE_DBG (bvr, 6) }, 244 { DEFINE_DBG (bvr, 7) }, 245 { DEFINE_DBG (bvr, 8) }, 246 { DEFINE_DBG (bvr, 9) }, 247 { DEFINE_DBG (bvr, 10) }, 248 { DEFINE_DBG (bvr, 11) }, 249 { DEFINE_DBG (bvr, 12) }, 250 { DEFINE_DBG (bvr, 13) }, 251 { DEFINE_DBG (bvr, 14) }, 252 { DEFINE_DBG (bvr, 15) }, 253 254 { DEFINE_DBG (bcr, 0) }, 255 { DEFINE_DBG (bcr, 1) }, 256 { DEFINE_DBG (bcr, 2) }, 257 { DEFINE_DBG (bcr, 3) }, 258 { DEFINE_DBG (bcr, 4) }, 259 { DEFINE_DBG (bcr, 5) }, 260 { DEFINE_DBG (bcr, 6) }, 261 { DEFINE_DBG (bcr, 7) }, 262 { DEFINE_DBG (bcr, 8) }, 263 { DEFINE_DBG (bcr, 9) }, 264 { DEFINE_DBG (bcr, 10) }, 265 { DEFINE_DBG (bcr, 11) }, 266 { DEFINE_DBG (bcr, 12) }, 267 { DEFINE_DBG (bcr, 13) }, 268 { DEFINE_DBG (bcr, 14) }, 269 { DEFINE_DBG (bcr, 15) }, 270 271 { DEFINE_DBG (wvr, 0) }, 272 { DEFINE_DBG (wvr, 1) }, 273 { DEFINE_DBG (wvr, 2) }, 274 { DEFINE_DBG (wvr, 3) }, 275 { DEFINE_DBG (wvr, 4) }, 276 { DEFINE_DBG (wvr, 5) }, 277 { DEFINE_DBG (wvr, 6) }, 278 { DEFINE_DBG (wvr, 7) }, 279 { DEFINE_DBG (wvr, 8) }, 280 { DEFINE_DBG (wvr, 9) }, 281 { DEFINE_DBG (wvr, 10) }, 282 { DEFINE_DBG (wvr, 11) }, 283 { DEFINE_DBG (wvr, 12) }, 284 { DEFINE_DBG (wvr, 13) }, 285 { DEFINE_DBG (wvr, 14) }, 286 { DEFINE_DBG (wvr, 15) }, 287 288 { DEFINE_DBG (wcr, 0) }, 289 { DEFINE_DBG (wcr, 1) }, 290 { DEFINE_DBG (wcr, 2) }, 291 { DEFINE_DBG (wcr, 3) }, 292 { DEFINE_DBG (wcr, 4) }, 293 { DEFINE_DBG (wcr, 5) }, 294 { DEFINE_DBG (wcr, 6) }, 295 { DEFINE_DBG (wcr, 7) }, 296 { DEFINE_DBG (wcr, 8) }, 297 { DEFINE_DBG (wcr, 9) }, 298 { DEFINE_DBG (wcr, 10) }, 299 { DEFINE_DBG (wcr, 11) }, 300 { DEFINE_DBG (wcr, 12) }, 301 { DEFINE_DBG (wcr, 13) }, 302 { DEFINE_DBG (wcr, 14) }, 303 { DEFINE_DBG (wcr, 15) } 304 }; 305 306 #endif // DECLARE_REGISTER_INFOS_ARM_STRUCT 307