1 //===-- RegisterInfos_arm.h -------------------------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifdef DECLARE_REGISTER_INFOS_ARM_STRUCT
11 
12 // C Includes
13 #include <stddef.h>
14 
15 // C++ Includes
16 // Other libraries and framework includes
17 // Project includes
18 #include "lldb/lldb-defines.h"
19 #include "lldb/lldb-enumerations.h"
20 #include "lldb/lldb-private.h"
21 
22 #include "Utility/ARM_DWARF_Registers.h"
23 #include "Utility/ARM_ehframe_Registers.h"
24 
25 using namespace lldb;
26 using namespace lldb_private;
27 
28 #ifndef GPR_OFFSET
29 #error GPR_OFFSET must be defined before including this header file
30 #endif
31 
32 #ifndef FPU_OFFSET
33 #error FPU_OFFSET must be defined before including this header file
34 #endif
35 
36 #ifndef FPSCR_OFFSET
37 #error FPSCR_OFFSET must be defined before including this header file
38 #endif
39 
40 #ifndef EXC_OFFSET
41 #error EXC_OFFSET_NAME must be defined before including this header file
42 #endif
43 
44 #ifndef DEFINE_DBG
45 #error DEFINE_DBG must be defined before including this header file
46 #endif
47 
48 enum {
49   gpr_r0 = 0,
50   gpr_r1,
51   gpr_r2,
52   gpr_r3,
53   gpr_r4,
54   gpr_r5,
55   gpr_r6,
56   gpr_r7,
57   gpr_r8,
58   gpr_r9,
59   gpr_r10,
60   gpr_r11,
61   gpr_r12,
62   gpr_r13,
63   gpr_sp = gpr_r13,
64   gpr_r14,
65   gpr_lr = gpr_r14,
66   gpr_r15,
67   gpr_pc = gpr_r15,
68   gpr_cpsr,
69 
70   fpu_s0,
71   fpu_s1,
72   fpu_s2,
73   fpu_s3,
74   fpu_s4,
75   fpu_s5,
76   fpu_s6,
77   fpu_s7,
78   fpu_s8,
79   fpu_s9,
80   fpu_s10,
81   fpu_s11,
82   fpu_s12,
83   fpu_s13,
84   fpu_s14,
85   fpu_s15,
86   fpu_s16,
87   fpu_s17,
88   fpu_s18,
89   fpu_s19,
90   fpu_s20,
91   fpu_s21,
92   fpu_s22,
93   fpu_s23,
94   fpu_s24,
95   fpu_s25,
96   fpu_s26,
97   fpu_s27,
98   fpu_s28,
99   fpu_s29,
100   fpu_s30,
101   fpu_s31,
102   fpu_fpscr,
103 
104   fpu_d0,
105   fpu_d1,
106   fpu_d2,
107   fpu_d3,
108   fpu_d4,
109   fpu_d5,
110   fpu_d6,
111   fpu_d7,
112   fpu_d8,
113   fpu_d9,
114   fpu_d10,
115   fpu_d11,
116   fpu_d12,
117   fpu_d13,
118   fpu_d14,
119   fpu_d15,
120   fpu_d16,
121   fpu_d17,
122   fpu_d18,
123   fpu_d19,
124   fpu_d20,
125   fpu_d21,
126   fpu_d22,
127   fpu_d23,
128   fpu_d24,
129   fpu_d25,
130   fpu_d26,
131   fpu_d27,
132   fpu_d28,
133   fpu_d29,
134   fpu_d30,
135   fpu_d31,
136 
137   fpu_q0,
138   fpu_q1,
139   fpu_q2,
140   fpu_q3,
141   fpu_q4,
142   fpu_q5,
143   fpu_q6,
144   fpu_q7,
145   fpu_q8,
146   fpu_q9,
147   fpu_q10,
148   fpu_q11,
149   fpu_q12,
150   fpu_q13,
151   fpu_q14,
152   fpu_q15,
153 
154   exc_exception,
155   exc_fsr,
156   exc_far,
157 
158   dbg_bvr0,
159   dbg_bvr1,
160   dbg_bvr2,
161   dbg_bvr3,
162   dbg_bvr4,
163   dbg_bvr5,
164   dbg_bvr6,
165   dbg_bvr7,
166   dbg_bvr8,
167   dbg_bvr9,
168   dbg_bvr10,
169   dbg_bvr11,
170   dbg_bvr12,
171   dbg_bvr13,
172   dbg_bvr14,
173   dbg_bvr15,
174 
175   dbg_bcr0,
176   dbg_bcr1,
177   dbg_bcr2,
178   dbg_bcr3,
179   dbg_bcr4,
180   dbg_bcr5,
181   dbg_bcr6,
182   dbg_bcr7,
183   dbg_bcr8,
184   dbg_bcr9,
185   dbg_bcr10,
186   dbg_bcr11,
187   dbg_bcr12,
188   dbg_bcr13,
189   dbg_bcr14,
190   dbg_bcr15,
191 
192   dbg_wvr0,
193   dbg_wvr1,
194   dbg_wvr2,
195   dbg_wvr3,
196   dbg_wvr4,
197   dbg_wvr5,
198   dbg_wvr6,
199   dbg_wvr7,
200   dbg_wvr8,
201   dbg_wvr9,
202   dbg_wvr10,
203   dbg_wvr11,
204   dbg_wvr12,
205   dbg_wvr13,
206   dbg_wvr14,
207   dbg_wvr15,
208 
209   dbg_wcr0,
210   dbg_wcr1,
211   dbg_wcr2,
212   dbg_wcr3,
213   dbg_wcr4,
214   dbg_wcr5,
215   dbg_wcr6,
216   dbg_wcr7,
217   dbg_wcr8,
218   dbg_wcr9,
219   dbg_wcr10,
220   dbg_wcr11,
221   dbg_wcr12,
222   dbg_wcr13,
223   dbg_wcr14,
224   dbg_wcr15,
225 
226   k_num_registers
227 };
228 
229 static uint32_t g_s0_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM};
230 static uint32_t g_s1_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM};
231 static uint32_t g_s2_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM};
232 static uint32_t g_s3_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM};
233 static uint32_t g_s4_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM};
234 static uint32_t g_s5_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM};
235 static uint32_t g_s6_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM};
236 static uint32_t g_s7_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM};
237 static uint32_t g_s8_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM};
238 static uint32_t g_s9_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM};
239 static uint32_t g_s10_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM};
240 static uint32_t g_s11_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM};
241 static uint32_t g_s12_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM};
242 static uint32_t g_s13_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM};
243 static uint32_t g_s14_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM};
244 static uint32_t g_s15_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM};
245 static uint32_t g_s16_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM};
246 static uint32_t g_s17_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM};
247 static uint32_t g_s18_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM};
248 static uint32_t g_s19_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM};
249 static uint32_t g_s20_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM};
250 static uint32_t g_s21_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM};
251 static uint32_t g_s22_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM};
252 static uint32_t g_s23_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM};
253 static uint32_t g_s24_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM};
254 static uint32_t g_s25_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM};
255 static uint32_t g_s26_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM};
256 static uint32_t g_s27_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM};
257 static uint32_t g_s28_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM};
258 static uint32_t g_s29_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM};
259 static uint32_t g_s30_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM};
260 static uint32_t g_s31_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM};
261 
262 static uint32_t g_d0_contains[] = {fpu_s0, fpu_s1, LLDB_INVALID_REGNUM};
263 static uint32_t g_d1_contains[] = {fpu_s2, fpu_s3, LLDB_INVALID_REGNUM};
264 static uint32_t g_d2_contains[] = {fpu_s4, fpu_s5, LLDB_INVALID_REGNUM};
265 static uint32_t g_d3_contains[] = {fpu_s6, fpu_s7, LLDB_INVALID_REGNUM};
266 static uint32_t g_d4_contains[] = {fpu_s8, fpu_s9, LLDB_INVALID_REGNUM};
267 static uint32_t g_d5_contains[] = {fpu_s10, fpu_s11, LLDB_INVALID_REGNUM};
268 static uint32_t g_d6_contains[] = {fpu_s12, fpu_s13, LLDB_INVALID_REGNUM};
269 static uint32_t g_d7_contains[] = {fpu_s14, fpu_s15, LLDB_INVALID_REGNUM};
270 static uint32_t g_d8_contains[] = {fpu_s16, fpu_s17, LLDB_INVALID_REGNUM};
271 static uint32_t g_d9_contains[] = {fpu_s18, fpu_s19, LLDB_INVALID_REGNUM};
272 static uint32_t g_d10_contains[] = {fpu_s20, fpu_s21, LLDB_INVALID_REGNUM};
273 static uint32_t g_d11_contains[] = {fpu_s22, fpu_s23, LLDB_INVALID_REGNUM};
274 static uint32_t g_d12_contains[] = {fpu_s24, fpu_s25, LLDB_INVALID_REGNUM};
275 static uint32_t g_d13_contains[] = {fpu_s26, fpu_s27, LLDB_INVALID_REGNUM};
276 static uint32_t g_d14_contains[] = {fpu_s28, fpu_s29, LLDB_INVALID_REGNUM};
277 static uint32_t g_d15_contains[] = {fpu_s30, fpu_s31, LLDB_INVALID_REGNUM};
278 
279 static uint32_t g_d0_invalidates[] = {fpu_q0, LLDB_INVALID_REGNUM};
280 static uint32_t g_d1_invalidates[] = {fpu_q0, LLDB_INVALID_REGNUM};
281 static uint32_t g_d2_invalidates[] = {fpu_q1, LLDB_INVALID_REGNUM};
282 static uint32_t g_d3_invalidates[] = {fpu_q1, LLDB_INVALID_REGNUM};
283 static uint32_t g_d4_invalidates[] = {fpu_q2, LLDB_INVALID_REGNUM};
284 static uint32_t g_d5_invalidates[] = {fpu_q2, LLDB_INVALID_REGNUM};
285 static uint32_t g_d6_invalidates[] = {fpu_q3, LLDB_INVALID_REGNUM};
286 static uint32_t g_d7_invalidates[] = {fpu_q3, LLDB_INVALID_REGNUM};
287 static uint32_t g_d8_invalidates[] = {fpu_q4, LLDB_INVALID_REGNUM};
288 static uint32_t g_d9_invalidates[] = {fpu_q4, LLDB_INVALID_REGNUM};
289 static uint32_t g_d10_invalidates[] = {fpu_q5, LLDB_INVALID_REGNUM};
290 static uint32_t g_d11_invalidates[] = {fpu_q5, LLDB_INVALID_REGNUM};
291 static uint32_t g_d12_invalidates[] = {fpu_q6, LLDB_INVALID_REGNUM};
292 static uint32_t g_d13_invalidates[] = {fpu_q6, LLDB_INVALID_REGNUM};
293 static uint32_t g_d14_invalidates[] = {fpu_q7, LLDB_INVALID_REGNUM};
294 static uint32_t g_d15_invalidates[] = {fpu_q7, LLDB_INVALID_REGNUM};
295 static uint32_t g_d16_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM};
296 static uint32_t g_d17_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM};
297 static uint32_t g_d18_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM};
298 static uint32_t g_d19_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM};
299 static uint32_t g_d20_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM};
300 static uint32_t g_d21_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM};
301 static uint32_t g_d22_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM};
302 static uint32_t g_d23_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM};
303 static uint32_t g_d24_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM};
304 static uint32_t g_d25_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM};
305 static uint32_t g_d26_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM};
306 static uint32_t g_d27_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM};
307 static uint32_t g_d28_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM};
308 static uint32_t g_d29_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM};
309 static uint32_t g_d30_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM};
310 static uint32_t g_d31_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM};
311 
312 static uint32_t g_q0_contains[] = {
313     fpu_d0, fpu_d1, fpu_s0, fpu_s1, fpu_s2, fpu_s3, LLDB_INVALID_REGNUM};
314 static uint32_t g_q1_contains[] = {
315     fpu_d2, fpu_d3, fpu_s4, fpu_s5, fpu_s6, fpu_s7, LLDB_INVALID_REGNUM};
316 static uint32_t g_q2_contains[] = {
317     fpu_d4, fpu_d5, fpu_s8, fpu_s9, fpu_s10, fpu_s11, LLDB_INVALID_REGNUM};
318 static uint32_t g_q3_contains[] = {
319     fpu_d6, fpu_d7, fpu_s12, fpu_s13, fpu_s14, fpu_s15, LLDB_INVALID_REGNUM};
320 static uint32_t g_q4_contains[] = {
321     fpu_d8, fpu_d9, fpu_s16, fpu_s17, fpu_s18, fpu_s19, LLDB_INVALID_REGNUM};
322 static uint32_t g_q5_contains[] = {
323     fpu_d10, fpu_d11, fpu_s20, fpu_s21, fpu_s22, fpu_s23, LLDB_INVALID_REGNUM};
324 static uint32_t g_q6_contains[] = {
325     fpu_d12, fpu_d13, fpu_s24, fpu_s25, fpu_s26, fpu_s27, LLDB_INVALID_REGNUM};
326 static uint32_t g_q7_contains[] = {
327     fpu_d14, fpu_d15, fpu_s28, fpu_s29, fpu_s30, fpu_s31, LLDB_INVALID_REGNUM};
328 static uint32_t g_q8_contains[] = {fpu_d16, fpu_d17, LLDB_INVALID_REGNUM};
329 static uint32_t g_q9_contains[] = {fpu_d18, fpu_d19, LLDB_INVALID_REGNUM};
330 static uint32_t g_q10_contains[] = {fpu_d20, fpu_d21, LLDB_INVALID_REGNUM};
331 static uint32_t g_q11_contains[] = {fpu_d22, fpu_d23, LLDB_INVALID_REGNUM};
332 static uint32_t g_q12_contains[] = {fpu_d24, fpu_d25, LLDB_INVALID_REGNUM};
333 static uint32_t g_q13_contains[] = {fpu_d26, fpu_d27, LLDB_INVALID_REGNUM};
334 static uint32_t g_q14_contains[] = {fpu_d28, fpu_d29, LLDB_INVALID_REGNUM};
335 static uint32_t g_q15_contains[] = {fpu_d30, fpu_d31, LLDB_INVALID_REGNUM};
336 
337 static RegisterInfo g_register_infos_arm[] = {
338     //  NAME         ALT     SZ   OFFSET          ENCODING          FORMAT
339     //  EH_FRAME             DWARF                GENERIC
340     //  PROCESS PLUGIN       LLDB NATIVE      VALUE REGS      INVALIDATE REGS
341     //  ===========  ======= ==   ==============  ================
342     //  ====================    ===================  ===================
343     //  ==========================  ===================  =============
344     //  ==============  =================
345     {"r0",
346      nullptr,
347      4,
348      GPR_OFFSET(0),
349      eEncodingUint,
350      eFormatHex,
351      {ehframe_r0, dwarf_r0, LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM,
352       gpr_r0},
353      nullptr,
354      nullptr,
355      nullptr,
356      0},
357     {"r1",
358      nullptr,
359      4,
360      GPR_OFFSET(1),
361      eEncodingUint,
362      eFormatHex,
363      {ehframe_r1, dwarf_r1, LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM,
364       gpr_r1},
365      nullptr,
366      nullptr,
367      nullptr,
368      0},
369     {"r2",
370      nullptr,
371      4,
372      GPR_OFFSET(2),
373      eEncodingUint,
374      eFormatHex,
375      {ehframe_r2, dwarf_r2, LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM,
376       gpr_r2},
377      nullptr,
378      nullptr,
379      nullptr,
380      0},
381     {"r3",
382      nullptr,
383      4,
384      GPR_OFFSET(3),
385      eEncodingUint,
386      eFormatHex,
387      {ehframe_r3, dwarf_r3, LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM,
388       gpr_r3},
389      nullptr,
390      nullptr,
391      nullptr,
392      0},
393     {"r4",
394      nullptr,
395      4,
396      GPR_OFFSET(4),
397      eEncodingUint,
398      eFormatHex,
399      {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4},
400      nullptr,
401      nullptr,
402      nullptr,
403      0},
404     {"r5",
405      nullptr,
406      4,
407      GPR_OFFSET(5),
408      eEncodingUint,
409      eFormatHex,
410      {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5},
411      nullptr,
412      nullptr,
413      nullptr,
414      0},
415     {"r6",
416      nullptr,
417      4,
418      GPR_OFFSET(6),
419      eEncodingUint,
420      eFormatHex,
421      {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6},
422      nullptr,
423      nullptr,
424      nullptr,
425      0},
426     {"r7",
427      nullptr,
428      4,
429      GPR_OFFSET(7),
430      eEncodingUint,
431      eFormatHex,
432      {ehframe_r7, dwarf_r7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r7},
433      nullptr,
434      nullptr,
435      nullptr,
436      0},
437     {"r8",
438      nullptr,
439      4,
440      GPR_OFFSET(8),
441      eEncodingUint,
442      eFormatHex,
443      {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8},
444      nullptr,
445      nullptr,
446      nullptr,
447      0},
448     {"r9",
449      nullptr,
450      4,
451      GPR_OFFSET(9),
452      eEncodingUint,
453      eFormatHex,
454      {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9},
455      nullptr,
456      nullptr,
457      nullptr,
458      0},
459     {"r10",
460      nullptr,
461      4,
462      GPR_OFFSET(10),
463      eEncodingUint,
464      eFormatHex,
465      {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
466       gpr_r10},
467      nullptr,
468      nullptr,
469      nullptr,
470      0},
471     {"r11",
472      nullptr,
473      4,
474      GPR_OFFSET(11),
475      eEncodingUint,
476      eFormatHex,
477      {ehframe_r11, dwarf_r11, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM,
478       gpr_r11},
479      nullptr,
480      nullptr,
481      nullptr,
482      0},
483     {"r12",
484      nullptr,
485      4,
486      GPR_OFFSET(12),
487      eEncodingUint,
488      eFormatHex,
489      {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
490       gpr_r12},
491      nullptr,
492      nullptr,
493      nullptr,
494      0},
495     {"sp",
496      "r13",
497      4,
498      GPR_OFFSET(13),
499      eEncodingUint,
500      eFormatHex,
501      {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM,
502       gpr_sp},
503      nullptr,
504      nullptr,
505      nullptr,
506      0},
507     {"lr",
508      "r14",
509      4,
510      GPR_OFFSET(14),
511      eEncodingUint,
512      eFormatHex,
513      {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM,
514       gpr_lr},
515      nullptr,
516      nullptr,
517      nullptr,
518      0},
519     {"pc",
520      "r15",
521      4,
522      GPR_OFFSET(15),
523      eEncodingUint,
524      eFormatHex,
525      {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM,
526       gpr_pc},
527      nullptr,
528      nullptr,
529      nullptr,
530      0},
531     {"cpsr",
532      "psr",
533      4,
534      GPR_OFFSET(16),
535      eEncodingUint,
536      eFormatHex,
537      {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM,
538       gpr_cpsr},
539      nullptr,
540      nullptr,
541      nullptr,
542      0},
543 
544     {"s0",
545      nullptr,
546      4,
547      FPU_OFFSET(0),
548      eEncodingIEEE754,
549      eFormatFloat,
550      {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
551       fpu_s0},
552      nullptr,
553      g_s0_invalidates,
554      nullptr,
555      0},
556     {"s1",
557      nullptr,
558      4,
559      FPU_OFFSET(1),
560      eEncodingIEEE754,
561      eFormatFloat,
562      {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
563       fpu_s1},
564      nullptr,
565      g_s1_invalidates,
566      nullptr,
567      0},
568     {"s2",
569      nullptr,
570      4,
571      FPU_OFFSET(2),
572      eEncodingIEEE754,
573      eFormatFloat,
574      {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
575       fpu_s2},
576      nullptr,
577      g_s2_invalidates,
578      nullptr,
579      0},
580     {"s3",
581      nullptr,
582      4,
583      FPU_OFFSET(3),
584      eEncodingIEEE754,
585      eFormatFloat,
586      {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
587       fpu_s3},
588      nullptr,
589      g_s3_invalidates,
590      nullptr,
591      0},
592     {"s4",
593      nullptr,
594      4,
595      FPU_OFFSET(4),
596      eEncodingIEEE754,
597      eFormatFloat,
598      {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
599       fpu_s4},
600      nullptr,
601      g_s4_invalidates,
602      nullptr,
603      0},
604     {"s5",
605      nullptr,
606      4,
607      FPU_OFFSET(5),
608      eEncodingIEEE754,
609      eFormatFloat,
610      {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
611       fpu_s5},
612      nullptr,
613      g_s5_invalidates,
614      nullptr,
615      0},
616     {"s6",
617      nullptr,
618      4,
619      FPU_OFFSET(6),
620      eEncodingIEEE754,
621      eFormatFloat,
622      {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
623       fpu_s6},
624      nullptr,
625      g_s6_invalidates,
626      nullptr,
627      0},
628     {"s7",
629      nullptr,
630      4,
631      FPU_OFFSET(7),
632      eEncodingIEEE754,
633      eFormatFloat,
634      {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
635       fpu_s7},
636      nullptr,
637      g_s7_invalidates,
638      nullptr,
639      0},
640     {"s8",
641      nullptr,
642      4,
643      FPU_OFFSET(8),
644      eEncodingIEEE754,
645      eFormatFloat,
646      {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
647       fpu_s8},
648      nullptr,
649      g_s8_invalidates,
650      nullptr,
651      0},
652     {"s9",
653      nullptr,
654      4,
655      FPU_OFFSET(9),
656      eEncodingIEEE754,
657      eFormatFloat,
658      {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
659       fpu_s9},
660      nullptr,
661      g_s9_invalidates,
662      nullptr,
663      0},
664     {"s10",
665      nullptr,
666      4,
667      FPU_OFFSET(10),
668      eEncodingIEEE754,
669      eFormatFloat,
670      {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
671       fpu_s10},
672      nullptr,
673      g_s10_invalidates,
674      nullptr,
675      0},
676     {"s11",
677      nullptr,
678      4,
679      FPU_OFFSET(11),
680      eEncodingIEEE754,
681      eFormatFloat,
682      {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
683       fpu_s11},
684      nullptr,
685      g_s11_invalidates,
686      nullptr,
687      0},
688     {"s12",
689      nullptr,
690      4,
691      FPU_OFFSET(12),
692      eEncodingIEEE754,
693      eFormatFloat,
694      {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
695       fpu_s12},
696      nullptr,
697      g_s12_invalidates,
698      nullptr,
699      0},
700     {"s13",
701      nullptr,
702      4,
703      FPU_OFFSET(13),
704      eEncodingIEEE754,
705      eFormatFloat,
706      {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
707       fpu_s13},
708      nullptr,
709      g_s13_invalidates,
710      nullptr,
711      0},
712     {"s14",
713      nullptr,
714      4,
715      FPU_OFFSET(14),
716      eEncodingIEEE754,
717      eFormatFloat,
718      {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
719       fpu_s14},
720      nullptr,
721      g_s14_invalidates,
722      nullptr,
723      0},
724     {"s15",
725      nullptr,
726      4,
727      FPU_OFFSET(15),
728      eEncodingIEEE754,
729      eFormatFloat,
730      {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
731       fpu_s15},
732      nullptr,
733      g_s15_invalidates,
734      nullptr,
735      0},
736     {"s16",
737      nullptr,
738      4,
739      FPU_OFFSET(16),
740      eEncodingIEEE754,
741      eFormatFloat,
742      {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
743       fpu_s16},
744      nullptr,
745      g_s16_invalidates,
746      nullptr,
747      0},
748     {"s17",
749      nullptr,
750      4,
751      FPU_OFFSET(17),
752      eEncodingIEEE754,
753      eFormatFloat,
754      {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
755       fpu_s17},
756      nullptr,
757      g_s17_invalidates,
758      nullptr,
759      0},
760     {"s18",
761      nullptr,
762      4,
763      FPU_OFFSET(18),
764      eEncodingIEEE754,
765      eFormatFloat,
766      {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
767       fpu_s18},
768      nullptr,
769      g_s18_invalidates,
770      nullptr,
771      0},
772     {"s19",
773      nullptr,
774      4,
775      FPU_OFFSET(19),
776      eEncodingIEEE754,
777      eFormatFloat,
778      {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
779       fpu_s19},
780      nullptr,
781      g_s19_invalidates,
782      nullptr,
783      0},
784     {"s20",
785      nullptr,
786      4,
787      FPU_OFFSET(20),
788      eEncodingIEEE754,
789      eFormatFloat,
790      {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
791       fpu_s20},
792      nullptr,
793      g_s20_invalidates,
794      nullptr,
795      0},
796     {"s21",
797      nullptr,
798      4,
799      FPU_OFFSET(21),
800      eEncodingIEEE754,
801      eFormatFloat,
802      {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
803       fpu_s21},
804      nullptr,
805      g_s21_invalidates,
806      nullptr,
807      0},
808     {"s22",
809      nullptr,
810      4,
811      FPU_OFFSET(22),
812      eEncodingIEEE754,
813      eFormatFloat,
814      {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
815       fpu_s22},
816      nullptr,
817      g_s22_invalidates,
818      nullptr,
819      0},
820     {"s23",
821      nullptr,
822      4,
823      FPU_OFFSET(23),
824      eEncodingIEEE754,
825      eFormatFloat,
826      {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
827       fpu_s23},
828      nullptr,
829      g_s23_invalidates,
830      nullptr,
831      0},
832     {"s24",
833      nullptr,
834      4,
835      FPU_OFFSET(24),
836      eEncodingIEEE754,
837      eFormatFloat,
838      {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
839       fpu_s24},
840      nullptr,
841      g_s24_invalidates,
842      nullptr,
843      0},
844     {"s25",
845      nullptr,
846      4,
847      FPU_OFFSET(25),
848      eEncodingIEEE754,
849      eFormatFloat,
850      {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
851       fpu_s25},
852      nullptr,
853      g_s25_invalidates,
854      nullptr,
855      0},
856     {"s26",
857      nullptr,
858      4,
859      FPU_OFFSET(26),
860      eEncodingIEEE754,
861      eFormatFloat,
862      {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
863       fpu_s26},
864      nullptr,
865      g_s26_invalidates,
866      nullptr,
867      0},
868     {"s27",
869      nullptr,
870      4,
871      FPU_OFFSET(27),
872      eEncodingIEEE754,
873      eFormatFloat,
874      {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
875       fpu_s27},
876      nullptr,
877      g_s27_invalidates,
878      nullptr,
879      0},
880     {"s28",
881      nullptr,
882      4,
883      FPU_OFFSET(28),
884      eEncodingIEEE754,
885      eFormatFloat,
886      {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
887       fpu_s28},
888      nullptr,
889      g_s28_invalidates,
890      nullptr,
891      0},
892     {"s29",
893      nullptr,
894      4,
895      FPU_OFFSET(29),
896      eEncodingIEEE754,
897      eFormatFloat,
898      {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
899       fpu_s29},
900      nullptr,
901      g_s29_invalidates,
902      nullptr,
903      0},
904     {"s30",
905      nullptr,
906      4,
907      FPU_OFFSET(30),
908      eEncodingIEEE754,
909      eFormatFloat,
910      {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
911       fpu_s30},
912      nullptr,
913      g_s30_invalidates,
914      nullptr,
915      0},
916     {"s31",
917      nullptr,
918      4,
919      FPU_OFFSET(31),
920      eEncodingIEEE754,
921      eFormatFloat,
922      {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
923       fpu_s31},
924      nullptr,
925      g_s31_invalidates,
926      nullptr,
927      0},
928     {"fpscr",
929      nullptr,
930      4,
931      FPSCR_OFFSET,
932      eEncodingUint,
933      eFormatHex,
934      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
935       LLDB_INVALID_REGNUM, fpu_fpscr},
936      nullptr,
937      nullptr,
938      nullptr,
939      0},
940 
941     {"d0",
942      nullptr,
943      8,
944      FPU_OFFSET(0),
945      eEncodingIEEE754,
946      eFormatFloat,
947      {LLDB_INVALID_REGNUM, dwarf_d0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
948       fpu_d0},
949      g_d0_contains,
950      g_d0_invalidates,
951      nullptr,
952      0},
953     {"d1",
954      nullptr,
955      8,
956      FPU_OFFSET(2),
957      eEncodingIEEE754,
958      eFormatFloat,
959      {LLDB_INVALID_REGNUM, dwarf_d1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
960       fpu_d1},
961      g_d1_contains,
962      g_d1_invalidates,
963      nullptr,
964      0},
965     {"d2",
966      nullptr,
967      8,
968      FPU_OFFSET(4),
969      eEncodingIEEE754,
970      eFormatFloat,
971      {LLDB_INVALID_REGNUM, dwarf_d2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
972       fpu_d2},
973      g_d2_contains,
974      g_d2_invalidates,
975      nullptr,
976      0},
977     {"d3",
978      nullptr,
979      8,
980      FPU_OFFSET(6),
981      eEncodingIEEE754,
982      eFormatFloat,
983      {LLDB_INVALID_REGNUM, dwarf_d3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
984       fpu_d3},
985      g_d3_contains,
986      g_d3_invalidates,
987      nullptr,
988      0},
989     {"d4",
990      nullptr,
991      8,
992      FPU_OFFSET(8),
993      eEncodingIEEE754,
994      eFormatFloat,
995      {LLDB_INVALID_REGNUM, dwarf_d4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
996       fpu_d4},
997      g_d4_contains,
998      g_d4_invalidates,
999      nullptr,
1000      0},
1001     {"d5",
1002      nullptr,
1003      8,
1004      FPU_OFFSET(10),
1005      eEncodingIEEE754,
1006      eFormatFloat,
1007      {LLDB_INVALID_REGNUM, dwarf_d5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1008       fpu_d5},
1009      g_d5_contains,
1010      g_d5_invalidates,
1011      nullptr,
1012      0},
1013     {"d6",
1014      nullptr,
1015      8,
1016      FPU_OFFSET(12),
1017      eEncodingIEEE754,
1018      eFormatFloat,
1019      {LLDB_INVALID_REGNUM, dwarf_d6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1020       fpu_d6},
1021      g_d6_contains,
1022      g_d6_invalidates,
1023      nullptr,
1024      0},
1025     {"d7",
1026      nullptr,
1027      8,
1028      FPU_OFFSET(14),
1029      eEncodingIEEE754,
1030      eFormatFloat,
1031      {LLDB_INVALID_REGNUM, dwarf_d7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1032       fpu_d7},
1033      g_d7_contains,
1034      g_d7_invalidates,
1035      nullptr,
1036      0},
1037     {"d8",
1038      nullptr,
1039      8,
1040      FPU_OFFSET(16),
1041      eEncodingIEEE754,
1042      eFormatFloat,
1043      {LLDB_INVALID_REGNUM, dwarf_d8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1044       fpu_d8},
1045      g_d8_contains,
1046      g_d8_invalidates,
1047      nullptr,
1048      0},
1049     {"d9",
1050      nullptr,
1051      8,
1052      FPU_OFFSET(18),
1053      eEncodingIEEE754,
1054      eFormatFloat,
1055      {LLDB_INVALID_REGNUM, dwarf_d9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1056       fpu_d9},
1057      g_d9_contains,
1058      g_d9_invalidates,
1059      nullptr,
1060      0},
1061     {"d10",
1062      nullptr,
1063      8,
1064      FPU_OFFSET(20),
1065      eEncodingIEEE754,
1066      eFormatFloat,
1067      {LLDB_INVALID_REGNUM, dwarf_d10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1068       fpu_d10},
1069      g_d10_contains,
1070      g_d10_invalidates,
1071      nullptr,
1072      0},
1073     {"d11",
1074      nullptr,
1075      8,
1076      FPU_OFFSET(22),
1077      eEncodingIEEE754,
1078      eFormatFloat,
1079      {LLDB_INVALID_REGNUM, dwarf_d11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1080       fpu_d11},
1081      g_d11_contains,
1082      g_d11_invalidates,
1083      nullptr,
1084      0},
1085     {"d12",
1086      nullptr,
1087      8,
1088      FPU_OFFSET(24),
1089      eEncodingIEEE754,
1090      eFormatFloat,
1091      {LLDB_INVALID_REGNUM, dwarf_d12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1092       fpu_d12},
1093      g_d12_contains,
1094      g_d12_invalidates,
1095      nullptr,
1096      0},
1097     {"d13",
1098      nullptr,
1099      8,
1100      FPU_OFFSET(26),
1101      eEncodingIEEE754,
1102      eFormatFloat,
1103      {LLDB_INVALID_REGNUM, dwarf_d13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1104       fpu_d13},
1105      g_d13_contains,
1106      g_d13_invalidates,
1107      nullptr,
1108      0},
1109     {"d14",
1110      nullptr,
1111      8,
1112      FPU_OFFSET(28),
1113      eEncodingIEEE754,
1114      eFormatFloat,
1115      {LLDB_INVALID_REGNUM, dwarf_d14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1116       fpu_d14},
1117      g_d14_contains,
1118      g_d14_invalidates,
1119      nullptr,
1120      0},
1121     {"d15",
1122      nullptr,
1123      8,
1124      FPU_OFFSET(30),
1125      eEncodingIEEE754,
1126      eFormatFloat,
1127      {LLDB_INVALID_REGNUM, dwarf_d15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1128       fpu_d15},
1129      g_d15_contains,
1130      g_d15_invalidates,
1131      nullptr,
1132      0},
1133     {"d16",
1134      nullptr,
1135      8,
1136      FPU_OFFSET(32),
1137      eEncodingIEEE754,
1138      eFormatFloat,
1139      {LLDB_INVALID_REGNUM, dwarf_d16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1140       fpu_d16},
1141      nullptr,
1142      g_d16_invalidates,
1143      nullptr,
1144      0},
1145     {"d17",
1146      nullptr,
1147      8,
1148      FPU_OFFSET(34),
1149      eEncodingIEEE754,
1150      eFormatFloat,
1151      {LLDB_INVALID_REGNUM, dwarf_d17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1152       fpu_d17},
1153      nullptr,
1154      g_d17_invalidates,
1155      nullptr,
1156      0},
1157     {"d18",
1158      nullptr,
1159      8,
1160      FPU_OFFSET(36),
1161      eEncodingIEEE754,
1162      eFormatFloat,
1163      {LLDB_INVALID_REGNUM, dwarf_d18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1164       fpu_d18},
1165      nullptr,
1166      g_d18_invalidates,
1167      nullptr,
1168      0},
1169     {"d19",
1170      nullptr,
1171      8,
1172      FPU_OFFSET(38),
1173      eEncodingIEEE754,
1174      eFormatFloat,
1175      {LLDB_INVALID_REGNUM, dwarf_d19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1176       fpu_d19},
1177      nullptr,
1178      g_d19_invalidates,
1179      nullptr,
1180      0},
1181     {"d20",
1182      nullptr,
1183      8,
1184      FPU_OFFSET(40),
1185      eEncodingIEEE754,
1186      eFormatFloat,
1187      {LLDB_INVALID_REGNUM, dwarf_d20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1188       fpu_d20},
1189      nullptr,
1190      g_d20_invalidates,
1191      nullptr,
1192      0},
1193     {"d21",
1194      nullptr,
1195      8,
1196      FPU_OFFSET(42),
1197      eEncodingIEEE754,
1198      eFormatFloat,
1199      {LLDB_INVALID_REGNUM, dwarf_d21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1200       fpu_d21},
1201      nullptr,
1202      g_d21_invalidates,
1203      nullptr,
1204      0},
1205     {"d22",
1206      nullptr,
1207      8,
1208      FPU_OFFSET(44),
1209      eEncodingIEEE754,
1210      eFormatFloat,
1211      {LLDB_INVALID_REGNUM, dwarf_d22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1212       fpu_d22},
1213      nullptr,
1214      g_d22_invalidates,
1215      nullptr,
1216      0},
1217     {"d23",
1218      nullptr,
1219      8,
1220      FPU_OFFSET(46),
1221      eEncodingIEEE754,
1222      eFormatFloat,
1223      {LLDB_INVALID_REGNUM, dwarf_d23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1224       fpu_d23},
1225      nullptr,
1226      g_d23_invalidates,
1227      nullptr,
1228      0},
1229     {"d24",
1230      nullptr,
1231      8,
1232      FPU_OFFSET(48),
1233      eEncodingIEEE754,
1234      eFormatFloat,
1235      {LLDB_INVALID_REGNUM, dwarf_d24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1236       fpu_d24},
1237      nullptr,
1238      g_d24_invalidates,
1239      nullptr,
1240      0},
1241     {"d25",
1242      nullptr,
1243      8,
1244      FPU_OFFSET(50),
1245      eEncodingIEEE754,
1246      eFormatFloat,
1247      {LLDB_INVALID_REGNUM, dwarf_d25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1248       fpu_d25},
1249      nullptr,
1250      g_d25_invalidates,
1251      nullptr,
1252      0},
1253     {"d26",
1254      nullptr,
1255      8,
1256      FPU_OFFSET(52),
1257      eEncodingIEEE754,
1258      eFormatFloat,
1259      {LLDB_INVALID_REGNUM, dwarf_d26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1260       fpu_d26},
1261      nullptr,
1262      g_d26_invalidates,
1263      nullptr,
1264      0},
1265     {"d27",
1266      nullptr,
1267      8,
1268      FPU_OFFSET(54),
1269      eEncodingIEEE754,
1270      eFormatFloat,
1271      {LLDB_INVALID_REGNUM, dwarf_d27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1272       fpu_d27},
1273      nullptr,
1274      g_d27_invalidates,
1275      nullptr,
1276      0},
1277     {"d28",
1278      nullptr,
1279      8,
1280      FPU_OFFSET(56),
1281      eEncodingIEEE754,
1282      eFormatFloat,
1283      {LLDB_INVALID_REGNUM, dwarf_d28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1284       fpu_d28},
1285      nullptr,
1286      g_d28_invalidates,
1287      nullptr,
1288      0},
1289     {"d29",
1290      nullptr,
1291      8,
1292      FPU_OFFSET(58),
1293      eEncodingIEEE754,
1294      eFormatFloat,
1295      {LLDB_INVALID_REGNUM, dwarf_d29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1296       fpu_d29},
1297      nullptr,
1298      g_d29_invalidates,
1299      nullptr,
1300      0},
1301     {"d30",
1302      nullptr,
1303      8,
1304      FPU_OFFSET(60),
1305      eEncodingIEEE754,
1306      eFormatFloat,
1307      {LLDB_INVALID_REGNUM, dwarf_d30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1308       fpu_d30},
1309      nullptr,
1310      g_d30_invalidates,
1311      nullptr,
1312      0},
1313     {"d31",
1314      nullptr,
1315      8,
1316      FPU_OFFSET(62),
1317      eEncodingIEEE754,
1318      eFormatFloat,
1319      {LLDB_INVALID_REGNUM, dwarf_d31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1320       fpu_d31},
1321      nullptr,
1322      g_d31_invalidates,
1323      nullptr,
1324      0},
1325 
1326     {"q0",
1327      nullptr,
1328      16,
1329      FPU_OFFSET(0),
1330      eEncodingVector,
1331      eFormatVectorOfUInt8,
1332      {LLDB_INVALID_REGNUM, dwarf_q0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1333       fpu_q0},
1334      g_q0_contains,
1335      nullptr,
1336      nullptr,
1337      0},
1338     {"q1",
1339      nullptr,
1340      16,
1341      FPU_OFFSET(4),
1342      eEncodingVector,
1343      eFormatVectorOfUInt8,
1344      {LLDB_INVALID_REGNUM, dwarf_q1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1345       fpu_q1},
1346      g_q1_contains,
1347      nullptr,
1348      nullptr,
1349      0},
1350     {"q2",
1351      nullptr,
1352      16,
1353      FPU_OFFSET(8),
1354      eEncodingVector,
1355      eFormatVectorOfUInt8,
1356      {LLDB_INVALID_REGNUM, dwarf_q2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1357       fpu_q2},
1358      g_q2_contains,
1359      nullptr,
1360      nullptr,
1361      0},
1362     {"q3",
1363      nullptr,
1364      16,
1365      FPU_OFFSET(12),
1366      eEncodingVector,
1367      eFormatVectorOfUInt8,
1368      {LLDB_INVALID_REGNUM, dwarf_q3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1369       fpu_q3},
1370      g_q3_contains,
1371      nullptr,
1372      nullptr,
1373      0},
1374     {"q4",
1375      nullptr,
1376      16,
1377      FPU_OFFSET(16),
1378      eEncodingVector,
1379      eFormatVectorOfUInt8,
1380      {LLDB_INVALID_REGNUM, dwarf_q4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1381       fpu_q4},
1382      g_q4_contains,
1383      nullptr,
1384      nullptr,
1385      0},
1386     {"q5",
1387      nullptr,
1388      16,
1389      FPU_OFFSET(20),
1390      eEncodingVector,
1391      eFormatVectorOfUInt8,
1392      {LLDB_INVALID_REGNUM, dwarf_q5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1393       fpu_q5},
1394      g_q5_contains,
1395      nullptr,
1396      nullptr,
1397      0},
1398     {"q6",
1399      nullptr,
1400      16,
1401      FPU_OFFSET(24),
1402      eEncodingVector,
1403      eFormatVectorOfUInt8,
1404      {LLDB_INVALID_REGNUM, dwarf_q6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1405       fpu_q6},
1406      g_q6_contains,
1407      nullptr,
1408      nullptr,
1409      0},
1410     {"q7",
1411      nullptr,
1412      16,
1413      FPU_OFFSET(28),
1414      eEncodingVector,
1415      eFormatVectorOfUInt8,
1416      {LLDB_INVALID_REGNUM, dwarf_q7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1417       fpu_q7},
1418      g_q7_contains,
1419      nullptr,
1420      nullptr,
1421      0},
1422     {"q8",
1423      nullptr,
1424      16,
1425      FPU_OFFSET(32),
1426      eEncodingVector,
1427      eFormatVectorOfUInt8,
1428      {LLDB_INVALID_REGNUM, dwarf_q8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1429       fpu_q8},
1430      g_q8_contains,
1431      nullptr,
1432      nullptr,
1433      0},
1434     {"q9",
1435      nullptr,
1436      16,
1437      FPU_OFFSET(36),
1438      eEncodingVector,
1439      eFormatVectorOfUInt8,
1440      {LLDB_INVALID_REGNUM, dwarf_q9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1441       fpu_q9},
1442      g_q9_contains,
1443      nullptr,
1444      nullptr,
1445      0},
1446     {"q10",
1447      nullptr,
1448      16,
1449      FPU_OFFSET(40),
1450      eEncodingVector,
1451      eFormatVectorOfUInt8,
1452      {LLDB_INVALID_REGNUM, dwarf_q10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1453       fpu_q10},
1454      g_q10_contains,
1455      nullptr,
1456      nullptr,
1457      0},
1458     {"q11",
1459      nullptr,
1460      16,
1461      FPU_OFFSET(44),
1462      eEncodingVector,
1463      eFormatVectorOfUInt8,
1464      {LLDB_INVALID_REGNUM, dwarf_q11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1465       fpu_q11},
1466      g_q11_contains,
1467      nullptr,
1468      nullptr,
1469      0},
1470     {"q12",
1471      nullptr,
1472      16,
1473      FPU_OFFSET(48),
1474      eEncodingVector,
1475      eFormatVectorOfUInt8,
1476      {LLDB_INVALID_REGNUM, dwarf_q12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1477       fpu_q12},
1478      g_q12_contains,
1479      nullptr,
1480      nullptr,
1481      0},
1482     {"q13",
1483      nullptr,
1484      16,
1485      FPU_OFFSET(52),
1486      eEncodingVector,
1487      eFormatVectorOfUInt8,
1488      {LLDB_INVALID_REGNUM, dwarf_q13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1489       fpu_q13},
1490      g_q13_contains,
1491      nullptr,
1492      nullptr,
1493      0},
1494     {"q14",
1495      nullptr,
1496      16,
1497      FPU_OFFSET(56),
1498      eEncodingVector,
1499      eFormatVectorOfUInt8,
1500      {LLDB_INVALID_REGNUM, dwarf_q14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1501       fpu_q14},
1502      g_q14_contains,
1503      nullptr,
1504      nullptr,
1505      0},
1506     {"q15",
1507      nullptr,
1508      16,
1509      FPU_OFFSET(60),
1510      eEncodingVector,
1511      eFormatVectorOfUInt8,
1512      {LLDB_INVALID_REGNUM, dwarf_q15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1513       fpu_q15},
1514      g_q15_contains,
1515      nullptr,
1516      nullptr,
1517      0},
1518 
1519     {"exception",
1520      nullptr,
1521      4,
1522      EXC_OFFSET(0),
1523      eEncodingUint,
1524      eFormatHex,
1525      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1526       LLDB_INVALID_REGNUM, exc_exception},
1527      nullptr,
1528      nullptr,
1529      nullptr,
1530      0},
1531     {"fsr",
1532      nullptr,
1533      4,
1534      EXC_OFFSET(1),
1535      eEncodingUint,
1536      eFormatHex,
1537      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1538       LLDB_INVALID_REGNUM, exc_fsr},
1539      nullptr,
1540      nullptr,
1541      nullptr,
1542      0},
1543     {"far",
1544      nullptr,
1545      4,
1546      EXC_OFFSET(2),
1547      eEncodingUint,
1548      eFormatHex,
1549      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
1550       LLDB_INVALID_REGNUM, exc_far},
1551      nullptr,
1552      nullptr,
1553      nullptr,
1554      0},
1555 
1556     {DEFINE_DBG(bvr, 0)},
1557     {DEFINE_DBG(bvr, 1)},
1558     {DEFINE_DBG(bvr, 2)},
1559     {DEFINE_DBG(bvr, 3)},
1560     {DEFINE_DBG(bvr, 4)},
1561     {DEFINE_DBG(bvr, 5)},
1562     {DEFINE_DBG(bvr, 6)},
1563     {DEFINE_DBG(bvr, 7)},
1564     {DEFINE_DBG(bvr, 8)},
1565     {DEFINE_DBG(bvr, 9)},
1566     {DEFINE_DBG(bvr, 10)},
1567     {DEFINE_DBG(bvr, 11)},
1568     {DEFINE_DBG(bvr, 12)},
1569     {DEFINE_DBG(bvr, 13)},
1570     {DEFINE_DBG(bvr, 14)},
1571     {DEFINE_DBG(bvr, 15)},
1572 
1573     {DEFINE_DBG(bcr, 0)},
1574     {DEFINE_DBG(bcr, 1)},
1575     {DEFINE_DBG(bcr, 2)},
1576     {DEFINE_DBG(bcr, 3)},
1577     {DEFINE_DBG(bcr, 4)},
1578     {DEFINE_DBG(bcr, 5)},
1579     {DEFINE_DBG(bcr, 6)},
1580     {DEFINE_DBG(bcr, 7)},
1581     {DEFINE_DBG(bcr, 8)},
1582     {DEFINE_DBG(bcr, 9)},
1583     {DEFINE_DBG(bcr, 10)},
1584     {DEFINE_DBG(bcr, 11)},
1585     {DEFINE_DBG(bcr, 12)},
1586     {DEFINE_DBG(bcr, 13)},
1587     {DEFINE_DBG(bcr, 14)},
1588     {DEFINE_DBG(bcr, 15)},
1589 
1590     {DEFINE_DBG(wvr, 0)},
1591     {DEFINE_DBG(wvr, 1)},
1592     {DEFINE_DBG(wvr, 2)},
1593     {DEFINE_DBG(wvr, 3)},
1594     {DEFINE_DBG(wvr, 4)},
1595     {DEFINE_DBG(wvr, 5)},
1596     {DEFINE_DBG(wvr, 6)},
1597     {DEFINE_DBG(wvr, 7)},
1598     {DEFINE_DBG(wvr, 8)},
1599     {DEFINE_DBG(wvr, 9)},
1600     {DEFINE_DBG(wvr, 10)},
1601     {DEFINE_DBG(wvr, 11)},
1602     {DEFINE_DBG(wvr, 12)},
1603     {DEFINE_DBG(wvr, 13)},
1604     {DEFINE_DBG(wvr, 14)},
1605     {DEFINE_DBG(wvr, 15)},
1606 
1607     {DEFINE_DBG(wcr, 0)},
1608     {DEFINE_DBG(wcr, 1)},
1609     {DEFINE_DBG(wcr, 2)},
1610     {DEFINE_DBG(wcr, 3)},
1611     {DEFINE_DBG(wcr, 4)},
1612     {DEFINE_DBG(wcr, 5)},
1613     {DEFINE_DBG(wcr, 6)},
1614     {DEFINE_DBG(wcr, 7)},
1615     {DEFINE_DBG(wcr, 8)},
1616     {DEFINE_DBG(wcr, 9)},
1617     {DEFINE_DBG(wcr, 10)},
1618     {DEFINE_DBG(wcr, 11)},
1619     {DEFINE_DBG(wcr, 12)},
1620     {DEFINE_DBG(wcr, 13)},
1621     {DEFINE_DBG(wcr, 14)},
1622     {DEFINE_DBG(wcr, 15)}};
1623 
1624 #endif // DECLARE_REGISTER_INFOS_ARM_STRUCT
1625