1 //===-- RegisterInfoPOSIX_arm64.h -------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H
10 #define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H
11 
12 #include "RegisterInfoAndSetInterface.h"
13 #include "lldb/Target/RegisterContext.h"
14 #include "lldb/lldb-private.h"
15 #include <map>
16 
17 enum class SVEState { Unknown, Disabled, FPSIMD, Full };
18 
19 class RegisterInfoPOSIX_arm64
20     : public lldb_private::RegisterInfoAndSetInterface {
21 public:
22   enum { GPRegSet = 0, FPRegSet, SVERegSet };
23 
24   // AArch64 Register set FP/SIMD feature configuration
25   enum {
26     eVectorQuadwordAArch64,
27     eVectorQuadwordAArch64SVE,
28     eVectorQuadwordAArch64SVEMax = 256
29   };
30 
31   // based on RegisterContextDarwin_arm64.h
32   struct GPR {
33     uint64_t x[29]; // x0-x28
34     uint64_t fp;    // x29
35     uint64_t lr;    // x30
36     uint64_t sp;    // x31
37     uint64_t pc;    // pc
38     uint32_t cpsr;  // cpsr
39   };
40 
41   // based on RegisterContextDarwin_arm64.h
42   struct VReg {
43     uint8_t bytes[16];
44   };
45 
46   // based on RegisterContextDarwin_arm64.h
47   struct FPU {
48     VReg v[32];
49     uint32_t fpsr;
50     uint32_t fpcr;
51   };
52 
53   // based on RegisterContextDarwin_arm64.h
54   struct EXC {
55     uint64_t far;       // Virtual Fault Address
56     uint32_t esr;       // Exception syndrome
57     uint32_t exception; // number of arm exception token
58   };
59 
60   // based on RegisterContextDarwin_arm64.h
61   struct DBG {
62     uint64_t bvr[16];
63     uint64_t bcr[16];
64     uint64_t wvr[16];
65     uint64_t wcr[16];
66     uint64_t mdscr_el1;
67   };
68 
69   RegisterInfoPOSIX_arm64(const lldb_private::ArchSpec &target_arch);
70 
71   size_t GetGPRSize() const override;
72 
73   size_t GetFPRSize() const override;
74 
75   const lldb_private::RegisterInfo *GetRegisterInfo() const override;
76 
77   uint32_t GetRegisterCount() const override;
78 
79   const lldb_private::RegisterSet *
80   GetRegisterSet(size_t reg_set) const override;
81 
82   size_t GetRegisterSetCount() const override;
83 
84   size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
85 
86   uint32_t ConfigureVectorRegisterInfos(uint32_t mode);
87 
88   bool VectorSizeIsValid(uint32_t vq) {
89     if (vq >= eVectorQuadwordAArch64 && vq <= eVectorQuadwordAArch64SVEMax)
90       return true;
91     return false;
92   }
93 
94   bool IsSVEEnabled() const { return m_vector_reg_vq > eVectorQuadwordAArch64; }
95 
96   bool IsSVEZReg(unsigned reg) const;
97   bool IsSVEPReg(unsigned reg) const;
98   bool IsSVERegVG(unsigned reg) const;
99 
100   uint32_t GetRegNumSVEZ0() const;
101   uint32_t GetRegNumSVEFFR() const;
102   uint32_t GetRegNumFPCR() const;
103   uint32_t GetRegNumFPSR() const;
104 
105 private:
106   typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>>
107       per_vq_register_infos;
108 
109   per_vq_register_infos m_per_vq_reg_infos;
110 
111   uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;
112 
113   const lldb_private::RegisterInfo *m_register_info_p;
114   uint32_t m_register_info_count;
115 };
116 
117 #endif
118