1 //===-- RegisterContext_x86.h -----------------------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef liblldb_RegisterContext_x86_H_
11 #define liblldb_RegisterContext_x86_H_
12 
13 #include <cstddef>
14 #include <cstdint>
15 
16 #include "llvm/ADT/BitmaskEnum.h"
17 #include "llvm/Support/Compiler.h"
18 
19 namespace lldb_private {
20 //---------------------------------------------------------------------------
21 // i386 ehframe, dwarf regnums
22 //---------------------------------------------------------------------------
23 
24 // Register numbers seen in eh_frame (eRegisterKindEHFrame) on i386 systems
25 // (non-Darwin)
26 //
27 enum {
28   ehframe_eax_i386 = 0,
29   ehframe_ecx_i386,
30   ehframe_edx_i386,
31   ehframe_ebx_i386,
32 
33   // on Darwin esp & ebp are reversed in the eh_frame section for i386 (versus
34   // dwarf's reg numbering).
35   // To be specific:
36   //    i386+darwin eh_frame:        4 is ebp, 5 is esp
37   //    i386+everyone else eh_frame: 4 is esp, 5 is ebp
38   //    i386 dwarf:                  4 is esp, 5 is ebp
39   // lldb will get the darwin-specific eh_frame reg numberings from debugserver,
40   // or the ABI, so we
41   // only encode the generally correct 4 == esp, 5 == ebp numbers in this
42   // generic header.
43 
44   ehframe_esp_i386,
45   ehframe_ebp_i386,
46   ehframe_esi_i386,
47   ehframe_edi_i386,
48   ehframe_eip_i386,
49   ehframe_eflags_i386,
50   ehframe_st0_i386 = 12,
51   ehframe_st1_i386,
52   ehframe_st2_i386,
53   ehframe_st3_i386,
54   ehframe_st4_i386,
55   ehframe_st5_i386,
56   ehframe_st6_i386,
57   ehframe_st7_i386,
58   ehframe_xmm0_i386 = 21,
59   ehframe_xmm1_i386,
60   ehframe_xmm2_i386,
61   ehframe_xmm3_i386,
62   ehframe_xmm4_i386,
63   ehframe_xmm5_i386,
64   ehframe_xmm6_i386,
65   ehframe_xmm7_i386,
66   ehframe_mm0_i386 = 29,
67   ehframe_mm1_i386,
68   ehframe_mm2_i386,
69   ehframe_mm3_i386,
70   ehframe_mm4_i386,
71   ehframe_mm5_i386,
72   ehframe_mm6_i386,
73   ehframe_mm7_i386,
74 };
75 
76 // DWARF register numbers (eRegisterKindDWARF)
77 // Intel's x86 or IA-32
78 enum {
79   // General Purpose Registers.
80   dwarf_eax_i386 = 0,
81   dwarf_ecx_i386,
82   dwarf_edx_i386,
83   dwarf_ebx_i386,
84   dwarf_esp_i386,
85   dwarf_ebp_i386,
86   dwarf_esi_i386,
87   dwarf_edi_i386,
88   dwarf_eip_i386,
89   dwarf_eflags_i386,
90   // Floating Point Registers
91   dwarf_st0_i386 = 11,
92   dwarf_st1_i386,
93   dwarf_st2_i386,
94   dwarf_st3_i386,
95   dwarf_st4_i386,
96   dwarf_st5_i386,
97   dwarf_st6_i386,
98   dwarf_st7_i386,
99   // SSE Registers
100   dwarf_xmm0_i386 = 21,
101   dwarf_xmm1_i386,
102   dwarf_xmm2_i386,
103   dwarf_xmm3_i386,
104   dwarf_xmm4_i386,
105   dwarf_xmm5_i386,
106   dwarf_xmm6_i386,
107   dwarf_xmm7_i386,
108   // MMX Registers
109   dwarf_mm0_i386 = 29,
110   dwarf_mm1_i386,
111   dwarf_mm2_i386,
112   dwarf_mm3_i386,
113   dwarf_mm4_i386,
114   dwarf_mm5_i386,
115   dwarf_mm6_i386,
116   dwarf_mm7_i386,
117   dwarf_fctrl_i386 = 37, // x87 control word
118   dwarf_fstat_i386 = 38, // x87 status word
119   dwarf_mxcsr_i386 = 39,
120   dwarf_es_i386 = 40,
121   dwarf_cs_i386 = 41,
122   dwarf_ss_i386 = 42,
123   dwarf_ds_i386 = 43,
124   dwarf_fs_i386 = 44,
125   dwarf_gs_i386 = 45,
126 
127   // I believe the ymm registers use the dwarf_xmm%_i386 register numbers and
128   //  then differentiate based on size of the register.
129   dwarf_bnd0_i386 = 101,
130   dwarf_bnd1_i386,
131   dwarf_bnd2_i386,
132   dwarf_bnd3_i386,
133 };
134 
135 //---------------------------------------------------------------------------
136 // AMD x86_64, AMD64, Intel EM64T, or Intel 64 ehframe, dwarf regnums
137 //---------------------------------------------------------------------------
138 
139 // EHFrame and DWARF Register numbers (eRegisterKindEHFrame &
140 // eRegisterKindDWARF)
141 //  This is the spec I used (as opposed to x86-64-abi-0.99.pdf):
142 //  http://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf
143 enum {
144   // GP Registers
145   dwarf_rax_x86_64 = 0,
146   dwarf_rdx_x86_64,
147   dwarf_rcx_x86_64,
148   dwarf_rbx_x86_64,
149   dwarf_rsi_x86_64,
150   dwarf_rdi_x86_64,
151   dwarf_rbp_x86_64,
152   dwarf_rsp_x86_64,
153   // Extended GP Registers
154   dwarf_r8_x86_64 = 8,
155   dwarf_r9_x86_64,
156   dwarf_r10_x86_64,
157   dwarf_r11_x86_64,
158   dwarf_r12_x86_64,
159   dwarf_r13_x86_64,
160   dwarf_r14_x86_64,
161   dwarf_r15_x86_64,
162   // Return Address (RA) mapped to RIP
163   dwarf_rip_x86_64 = 16,
164   // SSE Vector Registers
165   dwarf_xmm0_x86_64 = 17,
166   dwarf_xmm1_x86_64,
167   dwarf_xmm2_x86_64,
168   dwarf_xmm3_x86_64,
169   dwarf_xmm4_x86_64,
170   dwarf_xmm5_x86_64,
171   dwarf_xmm6_x86_64,
172   dwarf_xmm7_x86_64,
173   dwarf_xmm8_x86_64,
174   dwarf_xmm9_x86_64,
175   dwarf_xmm10_x86_64,
176   dwarf_xmm11_x86_64,
177   dwarf_xmm12_x86_64,
178   dwarf_xmm13_x86_64,
179   dwarf_xmm14_x86_64,
180   dwarf_xmm15_x86_64,
181   // Floating Point Registers
182   dwarf_st0_x86_64 = 33,
183   dwarf_st1_x86_64,
184   dwarf_st2_x86_64,
185   dwarf_st3_x86_64,
186   dwarf_st4_x86_64,
187   dwarf_st5_x86_64,
188   dwarf_st6_x86_64,
189   dwarf_st7_x86_64,
190   // MMX Registers
191   dwarf_mm0_x86_64 = 41,
192   dwarf_mm1_x86_64,
193   dwarf_mm2_x86_64,
194   dwarf_mm3_x86_64,
195   dwarf_mm4_x86_64,
196   dwarf_mm5_x86_64,
197   dwarf_mm6_x86_64,
198   dwarf_mm7_x86_64,
199   // Control and Status Flags Register
200   dwarf_rflags_x86_64 = 49,
201   //  selector registers
202   dwarf_es_x86_64 = 50,
203   dwarf_cs_x86_64,
204   dwarf_ss_x86_64,
205   dwarf_ds_x86_64,
206   dwarf_fs_x86_64,
207   dwarf_gs_x86_64,
208   // Floating point control registers
209   dwarf_mxcsr_x86_64 = 64, // Media Control and Status
210   dwarf_fctrl_x86_64,      // x87 control word
211   dwarf_fstat_x86_64,      // x87 status word
212   // Upper Vector Registers
213   dwarf_ymm0h_x86_64 = 67,
214   dwarf_ymm1h_x86_64,
215   dwarf_ymm2h_x86_64,
216   dwarf_ymm3h_x86_64,
217   dwarf_ymm4h_x86_64,
218   dwarf_ymm5h_x86_64,
219   dwarf_ymm6h_x86_64,
220   dwarf_ymm7h_x86_64,
221   dwarf_ymm8h_x86_64,
222   dwarf_ymm9h_x86_64,
223   dwarf_ymm10h_x86_64,
224   dwarf_ymm11h_x86_64,
225   dwarf_ymm12h_x86_64,
226   dwarf_ymm13h_x86_64,
227   dwarf_ymm14h_x86_64,
228   dwarf_ymm15h_x86_64,
229   // MPX registers
230   dwarf_bnd0_x86_64 = 126,
231   dwarf_bnd1_x86_64,
232   dwarf_bnd2_x86_64,
233   dwarf_bnd3_x86_64,
234   // AVX2 Vector Mask Registers
235   // dwarf_k0_x86_64 = 118,
236   // dwarf_k1_x86_64,
237   // dwarf_k2_x86_64,
238   // dwarf_k3_x86_64,
239   // dwarf_k4_x86_64,
240   // dwarf_k5_x86_64,
241   // dwarf_k6_x86_64,
242   // dwarf_k7_x86_64,
243 };
244 
245 //---------------------------------------------------------------------------
246 // Generic floating-point registers
247 //---------------------------------------------------------------------------
248 
249 struct MMSReg {
250   uint8_t bytes[10];
251   uint8_t pad[6];
252 };
253 
254 struct XMMReg {
255   uint8_t bytes[16]; // 128-bits for each XMM register
256 };
257 
258 // i387_fxsave_struct
259 struct FXSAVE {
260   uint16_t fctrl;     // FPU Control Word (fcw)
261   uint16_t fstat;     // FPU Status Word (fsw)
262   uint16_t ftag;      // FPU Tag Word (ftw)
263   uint16_t fop;       // Last Instruction Opcode (fop)
264   union {
265     struct {
266       uint64_t fip; // Instruction Pointer
267       uint64_t fdp; // Data Pointer
268     } x86_64;
269     struct {
270       uint32_t fioff; // FPU IP Offset (fip)
271       uint32_t fiseg; // FPU IP Selector (fcs)
272       uint32_t fooff; // FPU Operand Pointer Offset (foo)
273       uint32_t foseg; // FPU Operand Pointer Selector (fos)
274     } i386_; // Added _ in the end to avoid error with gcc defining i386 in some
275              // cases
276   } ptr;
277   uint32_t mxcsr;     // MXCSR Register State
278   uint32_t mxcsrmask; // MXCSR Mask
279   MMSReg stmm[8];     // 8*16 bytes for each FP-reg = 128 bytes
280   XMMReg xmm[16];     // 16*16 bytes for each XMM-reg = 256 bytes
281   uint8_t padding1[48];
282   uint64_t xcr0;
283   uint8_t padding2[40];
284 };
285 
286 //---------------------------------------------------------------------------
287 // Extended floating-point registers
288 //---------------------------------------------------------------------------
289 
290 struct YMMHReg {
291   uint8_t bytes[16]; // 16 * 8 bits for the high bytes of each YMM register
292 };
293 
294 struct YMMReg {
295   uint8_t bytes[32]; // 16 * 16 bits for each YMM register
296 };
297 
298 struct YMM {
299   YMMReg ymm[16]; // assembled from ymmh and xmm registers
300 };
301 
302 struct MPXReg {
303   uint8_t bytes[16]; // MPX 128 bit bound registers
304 };
305 
306 struct MPXCsr {
307   uint8_t bytes[8]; // MPX 64 bit bndcfgu and bndstatus registers (collectively
308                     // BNDCSR state)
309 };
310 
311 struct MPX {
312   MPXReg mpxr[4];
313   MPXCsr mpxc[2];
314 };
315 
316 LLVM_PACKED_START
317 struct XSAVE_HDR {
318   enum class XFeature : uint64_t {
319     FP = 1,
320     SSE = FP << 1,
321     YMM = SSE << 1,
322     BNDREGS = YMM << 1,
323     BNDCSR = BNDREGS << 1,
324     OPMASK = BNDCSR << 1,
325     ZMM_Hi256 = OPMASK << 1,
326     Hi16_ZMM = ZMM_Hi256 << 1,
327     PT = Hi16_ZMM << 1,
328     PKRU = PT << 1,
329     LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue*/ PKRU)
330   };
331 
332   XFeature xstate_bv; // OS enabled xstate mask to determine the extended states
333                       // supported by the processor
334   XFeature xcomp_bv;  // Mask to indicate the format of the XSAVE area and of
335                       // the XRSTOR instruction
336   uint64_t reserved1[1];
337   uint64_t reserved2[5];
338 };
339 static_assert(sizeof(XSAVE_HDR) == 64, "XSAVE_HDR layout incorrect");
340 LLVM_PACKED_END
341 
342 // x86 extensions to FXSAVE (i.e. for AVX and MPX processors)
343 LLVM_PACKED_START
344 struct LLVM_ALIGNAS(16) XSAVE {
345   FXSAVE i387;      // floating point registers typical in i387_fxsave_struct
346   XSAVE_HDR header; // The xsave_hdr_struct can be used to determine if the
347                     // following extensions are usable
348   YMMHReg ymmh[16]; // High 16 bytes of each of 16 YMM registers (the low bytes
349                     // are in FXSAVE.xmm for compatibility with SSE)
350   uint64_t reserved3[16];
351   MPXReg mpxr[4];   // MPX BNDREG state, containing 128-bit bound registers
352   MPXCsr mpxc[2];   // MPX BNDCSR state, containing 64-bit BNDCFGU and
353                     // BNDSTATUS registers
354 };
355 LLVM_PACKED_END
356 
357 // Floating-point registers
358 union FPR {
359   FXSAVE fxsave; // Generic floating-point registers.
360   XSAVE xsave;   // x86 extended processor state.
361 };
362 
363 LLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE();
364 
365 } // namespace lldb_private
366 
367 #endif
368