1 //===-- RegisterContext_x86.h -----------------------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef liblldb_RegisterContext_x86_H_
11 #define liblldb_RegisterContext_x86_H_
12 
13 #include <cstddef>
14 #include <cstdint>
15 
16 #include "llvm/Support/Compiler.h"
17 
18 //---------------------------------------------------------------------------
19 // i386 ehframe, dwarf regnums
20 //---------------------------------------------------------------------------
21 
22 // Register numbers seen in eh_frame (eRegisterKindEHFrame) on i386 systems
23 // (non-Darwin)
24 //
25 enum {
26   ehframe_eax_i386 = 0,
27   ehframe_ecx_i386,
28   ehframe_edx_i386,
29   ehframe_ebx_i386,
30 
31   // on Darwin esp & ebp are reversed in the eh_frame section for i386 (versus
32   // dwarf's reg numbering).
33   // To be specific:
34   //    i386+darwin eh_frame:        4 is ebp, 5 is esp
35   //    i386+everyone else eh_frame: 4 is esp, 5 is ebp
36   //    i386 dwarf:                  4 is esp, 5 is ebp
37   // lldb will get the darwin-specific eh_frame reg numberings from debugserver,
38   // or the ABI, so we
39   // only encode the generally correct 4 == esp, 5 == ebp numbers in this
40   // generic header.
41 
42   ehframe_esp_i386,
43   ehframe_ebp_i386,
44   ehframe_esi_i386,
45   ehframe_edi_i386,
46   ehframe_eip_i386,
47   ehframe_eflags_i386,
48   ehframe_st0_i386 = 12,
49   ehframe_st1_i386,
50   ehframe_st2_i386,
51   ehframe_st3_i386,
52   ehframe_st4_i386,
53   ehframe_st5_i386,
54   ehframe_st6_i386,
55   ehframe_st7_i386,
56   ehframe_xmm0_i386 = 21,
57   ehframe_xmm1_i386,
58   ehframe_xmm2_i386,
59   ehframe_xmm3_i386,
60   ehframe_xmm4_i386,
61   ehframe_xmm5_i386,
62   ehframe_xmm6_i386,
63   ehframe_xmm7_i386,
64   ehframe_mm0_i386 = 29,
65   ehframe_mm1_i386,
66   ehframe_mm2_i386,
67   ehframe_mm3_i386,
68   ehframe_mm4_i386,
69   ehframe_mm5_i386,
70   ehframe_mm6_i386,
71   ehframe_mm7_i386,
72 };
73 
74 // DWARF register numbers (eRegisterKindDWARF)
75 // Intel's x86 or IA-32
76 enum {
77   // General Purpose Registers.
78   dwarf_eax_i386 = 0,
79   dwarf_ecx_i386,
80   dwarf_edx_i386,
81   dwarf_ebx_i386,
82   dwarf_esp_i386,
83   dwarf_ebp_i386,
84   dwarf_esi_i386,
85   dwarf_edi_i386,
86   dwarf_eip_i386,
87   dwarf_eflags_i386,
88   // Floating Point Registers
89   dwarf_st0_i386 = 11,
90   dwarf_st1_i386,
91   dwarf_st2_i386,
92   dwarf_st3_i386,
93   dwarf_st4_i386,
94   dwarf_st5_i386,
95   dwarf_st6_i386,
96   dwarf_st7_i386,
97   // SSE Registers
98   dwarf_xmm0_i386 = 21,
99   dwarf_xmm1_i386,
100   dwarf_xmm2_i386,
101   dwarf_xmm3_i386,
102   dwarf_xmm4_i386,
103   dwarf_xmm5_i386,
104   dwarf_xmm6_i386,
105   dwarf_xmm7_i386,
106   // MMX Registers
107   dwarf_mm0_i386 = 29,
108   dwarf_mm1_i386,
109   dwarf_mm2_i386,
110   dwarf_mm3_i386,
111   dwarf_mm4_i386,
112   dwarf_mm5_i386,
113   dwarf_mm6_i386,
114   dwarf_mm7_i386,
115   dwarf_fctrl_i386 = 37, // x87 control word
116   dwarf_fstat_i386 = 38, // x87 status word
117   dwarf_mxcsr_i386 = 39,
118   dwarf_es_i386 = 40,
119   dwarf_cs_i386 = 41,
120   dwarf_ss_i386 = 42,
121   dwarf_ds_i386 = 43,
122   dwarf_fs_i386 = 44,
123   dwarf_gs_i386 = 45,
124 
125   // I believe the ymm registers use the dwarf_xmm%_i386 register numbers and
126   //  then differentiate based on size of the register.
127   dwarf_bnd0_i386 = 101,
128   dwarf_bnd1_i386,
129   dwarf_bnd2_i386,
130   dwarf_bnd3_i386,
131 };
132 
133 //---------------------------------------------------------------------------
134 // AMD x86_64, AMD64, Intel EM64T, or Intel 64 ehframe, dwarf regnums
135 //---------------------------------------------------------------------------
136 
137 // EHFrame and DWARF Register numbers (eRegisterKindEHFrame &
138 // eRegisterKindDWARF)
139 //  This is the spec I used (as opposed to x86-64-abi-0.99.pdf):
140 //  http://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf
141 enum {
142   // GP Registers
143   dwarf_rax_x86_64 = 0,
144   dwarf_rdx_x86_64,
145   dwarf_rcx_x86_64,
146   dwarf_rbx_x86_64,
147   dwarf_rsi_x86_64,
148   dwarf_rdi_x86_64,
149   dwarf_rbp_x86_64,
150   dwarf_rsp_x86_64,
151   // Extended GP Registers
152   dwarf_r8_x86_64 = 8,
153   dwarf_r9_x86_64,
154   dwarf_r10_x86_64,
155   dwarf_r11_x86_64,
156   dwarf_r12_x86_64,
157   dwarf_r13_x86_64,
158   dwarf_r14_x86_64,
159   dwarf_r15_x86_64,
160   // Return Address (RA) mapped to RIP
161   dwarf_rip_x86_64 = 16,
162   // SSE Vector Registers
163   dwarf_xmm0_x86_64 = 17,
164   dwarf_xmm1_x86_64,
165   dwarf_xmm2_x86_64,
166   dwarf_xmm3_x86_64,
167   dwarf_xmm4_x86_64,
168   dwarf_xmm5_x86_64,
169   dwarf_xmm6_x86_64,
170   dwarf_xmm7_x86_64,
171   dwarf_xmm8_x86_64,
172   dwarf_xmm9_x86_64,
173   dwarf_xmm10_x86_64,
174   dwarf_xmm11_x86_64,
175   dwarf_xmm12_x86_64,
176   dwarf_xmm13_x86_64,
177   dwarf_xmm14_x86_64,
178   dwarf_xmm15_x86_64,
179   // Floating Point Registers
180   dwarf_st0_x86_64 = 33,
181   dwarf_st1_x86_64,
182   dwarf_st2_x86_64,
183   dwarf_st3_x86_64,
184   dwarf_st4_x86_64,
185   dwarf_st5_x86_64,
186   dwarf_st6_x86_64,
187   dwarf_st7_x86_64,
188   // MMX Registers
189   dwarf_mm0_x86_64 = 41,
190   dwarf_mm1_x86_64,
191   dwarf_mm2_x86_64,
192   dwarf_mm3_x86_64,
193   dwarf_mm4_x86_64,
194   dwarf_mm5_x86_64,
195   dwarf_mm6_x86_64,
196   dwarf_mm7_x86_64,
197   // Control and Status Flags Register
198   dwarf_rflags_x86_64 = 49,
199   //  selector registers
200   dwarf_es_x86_64 = 50,
201   dwarf_cs_x86_64,
202   dwarf_ss_x86_64,
203   dwarf_ds_x86_64,
204   dwarf_fs_x86_64,
205   dwarf_gs_x86_64,
206   // Floating point control registers
207   dwarf_mxcsr_x86_64 = 64, // Media Control and Status
208   dwarf_fctrl_x86_64,      // x87 control word
209   dwarf_fstat_x86_64,      // x87 status word
210   // Upper Vector Registers
211   dwarf_ymm0h_x86_64 = 67,
212   dwarf_ymm1h_x86_64,
213   dwarf_ymm2h_x86_64,
214   dwarf_ymm3h_x86_64,
215   dwarf_ymm4h_x86_64,
216   dwarf_ymm5h_x86_64,
217   dwarf_ymm6h_x86_64,
218   dwarf_ymm7h_x86_64,
219   dwarf_ymm8h_x86_64,
220   dwarf_ymm9h_x86_64,
221   dwarf_ymm10h_x86_64,
222   dwarf_ymm11h_x86_64,
223   dwarf_ymm12h_x86_64,
224   dwarf_ymm13h_x86_64,
225   dwarf_ymm14h_x86_64,
226   dwarf_ymm15h_x86_64,
227   // MPX registers
228   dwarf_bnd0_x86_64 = 126,
229   dwarf_bnd1_x86_64,
230   dwarf_bnd2_x86_64,
231   dwarf_bnd3_x86_64,
232   // AVX2 Vector Mask Registers
233   // dwarf_k0_x86_64 = 118,
234   // dwarf_k1_x86_64,
235   // dwarf_k2_x86_64,
236   // dwarf_k3_x86_64,
237   // dwarf_k4_x86_64,
238   // dwarf_k5_x86_64,
239   // dwarf_k6_x86_64,
240   // dwarf_k7_x86_64,
241 };
242 
243 //---------------------------------------------------------------------------
244 // Generic floating-point registers
245 //---------------------------------------------------------------------------
246 
247 struct MMSReg {
248   uint8_t bytes[10];
249   uint8_t pad[6];
250 };
251 
252 struct XMMReg {
253   uint8_t bytes[16]; // 128-bits for each XMM register
254 };
255 
256 // i387_fxsave_struct
257 struct FXSAVE {
258   uint16_t fctrl;     // FPU Control Word (fcw)
259   uint16_t fstat;     // FPU Status Word (fsw)
260   uint8_t ftag;       // FPU Tag Word (ftw)
261   uint8_t reserved_1; // Reserved
262   uint16_t fop;       // Last Instruction Opcode (fop)
263   union {
264     struct {
265       uint64_t fip; // Instruction Pointer
266       uint64_t fdp; // Data Pointer
267     } x86_64;
268     struct {
269       uint32_t fioff; // FPU IP Offset (fip)
270       uint32_t fiseg; // FPU IP Selector (fcs)
271       uint32_t fooff; // FPU Operand Pointer Offset (foo)
272       uint32_t foseg; // FPU Operand Pointer Selector (fos)
273     } i386_; // Added _ in the end to avoid error with gcc defining i386 in some
274              // cases
275   } ptr;
276   uint32_t mxcsr;     // MXCSR Register State
277   uint32_t mxcsrmask; // MXCSR Mask
278   MMSReg stmm[8];     // 8*16 bytes for each FP-reg = 128 bytes
279   XMMReg xmm[16];     // 16*16 bytes for each XMM-reg = 256 bytes
280   uint8_t padding1[48];
281   uint64_t xcr0;
282   uint8_t padding2[40];
283 };
284 
285 //---------------------------------------------------------------------------
286 // Extended floating-point registers
287 //---------------------------------------------------------------------------
288 
289 struct YMMHReg {
290   uint8_t bytes[16]; // 16 * 8 bits for the high bytes of each YMM register
291 };
292 
293 struct YMMReg {
294   uint8_t bytes[32]; // 16 * 16 bits for each YMM register
295 };
296 
297 struct YMM {
298   YMMReg ymm[16]; // assembled from ymmh and xmm registers
299 };
300 
301 struct MPXReg {
302   uint8_t bytes[16]; // MPX 128 bit bound registers
303 };
304 
305 struct MPXCsr {
306   uint8_t bytes[8]; // MPX 64 bit bndcfgu and bndstatus registers (collectively
307                     // BNDCSR state)
308 };
309 
310 struct MPX {
311   MPXReg mpxr[4];
312   MPXCsr mpxc[2];
313 };
314 
315 LLVM_PACKED_START
316 struct XSAVE_HDR {
317   uint64_t xstate_bv; // OS enabled xstate mask to determine the extended states
318                       // supported by the processor
319   uint64_t xcomp_bv;  // Mask to indicate the format of the XSAVE area and of
320                       // the XRSTOR instruction
321   uint64_t reserved1[1];
322   uint64_t reserved2[5];
323 };
324 LLVM_PACKED_END
325 
326 // x86 extensions to FXSAVE (i.e. for AVX and MPX processors)
327 LLVM_PACKED_START
328 struct LLVM_ALIGNAS(64) XSAVE {
329   FXSAVE i387;      // floating point registers typical in i387_fxsave_struct
330   XSAVE_HDR header; // The xsave_hdr_struct can be used to determine if the
331                     // following extensions are usable
332   YMMHReg ymmh[16]; // High 16 bytes of each of 16 YMM registers (the low bytes
333                     // are in FXSAVE.xmm for compatibility with SSE)
334   uint64_t reserved3[16];
335   MPXReg mpxr[4];   // MPX BNDREG state, containing 128-bit bound registers
336   MPXCsr mpxc[2];   // MPX BNDCSR state, containing 64-bit BNDCFGU and
337                     // BNDSTATUS registers
338 };
339 LLVM_PACKED_END
340 
341 // Floating-point registers
342 struct FPR {
343   // Thread state for the floating-point unit of the processor read by ptrace.
344   union XSTATE {
345     FXSAVE fxsave; // Generic floating-point registers.
346     XSAVE xsave;   // x86 extended processor state.
347   } xstate;
348 };
349 
350 //---------------------------------------------------------------------------
351 // ptrace PTRACE_GETREGSET, PTRACE_SETREGSET structure
352 //---------------------------------------------------------------------------
353 
354 struct IOVEC {
355   void *iov_base; // pointer to XSAVE
356   size_t iov_len; // sizeof(XSAVE)
357 };
358 
359 #endif
360