1 //===-- RegisterContext_mips.h --------------------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef liblldb_RegisterContext_mips64_H_
11 #define liblldb_RegisterContext_mips64_H_
12 
13 #include <cstddef>
14 #include <cstdint>
15 
16 // eh_frame and DWARF Register numbers (eRegisterKindEHFrame &
17 // eRegisterKindDWARF)
18 
19 enum {
20   // GP Registers
21   dwarf_zero_mips = 0,
22   dwarf_r1_mips,
23   dwarf_r2_mips,
24   dwarf_r3_mips,
25   dwarf_r4_mips,
26   dwarf_r5_mips,
27   dwarf_r6_mips,
28   dwarf_r7_mips,
29   dwarf_r8_mips,
30   dwarf_r9_mips,
31   dwarf_r10_mips,
32   dwarf_r11_mips,
33   dwarf_r12_mips,
34   dwarf_r13_mips,
35   dwarf_r14_mips,
36   dwarf_r15_mips,
37   dwarf_r16_mips,
38   dwarf_r17_mips,
39   dwarf_r18_mips,
40   dwarf_r19_mips,
41   dwarf_r20_mips,
42   dwarf_r21_mips,
43   dwarf_r22_mips,
44   dwarf_r23_mips,
45   dwarf_r24_mips,
46   dwarf_r25_mips,
47   dwarf_r26_mips,
48   dwarf_r27_mips,
49   dwarf_gp_mips,
50   dwarf_sp_mips,
51   dwarf_r30_mips,
52   dwarf_ra_mips,
53   dwarf_sr_mips,
54   dwarf_lo_mips,
55   dwarf_hi_mips,
56   dwarf_bad_mips,
57   dwarf_cause_mips,
58   dwarf_pc_mips,
59   dwarf_f0_mips,
60   dwarf_f1_mips,
61   dwarf_f2_mips,
62   dwarf_f3_mips,
63   dwarf_f4_mips,
64   dwarf_f5_mips,
65   dwarf_f6_mips,
66   dwarf_f7_mips,
67   dwarf_f8_mips,
68   dwarf_f9_mips,
69   dwarf_f10_mips,
70   dwarf_f11_mips,
71   dwarf_f12_mips,
72   dwarf_f13_mips,
73   dwarf_f14_mips,
74   dwarf_f15_mips,
75   dwarf_f16_mips,
76   dwarf_f17_mips,
77   dwarf_f18_mips,
78   dwarf_f19_mips,
79   dwarf_f20_mips,
80   dwarf_f21_mips,
81   dwarf_f22_mips,
82   dwarf_f23_mips,
83   dwarf_f24_mips,
84   dwarf_f25_mips,
85   dwarf_f26_mips,
86   dwarf_f27_mips,
87   dwarf_f28_mips,
88   dwarf_f29_mips,
89   dwarf_f30_mips,
90   dwarf_f31_mips,
91   dwarf_fcsr_mips,
92   dwarf_fir_mips,
93   dwarf_w0_mips,
94   dwarf_w1_mips,
95   dwarf_w2_mips,
96   dwarf_w3_mips,
97   dwarf_w4_mips,
98   dwarf_w5_mips,
99   dwarf_w6_mips,
100   dwarf_w7_mips,
101   dwarf_w8_mips,
102   dwarf_w9_mips,
103   dwarf_w10_mips,
104   dwarf_w11_mips,
105   dwarf_w12_mips,
106   dwarf_w13_mips,
107   dwarf_w14_mips,
108   dwarf_w15_mips,
109   dwarf_w16_mips,
110   dwarf_w17_mips,
111   dwarf_w18_mips,
112   dwarf_w19_mips,
113   dwarf_w20_mips,
114   dwarf_w21_mips,
115   dwarf_w22_mips,
116   dwarf_w23_mips,
117   dwarf_w24_mips,
118   dwarf_w25_mips,
119   dwarf_w26_mips,
120   dwarf_w27_mips,
121   dwarf_w28_mips,
122   dwarf_w29_mips,
123   dwarf_w30_mips,
124   dwarf_w31_mips,
125   dwarf_mcsr_mips,
126   dwarf_mir_mips,
127   dwarf_config5_mips,
128   dwarf_ic_mips,
129   dwarf_dummy_mips
130 };
131 
132 enum {
133   dwarf_zero_mips64 = 0,
134   dwarf_r1_mips64,
135   dwarf_r2_mips64,
136   dwarf_r3_mips64,
137   dwarf_r4_mips64,
138   dwarf_r5_mips64,
139   dwarf_r6_mips64,
140   dwarf_r7_mips64,
141   dwarf_r8_mips64,
142   dwarf_r9_mips64,
143   dwarf_r10_mips64,
144   dwarf_r11_mips64,
145   dwarf_r12_mips64,
146   dwarf_r13_mips64,
147   dwarf_r14_mips64,
148   dwarf_r15_mips64,
149   dwarf_r16_mips64,
150   dwarf_r17_mips64,
151   dwarf_r18_mips64,
152   dwarf_r19_mips64,
153   dwarf_r20_mips64,
154   dwarf_r21_mips64,
155   dwarf_r22_mips64,
156   dwarf_r23_mips64,
157   dwarf_r24_mips64,
158   dwarf_r25_mips64,
159   dwarf_r26_mips64,
160   dwarf_r27_mips64,
161   dwarf_gp_mips64,
162   dwarf_sp_mips64,
163   dwarf_r30_mips64,
164   dwarf_ra_mips64,
165   dwarf_sr_mips64,
166   dwarf_lo_mips64,
167   dwarf_hi_mips64,
168   dwarf_bad_mips64,
169   dwarf_cause_mips64,
170   dwarf_pc_mips64,
171   dwarf_f0_mips64,
172   dwarf_f1_mips64,
173   dwarf_f2_mips64,
174   dwarf_f3_mips64,
175   dwarf_f4_mips64,
176   dwarf_f5_mips64,
177   dwarf_f6_mips64,
178   dwarf_f7_mips64,
179   dwarf_f8_mips64,
180   dwarf_f9_mips64,
181   dwarf_f10_mips64,
182   dwarf_f11_mips64,
183   dwarf_f12_mips64,
184   dwarf_f13_mips64,
185   dwarf_f14_mips64,
186   dwarf_f15_mips64,
187   dwarf_f16_mips64,
188   dwarf_f17_mips64,
189   dwarf_f18_mips64,
190   dwarf_f19_mips64,
191   dwarf_f20_mips64,
192   dwarf_f21_mips64,
193   dwarf_f22_mips64,
194   dwarf_f23_mips64,
195   dwarf_f24_mips64,
196   dwarf_f25_mips64,
197   dwarf_f26_mips64,
198   dwarf_f27_mips64,
199   dwarf_f28_mips64,
200   dwarf_f29_mips64,
201   dwarf_f30_mips64,
202   dwarf_f31_mips64,
203   dwarf_fcsr_mips64,
204   dwarf_fir_mips64,
205   dwarf_ic_mips64,
206   dwarf_dummy_mips64,
207   dwarf_w0_mips64,
208   dwarf_w1_mips64,
209   dwarf_w2_mips64,
210   dwarf_w3_mips64,
211   dwarf_w4_mips64,
212   dwarf_w5_mips64,
213   dwarf_w6_mips64,
214   dwarf_w7_mips64,
215   dwarf_w8_mips64,
216   dwarf_w9_mips64,
217   dwarf_w10_mips64,
218   dwarf_w11_mips64,
219   dwarf_w12_mips64,
220   dwarf_w13_mips64,
221   dwarf_w14_mips64,
222   dwarf_w15_mips64,
223   dwarf_w16_mips64,
224   dwarf_w17_mips64,
225   dwarf_w18_mips64,
226   dwarf_w19_mips64,
227   dwarf_w20_mips64,
228   dwarf_w21_mips64,
229   dwarf_w22_mips64,
230   dwarf_w23_mips64,
231   dwarf_w24_mips64,
232   dwarf_w25_mips64,
233   dwarf_w26_mips64,
234   dwarf_w27_mips64,
235   dwarf_w28_mips64,
236   dwarf_w29_mips64,
237   dwarf_w30_mips64,
238   dwarf_w31_mips64,
239   dwarf_mcsr_mips64,
240   dwarf_mir_mips64,
241   dwarf_config5_mips64,
242 };
243 
244 struct IOVEC_mips {
245   void *iov_base;
246   size_t iov_len;
247 };
248 
249 // GP registers
250 struct GPR_linux_mips {
251   uint64_t zero;
252   uint64_t r1;
253   uint64_t r2;
254   uint64_t r3;
255   uint64_t r4;
256   uint64_t r5;
257   uint64_t r6;
258   uint64_t r7;
259   uint64_t r8;
260   uint64_t r9;
261   uint64_t r10;
262   uint64_t r11;
263   uint64_t r12;
264   uint64_t r13;
265   uint64_t r14;
266   uint64_t r15;
267   uint64_t r16;
268   uint64_t r17;
269   uint64_t r18;
270   uint64_t r19;
271   uint64_t r20;
272   uint64_t r21;
273   uint64_t r22;
274   uint64_t r23;
275   uint64_t r24;
276   uint64_t r25;
277   uint64_t r26;
278   uint64_t r27;
279   uint64_t gp;
280   uint64_t sp;
281   uint64_t r30;
282   uint64_t ra;
283   uint64_t mullo;
284   uint64_t mulhi;
285   uint64_t pc;
286   uint64_t badvaddr;
287   uint64_t sr;
288   uint64_t cause;
289   uint64_t config5;
290 };
291 
292 struct FPR_linux_mips {
293   uint64_t f0;
294   uint64_t f1;
295   uint64_t f2;
296   uint64_t f3;
297   uint64_t f4;
298   uint64_t f5;
299   uint64_t f6;
300   uint64_t f7;
301   uint64_t f8;
302   uint64_t f9;
303   uint64_t f10;
304   uint64_t f11;
305   uint64_t f12;
306   uint64_t f13;
307   uint64_t f14;
308   uint64_t f15;
309   uint64_t f16;
310   uint64_t f17;
311   uint64_t f18;
312   uint64_t f19;
313   uint64_t f20;
314   uint64_t f21;
315   uint64_t f22;
316   uint64_t f23;
317   uint64_t f24;
318   uint64_t f25;
319   uint64_t f26;
320   uint64_t f27;
321   uint64_t f28;
322   uint64_t f29;
323   uint64_t f30;
324   uint64_t f31;
325   uint32_t fcsr;
326   uint32_t fir;
327   uint32_t config5;
328 };
329 
330 struct MSAReg {
331   uint8_t byte[16];
332 };
333 
334 struct MSA_linux_mips {
335   MSAReg w0;
336   MSAReg w1;
337   MSAReg w2;
338   MSAReg w3;
339   MSAReg w4;
340   MSAReg w5;
341   MSAReg w6;
342   MSAReg w7;
343   MSAReg w8;
344   MSAReg w9;
345   MSAReg w10;
346   MSAReg w11;
347   MSAReg w12;
348   MSAReg w13;
349   MSAReg w14;
350   MSAReg w15;
351   MSAReg w16;
352   MSAReg w17;
353   MSAReg w18;
354   MSAReg w19;
355   MSAReg w20;
356   MSAReg w21;
357   MSAReg w22;
358   MSAReg w23;
359   MSAReg w24;
360   MSAReg w25;
361   MSAReg w26;
362   MSAReg w27;
363   MSAReg w28;
364   MSAReg w29;
365   MSAReg w30;
366   MSAReg w31;
367   uint32_t fcsr;    /* FPU control status register */
368   uint32_t fir;     /* FPU implementaion revision */
369   uint32_t mcsr;    /* MSA control status register */
370   uint32_t mir;     /* MSA implementation revision */
371   uint32_t config5; /* Config5 register */
372 };
373 
374 struct UserArea {
375   GPR_linux_mips gpr; // General purpose registers.
376   FPR_linux_mips fpr; // Floating point registers.
377   MSA_linux_mips msa; // MSA registers.
378 };
379 
380 #endif // liblldb_RegisterContext_mips64_H_
381