1 //===-- RegisterContextNetBSD_x86_64.cpp ----------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===---------------------------------------------------------------------===// 9 10 #include <cstddef> 11 #include <vector> 12 13 #include "llvm/Support/Compiler.h" 14 15 #include "RegisterContextPOSIX_x86.h" 16 #include "RegisterContextNetBSD_x86_64.h" 17 18 using namespace lldb_private; 19 using namespace lldb; 20 21 // src/sys/arch/amd64/include/frame_regs.h 22 typedef struct _GPR 23 { 24 uint64_t rdi; /* 0 */ 25 uint64_t rsi; /* 1 */ 26 uint64_t rdx; /* 2 */ 27 uint64_t rcx; /* 3 */ 28 uint64_t r8; /* 4 */ 29 uint64_t r9; /* 5 */ 30 uint64_t r10; /* 6 */ 31 uint64_t r11; /* 7 */ 32 uint64_t r12; /* 8 */ 33 uint64_t r13; /* 9 */ 34 uint64_t r14; /* 10 */ 35 uint64_t r15; /* 11 */ 36 uint64_t rbp; /* 12 */ 37 uint64_t rbx; /* 13 */ 38 uint64_t rax; /* 14 */ 39 uint64_t gs; /* 15 */ 40 uint64_t fs; /* 16 */ 41 uint64_t es; /* 17 */ 42 uint64_t ds; /* 18 */ 43 uint64_t trapno; /* 19 */ 44 uint64_t err; /* 20 */ 45 uint64_t rip; /* 21 */ 46 uint64_t cs; /* 22 */ 47 uint64_t rflags; /* 23 */ 48 uint64_t rsp; /* 24 */ 49 uint64_t ss; /* 25 */ 50 } GPR; 51 52 /* 53 * As of NetBSD-7.99.25 there is no support for debug registers 54 * https://en.wikipedia.org/wiki/X86_debug_register 55 */ 56 57 /* 58 * src/sys/arch/amd64/include/mcontext.h 59 * 60 * typedef struct { 61 * __gregset_t __gregs; 62 * __greg_t _mc_tlsbase; 63 * __fpregset_t __fpregs; 64 * } mcontext_t; 65 */ 66 67 struct UserArea { 68 GPR gpr; 69 uint64_t mc_tlsbase; 70 FPR fpr; 71 }; 72 73 74 //--------------------------------------------------------------------------- 75 // Cherry-pick parts of RegisterInfos_x86_64.h, without debug registers 76 //--------------------------------------------------------------------------- 77 // Computes the offset of the given GPR in the user data area. 78 #define GPR_OFFSET(regname) \ 79 (LLVM_EXTENSION offsetof(GPR, regname)) 80 81 // Computes the offset of the given FPR in the extended data area. 82 #define FPR_OFFSET(regname) \ 83 (LLVM_EXTENSION offsetof(UserArea, fpr) + \ 84 LLVM_EXTENSION offsetof(FPR, xstate) + \ 85 LLVM_EXTENSION offsetof(FXSAVE, regname)) 86 87 // Computes the offset of the YMM register assembled from register halves. 88 // Based on DNBArchImplX86_64.cpp from debugserver 89 #define YMM_OFFSET(reg_index) \ 90 (LLVM_EXTENSION offsetof(UserArea, fpr) + \ 91 LLVM_EXTENSION offsetof(FPR, xstate) + \ 92 LLVM_EXTENSION offsetof(XSAVE, ymmh[0]) + \ 93 (32 * reg_index)) 94 95 // Number of bytes needed to represent a FPR. 96 #define FPR_SIZE(reg) sizeof(((FXSAVE*)NULL)->reg) 97 98 // Number of bytes needed to represent the i'th FP register. 99 #define FP_SIZE sizeof(((MMSReg*)NULL)->bytes) 100 101 // Number of bytes needed to represent an XMM register. 102 #define XMM_SIZE sizeof(XMMReg) 103 104 // Number of bytes needed to represent a YMM register. 105 #define YMM_SIZE sizeof(YMMReg) 106 107 // RegisterKind: EHFrame, DWARF, Generic, Process Plugin, LLDB 108 109 // Note that the size and offset will be updated by platform-specific classes. 110 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \ 111 { #reg, alt, sizeof(((GPR*)NULL)->reg), GPR_OFFSET(reg), eEncodingUint, \ 112 eFormatHex, { kind1, kind2, kind3, kind4, lldb_##reg##_x86_64 }, NULL, NULL } 113 114 #define DEFINE_FPR(name, reg, kind1, kind2, kind3, kind4) \ 115 { #name, NULL, FPR_SIZE(reg), FPR_OFFSET(reg), eEncodingUint, \ 116 eFormatHex, { kind1, kind2, kind3, kind4, lldb_##name##_x86_64 }, NULL, NULL } 117 118 #define DEFINE_FP_ST(reg, i) \ 119 { #reg#i, NULL, FP_SIZE, LLVM_EXTENSION FPR_OFFSET(stmm[i]), \ 120 eEncodingVector, eFormatVectorOfUInt8, \ 121 { dwarf_st##i##_x86_64, dwarf_st##i##_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_st##i##_x86_64 }, \ 122 NULL, NULL } 123 124 #define DEFINE_FP_MM(reg, i) \ 125 { #reg#i, NULL, sizeof(uint64_t), LLVM_EXTENSION FPR_OFFSET(stmm[i]), \ 126 eEncodingUint, eFormatHex, \ 127 { dwarf_mm##i##_x86_64, dwarf_mm##i##_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_mm##i##_x86_64 }, \ 128 NULL, NULL } 129 130 #define DEFINE_XMM(reg, i) \ 131 { #reg#i, NULL, XMM_SIZE, LLVM_EXTENSION FPR_OFFSET(reg[i]), \ 132 eEncodingVector, eFormatVectorOfUInt8, \ 133 { dwarf_##reg##i##_x86_64, dwarf_##reg##i##_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_##reg##i##_x86_64}, \ 134 NULL, NULL } 135 136 #define DEFINE_YMM(reg, i) \ 137 { #reg#i, NULL, YMM_SIZE, LLVM_EXTENSION YMM_OFFSET(i), \ 138 eEncodingVector, eFormatVectorOfUInt8, \ 139 { dwarf_##reg##i##h_x86_64, dwarf_##reg##i##h_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_##reg##i##_x86_64 }, \ 140 NULL, NULL } 141 142 #define DEFINE_GPR_PSEUDO_32(reg32, reg64) \ 143 { #reg32, NULL, 4, GPR_OFFSET(reg64), eEncodingUint, \ 144 eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_##reg32##_x86_64 }, RegisterContextPOSIX_x86::g_contained_##reg64, RegisterContextPOSIX_x86::g_invalidate_##reg64 } 145 #define DEFINE_GPR_PSEUDO_16(reg16, reg64) \ 146 { #reg16, NULL, 2, GPR_OFFSET(reg64), eEncodingUint, \ 147 eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_##reg16##_x86_64 }, RegisterContextPOSIX_x86::g_contained_##reg64, RegisterContextPOSIX_x86::g_invalidate_##reg64 } 148 #define DEFINE_GPR_PSEUDO_8H(reg8, reg64) \ 149 { #reg8, NULL, 1, GPR_OFFSET(reg64)+1, eEncodingUint, \ 150 eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_##reg8##_x86_64 }, RegisterContextPOSIX_x86::g_contained_##reg64, RegisterContextPOSIX_x86::g_invalidate_##reg64 } 151 #define DEFINE_GPR_PSEUDO_8L(reg8, reg64) \ 152 { #reg8, NULL, 1, GPR_OFFSET(reg64), eEncodingUint, \ 153 eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_##reg8##_x86_64 }, RegisterContextPOSIX_x86::g_contained_##reg64, RegisterContextPOSIX_x86::g_invalidate_##reg64 } 154 155 static RegisterInfo 156 g_register_infos_x86_64[] = 157 { 158 // General purpose registers. EH_Frame, DWARF, Generic, Process Plugin 159 DEFINE_GPR(rax, nullptr, dwarf_rax_x86_64, dwarf_rax_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 160 DEFINE_GPR(rbx, nullptr, dwarf_rbx_x86_64, dwarf_rbx_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 161 DEFINE_GPR(rcx, "arg4", dwarf_rcx_x86_64, dwarf_rcx_x86_64, LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM), 162 DEFINE_GPR(rdx, "arg3", dwarf_rdx_x86_64, dwarf_rdx_x86_64, LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM), 163 DEFINE_GPR(rdi, "arg1", dwarf_rdi_x86_64, dwarf_rdi_x86_64, LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM), 164 DEFINE_GPR(rsi, "arg2", dwarf_rsi_x86_64, dwarf_rsi_x86_64, LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM), 165 DEFINE_GPR(rbp, "fp", dwarf_rbp_x86_64, dwarf_rbp_x86_64, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM), 166 DEFINE_GPR(rsp, "sp", dwarf_rsp_x86_64, dwarf_rsp_x86_64, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM), 167 DEFINE_GPR(r8, "arg5", dwarf_r8_x86_64, dwarf_r8_x86_64, LLDB_REGNUM_GENERIC_ARG5, LLDB_INVALID_REGNUM), 168 DEFINE_GPR(r9, "arg6", dwarf_r9_x86_64, dwarf_r9_x86_64, LLDB_REGNUM_GENERIC_ARG6, LLDB_INVALID_REGNUM), 169 DEFINE_GPR(r10, nullptr, dwarf_r10_x86_64, dwarf_r10_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 170 DEFINE_GPR(r11, nullptr, dwarf_r11_x86_64, dwarf_r11_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 171 DEFINE_GPR(r12, nullptr, dwarf_r12_x86_64, dwarf_r12_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 172 DEFINE_GPR(r13, nullptr, dwarf_r13_x86_64, dwarf_r13_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 173 DEFINE_GPR(r14, nullptr, dwarf_r14_x86_64, dwarf_r14_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 174 DEFINE_GPR(r15, nullptr, dwarf_r15_x86_64, dwarf_r15_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 175 DEFINE_GPR(rip, "pc", dwarf_rip_x86_64, dwarf_rip_x86_64, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM), 176 DEFINE_GPR(rflags, "flags", dwarf_rflags_x86_64, dwarf_rflags_x86_64, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM), 177 DEFINE_GPR(cs, nullptr, dwarf_cs_x86_64, dwarf_cs_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 178 DEFINE_GPR(fs, nullptr, dwarf_fs_x86_64, dwarf_fs_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 179 DEFINE_GPR(gs, nullptr, dwarf_gs_x86_64, dwarf_gs_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 180 DEFINE_GPR(ss, nullptr, dwarf_ss_x86_64, dwarf_ss_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 181 DEFINE_GPR(ds, nullptr, dwarf_ds_x86_64, dwarf_ds_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 182 DEFINE_GPR(es, nullptr, dwarf_es_x86_64, dwarf_es_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 183 184 DEFINE_GPR_PSEUDO_32(eax, rax), 185 DEFINE_GPR_PSEUDO_32(ebx, rbx), 186 DEFINE_GPR_PSEUDO_32(ecx, rcx), 187 DEFINE_GPR_PSEUDO_32(edx, rdx), 188 DEFINE_GPR_PSEUDO_32(edi, rdi), 189 DEFINE_GPR_PSEUDO_32(esi, rsi), 190 DEFINE_GPR_PSEUDO_32(ebp, rbp), 191 DEFINE_GPR_PSEUDO_32(esp, rsp), 192 DEFINE_GPR_PSEUDO_32(r8d, r8), 193 DEFINE_GPR_PSEUDO_32(r9d, r9), 194 DEFINE_GPR_PSEUDO_32(r10d, r10), 195 DEFINE_GPR_PSEUDO_32(r11d, r11), 196 DEFINE_GPR_PSEUDO_32(r12d, r12), 197 DEFINE_GPR_PSEUDO_32(r13d, r13), 198 DEFINE_GPR_PSEUDO_32(r14d, r14), 199 DEFINE_GPR_PSEUDO_32(r15d, r15), 200 DEFINE_GPR_PSEUDO_16(ax, rax), 201 DEFINE_GPR_PSEUDO_16(bx, rbx), 202 DEFINE_GPR_PSEUDO_16(cx, rcx), 203 DEFINE_GPR_PSEUDO_16(dx, rdx), 204 DEFINE_GPR_PSEUDO_16(di, rdi), 205 DEFINE_GPR_PSEUDO_16(si, rsi), 206 DEFINE_GPR_PSEUDO_16(bp, rbp), 207 DEFINE_GPR_PSEUDO_16(sp, rsp), 208 DEFINE_GPR_PSEUDO_16(r8w, r8), 209 DEFINE_GPR_PSEUDO_16(r9w, r9), 210 DEFINE_GPR_PSEUDO_16(r10w, r10), 211 DEFINE_GPR_PSEUDO_16(r11w, r11), 212 DEFINE_GPR_PSEUDO_16(r12w, r12), 213 DEFINE_GPR_PSEUDO_16(r13w, r13), 214 DEFINE_GPR_PSEUDO_16(r14w, r14), 215 DEFINE_GPR_PSEUDO_16(r15w, r15), 216 DEFINE_GPR_PSEUDO_8H(ah, rax), 217 DEFINE_GPR_PSEUDO_8H(bh, rbx), 218 DEFINE_GPR_PSEUDO_8H(ch, rcx), 219 DEFINE_GPR_PSEUDO_8H(dh, rdx), 220 DEFINE_GPR_PSEUDO_8L(al, rax), 221 DEFINE_GPR_PSEUDO_8L(bl, rbx), 222 DEFINE_GPR_PSEUDO_8L(cl, rcx), 223 DEFINE_GPR_PSEUDO_8L(dl, rdx), 224 DEFINE_GPR_PSEUDO_8L(dil, rdi), 225 DEFINE_GPR_PSEUDO_8L(sil, rsi), 226 DEFINE_GPR_PSEUDO_8L(bpl, rbp), 227 DEFINE_GPR_PSEUDO_8L(spl, rsp), 228 DEFINE_GPR_PSEUDO_8L(r8l, r8), 229 DEFINE_GPR_PSEUDO_8L(r9l, r9), 230 DEFINE_GPR_PSEUDO_8L(r10l, r10), 231 DEFINE_GPR_PSEUDO_8L(r11l, r11), 232 DEFINE_GPR_PSEUDO_8L(r12l, r12), 233 DEFINE_GPR_PSEUDO_8L(r13l, r13), 234 DEFINE_GPR_PSEUDO_8L(r14l, r14), 235 DEFINE_GPR_PSEUDO_8L(r15l, r15), 236 237 // i387 Floating point registers. EH_frame, DWARF, Generic, Process Plugin 238 DEFINE_FPR(fctrl, fctrl, dwarf_fctrl_x86_64, dwarf_fctrl_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 239 DEFINE_FPR(fstat, fstat, dwarf_fstat_x86_64, dwarf_fstat_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 240 DEFINE_FPR(ftag, ftag, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 241 DEFINE_FPR(fop, fop, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 242 DEFINE_FPR(fiseg, ptr.i386_.fiseg, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 243 DEFINE_FPR(fioff, ptr.i386_.fioff, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 244 DEFINE_FPR(foseg, ptr.i386_.foseg, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 245 DEFINE_FPR(fooff, ptr.i386_.fooff, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 246 DEFINE_FPR(mxcsr, mxcsr, dwarf_mxcsr_x86_64, dwarf_mxcsr_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 247 DEFINE_FPR(mxcsrmask, mxcsrmask, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 248 249 // FP registers. 250 DEFINE_FP_ST(st, 0), 251 DEFINE_FP_ST(st, 1), 252 DEFINE_FP_ST(st, 2), 253 DEFINE_FP_ST(st, 3), 254 DEFINE_FP_ST(st, 4), 255 DEFINE_FP_ST(st, 5), 256 DEFINE_FP_ST(st, 6), 257 DEFINE_FP_ST(st, 7), 258 DEFINE_FP_MM(mm, 0), 259 DEFINE_FP_MM(mm, 1), 260 DEFINE_FP_MM(mm, 2), 261 DEFINE_FP_MM(mm, 3), 262 DEFINE_FP_MM(mm, 4), 263 DEFINE_FP_MM(mm, 5), 264 DEFINE_FP_MM(mm, 6), 265 DEFINE_FP_MM(mm, 7), 266 267 // XMM registers 268 DEFINE_XMM(xmm, 0), 269 DEFINE_XMM(xmm, 1), 270 DEFINE_XMM(xmm, 2), 271 DEFINE_XMM(xmm, 3), 272 DEFINE_XMM(xmm, 4), 273 DEFINE_XMM(xmm, 5), 274 DEFINE_XMM(xmm, 6), 275 DEFINE_XMM(xmm, 7), 276 DEFINE_XMM(xmm, 8), 277 DEFINE_XMM(xmm, 9), 278 DEFINE_XMM(xmm, 10), 279 DEFINE_XMM(xmm, 11), 280 DEFINE_XMM(xmm, 12), 281 DEFINE_XMM(xmm, 13), 282 DEFINE_XMM(xmm, 14), 283 DEFINE_XMM(xmm, 15), 284 285 // Copy of YMM registers assembled from xmm and ymmh 286 DEFINE_YMM(ymm, 0), 287 DEFINE_YMM(ymm, 1), 288 DEFINE_YMM(ymm, 2), 289 DEFINE_YMM(ymm, 3), 290 DEFINE_YMM(ymm, 4), 291 DEFINE_YMM(ymm, 5), 292 DEFINE_YMM(ymm, 6), 293 DEFINE_YMM(ymm, 7), 294 DEFINE_YMM(ymm, 8), 295 DEFINE_YMM(ymm, 9), 296 DEFINE_YMM(ymm, 10), 297 DEFINE_YMM(ymm, 11), 298 DEFINE_YMM(ymm, 12), 299 DEFINE_YMM(ymm, 13), 300 DEFINE_YMM(ymm, 14), 301 DEFINE_YMM(ymm, 15), 302 }; 303 304 //--------------------------------------------------------------------------- 305 // End of cherry-pick of RegisterInfos_x86_64.h 306 //--------------------------------------------------------------------------- 307 308 static const RegisterInfo * 309 PrivateGetRegisterInfoPtr (const lldb_private::ArchSpec& target_arch) 310 { 311 switch (target_arch.GetMachine()) 312 { 313 case llvm::Triple::x86_64: 314 return g_register_infos_x86_64; 315 default: 316 assert(false && "Unhandled target architecture."); 317 return nullptr; 318 } 319 } 320 321 static uint32_t 322 PrivateGetRegisterCount (const lldb_private::ArchSpec& target_arch) 323 { 324 switch (target_arch.GetMachine()) 325 { 326 case llvm::Triple::x86_64: 327 return static_cast<uint32_t> (sizeof (g_register_infos_x86_64) / sizeof (g_register_infos_x86_64 [0])); 328 default: 329 assert(false && "Unhandled target architecture."); 330 return 0; 331 } 332 } 333 334 RegisterContextNetBSD_x86_64::RegisterContextNetBSD_x86_64(const ArchSpec &target_arch) : 335 lldb_private::RegisterInfoInterface(target_arch), 336 m_register_info_p (PrivateGetRegisterInfoPtr (target_arch)), 337 m_register_count (PrivateGetRegisterCount (target_arch)) 338 { 339 } 340 341 size_t 342 RegisterContextNetBSD_x86_64::GetGPRSize() const 343 { 344 return sizeof(GPR); 345 } 346 347 const RegisterInfo * 348 RegisterContextNetBSD_x86_64::GetRegisterInfo() const 349 { 350 return m_register_info_p; 351 } 352 353 uint32_t 354 RegisterContextNetBSD_x86_64::GetRegisterCount () const 355 { 356 return m_register_count; 357 } 358