1 //===-- RegisterContextNetBSD_x86_64.cpp ------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "RegisterContextNetBSD_x86_64.h" 11 #include "RegisterContextPOSIX_x86.h" 12 #include "llvm/ADT/Triple.h" 13 #include "llvm/Support/Compiler.h" 14 #include <cassert> 15 #include <cstddef> 16 17 using namespace lldb_private; 18 using namespace lldb; 19 20 // src/sys/arch/amd64/include/frame_regs.h 21 typedef struct _GPR { 22 uint64_t rdi; /* 0 */ 23 uint64_t rsi; /* 1 */ 24 uint64_t rdx; /* 2 */ 25 uint64_t rcx; /* 3 */ 26 uint64_t r8; /* 4 */ 27 uint64_t r9; /* 5 */ 28 uint64_t r10; /* 6 */ 29 uint64_t r11; /* 7 */ 30 uint64_t r12; /* 8 */ 31 uint64_t r13; /* 9 */ 32 uint64_t r14; /* 10 */ 33 uint64_t r15; /* 11 */ 34 uint64_t rbp; /* 12 */ 35 uint64_t rbx; /* 13 */ 36 uint64_t rax; /* 14 */ 37 uint64_t gs; /* 15 */ 38 uint64_t fs; /* 16 */ 39 uint64_t es; /* 17 */ 40 uint64_t ds; /* 18 */ 41 uint64_t trapno; /* 19 */ 42 uint64_t err; /* 20 */ 43 uint64_t rip; /* 21 */ 44 uint64_t cs; /* 22 */ 45 uint64_t rflags; /* 23 */ 46 uint64_t rsp; /* 24 */ 47 uint64_t ss; /* 25 */ 48 } GPR; 49 50 /* 51 * As of NetBSD-7.99.25 there is no support for debug registers 52 * https://en.wikipedia.org/wiki/X86_debug_register 53 */ 54 55 /* 56 * src/sys/arch/amd64/include/mcontext.h 57 * 58 * typedef struct { 59 * __gregset_t __gregs; 60 * __greg_t _mc_tlsbase; 61 * __fpregset_t __fpregs; 62 * } mcontext_t; 63 */ 64 65 struct UserArea { 66 GPR gpr; 67 uint64_t mc_tlsbase; 68 FPR fpr; 69 }; 70 71 //--------------------------------------------------------------------------- 72 // Cherry-pick parts of RegisterInfos_x86_64.h, without debug registers 73 //--------------------------------------------------------------------------- 74 // Computes the offset of the given GPR in the user data area. 75 #define GPR_OFFSET(regname) (LLVM_EXTENSION offsetof(GPR, regname)) 76 77 // Computes the offset of the given FPR in the extended data area. 78 #define FPR_OFFSET(regname) \ 79 (LLVM_EXTENSION offsetof(UserArea, fpr) + \ 80 LLVM_EXTENSION offsetof(FPR, xstate) + \ 81 LLVM_EXTENSION offsetof(FXSAVE, regname)) 82 83 // Computes the offset of the YMM register assembled from register halves. 84 // Based on DNBArchImplX86_64.cpp from debugserver 85 #define YMM_OFFSET(reg_index) \ 86 (LLVM_EXTENSION offsetof(UserArea, fpr) + \ 87 LLVM_EXTENSION offsetof(FPR, xstate) + \ 88 LLVM_EXTENSION offsetof(XSAVE, ymmh[0]) + (32 * reg_index)) 89 90 // Number of bytes needed to represent a FPR. 91 #define FPR_SIZE(reg) sizeof(((FXSAVE *)nullptr)->reg) 92 93 // Number of bytes needed to represent the i'th FP register. 94 #define FP_SIZE sizeof(((MMSReg *)nullptr)->bytes) 95 96 // Number of bytes needed to represent an XMM register. 97 #define XMM_SIZE sizeof(XMMReg) 98 99 // Number of bytes needed to represent a YMM register. 100 #define YMM_SIZE sizeof(YMMReg) 101 102 // RegisterKind: EHFrame, DWARF, Generic, Process Plugin, LLDB 103 104 // Note that the size and offset will be updated by platform-specific classes. 105 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \ 106 { \ 107 #reg, alt, sizeof(((GPR *)nullptr)->reg), \ 108 GPR_OFFSET(reg), eEncodingUint, eFormatHex, \ 109 {kind1, kind2, kind3, kind4, \ 110 lldb_##reg##_x86_64 }, \ 111 nullptr, nullptr, nullptr, 0 \ 112 } 113 114 #define DEFINE_FPR(name, reg, kind1, kind2, kind3, kind4) \ 115 { \ 116 #name, nullptr, FPR_SIZE(reg), FPR_OFFSET(reg), eEncodingUint, eFormatHex, \ 117 {kind1, kind2, kind3, kind4, \ 118 lldb_##name##_x86_64 }, \ 119 nullptr, nullptr, nullptr, 0 \ 120 } 121 122 #define DEFINE_FP_ST(reg, i) \ 123 { \ 124 #reg #i, nullptr, FP_SIZE, \ 125 LLVM_EXTENSION FPR_OFFSET( \ 126 stmm[i]), eEncodingVector, eFormatVectorOfUInt8, \ 127 {dwarf_st##i##_x86_64, dwarf_st##i##_x86_64, LLDB_INVALID_REGNUM, \ 128 LLDB_INVALID_REGNUM, lldb_st##i##_x86_64 }, \ 129 nullptr, nullptr, nullptr, 0 \ 130 } 131 132 #define DEFINE_FP_MM(reg, i) \ 133 { \ 134 #reg #i, nullptr, sizeof(uint64_t), \ 135 LLVM_EXTENSION FPR_OFFSET( \ 136 stmm[i]), eEncodingUint, eFormatHex, \ 137 {dwarf_mm##i##_x86_64, dwarf_mm##i##_x86_64, \ 138 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 139 lldb_mm##i##_x86_64 }, \ 140 nullptr, nullptr, nullptr, 0 \ 141 } 142 143 #define DEFINE_XMM(reg, i) \ 144 { \ 145 #reg #i, nullptr, XMM_SIZE, \ 146 LLVM_EXTENSION FPR_OFFSET( \ 147 reg[i]), eEncodingVector, eFormatVectorOfUInt8, \ 148 {dwarf_##reg##i##_x86_64, dwarf_##reg##i##_x86_64, \ 149 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 150 lldb_##reg##i##_x86_64 }, \ 151 nullptr, nullptr, nullptr, 0 \ 152 } 153 154 #define DEFINE_YMM(reg, i) \ 155 { \ 156 #reg #i, nullptr, YMM_SIZE, \ 157 LLVM_EXTENSION YMM_OFFSET(i), eEncodingVector, eFormatVectorOfUInt8, \ 158 {dwarf_##reg##i##h_x86_64, \ 159 dwarf_##reg##i##h_x86_64, \ 160 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 161 lldb_##reg##i##_x86_64 }, \ 162 nullptr, nullptr, nullptr, 0 \ 163 } 164 165 #define DEFINE_GPR_PSEUDO_32(reg32, reg64) \ 166 { \ 167 #reg32, nullptr, 4, \ 168 GPR_OFFSET(reg64), eEncodingUint, eFormatHex, \ 169 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 170 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 171 lldb_##reg32##_x86_64 }, \ 172 RegisterContextPOSIX_x86::g_contained_##reg64, \ 173 RegisterContextPOSIX_x86::g_invalidate_##reg64, nullptr, 0 \ 174 } 175 176 #define DEFINE_GPR_PSEUDO_16(reg16, reg64) \ 177 { \ 178 #reg16, nullptr, 2, \ 179 GPR_OFFSET(reg64), eEncodingUint, eFormatHex, \ 180 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 181 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 182 lldb_##reg16##_x86_64 }, \ 183 RegisterContextPOSIX_x86::g_contained_##reg64, \ 184 RegisterContextPOSIX_x86::g_invalidate_##reg64, nullptr, 0 \ 185 } 186 187 #define DEFINE_GPR_PSEUDO_8H(reg8, reg64) \ 188 { \ 189 #reg8, nullptr, 1, GPR_OFFSET(reg64) + 1, eEncodingUint, eFormatHex, \ 190 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 191 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 192 lldb_##reg8##_x86_64 }, \ 193 RegisterContextPOSIX_x86::g_contained_##reg64, \ 194 RegisterContextPOSIX_x86::g_invalidate_##reg64,\ 195 nullptr, 0 \ 196 } 197 198 #define DEFINE_GPR_PSEUDO_8L(reg8, reg64) \ 199 { \ 200 #reg8, nullptr, 1, GPR_OFFSET(reg64), eEncodingUint, eFormatHex, \ 201 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 202 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 203 lldb_##reg8##_x86_64 }, \ 204 RegisterContextPOSIX_x86::g_contained_##reg64, \ 205 RegisterContextPOSIX_x86::g_invalidate_##reg64,\ 206 nullptr, 0 \ 207 } 208 209 static RegisterInfo g_register_infos_x86_64[] = { 210 // General purpose registers. EH_Frame, DWARF, 211 // Generic, Process Plugin 212 DEFINE_GPR(rax, nullptr, dwarf_rax_x86_64, dwarf_rax_x86_64, 213 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 214 DEFINE_GPR(rbx, nullptr, dwarf_rbx_x86_64, dwarf_rbx_x86_64, 215 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 216 DEFINE_GPR(rcx, "arg4", dwarf_rcx_x86_64, dwarf_rcx_x86_64, 217 LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM), 218 DEFINE_GPR(rdx, "arg3", dwarf_rdx_x86_64, dwarf_rdx_x86_64, 219 LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM), 220 DEFINE_GPR(rdi, "arg1", dwarf_rdi_x86_64, dwarf_rdi_x86_64, 221 LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM), 222 DEFINE_GPR(rsi, "arg2", dwarf_rsi_x86_64, dwarf_rsi_x86_64, 223 LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM), 224 DEFINE_GPR(rbp, "fp", dwarf_rbp_x86_64, dwarf_rbp_x86_64, 225 LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM), 226 DEFINE_GPR(rsp, "sp", dwarf_rsp_x86_64, dwarf_rsp_x86_64, 227 LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM), 228 DEFINE_GPR(r8, "arg5", dwarf_r8_x86_64, dwarf_r8_x86_64, 229 LLDB_REGNUM_GENERIC_ARG5, LLDB_INVALID_REGNUM), 230 DEFINE_GPR(r9, "arg6", dwarf_r9_x86_64, dwarf_r9_x86_64, 231 LLDB_REGNUM_GENERIC_ARG6, LLDB_INVALID_REGNUM), 232 DEFINE_GPR(r10, nullptr, dwarf_r10_x86_64, dwarf_r10_x86_64, 233 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 234 DEFINE_GPR(r11, nullptr, dwarf_r11_x86_64, dwarf_r11_x86_64, 235 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 236 DEFINE_GPR(r12, nullptr, dwarf_r12_x86_64, dwarf_r12_x86_64, 237 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 238 DEFINE_GPR(r13, nullptr, dwarf_r13_x86_64, dwarf_r13_x86_64, 239 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 240 DEFINE_GPR(r14, nullptr, dwarf_r14_x86_64, dwarf_r14_x86_64, 241 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 242 DEFINE_GPR(r15, nullptr, dwarf_r15_x86_64, dwarf_r15_x86_64, 243 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 244 DEFINE_GPR(rip, "pc", dwarf_rip_x86_64, dwarf_rip_x86_64, 245 LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM), 246 DEFINE_GPR(rflags, "flags", dwarf_rflags_x86_64, dwarf_rflags_x86_64, 247 LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM), 248 DEFINE_GPR(cs, nullptr, dwarf_cs_x86_64, dwarf_cs_x86_64, 249 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 250 DEFINE_GPR(fs, nullptr, dwarf_fs_x86_64, dwarf_fs_x86_64, 251 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 252 DEFINE_GPR(gs, nullptr, dwarf_gs_x86_64, dwarf_gs_x86_64, 253 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 254 DEFINE_GPR(ss, nullptr, dwarf_ss_x86_64, dwarf_ss_x86_64, 255 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 256 DEFINE_GPR(ds, nullptr, dwarf_ds_x86_64, dwarf_ds_x86_64, 257 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 258 DEFINE_GPR(es, nullptr, dwarf_es_x86_64, dwarf_es_x86_64, 259 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 260 261 DEFINE_GPR_PSEUDO_32(eax, rax), DEFINE_GPR_PSEUDO_32(ebx, rbx), 262 DEFINE_GPR_PSEUDO_32(ecx, rcx), DEFINE_GPR_PSEUDO_32(edx, rdx), 263 DEFINE_GPR_PSEUDO_32(edi, rdi), DEFINE_GPR_PSEUDO_32(esi, rsi), 264 DEFINE_GPR_PSEUDO_32(ebp, rbp), DEFINE_GPR_PSEUDO_32(esp, rsp), 265 DEFINE_GPR_PSEUDO_32(r8d, r8), DEFINE_GPR_PSEUDO_32(r9d, r9), 266 DEFINE_GPR_PSEUDO_32(r10d, r10), DEFINE_GPR_PSEUDO_32(r11d, r11), 267 DEFINE_GPR_PSEUDO_32(r12d, r12), DEFINE_GPR_PSEUDO_32(r13d, r13), 268 DEFINE_GPR_PSEUDO_32(r14d, r14), DEFINE_GPR_PSEUDO_32(r15d, r15), 269 DEFINE_GPR_PSEUDO_16(ax, rax), DEFINE_GPR_PSEUDO_16(bx, rbx), 270 DEFINE_GPR_PSEUDO_16(cx, rcx), DEFINE_GPR_PSEUDO_16(dx, rdx), 271 DEFINE_GPR_PSEUDO_16(di, rdi), DEFINE_GPR_PSEUDO_16(si, rsi), 272 DEFINE_GPR_PSEUDO_16(bp, rbp), DEFINE_GPR_PSEUDO_16(sp, rsp), 273 DEFINE_GPR_PSEUDO_16(r8w, r8), DEFINE_GPR_PSEUDO_16(r9w, r9), 274 DEFINE_GPR_PSEUDO_16(r10w, r10), DEFINE_GPR_PSEUDO_16(r11w, r11), 275 DEFINE_GPR_PSEUDO_16(r12w, r12), DEFINE_GPR_PSEUDO_16(r13w, r13), 276 DEFINE_GPR_PSEUDO_16(r14w, r14), DEFINE_GPR_PSEUDO_16(r15w, r15), 277 DEFINE_GPR_PSEUDO_8H(ah, rax), DEFINE_GPR_PSEUDO_8H(bh, rbx), 278 DEFINE_GPR_PSEUDO_8H(ch, rcx), DEFINE_GPR_PSEUDO_8H(dh, rdx), 279 DEFINE_GPR_PSEUDO_8L(al, rax), DEFINE_GPR_PSEUDO_8L(bl, rbx), 280 DEFINE_GPR_PSEUDO_8L(cl, rcx), DEFINE_GPR_PSEUDO_8L(dl, rdx), 281 DEFINE_GPR_PSEUDO_8L(dil, rdi), DEFINE_GPR_PSEUDO_8L(sil, rsi), 282 DEFINE_GPR_PSEUDO_8L(bpl, rbp), DEFINE_GPR_PSEUDO_8L(spl, rsp), 283 DEFINE_GPR_PSEUDO_8L(r8l, r8), DEFINE_GPR_PSEUDO_8L(r9l, r9), 284 DEFINE_GPR_PSEUDO_8L(r10l, r10), DEFINE_GPR_PSEUDO_8L(r11l, r11), 285 DEFINE_GPR_PSEUDO_8L(r12l, r12), DEFINE_GPR_PSEUDO_8L(r13l, r13), 286 DEFINE_GPR_PSEUDO_8L(r14l, r14), DEFINE_GPR_PSEUDO_8L(r15l, r15), 287 288 // i387 Floating point registers. EH_frame, 289 // DWARF, Generic, Process Plugin 290 DEFINE_FPR(fctrl, fctrl, dwarf_fctrl_x86_64, dwarf_fctrl_x86_64, 291 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 292 DEFINE_FPR(fstat, fstat, dwarf_fstat_x86_64, dwarf_fstat_x86_64, 293 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 294 DEFINE_FPR(ftag, ftag, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 295 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 296 DEFINE_FPR(fop, fop, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 297 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 298 DEFINE_FPR(fiseg, ptr.i386_.fiseg, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 299 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 300 DEFINE_FPR(fioff, ptr.i386_.fioff, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 301 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 302 DEFINE_FPR(foseg, ptr.i386_.foseg, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 303 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 304 DEFINE_FPR(fooff, ptr.i386_.fooff, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 305 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 306 DEFINE_FPR(mxcsr, mxcsr, dwarf_mxcsr_x86_64, dwarf_mxcsr_x86_64, 307 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 308 DEFINE_FPR(mxcsrmask, mxcsrmask, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 309 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 310 311 // FP registers. 312 DEFINE_FP_ST(st, 0), DEFINE_FP_ST(st, 1), DEFINE_FP_ST(st, 2), 313 DEFINE_FP_ST(st, 3), DEFINE_FP_ST(st, 4), DEFINE_FP_ST(st, 5), 314 DEFINE_FP_ST(st, 6), DEFINE_FP_ST(st, 7), DEFINE_FP_MM(mm, 0), 315 DEFINE_FP_MM(mm, 1), DEFINE_FP_MM(mm, 2), DEFINE_FP_MM(mm, 3), 316 DEFINE_FP_MM(mm, 4), DEFINE_FP_MM(mm, 5), DEFINE_FP_MM(mm, 6), 317 DEFINE_FP_MM(mm, 7), 318 319 // XMM registers 320 DEFINE_XMM(xmm, 0), DEFINE_XMM(xmm, 1), DEFINE_XMM(xmm, 2), 321 DEFINE_XMM(xmm, 3), DEFINE_XMM(xmm, 4), DEFINE_XMM(xmm, 5), 322 DEFINE_XMM(xmm, 6), DEFINE_XMM(xmm, 7), DEFINE_XMM(xmm, 8), 323 DEFINE_XMM(xmm, 9), DEFINE_XMM(xmm, 10), DEFINE_XMM(xmm, 11), 324 DEFINE_XMM(xmm, 12), DEFINE_XMM(xmm, 13), DEFINE_XMM(xmm, 14), 325 DEFINE_XMM(xmm, 15), 326 327 // Copy of YMM registers assembled from xmm and ymmh 328 DEFINE_YMM(ymm, 0), DEFINE_YMM(ymm, 1), DEFINE_YMM(ymm, 2), 329 DEFINE_YMM(ymm, 3), DEFINE_YMM(ymm, 4), DEFINE_YMM(ymm, 5), 330 DEFINE_YMM(ymm, 6), DEFINE_YMM(ymm, 7), DEFINE_YMM(ymm, 8), 331 DEFINE_YMM(ymm, 9), DEFINE_YMM(ymm, 10), DEFINE_YMM(ymm, 11), 332 DEFINE_YMM(ymm, 12), DEFINE_YMM(ymm, 13), DEFINE_YMM(ymm, 14), 333 DEFINE_YMM(ymm, 15), 334 }; 335 336 //--------------------------------------------------------------------------- 337 // End of cherry-pick of RegisterInfos_x86_64.h 338 //--------------------------------------------------------------------------- 339 340 static const RegisterInfo * 341 PrivateGetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) { 342 switch (target_arch.GetMachine()) { 343 case llvm::Triple::x86_64: 344 return g_register_infos_x86_64; 345 default: 346 assert(false && "Unhandled target architecture."); 347 return nullptr; 348 } 349 } 350 351 static uint32_t 352 PrivateGetRegisterCount(const lldb_private::ArchSpec &target_arch) { 353 switch (target_arch.GetMachine()) { 354 case llvm::Triple::x86_64: 355 return static_cast<uint32_t>(sizeof(g_register_infos_x86_64) / 356 sizeof(g_register_infos_x86_64[0])); 357 default: 358 assert(false && "Unhandled target architecture."); 359 return 0; 360 } 361 } 362 363 RegisterContextNetBSD_x86_64::RegisterContextNetBSD_x86_64( 364 const ArchSpec &target_arch) 365 : lldb_private::RegisterInfoInterface(target_arch), 366 m_register_info_p(PrivateGetRegisterInfoPtr(target_arch)), 367 m_register_count(PrivateGetRegisterCount(target_arch)) {} 368 369 size_t RegisterContextNetBSD_x86_64::GetGPRSize() const { return sizeof(GPR); } 370 371 const RegisterInfo *RegisterContextNetBSD_x86_64::GetRegisterInfo() const { 372 return m_register_info_p; 373 } 374 375 uint32_t RegisterContextNetBSD_x86_64::GetRegisterCount() const { 376 return m_register_count; 377 } 378