1 //===-- RegisterContextDarwin_x86_64.cpp ------------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 // C Includes
11 #include <inttypes.h> // PRIx64
12 #include <stdarg.h>
13 #include <stddef.h> // offsetof
14 
15 // C++ Includes
16 // Other libraries and framework includes
17 #include "lldb/Core/DataBufferHeap.h"
18 #include "lldb/Core/DataExtractor.h"
19 #include "lldb/Core/Log.h"
20 #include "lldb/Core/RegisterValue.h"
21 #include "lldb/Core/Scalar.h"
22 #include "lldb/Host/Endian.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/Support/Compiler.h"
25 
26 // Support building against older versions of LLVM, this macro was added
27 // recently.
28 #ifndef LLVM_EXTENSION
29 #define LLVM_EXTENSION
30 #endif
31 
32 // Project includes
33 #include "RegisterContextDarwin_x86_64.h"
34 
35 using namespace lldb;
36 using namespace lldb_private;
37 
38 enum {
39   gpr_rax = 0,
40   gpr_rbx,
41   gpr_rcx,
42   gpr_rdx,
43   gpr_rdi,
44   gpr_rsi,
45   gpr_rbp,
46   gpr_rsp,
47   gpr_r8,
48   gpr_r9,
49   gpr_r10,
50   gpr_r11,
51   gpr_r12,
52   gpr_r13,
53   gpr_r14,
54   gpr_r15,
55   gpr_rip,
56   gpr_rflags,
57   gpr_cs,
58   gpr_fs,
59   gpr_gs,
60 
61   fpu_fcw,
62   fpu_fsw,
63   fpu_ftw,
64   fpu_fop,
65   fpu_ip,
66   fpu_cs,
67   fpu_dp,
68   fpu_ds,
69   fpu_mxcsr,
70   fpu_mxcsrmask,
71   fpu_stmm0,
72   fpu_stmm1,
73   fpu_stmm2,
74   fpu_stmm3,
75   fpu_stmm4,
76   fpu_stmm5,
77   fpu_stmm6,
78   fpu_stmm7,
79   fpu_xmm0,
80   fpu_xmm1,
81   fpu_xmm2,
82   fpu_xmm3,
83   fpu_xmm4,
84   fpu_xmm5,
85   fpu_xmm6,
86   fpu_xmm7,
87   fpu_xmm8,
88   fpu_xmm9,
89   fpu_xmm10,
90   fpu_xmm11,
91   fpu_xmm12,
92   fpu_xmm13,
93   fpu_xmm14,
94   fpu_xmm15,
95 
96   exc_trapno,
97   exc_err,
98   exc_faultvaddr,
99 
100   k_num_registers,
101 
102   // Aliases
103   fpu_fctrl = fpu_fcw,
104   fpu_fstat = fpu_fsw,
105   fpu_ftag = fpu_ftw,
106   fpu_fiseg = fpu_cs,
107   fpu_fioff = fpu_ip,
108   fpu_foseg = fpu_ds,
109   fpu_fooff = fpu_dp
110 };
111 
112 enum ehframe_dwarf_regnums {
113   ehframe_dwarf_gpr_rax = 0,
114   ehframe_dwarf_gpr_rdx,
115   ehframe_dwarf_gpr_rcx,
116   ehframe_dwarf_gpr_rbx,
117   ehframe_dwarf_gpr_rsi,
118   ehframe_dwarf_gpr_rdi,
119   ehframe_dwarf_gpr_rbp,
120   ehframe_dwarf_gpr_rsp,
121   ehframe_dwarf_gpr_r8,
122   ehframe_dwarf_gpr_r9,
123   ehframe_dwarf_gpr_r10,
124   ehframe_dwarf_gpr_r11,
125   ehframe_dwarf_gpr_r12,
126   ehframe_dwarf_gpr_r13,
127   ehframe_dwarf_gpr_r14,
128   ehframe_dwarf_gpr_r15,
129   ehframe_dwarf_gpr_rip,
130   ehframe_dwarf_fpu_xmm0,
131   ehframe_dwarf_fpu_xmm1,
132   ehframe_dwarf_fpu_xmm2,
133   ehframe_dwarf_fpu_xmm3,
134   ehframe_dwarf_fpu_xmm4,
135   ehframe_dwarf_fpu_xmm5,
136   ehframe_dwarf_fpu_xmm6,
137   ehframe_dwarf_fpu_xmm7,
138   ehframe_dwarf_fpu_xmm8,
139   ehframe_dwarf_fpu_xmm9,
140   ehframe_dwarf_fpu_xmm10,
141   ehframe_dwarf_fpu_xmm11,
142   ehframe_dwarf_fpu_xmm12,
143   ehframe_dwarf_fpu_xmm13,
144   ehframe_dwarf_fpu_xmm14,
145   ehframe_dwarf_fpu_xmm15,
146   ehframe_dwarf_fpu_stmm0,
147   ehframe_dwarf_fpu_stmm1,
148   ehframe_dwarf_fpu_stmm2,
149   ehframe_dwarf_fpu_stmm3,
150   ehframe_dwarf_fpu_stmm4,
151   ehframe_dwarf_fpu_stmm5,
152   ehframe_dwarf_fpu_stmm6,
153   ehframe_dwarf_fpu_stmm7
154 
155 };
156 
157 #define GPR_OFFSET(reg)                                                        \
158   (LLVM_EXTENSION offsetof(RegisterContextDarwin_x86_64::GPR, reg))
159 #define FPU_OFFSET(reg)                                                        \
160   (LLVM_EXTENSION offsetof(RegisterContextDarwin_x86_64::FPU, reg) +           \
161    sizeof(RegisterContextDarwin_x86_64::GPR))
162 #define EXC_OFFSET(reg)                                                        \
163   (LLVM_EXTENSION offsetof(RegisterContextDarwin_x86_64::EXC, reg) +           \
164    sizeof(RegisterContextDarwin_x86_64::GPR) +                                 \
165    sizeof(RegisterContextDarwin_x86_64::FPU))
166 
167 // These macros will auto define the register name, alt name, register size,
168 // register offset, encoding, format and native register. This ensures that
169 // the register state structures are defined correctly and have the correct
170 // sizes and offsets.
171 #define DEFINE_GPR(reg, alt)                                                   \
172   #reg, alt, sizeof(((RegisterContextDarwin_x86_64::GPR *) NULL)->reg),        \
173                     GPR_OFFSET(reg), eEncodingUint, eFormatHex
174 #define DEFINE_FPU_UINT(reg)                                                   \
175   #reg, NULL, sizeof(((RegisterContextDarwin_x86_64::FPU *) NULL)->reg),       \
176                      FPU_OFFSET(reg), eEncodingUint, eFormatHex
177 #define DEFINE_FPU_VECT(reg, i)                                                \
178   #reg #i, NULL,                                                               \
179       sizeof(((RegisterContextDarwin_x86_64::FPU *) NULL)->reg[i].bytes),      \
180               FPU_OFFSET(reg[i]), eEncodingVector, eFormatVectorOfUInt8,       \
181                          {ehframe_dwarf_fpu_##reg##i,                          \
182                           ehframe_dwarf_fpu_##reg##i, LLDB_INVALID_REGNUM,     \
183                           LLDB_INVALID_REGNUM, fpu_##reg##i },                 \
184                           nullptr, nullptr, nullptr, 0
185 #define DEFINE_EXC(reg)                                                        \
186   #reg, NULL, sizeof(((RegisterContextDarwin_x86_64::EXC *) NULL)->reg),       \
187                      EXC_OFFSET(reg), eEncodingUint, eFormatHex
188 
189 #define REG_CONTEXT_SIZE                                                       \
190   (sizeof(RegisterContextDarwin_x86_64::GPR) +                                 \
191    sizeof(RegisterContextDarwin_x86_64::FPU) +                                 \
192    sizeof(RegisterContextDarwin_x86_64::EXC))
193 
194 // General purpose registers for 64 bit
195 static RegisterInfo g_register_infos[] = {
196     //  Macro auto defines most stuff   EH_FRAME                    DWARF
197     //  GENERIC                    PROCESS PLUGIN       LLDB
198     //  =============================== ======================
199     //  ===================      ========================== ====================
200     //  ===================
201     {DEFINE_GPR(rax, NULL),
202      {ehframe_dwarf_gpr_rax, ehframe_dwarf_gpr_rax, LLDB_INVALID_REGNUM,
203       LLDB_INVALID_REGNUM, gpr_rax},
204      nullptr,
205      nullptr,
206      nullptr,
207      0},
208     {DEFINE_GPR(rbx, NULL),
209      {ehframe_dwarf_gpr_rbx, ehframe_dwarf_gpr_rbx, LLDB_INVALID_REGNUM,
210       LLDB_INVALID_REGNUM, gpr_rbx},
211      nullptr,
212      nullptr,
213      nullptr,
214      0},
215     {DEFINE_GPR(rcx, NULL),
216      {ehframe_dwarf_gpr_rcx, ehframe_dwarf_gpr_rcx, LLDB_INVALID_REGNUM,
217       LLDB_INVALID_REGNUM, gpr_rcx},
218      nullptr,
219      nullptr,
220      nullptr,
221      0},
222     {DEFINE_GPR(rdx, NULL),
223      {ehframe_dwarf_gpr_rdx, ehframe_dwarf_gpr_rdx, LLDB_INVALID_REGNUM,
224       LLDB_INVALID_REGNUM, gpr_rdx},
225      nullptr,
226      nullptr,
227      nullptr,
228      0},
229     {DEFINE_GPR(rdi, NULL),
230      {ehframe_dwarf_gpr_rdi, ehframe_dwarf_gpr_rdi, LLDB_INVALID_REGNUM,
231       LLDB_INVALID_REGNUM, gpr_rdi},
232      nullptr,
233      nullptr,
234      nullptr,
235      0},
236     {DEFINE_GPR(rsi, NULL),
237      {ehframe_dwarf_gpr_rsi, ehframe_dwarf_gpr_rsi, LLDB_INVALID_REGNUM,
238       LLDB_INVALID_REGNUM, gpr_rsi},
239      nullptr,
240      nullptr,
241      nullptr,
242      0},
243     {DEFINE_GPR(rbp, "fp"),
244      {ehframe_dwarf_gpr_rbp, ehframe_dwarf_gpr_rbp, LLDB_REGNUM_GENERIC_FP,
245       LLDB_INVALID_REGNUM, gpr_rbp},
246      nullptr,
247      nullptr,
248      nullptr,
249      0},
250     {DEFINE_GPR(rsp, "sp"),
251      {ehframe_dwarf_gpr_rsp, ehframe_dwarf_gpr_rsp, LLDB_REGNUM_GENERIC_SP,
252       LLDB_INVALID_REGNUM, gpr_rsp},
253      nullptr,
254      nullptr,
255      nullptr,
256      0},
257     {DEFINE_GPR(r8, NULL),
258      {ehframe_dwarf_gpr_r8, ehframe_dwarf_gpr_r8, LLDB_INVALID_REGNUM,
259       LLDB_INVALID_REGNUM, gpr_r8},
260      nullptr,
261      nullptr,
262      nullptr,
263      0},
264     {DEFINE_GPR(r9, NULL),
265      {ehframe_dwarf_gpr_r9, ehframe_dwarf_gpr_r9, LLDB_INVALID_REGNUM,
266       LLDB_INVALID_REGNUM, gpr_r9},
267      nullptr,
268      nullptr,
269      nullptr,
270      0},
271     {DEFINE_GPR(r10, NULL),
272      {ehframe_dwarf_gpr_r10, ehframe_dwarf_gpr_r10, LLDB_INVALID_REGNUM,
273       LLDB_INVALID_REGNUM, gpr_r10},
274      nullptr,
275      nullptr,
276      nullptr,
277      0},
278     {DEFINE_GPR(r11, NULL),
279      {ehframe_dwarf_gpr_r11, ehframe_dwarf_gpr_r11, LLDB_INVALID_REGNUM,
280       LLDB_INVALID_REGNUM, gpr_r11},
281      nullptr,
282      nullptr,
283      nullptr,
284      0},
285     {DEFINE_GPR(r12, NULL),
286      {ehframe_dwarf_gpr_r12, ehframe_dwarf_gpr_r12, LLDB_INVALID_REGNUM,
287       LLDB_INVALID_REGNUM, gpr_r12},
288      nullptr,
289      nullptr,
290      nullptr,
291      0},
292     {DEFINE_GPR(r13, NULL),
293      {ehframe_dwarf_gpr_r13, ehframe_dwarf_gpr_r13, LLDB_INVALID_REGNUM,
294       LLDB_INVALID_REGNUM, gpr_r13},
295      nullptr,
296      nullptr,
297      nullptr,
298      0},
299     {DEFINE_GPR(r14, NULL),
300      {ehframe_dwarf_gpr_r14, ehframe_dwarf_gpr_r14, LLDB_INVALID_REGNUM,
301       LLDB_INVALID_REGNUM, gpr_r14},
302      nullptr,
303      nullptr,
304      nullptr,
305      0},
306     {DEFINE_GPR(r15, NULL),
307      {ehframe_dwarf_gpr_r15, ehframe_dwarf_gpr_r15, LLDB_INVALID_REGNUM,
308       LLDB_INVALID_REGNUM, gpr_r15},
309      nullptr,
310      nullptr,
311      nullptr,
312      0},
313     {DEFINE_GPR(rip, "pc"),
314      {ehframe_dwarf_gpr_rip, ehframe_dwarf_gpr_rip, LLDB_REGNUM_GENERIC_PC,
315       LLDB_INVALID_REGNUM, gpr_rip},
316      nullptr,
317      nullptr,
318      nullptr,
319      0},
320     {DEFINE_GPR(rflags, "flags"),
321      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_REGNUM_GENERIC_FLAGS,
322       LLDB_INVALID_REGNUM, gpr_rflags},
323      nullptr,
324      nullptr,
325      nullptr,
326      0},
327     {DEFINE_GPR(cs, NULL),
328      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
329       LLDB_INVALID_REGNUM, gpr_cs},
330      nullptr,
331      nullptr,
332      nullptr,
333      0},
334     {DEFINE_GPR(fs, NULL),
335      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
336       LLDB_INVALID_REGNUM, gpr_fs},
337      nullptr,
338      nullptr,
339      nullptr,
340      0},
341     {DEFINE_GPR(gs, NULL),
342      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
343       LLDB_INVALID_REGNUM, gpr_gs},
344      nullptr,
345      nullptr,
346      nullptr,
347      0},
348 
349     {DEFINE_FPU_UINT(fcw),
350      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
351       LLDB_INVALID_REGNUM, fpu_fcw},
352      nullptr,
353      nullptr,
354      nullptr,
355      0},
356     {DEFINE_FPU_UINT(fsw),
357      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
358       LLDB_INVALID_REGNUM, fpu_fsw},
359      nullptr,
360      nullptr,
361      nullptr,
362      0},
363     {DEFINE_FPU_UINT(ftw),
364      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
365       LLDB_INVALID_REGNUM, fpu_ftw},
366      nullptr,
367      nullptr,
368      nullptr,
369      0},
370     {DEFINE_FPU_UINT(fop),
371      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
372       LLDB_INVALID_REGNUM, fpu_fop},
373      nullptr,
374      nullptr,
375      nullptr,
376      0},
377     {DEFINE_FPU_UINT(ip),
378      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
379       LLDB_INVALID_REGNUM, fpu_ip},
380      nullptr,
381      nullptr,
382      nullptr,
383      0},
384     {DEFINE_FPU_UINT(cs),
385      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
386       LLDB_INVALID_REGNUM, fpu_cs},
387      nullptr,
388      nullptr,
389      nullptr,
390      0},
391     {DEFINE_FPU_UINT(dp),
392      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
393       LLDB_INVALID_REGNUM, fpu_dp},
394      nullptr,
395      nullptr,
396      nullptr,
397      0},
398     {DEFINE_FPU_UINT(ds),
399      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
400       LLDB_INVALID_REGNUM, fpu_ds},
401      nullptr,
402      nullptr,
403      nullptr,
404      0},
405     {DEFINE_FPU_UINT(mxcsr),
406      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
407       LLDB_INVALID_REGNUM, fpu_mxcsr},
408      nullptr,
409      nullptr,
410      nullptr,
411      0},
412     {DEFINE_FPU_UINT(mxcsrmask),
413      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
414       LLDB_INVALID_REGNUM, fpu_mxcsrmask},
415      nullptr,
416      nullptr,
417      nullptr,
418      0},
419     {DEFINE_FPU_VECT(stmm, 0)},
420     {DEFINE_FPU_VECT(stmm, 1)},
421     {DEFINE_FPU_VECT(stmm, 2)},
422     {DEFINE_FPU_VECT(stmm, 3)},
423     {DEFINE_FPU_VECT(stmm, 4)},
424     {DEFINE_FPU_VECT(stmm, 5)},
425     {DEFINE_FPU_VECT(stmm, 6)},
426     {DEFINE_FPU_VECT(stmm, 7)},
427     {DEFINE_FPU_VECT(xmm, 0)},
428     {DEFINE_FPU_VECT(xmm, 1)},
429     {DEFINE_FPU_VECT(xmm, 2)},
430     {DEFINE_FPU_VECT(xmm, 3)},
431     {DEFINE_FPU_VECT(xmm, 4)},
432     {DEFINE_FPU_VECT(xmm, 5)},
433     {DEFINE_FPU_VECT(xmm, 6)},
434     {DEFINE_FPU_VECT(xmm, 7)},
435     {DEFINE_FPU_VECT(xmm, 8)},
436     {DEFINE_FPU_VECT(xmm, 9)},
437     {DEFINE_FPU_VECT(xmm, 10)},
438     {DEFINE_FPU_VECT(xmm, 11)},
439     {DEFINE_FPU_VECT(xmm, 12)},
440     {DEFINE_FPU_VECT(xmm, 13)},
441     {DEFINE_FPU_VECT(xmm, 14)},
442     {DEFINE_FPU_VECT(xmm, 15)},
443 
444     {DEFINE_EXC(trapno),
445      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
446       LLDB_INVALID_REGNUM, exc_trapno},
447      nullptr,
448      nullptr,
449      nullptr,
450      0},
451     {DEFINE_EXC(err),
452      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
453       LLDB_INVALID_REGNUM, exc_err},
454      nullptr,
455      nullptr,
456      nullptr,
457      0},
458     {DEFINE_EXC(faultvaddr),
459      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
460       LLDB_INVALID_REGNUM, exc_faultvaddr},
461      nullptr,
462      nullptr,
463      nullptr,
464      0}};
465 
466 static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos);
467 
468 RegisterContextDarwin_x86_64::RegisterContextDarwin_x86_64(
469     Thread &thread, uint32_t concrete_frame_idx)
470     : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() {
471   uint32_t i;
472   for (i = 0; i < kNumErrors; i++) {
473     gpr_errs[i] = -1;
474     fpu_errs[i] = -1;
475     exc_errs[i] = -1;
476   }
477 }
478 
479 RegisterContextDarwin_x86_64::~RegisterContextDarwin_x86_64() {}
480 
481 void RegisterContextDarwin_x86_64::InvalidateAllRegisters() {
482   InvalidateAllRegisterStates();
483 }
484 
485 size_t RegisterContextDarwin_x86_64::GetRegisterCount() {
486   assert(k_num_register_infos == k_num_registers);
487   return k_num_registers;
488 }
489 
490 const RegisterInfo *
491 RegisterContextDarwin_x86_64::GetRegisterInfoAtIndex(size_t reg) {
492   assert(k_num_register_infos == k_num_registers);
493   if (reg < k_num_registers)
494     return &g_register_infos[reg];
495   return NULL;
496 }
497 
498 size_t RegisterContextDarwin_x86_64::GetRegisterInfosCount() {
499   return k_num_register_infos;
500 }
501 
502 const lldb_private::RegisterInfo *
503 RegisterContextDarwin_x86_64::GetRegisterInfos() {
504   return g_register_infos;
505 }
506 
507 static uint32_t g_gpr_regnums[] = {
508     gpr_rax, gpr_rbx, gpr_rcx, gpr_rdx,    gpr_rdi, gpr_rsi, gpr_rbp,
509     gpr_rsp, gpr_r8,  gpr_r9,  gpr_r10,    gpr_r11, gpr_r12, gpr_r13,
510     gpr_r14, gpr_r15, gpr_rip, gpr_rflags, gpr_cs,  gpr_fs,  gpr_gs};
511 
512 static uint32_t g_fpu_regnums[] = {
513     fpu_fcw,   fpu_fsw,   fpu_ftw,   fpu_fop,       fpu_ip,    fpu_cs,
514     fpu_dp,    fpu_ds,    fpu_mxcsr, fpu_mxcsrmask, fpu_stmm0, fpu_stmm1,
515     fpu_stmm2, fpu_stmm3, fpu_stmm4, fpu_stmm5,     fpu_stmm6, fpu_stmm7,
516     fpu_xmm0,  fpu_xmm1,  fpu_xmm2,  fpu_xmm3,      fpu_xmm4,  fpu_xmm5,
517     fpu_xmm6,  fpu_xmm7,  fpu_xmm8,  fpu_xmm9,      fpu_xmm10, fpu_xmm11,
518     fpu_xmm12, fpu_xmm13, fpu_xmm14, fpu_xmm15};
519 
520 static uint32_t g_exc_regnums[] = {exc_trapno, exc_err, exc_faultvaddr};
521 
522 // Number of registers in each register set
523 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums);
524 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums);
525 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums);
526 
527 //----------------------------------------------------------------------
528 // Register set definitions. The first definitions at register set index
529 // of zero is for all registers, followed by other registers sets. The
530 // register information for the all register set need not be filled in.
531 //----------------------------------------------------------------------
532 static const RegisterSet g_reg_sets[] = {
533     {
534         "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums,
535     },
536     {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums},
537     {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}};
538 
539 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets);
540 
541 size_t RegisterContextDarwin_x86_64::GetRegisterSetCount() {
542   return k_num_regsets;
543 }
544 
545 const RegisterSet *
546 RegisterContextDarwin_x86_64::GetRegisterSet(size_t reg_set) {
547   if (reg_set < k_num_regsets)
548     return &g_reg_sets[reg_set];
549   return NULL;
550 }
551 
552 int RegisterContextDarwin_x86_64::GetSetForNativeRegNum(int reg_num) {
553   if (reg_num < fpu_fcw)
554     return GPRRegSet;
555   else if (reg_num < exc_trapno)
556     return FPURegSet;
557   else if (reg_num < k_num_registers)
558     return EXCRegSet;
559   return -1;
560 }
561 
562 void RegisterContextDarwin_x86_64::LogGPR(Log *log, const char *format, ...) {
563   if (log) {
564     if (format) {
565       va_list args;
566       va_start(args, format);
567       log->VAPrintf(format, args);
568       va_end(args);
569     }
570     for (uint32_t i = 0; i < k_num_gpr_registers; i++) {
571       uint32_t reg = gpr_rax + i;
572       log->Printf("%12s = 0x%16.16" PRIx64, g_register_infos[reg].name,
573                   (&gpr.rax)[reg]);
574     }
575   }
576 }
577 
578 int RegisterContextDarwin_x86_64::ReadGPR(bool force) {
579   int set = GPRRegSet;
580   if (force || !RegisterSetIsCached(set)) {
581     SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
582   }
583   return GetError(GPRRegSet, Read);
584 }
585 
586 int RegisterContextDarwin_x86_64::ReadFPU(bool force) {
587   int set = FPURegSet;
588   if (force || !RegisterSetIsCached(set)) {
589     SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
590   }
591   return GetError(FPURegSet, Read);
592 }
593 
594 int RegisterContextDarwin_x86_64::ReadEXC(bool force) {
595   int set = EXCRegSet;
596   if (force || !RegisterSetIsCached(set)) {
597     SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
598   }
599   return GetError(EXCRegSet, Read);
600 }
601 
602 int RegisterContextDarwin_x86_64::WriteGPR() {
603   int set = GPRRegSet;
604   if (!RegisterSetIsCached(set)) {
605     SetError(set, Write, -1);
606     return -1;
607   }
608   SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
609   SetError(set, Read, -1);
610   return GetError(set, Write);
611 }
612 
613 int RegisterContextDarwin_x86_64::WriteFPU() {
614   int set = FPURegSet;
615   if (!RegisterSetIsCached(set)) {
616     SetError(set, Write, -1);
617     return -1;
618   }
619   SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu));
620   SetError(set, Read, -1);
621   return GetError(set, Write);
622 }
623 
624 int RegisterContextDarwin_x86_64::WriteEXC() {
625   int set = EXCRegSet;
626   if (!RegisterSetIsCached(set)) {
627     SetError(set, Write, -1);
628     return -1;
629   }
630   SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
631   SetError(set, Read, -1);
632   return GetError(set, Write);
633 }
634 
635 int RegisterContextDarwin_x86_64::ReadRegisterSet(uint32_t set, bool force) {
636   switch (set) {
637   case GPRRegSet:
638     return ReadGPR(force);
639   case FPURegSet:
640     return ReadFPU(force);
641   case EXCRegSet:
642     return ReadEXC(force);
643   default:
644     break;
645   }
646   return -1;
647 }
648 
649 int RegisterContextDarwin_x86_64::WriteRegisterSet(uint32_t set) {
650   // Make sure we have a valid context to set.
651   switch (set) {
652   case GPRRegSet:
653     return WriteGPR();
654   case FPURegSet:
655     return WriteFPU();
656   case EXCRegSet:
657     return WriteEXC();
658   default:
659     break;
660   }
661   return -1;
662 }
663 
664 bool RegisterContextDarwin_x86_64::ReadRegister(const RegisterInfo *reg_info,
665                                                 RegisterValue &value) {
666   const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
667   int set = RegisterContextDarwin_x86_64::GetSetForNativeRegNum(reg);
668   if (set == -1)
669     return false;
670 
671   if (ReadRegisterSet(set, false) != 0)
672     return false;
673 
674   switch (reg) {
675   case gpr_rax:
676   case gpr_rbx:
677   case gpr_rcx:
678   case gpr_rdx:
679   case gpr_rdi:
680   case gpr_rsi:
681   case gpr_rbp:
682   case gpr_rsp:
683   case gpr_r8:
684   case gpr_r9:
685   case gpr_r10:
686   case gpr_r11:
687   case gpr_r12:
688   case gpr_r13:
689   case gpr_r14:
690   case gpr_r15:
691   case gpr_rip:
692   case gpr_rflags:
693   case gpr_cs:
694   case gpr_fs:
695   case gpr_gs:
696     value = (&gpr.rax)[reg - gpr_rax];
697     break;
698 
699   case fpu_fcw:
700     value = fpu.fcw;
701     break;
702 
703   case fpu_fsw:
704     value = fpu.fsw;
705     break;
706 
707   case fpu_ftw:
708     value = fpu.ftw;
709     break;
710 
711   case fpu_fop:
712     value = fpu.fop;
713     break;
714 
715   case fpu_ip:
716     value = fpu.ip;
717     break;
718 
719   case fpu_cs:
720     value = fpu.cs;
721     break;
722 
723   case fpu_dp:
724     value = fpu.dp;
725     break;
726 
727   case fpu_ds:
728     value = fpu.ds;
729     break;
730 
731   case fpu_mxcsr:
732     value = fpu.mxcsr;
733     break;
734 
735   case fpu_mxcsrmask:
736     value = fpu.mxcsrmask;
737     break;
738 
739   case fpu_stmm0:
740   case fpu_stmm1:
741   case fpu_stmm2:
742   case fpu_stmm3:
743   case fpu_stmm4:
744   case fpu_stmm5:
745   case fpu_stmm6:
746   case fpu_stmm7:
747     value.SetBytes(fpu.stmm[reg - fpu_stmm0].bytes, reg_info->byte_size,
748                    endian::InlHostByteOrder());
749     break;
750 
751   case fpu_xmm0:
752   case fpu_xmm1:
753   case fpu_xmm2:
754   case fpu_xmm3:
755   case fpu_xmm4:
756   case fpu_xmm5:
757   case fpu_xmm6:
758   case fpu_xmm7:
759   case fpu_xmm8:
760   case fpu_xmm9:
761   case fpu_xmm10:
762   case fpu_xmm11:
763   case fpu_xmm12:
764   case fpu_xmm13:
765   case fpu_xmm14:
766   case fpu_xmm15:
767     value.SetBytes(fpu.xmm[reg - fpu_xmm0].bytes, reg_info->byte_size,
768                    endian::InlHostByteOrder());
769     break;
770 
771   case exc_trapno:
772     value = exc.trapno;
773     break;
774 
775   case exc_err:
776     value = exc.err;
777     break;
778 
779   case exc_faultvaddr:
780     value = exc.faultvaddr;
781     break;
782 
783   default:
784     return false;
785   }
786   return true;
787 }
788 
789 bool RegisterContextDarwin_x86_64::WriteRegister(const RegisterInfo *reg_info,
790                                                  const RegisterValue &value) {
791   const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
792   int set = RegisterContextDarwin_x86_64::GetSetForNativeRegNum(reg);
793 
794   if (set == -1)
795     return false;
796 
797   if (ReadRegisterSet(set, false) != 0)
798     return false;
799 
800   switch (reg) {
801   case gpr_rax:
802   case gpr_rbx:
803   case gpr_rcx:
804   case gpr_rdx:
805   case gpr_rdi:
806   case gpr_rsi:
807   case gpr_rbp:
808   case gpr_rsp:
809   case gpr_r8:
810   case gpr_r9:
811   case gpr_r10:
812   case gpr_r11:
813   case gpr_r12:
814   case gpr_r13:
815   case gpr_r14:
816   case gpr_r15:
817   case gpr_rip:
818   case gpr_rflags:
819   case gpr_cs:
820   case gpr_fs:
821   case gpr_gs:
822     (&gpr.rax)[reg - gpr_rax] = value.GetAsUInt64();
823     break;
824 
825   case fpu_fcw:
826     fpu.fcw = value.GetAsUInt16();
827     break;
828 
829   case fpu_fsw:
830     fpu.fsw = value.GetAsUInt16();
831     break;
832 
833   case fpu_ftw:
834     fpu.ftw = value.GetAsUInt8();
835     break;
836 
837   case fpu_fop:
838     fpu.fop = value.GetAsUInt16();
839     break;
840 
841   case fpu_ip:
842     fpu.ip = value.GetAsUInt32();
843     break;
844 
845   case fpu_cs:
846     fpu.cs = value.GetAsUInt16();
847     break;
848 
849   case fpu_dp:
850     fpu.dp = value.GetAsUInt32();
851     break;
852 
853   case fpu_ds:
854     fpu.ds = value.GetAsUInt16();
855     break;
856 
857   case fpu_mxcsr:
858     fpu.mxcsr = value.GetAsUInt32();
859     break;
860 
861   case fpu_mxcsrmask:
862     fpu.mxcsrmask = value.GetAsUInt32();
863     break;
864 
865   case fpu_stmm0:
866   case fpu_stmm1:
867   case fpu_stmm2:
868   case fpu_stmm3:
869   case fpu_stmm4:
870   case fpu_stmm5:
871   case fpu_stmm6:
872   case fpu_stmm7:
873     ::memcpy(fpu.stmm[reg - fpu_stmm0].bytes, value.GetBytes(),
874              value.GetByteSize());
875     break;
876 
877   case fpu_xmm0:
878   case fpu_xmm1:
879   case fpu_xmm2:
880   case fpu_xmm3:
881   case fpu_xmm4:
882   case fpu_xmm5:
883   case fpu_xmm6:
884   case fpu_xmm7:
885   case fpu_xmm8:
886   case fpu_xmm9:
887   case fpu_xmm10:
888   case fpu_xmm11:
889   case fpu_xmm12:
890   case fpu_xmm13:
891   case fpu_xmm14:
892   case fpu_xmm15:
893     ::memcpy(fpu.xmm[reg - fpu_xmm0].bytes, value.GetBytes(),
894              value.GetByteSize());
895     return false;
896 
897   case exc_trapno:
898     exc.trapno = value.GetAsUInt32();
899     break;
900 
901   case exc_err:
902     exc.err = value.GetAsUInt32();
903     break;
904 
905   case exc_faultvaddr:
906     exc.faultvaddr = value.GetAsUInt64();
907     break;
908 
909   default:
910     return false;
911   }
912   return WriteRegisterSet(set) == 0;
913 }
914 
915 bool RegisterContextDarwin_x86_64::ReadAllRegisterValues(
916     lldb::DataBufferSP &data_sp) {
917   data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0));
918   if (data_sp && ReadGPR(false) == 0 && ReadFPU(false) == 0 &&
919       ReadEXC(false) == 0) {
920     uint8_t *dst = data_sp->GetBytes();
921     ::memcpy(dst, &gpr, sizeof(gpr));
922     dst += sizeof(gpr);
923 
924     ::memcpy(dst, &fpu, sizeof(fpu));
925     dst += sizeof(gpr);
926 
927     ::memcpy(dst, &exc, sizeof(exc));
928     return true;
929   }
930   return false;
931 }
932 
933 bool RegisterContextDarwin_x86_64::WriteAllRegisterValues(
934     const lldb::DataBufferSP &data_sp) {
935   if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
936     const uint8_t *src = data_sp->GetBytes();
937     ::memcpy(&gpr, src, sizeof(gpr));
938     src += sizeof(gpr);
939 
940     ::memcpy(&fpu, src, sizeof(fpu));
941     src += sizeof(gpr);
942 
943     ::memcpy(&exc, src, sizeof(exc));
944     uint32_t success_count = 0;
945     if (WriteGPR() == 0)
946       ++success_count;
947     if (WriteFPU() == 0)
948       ++success_count;
949     if (WriteEXC() == 0)
950       ++success_count;
951     return success_count == 3;
952   }
953   return false;
954 }
955 
956 uint32_t RegisterContextDarwin_x86_64::ConvertRegisterKindToRegisterNumber(
957     lldb::RegisterKind kind, uint32_t reg) {
958   if (kind == eRegisterKindGeneric) {
959     switch (reg) {
960     case LLDB_REGNUM_GENERIC_PC:
961       return gpr_rip;
962     case LLDB_REGNUM_GENERIC_SP:
963       return gpr_rsp;
964     case LLDB_REGNUM_GENERIC_FP:
965       return gpr_rbp;
966     case LLDB_REGNUM_GENERIC_FLAGS:
967       return gpr_rflags;
968     case LLDB_REGNUM_GENERIC_RA:
969     default:
970       break;
971     }
972   } else if (kind == eRegisterKindEHFrame || kind == eRegisterKindDWARF) {
973     switch (reg) {
974     case ehframe_dwarf_gpr_rax:
975       return gpr_rax;
976     case ehframe_dwarf_gpr_rdx:
977       return gpr_rdx;
978     case ehframe_dwarf_gpr_rcx:
979       return gpr_rcx;
980     case ehframe_dwarf_gpr_rbx:
981       return gpr_rbx;
982     case ehframe_dwarf_gpr_rsi:
983       return gpr_rsi;
984     case ehframe_dwarf_gpr_rdi:
985       return gpr_rdi;
986     case ehframe_dwarf_gpr_rbp:
987       return gpr_rbp;
988     case ehframe_dwarf_gpr_rsp:
989       return gpr_rsp;
990     case ehframe_dwarf_gpr_r8:
991       return gpr_r8;
992     case ehframe_dwarf_gpr_r9:
993       return gpr_r9;
994     case ehframe_dwarf_gpr_r10:
995       return gpr_r10;
996     case ehframe_dwarf_gpr_r11:
997       return gpr_r11;
998     case ehframe_dwarf_gpr_r12:
999       return gpr_r12;
1000     case ehframe_dwarf_gpr_r13:
1001       return gpr_r13;
1002     case ehframe_dwarf_gpr_r14:
1003       return gpr_r14;
1004     case ehframe_dwarf_gpr_r15:
1005       return gpr_r15;
1006     case ehframe_dwarf_gpr_rip:
1007       return gpr_rip;
1008     case ehframe_dwarf_fpu_xmm0:
1009       return fpu_xmm0;
1010     case ehframe_dwarf_fpu_xmm1:
1011       return fpu_xmm1;
1012     case ehframe_dwarf_fpu_xmm2:
1013       return fpu_xmm2;
1014     case ehframe_dwarf_fpu_xmm3:
1015       return fpu_xmm3;
1016     case ehframe_dwarf_fpu_xmm4:
1017       return fpu_xmm4;
1018     case ehframe_dwarf_fpu_xmm5:
1019       return fpu_xmm5;
1020     case ehframe_dwarf_fpu_xmm6:
1021       return fpu_xmm6;
1022     case ehframe_dwarf_fpu_xmm7:
1023       return fpu_xmm7;
1024     case ehframe_dwarf_fpu_xmm8:
1025       return fpu_xmm8;
1026     case ehframe_dwarf_fpu_xmm9:
1027       return fpu_xmm9;
1028     case ehframe_dwarf_fpu_xmm10:
1029       return fpu_xmm10;
1030     case ehframe_dwarf_fpu_xmm11:
1031       return fpu_xmm11;
1032     case ehframe_dwarf_fpu_xmm12:
1033       return fpu_xmm12;
1034     case ehframe_dwarf_fpu_xmm13:
1035       return fpu_xmm13;
1036     case ehframe_dwarf_fpu_xmm14:
1037       return fpu_xmm14;
1038     case ehframe_dwarf_fpu_xmm15:
1039       return fpu_xmm15;
1040     case ehframe_dwarf_fpu_stmm0:
1041       return fpu_stmm0;
1042     case ehframe_dwarf_fpu_stmm1:
1043       return fpu_stmm1;
1044     case ehframe_dwarf_fpu_stmm2:
1045       return fpu_stmm2;
1046     case ehframe_dwarf_fpu_stmm3:
1047       return fpu_stmm3;
1048     case ehframe_dwarf_fpu_stmm4:
1049       return fpu_stmm4;
1050     case ehframe_dwarf_fpu_stmm5:
1051       return fpu_stmm5;
1052     case ehframe_dwarf_fpu_stmm6:
1053       return fpu_stmm6;
1054     case ehframe_dwarf_fpu_stmm7:
1055       return fpu_stmm7;
1056     default:
1057       break;
1058     }
1059   } else if (kind == eRegisterKindLLDB) {
1060     return reg;
1061   }
1062   return LLDB_INVALID_REGNUM;
1063 }
1064 
1065 bool RegisterContextDarwin_x86_64::HardwareSingleStep(bool enable) {
1066   if (ReadGPR(true) != 0)
1067     return false;
1068 
1069   const uint64_t trace_bit = 0x100ull;
1070   if (enable) {
1071 
1072     if (gpr.rflags & trace_bit)
1073       return true; // trace bit is already set, there is nothing to do
1074     else
1075       gpr.rflags |= trace_bit;
1076   } else {
1077     if (gpr.rflags & trace_bit)
1078       gpr.rflags &= ~trace_bit;
1079     else
1080       return true; // trace bit is clear, there is nothing to do
1081   }
1082 
1083   return WriteGPR() == 0;
1084 }
1085