1 //===-- RegisterContextDarwin_arm64.cpp ---------------------------*- C++ 2 //-*-===// 3 // 4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 5 // See https://llvm.org/LICENSE.txt for license information. 6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "RegisterContextDarwin_arm64.h" 11 #include "RegisterContextDarwinConstants.h" 12 13 #include "lldb/Target/Process.h" 14 #include "lldb/Target/Thread.h" 15 #include "lldb/Utility/DataBufferHeap.h" 16 #include "lldb/Utility/DataExtractor.h" 17 #include "lldb/Utility/Endian.h" 18 #include "lldb/Utility/Log.h" 19 #include "lldb/Utility/RegisterValue.h" 20 #include "lldb/Utility/Scalar.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/Support/Compiler.h" 23 24 #include "Plugins/Process/Utility/InstructionUtils.h" 25 26 #include <memory> 27 28 // Support building against older versions of LLVM, this macro was added 29 // recently. 30 #ifndef LLVM_EXTENSION 31 #define LLVM_EXTENSION 32 #endif 33 34 #include "Utility/ARM64_DWARF_Registers.h" 35 36 using namespace lldb; 37 using namespace lldb_private; 38 39 #define GPR_OFFSET(idx) ((idx)*8) 40 #define GPR_OFFSET_NAME(reg) \ 41 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::GPR, reg)) 42 43 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterContextDarwin_arm64::GPR)) 44 #define FPU_OFFSET_NAME(reg) \ 45 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::FPU, reg)) 46 47 #define EXC_OFFSET_NAME(reg) \ 48 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::EXC, reg) + \ 49 sizeof(RegisterContextDarwin_arm64::GPR) + \ 50 sizeof(RegisterContextDarwin_arm64::FPU)) 51 #define DBG_OFFSET_NAME(reg) \ 52 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::DBG, reg) + \ 53 sizeof(RegisterContextDarwin_arm64::GPR) + \ 54 sizeof(RegisterContextDarwin_arm64::FPU) + \ 55 sizeof(RegisterContextDarwin_arm64::EXC)) 56 57 #define DEFINE_DBG(reg, i) \ 58 #reg, NULL, \ 59 sizeof(((RegisterContextDarwin_arm64::DBG *) NULL)->reg[i]), \ 60 DBG_OFFSET_NAME(reg[i]), eEncodingUint, eFormatHex, \ 61 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 62 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 63 LLDB_INVALID_REGNUM }, \ 64 NULL, NULL, NULL, 0 65 #define REG_CONTEXT_SIZE \ 66 (sizeof(RegisterContextDarwin_arm64::GPR) + \ 67 sizeof(RegisterContextDarwin_arm64::FPU) + \ 68 sizeof(RegisterContextDarwin_arm64::EXC)) 69 70 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure. 71 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT 72 #include "RegisterInfos_arm64.h" 73 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT 74 75 // General purpose registers 76 static uint32_t g_gpr_regnums[] = { 77 gpr_x0, gpr_x1, gpr_x2, gpr_x3, gpr_x4, gpr_x5, gpr_x6, 78 gpr_x7, gpr_x8, gpr_x9, gpr_x10, gpr_x11, gpr_x12, gpr_x13, 79 gpr_x14, gpr_x15, gpr_x16, gpr_x17, gpr_x18, gpr_x19, gpr_x20, 80 gpr_x21, gpr_x22, gpr_x23, gpr_x24, gpr_x25, gpr_x26, gpr_x27, 81 gpr_x28, gpr_fp, gpr_lr, gpr_sp, gpr_pc, gpr_cpsr}; 82 83 // Floating point registers 84 static uint32_t g_fpu_regnums[] = { 85 fpu_v0, fpu_v1, fpu_v2, fpu_v3, fpu_v4, fpu_v5, fpu_v6, 86 fpu_v7, fpu_v8, fpu_v9, fpu_v10, fpu_v11, fpu_v12, fpu_v13, 87 fpu_v14, fpu_v15, fpu_v16, fpu_v17, fpu_v18, fpu_v19, fpu_v20, 88 fpu_v21, fpu_v22, fpu_v23, fpu_v24, fpu_v25, fpu_v26, fpu_v27, 89 fpu_v28, fpu_v29, fpu_v30, fpu_v31, fpu_fpsr, fpu_fpcr}; 90 91 // Exception registers 92 93 static uint32_t g_exc_regnums[] = {exc_far, exc_esr, exc_exception}; 94 95 static size_t k_num_register_infos = 96 llvm::array_lengthof(g_register_infos_arm64_le); 97 98 RegisterContextDarwin_arm64::RegisterContextDarwin_arm64( 99 Thread &thread, uint32_t concrete_frame_idx) 100 : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() { 101 uint32_t i; 102 for (i = 0; i < kNumErrors; i++) { 103 gpr_errs[i] = -1; 104 fpu_errs[i] = -1; 105 exc_errs[i] = -1; 106 } 107 } 108 109 RegisterContextDarwin_arm64::~RegisterContextDarwin_arm64() {} 110 111 void RegisterContextDarwin_arm64::InvalidateAllRegisters() { 112 InvalidateAllRegisterStates(); 113 } 114 115 size_t RegisterContextDarwin_arm64::GetRegisterCount() { 116 assert(k_num_register_infos == k_num_registers); 117 return k_num_registers; 118 } 119 120 const RegisterInfo * 121 RegisterContextDarwin_arm64::GetRegisterInfoAtIndex(size_t reg) { 122 assert(k_num_register_infos == k_num_registers); 123 if (reg < k_num_registers) 124 return &g_register_infos_arm64_le[reg]; 125 return nullptr; 126 } 127 128 size_t RegisterContextDarwin_arm64::GetRegisterInfosCount() { 129 return k_num_register_infos; 130 } 131 132 const RegisterInfo *RegisterContextDarwin_arm64::GetRegisterInfos() { 133 return g_register_infos_arm64_le; 134 } 135 136 // Number of registers in each register set 137 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums); 138 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums); 139 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums); 140 141 // Register set definitions. The first definitions at register set index of 142 // zero is for all registers, followed by other registers sets. The register 143 // information for the all register set need not be filled in. 144 static const RegisterSet g_reg_sets[] = { 145 { 146 "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, 147 }, 148 {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums}, 149 {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}}; 150 151 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets); 152 153 size_t RegisterContextDarwin_arm64::GetRegisterSetCount() { 154 return k_num_regsets; 155 } 156 157 const RegisterSet *RegisterContextDarwin_arm64::GetRegisterSet(size_t reg_set) { 158 if (reg_set < k_num_regsets) 159 return &g_reg_sets[reg_set]; 160 return nullptr; 161 } 162 163 // Register information definitions for arm64 164 int RegisterContextDarwin_arm64::GetSetForNativeRegNum(int reg) { 165 if (reg < fpu_v0) 166 return GPRRegSet; 167 else if (reg < exc_far) 168 return FPURegSet; 169 else if (reg < k_num_registers) 170 return EXCRegSet; 171 return -1; 172 } 173 174 int RegisterContextDarwin_arm64::ReadGPR(bool force) { 175 int set = GPRRegSet; 176 if (force || !RegisterSetIsCached(set)) { 177 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr)); 178 } 179 return GetError(GPRRegSet, Read); 180 } 181 182 int RegisterContextDarwin_arm64::ReadFPU(bool force) { 183 int set = FPURegSet; 184 if (force || !RegisterSetIsCached(set)) { 185 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu)); 186 } 187 return GetError(FPURegSet, Read); 188 } 189 190 int RegisterContextDarwin_arm64::ReadEXC(bool force) { 191 int set = EXCRegSet; 192 if (force || !RegisterSetIsCached(set)) { 193 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc)); 194 } 195 return GetError(EXCRegSet, Read); 196 } 197 198 int RegisterContextDarwin_arm64::ReadDBG(bool force) { 199 int set = DBGRegSet; 200 if (force || !RegisterSetIsCached(set)) { 201 SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg)); 202 } 203 return GetError(DBGRegSet, Read); 204 } 205 206 int RegisterContextDarwin_arm64::WriteGPR() { 207 int set = GPRRegSet; 208 if (!RegisterSetIsCached(set)) { 209 SetError(set, Write, -1); 210 return KERN_INVALID_ARGUMENT; 211 } 212 SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr)); 213 SetError(set, Read, -1); 214 return GetError(GPRRegSet, Write); 215 } 216 217 int RegisterContextDarwin_arm64::WriteFPU() { 218 int set = FPURegSet; 219 if (!RegisterSetIsCached(set)) { 220 SetError(set, Write, -1); 221 return KERN_INVALID_ARGUMENT; 222 } 223 SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu)); 224 SetError(set, Read, -1); 225 return GetError(FPURegSet, Write); 226 } 227 228 int RegisterContextDarwin_arm64::WriteEXC() { 229 int set = EXCRegSet; 230 if (!RegisterSetIsCached(set)) { 231 SetError(set, Write, -1); 232 return KERN_INVALID_ARGUMENT; 233 } 234 SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc)); 235 SetError(set, Read, -1); 236 return GetError(EXCRegSet, Write); 237 } 238 239 int RegisterContextDarwin_arm64::WriteDBG() { 240 int set = DBGRegSet; 241 if (!RegisterSetIsCached(set)) { 242 SetError(set, Write, -1); 243 return KERN_INVALID_ARGUMENT; 244 } 245 SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg)); 246 SetError(set, Read, -1); 247 return GetError(DBGRegSet, Write); 248 } 249 250 int RegisterContextDarwin_arm64::ReadRegisterSet(uint32_t set, bool force) { 251 switch (set) { 252 case GPRRegSet: 253 return ReadGPR(force); 254 case FPURegSet: 255 return ReadFPU(force); 256 case EXCRegSet: 257 return ReadEXC(force); 258 case DBGRegSet: 259 return ReadDBG(force); 260 default: 261 break; 262 } 263 return KERN_INVALID_ARGUMENT; 264 } 265 266 int RegisterContextDarwin_arm64::WriteRegisterSet(uint32_t set) { 267 // Make sure we have a valid context to set. 268 if (RegisterSetIsCached(set)) { 269 switch (set) { 270 case GPRRegSet: 271 return WriteGPR(); 272 case FPURegSet: 273 return WriteFPU(); 274 case EXCRegSet: 275 return WriteEXC(); 276 case DBGRegSet: 277 return WriteDBG(); 278 default: 279 break; 280 } 281 } 282 return KERN_INVALID_ARGUMENT; 283 } 284 285 void RegisterContextDarwin_arm64::LogDBGRegisters(Log *log, const DBG &dbg) { 286 if (log) { 287 for (uint32_t i = 0; i < 16; i++) 288 LLDB_LOGF(log, 289 "BVR%-2u/BCR%-2u = { 0x%8.8" PRIu64 ", 0x%8.8" PRIu64 290 " } WVR%-2u/WCR%-2u " 291 "= { 0x%8.8" PRIu64 ", 0x%8.8" PRIu64 " }", 292 i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]); 293 } 294 } 295 296 bool RegisterContextDarwin_arm64::ReadRegister(const RegisterInfo *reg_info, 297 RegisterValue &value) { 298 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 299 int set = RegisterContextDarwin_arm64::GetSetForNativeRegNum(reg); 300 301 if (set == -1) 302 return false; 303 304 if (ReadRegisterSet(set, false) != KERN_SUCCESS) 305 return false; 306 307 switch (reg) { 308 case gpr_x0: 309 case gpr_x1: 310 case gpr_x2: 311 case gpr_x3: 312 case gpr_x4: 313 case gpr_x5: 314 case gpr_x6: 315 case gpr_x7: 316 case gpr_x8: 317 case gpr_x9: 318 case gpr_x10: 319 case gpr_x11: 320 case gpr_x12: 321 case gpr_x13: 322 case gpr_x14: 323 case gpr_x15: 324 case gpr_x16: 325 case gpr_x17: 326 case gpr_x18: 327 case gpr_x19: 328 case gpr_x20: 329 case gpr_x21: 330 case gpr_x22: 331 case gpr_x23: 332 case gpr_x24: 333 case gpr_x25: 334 case gpr_x26: 335 case gpr_x27: 336 case gpr_x28: 337 value.SetUInt64(gpr.x[reg - gpr_x0]); 338 break; 339 case gpr_fp: 340 value.SetUInt64(gpr.fp); 341 break; 342 case gpr_sp: 343 value.SetUInt64(gpr.sp); 344 break; 345 case gpr_lr: 346 value.SetUInt64(gpr.lr); 347 break; 348 case gpr_pc: 349 value.SetUInt64(gpr.pc); 350 break; 351 case gpr_cpsr: 352 value.SetUInt64(gpr.cpsr); 353 break; 354 355 case gpr_w0: 356 case gpr_w1: 357 case gpr_w2: 358 case gpr_w3: 359 case gpr_w4: 360 case gpr_w5: 361 case gpr_w6: 362 case gpr_w7: 363 case gpr_w8: 364 case gpr_w9: 365 case gpr_w10: 366 case gpr_w11: 367 case gpr_w12: 368 case gpr_w13: 369 case gpr_w14: 370 case gpr_w15: 371 case gpr_w16: 372 case gpr_w17: 373 case gpr_w18: 374 case gpr_w19: 375 case gpr_w20: 376 case gpr_w21: 377 case gpr_w22: 378 case gpr_w23: 379 case gpr_w24: 380 case gpr_w25: 381 case gpr_w26: 382 case gpr_w27: 383 case gpr_w28: { 384 ProcessSP process_sp(m_thread.GetProcess()); 385 if (process_sp.get()) { 386 DataExtractor regdata(&gpr.x[reg - gpr_w0], 8, process_sp->GetByteOrder(), 387 process_sp->GetAddressByteSize()); 388 offset_t offset = 0; 389 uint64_t retval = regdata.GetMaxU64(&offset, 8); 390 uint32_t retval_lower32 = static_cast<uint32_t>(retval & 0xffffffff); 391 value.SetUInt32(retval_lower32); 392 } 393 } break; 394 395 case fpu_v0: 396 case fpu_v1: 397 case fpu_v2: 398 case fpu_v3: 399 case fpu_v4: 400 case fpu_v5: 401 case fpu_v6: 402 case fpu_v7: 403 case fpu_v8: 404 case fpu_v9: 405 case fpu_v10: 406 case fpu_v11: 407 case fpu_v12: 408 case fpu_v13: 409 case fpu_v14: 410 case fpu_v15: 411 case fpu_v16: 412 case fpu_v17: 413 case fpu_v18: 414 case fpu_v19: 415 case fpu_v20: 416 case fpu_v21: 417 case fpu_v22: 418 case fpu_v23: 419 case fpu_v24: 420 case fpu_v25: 421 case fpu_v26: 422 case fpu_v27: 423 case fpu_v28: 424 case fpu_v29: 425 case fpu_v30: 426 case fpu_v31: 427 value.SetBytes(fpu.v[reg - fpu_v0].bytes, reg_info->byte_size, 428 endian::InlHostByteOrder()); 429 break; 430 431 case fpu_s0: 432 case fpu_s1: 433 case fpu_s2: 434 case fpu_s3: 435 case fpu_s4: 436 case fpu_s5: 437 case fpu_s6: 438 case fpu_s7: 439 case fpu_s8: 440 case fpu_s9: 441 case fpu_s10: 442 case fpu_s11: 443 case fpu_s12: 444 case fpu_s13: 445 case fpu_s14: 446 case fpu_s15: 447 case fpu_s16: 448 case fpu_s17: 449 case fpu_s18: 450 case fpu_s19: 451 case fpu_s20: 452 case fpu_s21: 453 case fpu_s22: 454 case fpu_s23: 455 case fpu_s24: 456 case fpu_s25: 457 case fpu_s26: 458 case fpu_s27: 459 case fpu_s28: 460 case fpu_s29: 461 case fpu_s30: 462 case fpu_s31: { 463 ProcessSP process_sp(m_thread.GetProcess()); 464 if (process_sp.get()) { 465 DataExtractor regdata(&fpu.v[reg - fpu_s0], 4, process_sp->GetByteOrder(), 466 process_sp->GetAddressByteSize()); 467 offset_t offset = 0; 468 value.SetFloat(regdata.GetFloat(&offset)); 469 } 470 } break; 471 472 case fpu_d0: 473 case fpu_d1: 474 case fpu_d2: 475 case fpu_d3: 476 case fpu_d4: 477 case fpu_d5: 478 case fpu_d6: 479 case fpu_d7: 480 case fpu_d8: 481 case fpu_d9: 482 case fpu_d10: 483 case fpu_d11: 484 case fpu_d12: 485 case fpu_d13: 486 case fpu_d14: 487 case fpu_d15: 488 case fpu_d16: 489 case fpu_d17: 490 case fpu_d18: 491 case fpu_d19: 492 case fpu_d20: 493 case fpu_d21: 494 case fpu_d22: 495 case fpu_d23: 496 case fpu_d24: 497 case fpu_d25: 498 case fpu_d26: 499 case fpu_d27: 500 case fpu_d28: 501 case fpu_d29: 502 case fpu_d30: 503 case fpu_d31: { 504 ProcessSP process_sp(m_thread.GetProcess()); 505 if (process_sp.get()) { 506 DataExtractor regdata(&fpu.v[reg - fpu_s0], 8, process_sp->GetByteOrder(), 507 process_sp->GetAddressByteSize()); 508 offset_t offset = 0; 509 value.SetDouble(regdata.GetDouble(&offset)); 510 } 511 } break; 512 513 case fpu_fpsr: 514 value.SetUInt32(fpu.fpsr); 515 break; 516 517 case fpu_fpcr: 518 value.SetUInt32(fpu.fpcr); 519 break; 520 521 case exc_exception: 522 value.SetUInt32(exc.exception); 523 break; 524 case exc_esr: 525 value.SetUInt32(exc.esr); 526 break; 527 case exc_far: 528 value.SetUInt64(exc.far); 529 break; 530 531 default: 532 value.SetValueToInvalid(); 533 return false; 534 } 535 return true; 536 } 537 538 bool RegisterContextDarwin_arm64::WriteRegister(const RegisterInfo *reg_info, 539 const RegisterValue &value) { 540 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 541 int set = GetSetForNativeRegNum(reg); 542 543 if (set == -1) 544 return false; 545 546 if (ReadRegisterSet(set, false) != KERN_SUCCESS) 547 return false; 548 549 switch (reg) { 550 case gpr_x0: 551 case gpr_x1: 552 case gpr_x2: 553 case gpr_x3: 554 case gpr_x4: 555 case gpr_x5: 556 case gpr_x6: 557 case gpr_x7: 558 case gpr_x8: 559 case gpr_x9: 560 case gpr_x10: 561 case gpr_x11: 562 case gpr_x12: 563 case gpr_x13: 564 case gpr_x14: 565 case gpr_x15: 566 case gpr_x16: 567 case gpr_x17: 568 case gpr_x18: 569 case gpr_x19: 570 case gpr_x20: 571 case gpr_x21: 572 case gpr_x22: 573 case gpr_x23: 574 case gpr_x24: 575 case gpr_x25: 576 case gpr_x26: 577 case gpr_x27: 578 case gpr_x28: 579 case gpr_fp: 580 case gpr_sp: 581 case gpr_lr: 582 case gpr_pc: 583 case gpr_cpsr: 584 gpr.x[reg - gpr_x0] = value.GetAsUInt64(); 585 break; 586 587 case fpu_v0: 588 case fpu_v1: 589 case fpu_v2: 590 case fpu_v3: 591 case fpu_v4: 592 case fpu_v5: 593 case fpu_v6: 594 case fpu_v7: 595 case fpu_v8: 596 case fpu_v9: 597 case fpu_v10: 598 case fpu_v11: 599 case fpu_v12: 600 case fpu_v13: 601 case fpu_v14: 602 case fpu_v15: 603 case fpu_v16: 604 case fpu_v17: 605 case fpu_v18: 606 case fpu_v19: 607 case fpu_v20: 608 case fpu_v21: 609 case fpu_v22: 610 case fpu_v23: 611 case fpu_v24: 612 case fpu_v25: 613 case fpu_v26: 614 case fpu_v27: 615 case fpu_v28: 616 case fpu_v29: 617 case fpu_v30: 618 case fpu_v31: 619 ::memcpy(fpu.v[reg - fpu_v0].bytes, value.GetBytes(), 620 value.GetByteSize()); 621 break; 622 623 case fpu_fpsr: 624 fpu.fpsr = value.GetAsUInt32(); 625 break; 626 627 case fpu_fpcr: 628 fpu.fpcr = value.GetAsUInt32(); 629 break; 630 631 case exc_exception: 632 exc.exception = value.GetAsUInt32(); 633 break; 634 case exc_esr: 635 exc.esr = value.GetAsUInt32(); 636 break; 637 case exc_far: 638 exc.far = value.GetAsUInt64(); 639 break; 640 641 default: 642 return false; 643 } 644 return WriteRegisterSet(set) == KERN_SUCCESS; 645 } 646 647 bool RegisterContextDarwin_arm64::ReadAllRegisterValues( 648 lldb::DataBufferSP &data_sp) { 649 data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0); 650 if (ReadGPR(false) == KERN_SUCCESS && ReadFPU(false) == KERN_SUCCESS && 651 ReadEXC(false) == KERN_SUCCESS) { 652 uint8_t *dst = data_sp->GetBytes(); 653 ::memcpy(dst, &gpr, sizeof(gpr)); 654 dst += sizeof(gpr); 655 656 ::memcpy(dst, &fpu, sizeof(fpu)); 657 dst += sizeof(gpr); 658 659 ::memcpy(dst, &exc, sizeof(exc)); 660 return true; 661 } 662 return false; 663 } 664 665 bool RegisterContextDarwin_arm64::WriteAllRegisterValues( 666 const lldb::DataBufferSP &data_sp) { 667 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) { 668 const uint8_t *src = data_sp->GetBytes(); 669 ::memcpy(&gpr, src, sizeof(gpr)); 670 src += sizeof(gpr); 671 672 ::memcpy(&fpu, src, sizeof(fpu)); 673 src += sizeof(gpr); 674 675 ::memcpy(&exc, src, sizeof(exc)); 676 uint32_t success_count = 0; 677 if (WriteGPR() == KERN_SUCCESS) 678 ++success_count; 679 if (WriteFPU() == KERN_SUCCESS) 680 ++success_count; 681 if (WriteEXC() == KERN_SUCCESS) 682 ++success_count; 683 return success_count == 3; 684 } 685 return false; 686 } 687 688 uint32_t RegisterContextDarwin_arm64::ConvertRegisterKindToRegisterNumber( 689 RegisterKind kind, uint32_t reg) { 690 if (kind == eRegisterKindGeneric) { 691 switch (reg) { 692 case LLDB_REGNUM_GENERIC_PC: 693 return gpr_pc; 694 case LLDB_REGNUM_GENERIC_SP: 695 return gpr_sp; 696 case LLDB_REGNUM_GENERIC_FP: 697 return gpr_fp; 698 case LLDB_REGNUM_GENERIC_RA: 699 return gpr_lr; 700 case LLDB_REGNUM_GENERIC_FLAGS: 701 return gpr_cpsr; 702 default: 703 break; 704 } 705 } else if (kind == eRegisterKindDWARF) { 706 switch (reg) { 707 case arm64_dwarf::x0: 708 return gpr_x0; 709 case arm64_dwarf::x1: 710 return gpr_x1; 711 case arm64_dwarf::x2: 712 return gpr_x2; 713 case arm64_dwarf::x3: 714 return gpr_x3; 715 case arm64_dwarf::x4: 716 return gpr_x4; 717 case arm64_dwarf::x5: 718 return gpr_x5; 719 case arm64_dwarf::x6: 720 return gpr_x6; 721 case arm64_dwarf::x7: 722 return gpr_x7; 723 case arm64_dwarf::x8: 724 return gpr_x8; 725 case arm64_dwarf::x9: 726 return gpr_x9; 727 case arm64_dwarf::x10: 728 return gpr_x10; 729 case arm64_dwarf::x11: 730 return gpr_x11; 731 case arm64_dwarf::x12: 732 return gpr_x12; 733 case arm64_dwarf::x13: 734 return gpr_x13; 735 case arm64_dwarf::x14: 736 return gpr_x14; 737 case arm64_dwarf::x15: 738 return gpr_x15; 739 case arm64_dwarf::x16: 740 return gpr_x16; 741 case arm64_dwarf::x17: 742 return gpr_x17; 743 case arm64_dwarf::x18: 744 return gpr_x18; 745 case arm64_dwarf::x19: 746 return gpr_x19; 747 case arm64_dwarf::x20: 748 return gpr_x20; 749 case arm64_dwarf::x21: 750 return gpr_x21; 751 case arm64_dwarf::x22: 752 return gpr_x22; 753 case arm64_dwarf::x23: 754 return gpr_x23; 755 case arm64_dwarf::x24: 756 return gpr_x24; 757 case arm64_dwarf::x25: 758 return gpr_x25; 759 case arm64_dwarf::x26: 760 return gpr_x26; 761 case arm64_dwarf::x27: 762 return gpr_x27; 763 case arm64_dwarf::x28: 764 return gpr_x28; 765 766 case arm64_dwarf::fp: 767 return gpr_fp; 768 case arm64_dwarf::sp: 769 return gpr_sp; 770 case arm64_dwarf::lr: 771 return gpr_lr; 772 case arm64_dwarf::pc: 773 return gpr_pc; 774 case arm64_dwarf::cpsr: 775 return gpr_cpsr; 776 777 case arm64_dwarf::v0: 778 return fpu_v0; 779 case arm64_dwarf::v1: 780 return fpu_v1; 781 case arm64_dwarf::v2: 782 return fpu_v2; 783 case arm64_dwarf::v3: 784 return fpu_v3; 785 case arm64_dwarf::v4: 786 return fpu_v4; 787 case arm64_dwarf::v5: 788 return fpu_v5; 789 case arm64_dwarf::v6: 790 return fpu_v6; 791 case arm64_dwarf::v7: 792 return fpu_v7; 793 case arm64_dwarf::v8: 794 return fpu_v8; 795 case arm64_dwarf::v9: 796 return fpu_v9; 797 case arm64_dwarf::v10: 798 return fpu_v10; 799 case arm64_dwarf::v11: 800 return fpu_v11; 801 case arm64_dwarf::v12: 802 return fpu_v12; 803 case arm64_dwarf::v13: 804 return fpu_v13; 805 case arm64_dwarf::v14: 806 return fpu_v14; 807 case arm64_dwarf::v15: 808 return fpu_v15; 809 case arm64_dwarf::v16: 810 return fpu_v16; 811 case arm64_dwarf::v17: 812 return fpu_v17; 813 case arm64_dwarf::v18: 814 return fpu_v18; 815 case arm64_dwarf::v19: 816 return fpu_v19; 817 case arm64_dwarf::v20: 818 return fpu_v20; 819 case arm64_dwarf::v21: 820 return fpu_v21; 821 case arm64_dwarf::v22: 822 return fpu_v22; 823 case arm64_dwarf::v23: 824 return fpu_v23; 825 case arm64_dwarf::v24: 826 return fpu_v24; 827 case arm64_dwarf::v25: 828 return fpu_v25; 829 case arm64_dwarf::v26: 830 return fpu_v26; 831 case arm64_dwarf::v27: 832 return fpu_v27; 833 case arm64_dwarf::v28: 834 return fpu_v28; 835 case arm64_dwarf::v29: 836 return fpu_v29; 837 case arm64_dwarf::v30: 838 return fpu_v30; 839 case arm64_dwarf::v31: 840 return fpu_v31; 841 842 default: 843 break; 844 } 845 } else if (kind == eRegisterKindEHFrame) { 846 switch (reg) { 847 case arm64_ehframe::x0: 848 return gpr_x0; 849 case arm64_ehframe::x1: 850 return gpr_x1; 851 case arm64_ehframe::x2: 852 return gpr_x2; 853 case arm64_ehframe::x3: 854 return gpr_x3; 855 case arm64_ehframe::x4: 856 return gpr_x4; 857 case arm64_ehframe::x5: 858 return gpr_x5; 859 case arm64_ehframe::x6: 860 return gpr_x6; 861 case arm64_ehframe::x7: 862 return gpr_x7; 863 case arm64_ehframe::x8: 864 return gpr_x8; 865 case arm64_ehframe::x9: 866 return gpr_x9; 867 case arm64_ehframe::x10: 868 return gpr_x10; 869 case arm64_ehframe::x11: 870 return gpr_x11; 871 case arm64_ehframe::x12: 872 return gpr_x12; 873 case arm64_ehframe::x13: 874 return gpr_x13; 875 case arm64_ehframe::x14: 876 return gpr_x14; 877 case arm64_ehframe::x15: 878 return gpr_x15; 879 case arm64_ehframe::x16: 880 return gpr_x16; 881 case arm64_ehframe::x17: 882 return gpr_x17; 883 case arm64_ehframe::x18: 884 return gpr_x18; 885 case arm64_ehframe::x19: 886 return gpr_x19; 887 case arm64_ehframe::x20: 888 return gpr_x20; 889 case arm64_ehframe::x21: 890 return gpr_x21; 891 case arm64_ehframe::x22: 892 return gpr_x22; 893 case arm64_ehframe::x23: 894 return gpr_x23; 895 case arm64_ehframe::x24: 896 return gpr_x24; 897 case arm64_ehframe::x25: 898 return gpr_x25; 899 case arm64_ehframe::x26: 900 return gpr_x26; 901 case arm64_ehframe::x27: 902 return gpr_x27; 903 case arm64_ehframe::x28: 904 return gpr_x28; 905 case arm64_ehframe::fp: 906 return gpr_fp; 907 case arm64_ehframe::sp: 908 return gpr_sp; 909 case arm64_ehframe::lr: 910 return gpr_lr; 911 case arm64_ehframe::pc: 912 return gpr_pc; 913 case arm64_ehframe::cpsr: 914 return gpr_cpsr; 915 } 916 } else if (kind == eRegisterKindLLDB) { 917 return reg; 918 } 919 return LLDB_INVALID_REGNUM; 920 } 921 922 uint32_t RegisterContextDarwin_arm64::NumSupportedHardwareWatchpoints() { 923 #if defined(__APPLE__) && (defined(__arm64__) || defined(__aarch64__)) 924 // autodetect how many watchpoints are supported dynamically... 925 static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX; 926 if (g_num_supported_hw_watchpoints == UINT32_MAX) { 927 size_t len; 928 uint32_t n = 0; 929 len = sizeof(n); 930 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) { 931 g_num_supported_hw_watchpoints = n; 932 } 933 } 934 return g_num_supported_hw_watchpoints; 935 #else 936 // TODO: figure out remote case here! 937 return 2; 938 #endif 939 } 940 941 uint32_t RegisterContextDarwin_arm64::SetHardwareWatchpoint(lldb::addr_t addr, 942 size_t size, 943 bool read, 944 bool write) { 945 // if (log) log->Printf 946 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint(addr = %8.8p, 947 // size = %u, read = %u, write = %u)", addr, size, read, write); 948 949 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 950 951 // Can't watch zero bytes 952 if (size == 0) 953 return LLDB_INVALID_INDEX32; 954 955 // We must watch for either read or write 956 if (!read && !write) 957 return LLDB_INVALID_INDEX32; 958 959 // Can't watch more than 4 bytes per WVR/WCR pair 960 if (size > 4) 961 return LLDB_INVALID_INDEX32; 962 963 // We can only watch up to four bytes that follow a 4 byte aligned address 964 // per watchpoint register pair. Since we have at most so we can only watch 965 // until the next 4 byte boundary and we need to make sure we can properly 966 // encode this. 967 uint32_t addr_word_offset = addr % 4; 968 // if (log) log->Printf 969 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() - 970 // addr_word_offset = 0x%8.8x", addr_word_offset); 971 972 uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset; 973 // if (log) log->Printf 974 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() - byte_mask = 975 // 0x%8.8x", byte_mask); 976 if (byte_mask > 0xfu) 977 return LLDB_INVALID_INDEX32; 978 979 // Read the debug state 980 int kret = ReadDBG(false); 981 982 if (kret == KERN_SUCCESS) { 983 // Check to make sure we have the needed hardware support 984 uint32_t i = 0; 985 986 for (i = 0; i < num_hw_watchpoints; ++i) { 987 if ((dbg.wcr[i] & WCR_ENABLE) == 0) 988 break; // We found an available hw breakpoint slot (in i) 989 } 990 991 // See if we found an available hw breakpoint slot above 992 if (i < num_hw_watchpoints) { 993 // Make the byte_mask into a valid Byte Address Select mask 994 uint32_t byte_address_select = byte_mask << 5; 995 // Make sure bits 1:0 are clear in our address 996 dbg.wvr[i] = addr & ~((lldb::addr_t)3); 997 dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA 998 // that we will watch 999 S_USER | // Stop only in user mode 1000 (read ? WCR_LOAD : 0) | // Stop on read access? 1001 (write ? WCR_STORE : 0) | // Stop on write access? 1002 WCR_ENABLE; // Enable this watchpoint; 1003 1004 kret = WriteDBG(); 1005 // if (log) log->Printf 1006 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() 1007 // WriteDBG() => 0x%8.8x.", kret); 1008 1009 if (kret == KERN_SUCCESS) 1010 return i; 1011 } else { 1012 // if (log) log->Printf 1013 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint(): 1014 // All hardware resources (%u) are in use.", 1015 // num_hw_watchpoints); 1016 } 1017 } 1018 return LLDB_INVALID_INDEX32; 1019 } 1020 1021 bool RegisterContextDarwin_arm64::ClearHardwareWatchpoint(uint32_t hw_index) { 1022 int kret = ReadDBG(false); 1023 1024 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 1025 if (kret == KERN_SUCCESS) { 1026 if (hw_index < num_hw_points) { 1027 dbg.wcr[hw_index] = 0; 1028 // if (log) log->Printf 1029 // ("RegisterContextDarwin_arm64::ClearHardwareWatchpoint( %u ) 1030 // - WVR%u = 0x%8.8x WCR%u = 0x%8.8x", 1031 // hw_index, 1032 // hw_index, 1033 // dbg.wvr[hw_index], 1034 // hw_index, 1035 // dbg.wcr[hw_index]); 1036 1037 kret = WriteDBG(); 1038 1039 if (kret == KERN_SUCCESS) 1040 return true; 1041 } 1042 } 1043 return false; 1044 } 1045