1 //===-- RegisterContextDarwin_arm64.cpp ---------------------------*- C++ 2 //-*-===// 3 // 4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 5 // See https://llvm.org/LICENSE.txt for license information. 6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "RegisterContextDarwin_arm64.h" 11 #include "RegisterContextDarwinConstants.h" 12 13 #include "lldb/Target/Process.h" 14 #include "lldb/Target/Thread.h" 15 #include "lldb/Utility/DataBufferHeap.h" 16 #include "lldb/Utility/DataExtractor.h" 17 #include "lldb/Utility/Endian.h" 18 #include "lldb/Utility/Log.h" 19 #include "lldb/Utility/RegisterValue.h" 20 #include "lldb/Utility/Scalar.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/Support/Compiler.h" 23 24 #include "Plugins/Process/Utility/InstructionUtils.h" 25 26 #include <memory> 27 28 // Support building against older versions of LLVM, this macro was added 29 // recently. 30 #ifndef LLVM_EXTENSION 31 #define LLVM_EXTENSION 32 #endif 33 34 #include "Utility/ARM64_DWARF_Registers.h" 35 36 using namespace lldb; 37 using namespace lldb_private; 38 39 #define GPR_OFFSET(idx) ((idx)*8) 40 #define GPR_OFFSET_NAME(reg) \ 41 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::GPR, reg)) 42 43 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterContextDarwin_arm64::GPR)) 44 #define FPU_OFFSET_NAME(reg) \ 45 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::FPU, reg)) 46 47 #define EXC_OFFSET_NAME(reg) \ 48 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::EXC, reg) + \ 49 sizeof(RegisterContextDarwin_arm64::GPR) + \ 50 sizeof(RegisterContextDarwin_arm64::FPU)) 51 #define DBG_OFFSET_NAME(reg) \ 52 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::DBG, reg) + \ 53 sizeof(RegisterContextDarwin_arm64::GPR) + \ 54 sizeof(RegisterContextDarwin_arm64::FPU) + \ 55 sizeof(RegisterContextDarwin_arm64::EXC)) 56 57 #define DEFINE_DBG(reg, i) \ 58 #reg, NULL, \ 59 sizeof(((RegisterContextDarwin_arm64::DBG *) NULL)->reg[i]), \ 60 DBG_OFFSET_NAME(reg[i]), eEncodingUint, eFormatHex, \ 61 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 62 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 63 LLDB_INVALID_REGNUM }, \ 64 NULL, NULL, NULL, 0 65 #define REG_CONTEXT_SIZE \ 66 (sizeof(RegisterContextDarwin_arm64::GPR) + \ 67 sizeof(RegisterContextDarwin_arm64::FPU) + \ 68 sizeof(RegisterContextDarwin_arm64::EXC)) 69 70 //----------------------------------------------------------------------------- 71 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure. 72 //----------------------------------------------------------------------------- 73 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT 74 #include "RegisterInfos_arm64.h" 75 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT 76 77 // General purpose registers 78 static uint32_t g_gpr_regnums[] = { 79 gpr_x0, gpr_x1, gpr_x2, gpr_x3, gpr_x4, gpr_x5, gpr_x6, 80 gpr_x7, gpr_x8, gpr_x9, gpr_x10, gpr_x11, gpr_x12, gpr_x13, 81 gpr_x14, gpr_x15, gpr_x16, gpr_x17, gpr_x18, gpr_x19, gpr_x20, 82 gpr_x21, gpr_x22, gpr_x23, gpr_x24, gpr_x25, gpr_x26, gpr_x27, 83 gpr_x28, gpr_fp, gpr_lr, gpr_sp, gpr_pc, gpr_cpsr}; 84 85 // Floating point registers 86 static uint32_t g_fpu_regnums[] = { 87 fpu_v0, fpu_v1, fpu_v2, fpu_v3, fpu_v4, fpu_v5, fpu_v6, 88 fpu_v7, fpu_v8, fpu_v9, fpu_v10, fpu_v11, fpu_v12, fpu_v13, 89 fpu_v14, fpu_v15, fpu_v16, fpu_v17, fpu_v18, fpu_v19, fpu_v20, 90 fpu_v21, fpu_v22, fpu_v23, fpu_v24, fpu_v25, fpu_v26, fpu_v27, 91 fpu_v28, fpu_v29, fpu_v30, fpu_v31, fpu_fpsr, fpu_fpcr}; 92 93 // Exception registers 94 95 static uint32_t g_exc_regnums[] = {exc_far, exc_esr, exc_exception}; 96 97 static size_t k_num_register_infos = 98 llvm::array_lengthof(g_register_infos_arm64_le); 99 100 RegisterContextDarwin_arm64::RegisterContextDarwin_arm64( 101 Thread &thread, uint32_t concrete_frame_idx) 102 : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() { 103 uint32_t i; 104 for (i = 0; i < kNumErrors; i++) { 105 gpr_errs[i] = -1; 106 fpu_errs[i] = -1; 107 exc_errs[i] = -1; 108 } 109 } 110 111 RegisterContextDarwin_arm64::~RegisterContextDarwin_arm64() {} 112 113 void RegisterContextDarwin_arm64::InvalidateAllRegisters() { 114 InvalidateAllRegisterStates(); 115 } 116 117 size_t RegisterContextDarwin_arm64::GetRegisterCount() { 118 assert(k_num_register_infos == k_num_registers); 119 return k_num_registers; 120 } 121 122 const RegisterInfo * 123 RegisterContextDarwin_arm64::GetRegisterInfoAtIndex(size_t reg) { 124 assert(k_num_register_infos == k_num_registers); 125 if (reg < k_num_registers) 126 return &g_register_infos_arm64_le[reg]; 127 return NULL; 128 } 129 130 size_t RegisterContextDarwin_arm64::GetRegisterInfosCount() { 131 return k_num_register_infos; 132 } 133 134 const RegisterInfo *RegisterContextDarwin_arm64::GetRegisterInfos() { 135 return g_register_infos_arm64_le; 136 } 137 138 // Number of registers in each register set 139 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums); 140 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums); 141 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums); 142 143 //---------------------------------------------------------------------- 144 // Register set definitions. The first definitions at register set index of 145 // zero is for all registers, followed by other registers sets. The register 146 // information for the all register set need not be filled in. 147 //---------------------------------------------------------------------- 148 static const RegisterSet g_reg_sets[] = { 149 { 150 "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, 151 }, 152 {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums}, 153 {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}}; 154 155 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets); 156 157 size_t RegisterContextDarwin_arm64::GetRegisterSetCount() { 158 return k_num_regsets; 159 } 160 161 const RegisterSet *RegisterContextDarwin_arm64::GetRegisterSet(size_t reg_set) { 162 if (reg_set < k_num_regsets) 163 return &g_reg_sets[reg_set]; 164 return NULL; 165 } 166 167 //---------------------------------------------------------------------- 168 // Register information definitions for arm64 169 //---------------------------------------------------------------------- 170 int RegisterContextDarwin_arm64::GetSetForNativeRegNum(int reg) { 171 if (reg < fpu_v0) 172 return GPRRegSet; 173 else if (reg < exc_far) 174 return FPURegSet; 175 else if (reg < k_num_registers) 176 return EXCRegSet; 177 return -1; 178 } 179 180 int RegisterContextDarwin_arm64::ReadGPR(bool force) { 181 int set = GPRRegSet; 182 if (force || !RegisterSetIsCached(set)) { 183 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr)); 184 } 185 return GetError(GPRRegSet, Read); 186 } 187 188 int RegisterContextDarwin_arm64::ReadFPU(bool force) { 189 int set = FPURegSet; 190 if (force || !RegisterSetIsCached(set)) { 191 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu)); 192 } 193 return GetError(FPURegSet, Read); 194 } 195 196 int RegisterContextDarwin_arm64::ReadEXC(bool force) { 197 int set = EXCRegSet; 198 if (force || !RegisterSetIsCached(set)) { 199 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc)); 200 } 201 return GetError(EXCRegSet, Read); 202 } 203 204 int RegisterContextDarwin_arm64::ReadDBG(bool force) { 205 int set = DBGRegSet; 206 if (force || !RegisterSetIsCached(set)) { 207 SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg)); 208 } 209 return GetError(DBGRegSet, Read); 210 } 211 212 int RegisterContextDarwin_arm64::WriteGPR() { 213 int set = GPRRegSet; 214 if (!RegisterSetIsCached(set)) { 215 SetError(set, Write, -1); 216 return KERN_INVALID_ARGUMENT; 217 } 218 SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr)); 219 SetError(set, Read, -1); 220 return GetError(GPRRegSet, Write); 221 } 222 223 int RegisterContextDarwin_arm64::WriteFPU() { 224 int set = FPURegSet; 225 if (!RegisterSetIsCached(set)) { 226 SetError(set, Write, -1); 227 return KERN_INVALID_ARGUMENT; 228 } 229 SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu)); 230 SetError(set, Read, -1); 231 return GetError(FPURegSet, Write); 232 } 233 234 int RegisterContextDarwin_arm64::WriteEXC() { 235 int set = EXCRegSet; 236 if (!RegisterSetIsCached(set)) { 237 SetError(set, Write, -1); 238 return KERN_INVALID_ARGUMENT; 239 } 240 SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc)); 241 SetError(set, Read, -1); 242 return GetError(EXCRegSet, Write); 243 } 244 245 int RegisterContextDarwin_arm64::WriteDBG() { 246 int set = DBGRegSet; 247 if (!RegisterSetIsCached(set)) { 248 SetError(set, Write, -1); 249 return KERN_INVALID_ARGUMENT; 250 } 251 SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg)); 252 SetError(set, Read, -1); 253 return GetError(DBGRegSet, Write); 254 } 255 256 int RegisterContextDarwin_arm64::ReadRegisterSet(uint32_t set, bool force) { 257 switch (set) { 258 case GPRRegSet: 259 return ReadGPR(force); 260 case FPURegSet: 261 return ReadFPU(force); 262 case EXCRegSet: 263 return ReadEXC(force); 264 case DBGRegSet: 265 return ReadDBG(force); 266 default: 267 break; 268 } 269 return KERN_INVALID_ARGUMENT; 270 } 271 272 int RegisterContextDarwin_arm64::WriteRegisterSet(uint32_t set) { 273 // Make sure we have a valid context to set. 274 if (RegisterSetIsCached(set)) { 275 switch (set) { 276 case GPRRegSet: 277 return WriteGPR(); 278 case FPURegSet: 279 return WriteFPU(); 280 case EXCRegSet: 281 return WriteEXC(); 282 case DBGRegSet: 283 return WriteDBG(); 284 default: 285 break; 286 } 287 } 288 return KERN_INVALID_ARGUMENT; 289 } 290 291 void RegisterContextDarwin_arm64::LogDBGRegisters(Log *log, const DBG &dbg) { 292 if (log) { 293 for (uint32_t i = 0; i < 16; i++) 294 log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8" PRIu64 ", 0x%8.8" PRIu64 295 " } WVR%-2u/WCR%-2u " 296 "= { 0x%8.8" PRIu64 ", 0x%8.8" PRIu64 " }", 297 i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]); 298 } 299 } 300 301 bool RegisterContextDarwin_arm64::ReadRegister(const RegisterInfo *reg_info, 302 RegisterValue &value) { 303 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 304 int set = RegisterContextDarwin_arm64::GetSetForNativeRegNum(reg); 305 306 if (set == -1) 307 return false; 308 309 if (ReadRegisterSet(set, false) != KERN_SUCCESS) 310 return false; 311 312 switch (reg) { 313 case gpr_x0: 314 case gpr_x1: 315 case gpr_x2: 316 case gpr_x3: 317 case gpr_x4: 318 case gpr_x5: 319 case gpr_x6: 320 case gpr_x7: 321 case gpr_x8: 322 case gpr_x9: 323 case gpr_x10: 324 case gpr_x11: 325 case gpr_x12: 326 case gpr_x13: 327 case gpr_x14: 328 case gpr_x15: 329 case gpr_x16: 330 case gpr_x17: 331 case gpr_x18: 332 case gpr_x19: 333 case gpr_x20: 334 case gpr_x21: 335 case gpr_x22: 336 case gpr_x23: 337 case gpr_x24: 338 case gpr_x25: 339 case gpr_x26: 340 case gpr_x27: 341 case gpr_x28: 342 value.SetUInt64(gpr.x[reg - gpr_x0]); 343 break; 344 case gpr_fp: 345 value.SetUInt64(gpr.fp); 346 break; 347 case gpr_sp: 348 value.SetUInt64(gpr.sp); 349 break; 350 case gpr_lr: 351 value.SetUInt64(gpr.lr); 352 break; 353 case gpr_pc: 354 value.SetUInt64(gpr.pc); 355 break; 356 case gpr_cpsr: 357 value.SetUInt64(gpr.cpsr); 358 break; 359 360 case gpr_w0: 361 case gpr_w1: 362 case gpr_w2: 363 case gpr_w3: 364 case gpr_w4: 365 case gpr_w5: 366 case gpr_w6: 367 case gpr_w7: 368 case gpr_w8: 369 case gpr_w9: 370 case gpr_w10: 371 case gpr_w11: 372 case gpr_w12: 373 case gpr_w13: 374 case gpr_w14: 375 case gpr_w15: 376 case gpr_w16: 377 case gpr_w17: 378 case gpr_w18: 379 case gpr_w19: 380 case gpr_w20: 381 case gpr_w21: 382 case gpr_w22: 383 case gpr_w23: 384 case gpr_w24: 385 case gpr_w25: 386 case gpr_w26: 387 case gpr_w27: 388 case gpr_w28: { 389 ProcessSP process_sp(m_thread.GetProcess()); 390 if (process_sp.get()) { 391 DataExtractor regdata(&gpr.x[reg - gpr_w0], 8, process_sp->GetByteOrder(), 392 process_sp->GetAddressByteSize()); 393 offset_t offset = 0; 394 uint64_t retval = regdata.GetMaxU64(&offset, 8); 395 uint32_t retval_lower32 = static_cast<uint32_t>(retval & 0xffffffff); 396 value.SetUInt32(retval_lower32); 397 } 398 } break; 399 400 case fpu_v0: 401 case fpu_v1: 402 case fpu_v2: 403 case fpu_v3: 404 case fpu_v4: 405 case fpu_v5: 406 case fpu_v6: 407 case fpu_v7: 408 case fpu_v8: 409 case fpu_v9: 410 case fpu_v10: 411 case fpu_v11: 412 case fpu_v12: 413 case fpu_v13: 414 case fpu_v14: 415 case fpu_v15: 416 case fpu_v16: 417 case fpu_v17: 418 case fpu_v18: 419 case fpu_v19: 420 case fpu_v20: 421 case fpu_v21: 422 case fpu_v22: 423 case fpu_v23: 424 case fpu_v24: 425 case fpu_v25: 426 case fpu_v26: 427 case fpu_v27: 428 case fpu_v28: 429 case fpu_v29: 430 case fpu_v30: 431 case fpu_v31: 432 value.SetBytes(fpu.v[reg].bytes.buffer, reg_info->byte_size, 433 endian::InlHostByteOrder()); 434 break; 435 436 case fpu_s0: 437 case fpu_s1: 438 case fpu_s2: 439 case fpu_s3: 440 case fpu_s4: 441 case fpu_s5: 442 case fpu_s6: 443 case fpu_s7: 444 case fpu_s8: 445 case fpu_s9: 446 case fpu_s10: 447 case fpu_s11: 448 case fpu_s12: 449 case fpu_s13: 450 case fpu_s14: 451 case fpu_s15: 452 case fpu_s16: 453 case fpu_s17: 454 case fpu_s18: 455 case fpu_s19: 456 case fpu_s20: 457 case fpu_s21: 458 case fpu_s22: 459 case fpu_s23: 460 case fpu_s24: 461 case fpu_s25: 462 case fpu_s26: 463 case fpu_s27: 464 case fpu_s28: 465 case fpu_s29: 466 case fpu_s30: 467 case fpu_s31: { 468 ProcessSP process_sp(m_thread.GetProcess()); 469 if (process_sp.get()) { 470 DataExtractor regdata(&fpu.v[reg - fpu_s0], 4, process_sp->GetByteOrder(), 471 process_sp->GetAddressByteSize()); 472 offset_t offset = 0; 473 value.SetFloat(regdata.GetFloat(&offset)); 474 } 475 } break; 476 477 case fpu_d0: 478 case fpu_d1: 479 case fpu_d2: 480 case fpu_d3: 481 case fpu_d4: 482 case fpu_d5: 483 case fpu_d6: 484 case fpu_d7: 485 case fpu_d8: 486 case fpu_d9: 487 case fpu_d10: 488 case fpu_d11: 489 case fpu_d12: 490 case fpu_d13: 491 case fpu_d14: 492 case fpu_d15: 493 case fpu_d16: 494 case fpu_d17: 495 case fpu_d18: 496 case fpu_d19: 497 case fpu_d20: 498 case fpu_d21: 499 case fpu_d22: 500 case fpu_d23: 501 case fpu_d24: 502 case fpu_d25: 503 case fpu_d26: 504 case fpu_d27: 505 case fpu_d28: 506 case fpu_d29: 507 case fpu_d30: 508 case fpu_d31: { 509 ProcessSP process_sp(m_thread.GetProcess()); 510 if (process_sp.get()) { 511 DataExtractor regdata(&fpu.v[reg - fpu_s0], 8, process_sp->GetByteOrder(), 512 process_sp->GetAddressByteSize()); 513 offset_t offset = 0; 514 value.SetDouble(regdata.GetDouble(&offset)); 515 } 516 } break; 517 518 case fpu_fpsr: 519 value.SetUInt32(fpu.fpsr); 520 break; 521 522 case fpu_fpcr: 523 value.SetUInt32(fpu.fpcr); 524 break; 525 526 case exc_exception: 527 value.SetUInt32(exc.exception); 528 break; 529 case exc_esr: 530 value.SetUInt32(exc.esr); 531 break; 532 case exc_far: 533 value.SetUInt64(exc.far); 534 break; 535 536 default: 537 value.SetValueToInvalid(); 538 return false; 539 } 540 return true; 541 } 542 543 bool RegisterContextDarwin_arm64::WriteRegister(const RegisterInfo *reg_info, 544 const RegisterValue &value) { 545 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 546 int set = GetSetForNativeRegNum(reg); 547 548 if (set == -1) 549 return false; 550 551 if (ReadRegisterSet(set, false) != KERN_SUCCESS) 552 return false; 553 554 switch (reg) { 555 case gpr_x0: 556 case gpr_x1: 557 case gpr_x2: 558 case gpr_x3: 559 case gpr_x4: 560 case gpr_x5: 561 case gpr_x6: 562 case gpr_x7: 563 case gpr_x8: 564 case gpr_x9: 565 case gpr_x10: 566 case gpr_x11: 567 case gpr_x12: 568 case gpr_x13: 569 case gpr_x14: 570 case gpr_x15: 571 case gpr_x16: 572 case gpr_x17: 573 case gpr_x18: 574 case gpr_x19: 575 case gpr_x20: 576 case gpr_x21: 577 case gpr_x22: 578 case gpr_x23: 579 case gpr_x24: 580 case gpr_x25: 581 case gpr_x26: 582 case gpr_x27: 583 case gpr_x28: 584 case gpr_fp: 585 case gpr_sp: 586 case gpr_lr: 587 case gpr_pc: 588 case gpr_cpsr: 589 gpr.x[reg - gpr_x0] = value.GetAsUInt64(); 590 break; 591 592 case fpu_v0: 593 case fpu_v1: 594 case fpu_v2: 595 case fpu_v3: 596 case fpu_v4: 597 case fpu_v5: 598 case fpu_v6: 599 case fpu_v7: 600 case fpu_v8: 601 case fpu_v9: 602 case fpu_v10: 603 case fpu_v11: 604 case fpu_v12: 605 case fpu_v13: 606 case fpu_v14: 607 case fpu_v15: 608 case fpu_v16: 609 case fpu_v17: 610 case fpu_v18: 611 case fpu_v19: 612 case fpu_v20: 613 case fpu_v21: 614 case fpu_v22: 615 case fpu_v23: 616 case fpu_v24: 617 case fpu_v25: 618 case fpu_v26: 619 case fpu_v27: 620 case fpu_v28: 621 case fpu_v29: 622 case fpu_v30: 623 case fpu_v31: 624 ::memcpy(fpu.v[reg].bytes.buffer, value.GetBytes(), value.GetByteSize()); 625 break; 626 627 case fpu_fpsr: 628 fpu.fpsr = value.GetAsUInt32(); 629 break; 630 631 case fpu_fpcr: 632 fpu.fpcr = value.GetAsUInt32(); 633 break; 634 635 case exc_exception: 636 exc.exception = value.GetAsUInt32(); 637 break; 638 case exc_esr: 639 exc.esr = value.GetAsUInt32(); 640 break; 641 case exc_far: 642 exc.far = value.GetAsUInt64(); 643 break; 644 645 default: 646 return false; 647 } 648 return WriteRegisterSet(set) == KERN_SUCCESS; 649 } 650 651 bool RegisterContextDarwin_arm64::ReadAllRegisterValues( 652 lldb::DataBufferSP &data_sp) { 653 data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0); 654 if (data_sp && ReadGPR(false) == KERN_SUCCESS && 655 ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) { 656 uint8_t *dst = data_sp->GetBytes(); 657 ::memcpy(dst, &gpr, sizeof(gpr)); 658 dst += sizeof(gpr); 659 660 ::memcpy(dst, &fpu, sizeof(fpu)); 661 dst += sizeof(gpr); 662 663 ::memcpy(dst, &exc, sizeof(exc)); 664 return true; 665 } 666 return false; 667 } 668 669 bool RegisterContextDarwin_arm64::WriteAllRegisterValues( 670 const lldb::DataBufferSP &data_sp) { 671 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) { 672 const uint8_t *src = data_sp->GetBytes(); 673 ::memcpy(&gpr, src, sizeof(gpr)); 674 src += sizeof(gpr); 675 676 ::memcpy(&fpu, src, sizeof(fpu)); 677 src += sizeof(gpr); 678 679 ::memcpy(&exc, src, sizeof(exc)); 680 uint32_t success_count = 0; 681 if (WriteGPR() == KERN_SUCCESS) 682 ++success_count; 683 if (WriteFPU() == KERN_SUCCESS) 684 ++success_count; 685 if (WriteEXC() == KERN_SUCCESS) 686 ++success_count; 687 return success_count == 3; 688 } 689 return false; 690 } 691 692 uint32_t RegisterContextDarwin_arm64::ConvertRegisterKindToRegisterNumber( 693 RegisterKind kind, uint32_t reg) { 694 if (kind == eRegisterKindGeneric) { 695 switch (reg) { 696 case LLDB_REGNUM_GENERIC_PC: 697 return gpr_pc; 698 case LLDB_REGNUM_GENERIC_SP: 699 return gpr_sp; 700 case LLDB_REGNUM_GENERIC_FP: 701 return gpr_fp; 702 case LLDB_REGNUM_GENERIC_RA: 703 return gpr_lr; 704 case LLDB_REGNUM_GENERIC_FLAGS: 705 return gpr_cpsr; 706 default: 707 break; 708 } 709 } else if (kind == eRegisterKindDWARF) { 710 switch (reg) { 711 case arm64_dwarf::x0: 712 return gpr_x0; 713 case arm64_dwarf::x1: 714 return gpr_x1; 715 case arm64_dwarf::x2: 716 return gpr_x2; 717 case arm64_dwarf::x3: 718 return gpr_x3; 719 case arm64_dwarf::x4: 720 return gpr_x4; 721 case arm64_dwarf::x5: 722 return gpr_x5; 723 case arm64_dwarf::x6: 724 return gpr_x6; 725 case arm64_dwarf::x7: 726 return gpr_x7; 727 case arm64_dwarf::x8: 728 return gpr_x8; 729 case arm64_dwarf::x9: 730 return gpr_x9; 731 case arm64_dwarf::x10: 732 return gpr_x10; 733 case arm64_dwarf::x11: 734 return gpr_x11; 735 case arm64_dwarf::x12: 736 return gpr_x12; 737 case arm64_dwarf::x13: 738 return gpr_x13; 739 case arm64_dwarf::x14: 740 return gpr_x14; 741 case arm64_dwarf::x15: 742 return gpr_x15; 743 case arm64_dwarf::x16: 744 return gpr_x16; 745 case arm64_dwarf::x17: 746 return gpr_x17; 747 case arm64_dwarf::x18: 748 return gpr_x18; 749 case arm64_dwarf::x19: 750 return gpr_x19; 751 case arm64_dwarf::x20: 752 return gpr_x20; 753 case arm64_dwarf::x21: 754 return gpr_x21; 755 case arm64_dwarf::x22: 756 return gpr_x22; 757 case arm64_dwarf::x23: 758 return gpr_x23; 759 case arm64_dwarf::x24: 760 return gpr_x24; 761 case arm64_dwarf::x25: 762 return gpr_x25; 763 case arm64_dwarf::x26: 764 return gpr_x26; 765 case arm64_dwarf::x27: 766 return gpr_x27; 767 case arm64_dwarf::x28: 768 return gpr_x28; 769 770 case arm64_dwarf::fp: 771 return gpr_fp; 772 case arm64_dwarf::sp: 773 return gpr_sp; 774 case arm64_dwarf::lr: 775 return gpr_lr; 776 case arm64_dwarf::pc: 777 return gpr_pc; 778 case arm64_dwarf::cpsr: 779 return gpr_cpsr; 780 781 case arm64_dwarf::v0: 782 return fpu_v0; 783 case arm64_dwarf::v1: 784 return fpu_v1; 785 case arm64_dwarf::v2: 786 return fpu_v2; 787 case arm64_dwarf::v3: 788 return fpu_v3; 789 case arm64_dwarf::v4: 790 return fpu_v4; 791 case arm64_dwarf::v5: 792 return fpu_v5; 793 case arm64_dwarf::v6: 794 return fpu_v6; 795 case arm64_dwarf::v7: 796 return fpu_v7; 797 case arm64_dwarf::v8: 798 return fpu_v8; 799 case arm64_dwarf::v9: 800 return fpu_v9; 801 case arm64_dwarf::v10: 802 return fpu_v10; 803 case arm64_dwarf::v11: 804 return fpu_v11; 805 case arm64_dwarf::v12: 806 return fpu_v12; 807 case arm64_dwarf::v13: 808 return fpu_v13; 809 case arm64_dwarf::v14: 810 return fpu_v14; 811 case arm64_dwarf::v15: 812 return fpu_v15; 813 case arm64_dwarf::v16: 814 return fpu_v16; 815 case arm64_dwarf::v17: 816 return fpu_v17; 817 case arm64_dwarf::v18: 818 return fpu_v18; 819 case arm64_dwarf::v19: 820 return fpu_v19; 821 case arm64_dwarf::v20: 822 return fpu_v20; 823 case arm64_dwarf::v21: 824 return fpu_v21; 825 case arm64_dwarf::v22: 826 return fpu_v22; 827 case arm64_dwarf::v23: 828 return fpu_v23; 829 case arm64_dwarf::v24: 830 return fpu_v24; 831 case arm64_dwarf::v25: 832 return fpu_v25; 833 case arm64_dwarf::v26: 834 return fpu_v26; 835 case arm64_dwarf::v27: 836 return fpu_v27; 837 case arm64_dwarf::v28: 838 return fpu_v28; 839 case arm64_dwarf::v29: 840 return fpu_v29; 841 case arm64_dwarf::v30: 842 return fpu_v30; 843 case arm64_dwarf::v31: 844 return fpu_v31; 845 846 default: 847 break; 848 } 849 } else if (kind == eRegisterKindEHFrame) { 850 switch (reg) { 851 case arm64_ehframe::x0: 852 return gpr_x0; 853 case arm64_ehframe::x1: 854 return gpr_x1; 855 case arm64_ehframe::x2: 856 return gpr_x2; 857 case arm64_ehframe::x3: 858 return gpr_x3; 859 case arm64_ehframe::x4: 860 return gpr_x4; 861 case arm64_ehframe::x5: 862 return gpr_x5; 863 case arm64_ehframe::x6: 864 return gpr_x6; 865 case arm64_ehframe::x7: 866 return gpr_x7; 867 case arm64_ehframe::x8: 868 return gpr_x8; 869 case arm64_ehframe::x9: 870 return gpr_x9; 871 case arm64_ehframe::x10: 872 return gpr_x10; 873 case arm64_ehframe::x11: 874 return gpr_x11; 875 case arm64_ehframe::x12: 876 return gpr_x12; 877 case arm64_ehframe::x13: 878 return gpr_x13; 879 case arm64_ehframe::x14: 880 return gpr_x14; 881 case arm64_ehframe::x15: 882 return gpr_x15; 883 case arm64_ehframe::x16: 884 return gpr_x16; 885 case arm64_ehframe::x17: 886 return gpr_x17; 887 case arm64_ehframe::x18: 888 return gpr_x18; 889 case arm64_ehframe::x19: 890 return gpr_x19; 891 case arm64_ehframe::x20: 892 return gpr_x20; 893 case arm64_ehframe::x21: 894 return gpr_x21; 895 case arm64_ehframe::x22: 896 return gpr_x22; 897 case arm64_ehframe::x23: 898 return gpr_x23; 899 case arm64_ehframe::x24: 900 return gpr_x24; 901 case arm64_ehframe::x25: 902 return gpr_x25; 903 case arm64_ehframe::x26: 904 return gpr_x26; 905 case arm64_ehframe::x27: 906 return gpr_x27; 907 case arm64_ehframe::x28: 908 return gpr_x28; 909 case arm64_ehframe::fp: 910 return gpr_fp; 911 case arm64_ehframe::sp: 912 return gpr_sp; 913 case arm64_ehframe::lr: 914 return gpr_lr; 915 case arm64_ehframe::pc: 916 return gpr_pc; 917 case arm64_ehframe::cpsr: 918 return gpr_cpsr; 919 } 920 } else if (kind == eRegisterKindLLDB) { 921 return reg; 922 } 923 return LLDB_INVALID_REGNUM; 924 } 925 926 uint32_t RegisterContextDarwin_arm64::NumSupportedHardwareWatchpoints() { 927 #if defined(__APPLE__) && (defined(__arm64__) || defined(__aarch64__)) 928 // autodetect how many watchpoints are supported dynamically... 929 static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX; 930 if (g_num_supported_hw_watchpoints == UINT32_MAX) { 931 size_t len; 932 uint32_t n = 0; 933 len = sizeof(n); 934 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) { 935 g_num_supported_hw_watchpoints = n; 936 } 937 } 938 return g_num_supported_hw_watchpoints; 939 #else 940 // TODO: figure out remote case here! 941 return 2; 942 #endif 943 } 944 945 uint32_t RegisterContextDarwin_arm64::SetHardwareWatchpoint(lldb::addr_t addr, 946 size_t size, 947 bool read, 948 bool write) { 949 // if (log) log->Printf 950 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint(addr = %8.8p, 951 // size = %u, read = %u, write = %u)", addr, size, read, write); 952 953 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 954 955 // Can't watch zero bytes 956 if (size == 0) 957 return LLDB_INVALID_INDEX32; 958 959 // We must watch for either read or write 960 if (!read && !write) 961 return LLDB_INVALID_INDEX32; 962 963 // Can't watch more than 4 bytes per WVR/WCR pair 964 if (size > 4) 965 return LLDB_INVALID_INDEX32; 966 967 // We can only watch up to four bytes that follow a 4 byte aligned address 968 // per watchpoint register pair. Since we have at most so we can only watch 969 // until the next 4 byte boundary and we need to make sure we can properly 970 // encode this. 971 uint32_t addr_word_offset = addr % 4; 972 // if (log) log->Printf 973 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() - 974 // addr_word_offset = 0x%8.8x", addr_word_offset); 975 976 uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset; 977 // if (log) log->Printf 978 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() - byte_mask = 979 // 0x%8.8x", byte_mask); 980 if (byte_mask > 0xfu) 981 return LLDB_INVALID_INDEX32; 982 983 // Read the debug state 984 int kret = ReadDBG(false); 985 986 if (kret == KERN_SUCCESS) { 987 // Check to make sure we have the needed hardware support 988 uint32_t i = 0; 989 990 for (i = 0; i < num_hw_watchpoints; ++i) { 991 if ((dbg.wcr[i] & WCR_ENABLE) == 0) 992 break; // We found an available hw breakpoint slot (in i) 993 } 994 995 // See if we found an available hw breakpoint slot above 996 if (i < num_hw_watchpoints) { 997 // Make the byte_mask into a valid Byte Address Select mask 998 uint32_t byte_address_select = byte_mask << 5; 999 // Make sure bits 1:0 are clear in our address 1000 dbg.wvr[i] = addr & ~((lldb::addr_t)3); 1001 dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA 1002 // that we will watch 1003 S_USER | // Stop only in user mode 1004 (read ? WCR_LOAD : 0) | // Stop on read access? 1005 (write ? WCR_STORE : 0) | // Stop on write access? 1006 WCR_ENABLE; // Enable this watchpoint; 1007 1008 kret = WriteDBG(); 1009 // if (log) log->Printf 1010 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() 1011 // WriteDBG() => 0x%8.8x.", kret); 1012 1013 if (kret == KERN_SUCCESS) 1014 return i; 1015 } else { 1016 // if (log) log->Printf 1017 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint(): 1018 // All hardware resources (%u) are in use.", 1019 // num_hw_watchpoints); 1020 } 1021 } 1022 return LLDB_INVALID_INDEX32; 1023 } 1024 1025 bool RegisterContextDarwin_arm64::ClearHardwareWatchpoint(uint32_t hw_index) { 1026 int kret = ReadDBG(false); 1027 1028 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 1029 if (kret == KERN_SUCCESS) { 1030 if (hw_index < num_hw_points) { 1031 dbg.wcr[hw_index] = 0; 1032 // if (log) log->Printf 1033 // ("RegisterContextDarwin_arm64::ClearHardwareWatchpoint( %u ) 1034 // - WVR%u = 0x%8.8x WCR%u = 0x%8.8x", 1035 // hw_index, 1036 // hw_index, 1037 // dbg.wvr[hw_index], 1038 // hw_index, 1039 // dbg.wcr[hw_index]); 1040 1041 kret = WriteDBG(); 1042 1043 if (kret == KERN_SUCCESS) 1044 return true; 1045 } 1046 } 1047 return false; 1048 } 1049