1 //===-- RegisterContextDarwin_arm64.cpp ---------------------------*- C++ 2 //-*-===// 3 // 4 // The LLVM Compiler Infrastructure 5 // 6 // This file is distributed under the University of Illinois Open Source 7 // License. See LICENSE.TXT for details. 8 // 9 //===----------------------------------------------------------------------===// 10 11 #if defined(__APPLE__) 12 13 #include "RegisterContextDarwin_arm64.h" 14 15 // C Includes 16 #include <mach/mach_types.h> 17 #include <mach/thread_act.h> 18 #include <sys/sysctl.h> 19 20 // C++ Includes 21 // Other libraries and framework includes 22 #include "lldb/Core/DataBufferHeap.h" 23 #include "lldb/Core/DataExtractor.h" 24 #include "lldb/Core/Log.h" 25 #include "lldb/Core/RegisterValue.h" 26 #include "lldb/Core/Scalar.h" 27 #include "lldb/Host/Endian.h" 28 #include "llvm/ADT/STLExtras.h" 29 #include "llvm/Support/Compiler.h" 30 31 #include "Plugins/Process/Utility/InstructionUtils.h" 32 33 // Support building against older versions of LLVM, this macro was added 34 // recently. 35 #ifndef LLVM_EXTENSION 36 #define LLVM_EXTENSION 37 #endif 38 39 // Project includes 40 #include "ARM64_DWARF_Registers.h" 41 42 using namespace lldb; 43 using namespace lldb_private; 44 45 #define GPR_OFFSET(idx) ((idx)*8) 46 #define GPR_OFFSET_NAME(reg) \ 47 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::GPR, reg)) 48 49 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterContextDarwin_arm64::GPR)) 50 #define FPU_OFFSET_NAME(reg) \ 51 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::FPU, reg)) 52 53 #define EXC_OFFSET_NAME(reg) \ 54 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::EXC, reg) + \ 55 sizeof(RegisterContextDarwin_arm64::GPR) + \ 56 sizeof(RegisterContextDarwin_arm64::FPU)) 57 #define DBG_OFFSET_NAME(reg) \ 58 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::DBG, reg) + \ 59 sizeof(RegisterContextDarwin_arm64::GPR) + \ 60 sizeof(RegisterContextDarwin_arm64::FPU) + \ 61 sizeof(RegisterContextDarwin_arm64::EXC)) 62 63 #define DEFINE_DBG(reg, i) \ 64 #reg, NULL, \ 65 sizeof(((RegisterContextDarwin_arm64::DBG *) NULL)->reg[i]), \ 66 DBG_OFFSET_NAME(reg[i]), eEncodingUint, eFormatHex, \ 67 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 68 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 69 LLDB_INVALID_REGNUM }, \ 70 NULL, NULL, NULL, 0 71 #define REG_CONTEXT_SIZE \ 72 (sizeof(RegisterContextDarwin_arm64::GPR) + \ 73 sizeof(RegisterContextDarwin_arm64::FPU) + \ 74 sizeof(RegisterContextDarwin_arm64::EXC)) 75 76 //----------------------------------------------------------------------------- 77 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure. 78 //----------------------------------------------------------------------------- 79 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT 80 #include "RegisterInfos_arm64.h" 81 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT 82 83 // General purpose registers 84 static uint32_t g_gpr_regnums[] = { 85 gpr_x0, gpr_x1, gpr_x2, gpr_x3, gpr_x4, gpr_x5, gpr_x6, 86 gpr_x7, gpr_x8, gpr_x9, gpr_x10, gpr_x11, gpr_x12, gpr_x13, 87 gpr_x14, gpr_x15, gpr_x16, gpr_x17, gpr_x18, gpr_x19, gpr_x20, 88 gpr_x21, gpr_x22, gpr_x23, gpr_x24, gpr_x25, gpr_x26, gpr_x27, 89 gpr_x28, gpr_fp, gpr_lr, gpr_sp, gpr_pc, gpr_cpsr}; 90 91 // Floating point registers 92 static uint32_t g_fpu_regnums[] = { 93 fpu_v0, fpu_v1, fpu_v2, fpu_v3, fpu_v4, fpu_v5, fpu_v6, 94 fpu_v7, fpu_v8, fpu_v9, fpu_v10, fpu_v11, fpu_v12, fpu_v13, 95 fpu_v14, fpu_v15, fpu_v16, fpu_v17, fpu_v18, fpu_v19, fpu_v20, 96 fpu_v21, fpu_v22, fpu_v23, fpu_v24, fpu_v25, fpu_v26, fpu_v27, 97 fpu_v28, fpu_v29, fpu_v30, fpu_v31, fpu_fpsr, fpu_fpcr}; 98 99 // Exception registers 100 101 static uint32_t g_exc_regnums[] = {exc_far, exc_esr, exc_exception}; 102 103 static size_t k_num_register_infos = 104 llvm::array_lengthof(g_register_infos_arm64); 105 106 RegisterContextDarwin_arm64::RegisterContextDarwin_arm64( 107 Thread &thread, uint32_t concrete_frame_idx) 108 : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() { 109 uint32_t i; 110 for (i = 0; i < kNumErrors; i++) { 111 gpr_errs[i] = -1; 112 fpu_errs[i] = -1; 113 exc_errs[i] = -1; 114 } 115 } 116 117 RegisterContextDarwin_arm64::~RegisterContextDarwin_arm64() {} 118 119 void RegisterContextDarwin_arm64::InvalidateAllRegisters() { 120 InvalidateAllRegisterStates(); 121 } 122 123 size_t RegisterContextDarwin_arm64::GetRegisterCount() { 124 assert(k_num_register_infos == k_num_registers); 125 return k_num_registers; 126 } 127 128 const RegisterInfo * 129 RegisterContextDarwin_arm64::GetRegisterInfoAtIndex(size_t reg) { 130 assert(k_num_register_infos == k_num_registers); 131 if (reg < k_num_registers) 132 return &g_register_infos_arm64[reg]; 133 return NULL; 134 } 135 136 size_t RegisterContextDarwin_arm64::GetRegisterInfosCount() { 137 return k_num_register_infos; 138 } 139 140 const RegisterInfo *RegisterContextDarwin_arm64::GetRegisterInfos() { 141 return g_register_infos_arm64; 142 } 143 144 // Number of registers in each register set 145 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums); 146 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums); 147 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums); 148 149 //---------------------------------------------------------------------- 150 // Register set definitions. The first definitions at register set index 151 // of zero is for all registers, followed by other registers sets. The 152 // register information for the all register set need not be filled in. 153 //---------------------------------------------------------------------- 154 static const RegisterSet g_reg_sets[] = { 155 { 156 "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, 157 }, 158 {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums}, 159 {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}}; 160 161 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets); 162 163 size_t RegisterContextDarwin_arm64::GetRegisterSetCount() { 164 return k_num_regsets; 165 } 166 167 const RegisterSet *RegisterContextDarwin_arm64::GetRegisterSet(size_t reg_set) { 168 if (reg_set < k_num_regsets) 169 return &g_reg_sets[reg_set]; 170 return NULL; 171 } 172 173 //---------------------------------------------------------------------- 174 // Register information definitions for arm64 175 //---------------------------------------------------------------------- 176 int RegisterContextDarwin_arm64::GetSetForNativeRegNum(int reg) { 177 if (reg < fpu_v0) 178 return GPRRegSet; 179 else if (reg < exc_far) 180 return FPURegSet; 181 else if (reg < k_num_registers) 182 return EXCRegSet; 183 return -1; 184 } 185 186 int RegisterContextDarwin_arm64::ReadGPR(bool force) { 187 int set = GPRRegSet; 188 if (force || !RegisterSetIsCached(set)) { 189 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr)); 190 } 191 return GetError(GPRRegSet, Read); 192 } 193 194 int RegisterContextDarwin_arm64::ReadFPU(bool force) { 195 int set = FPURegSet; 196 if (force || !RegisterSetIsCached(set)) { 197 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu)); 198 } 199 return GetError(FPURegSet, Read); 200 } 201 202 int RegisterContextDarwin_arm64::ReadEXC(bool force) { 203 int set = EXCRegSet; 204 if (force || !RegisterSetIsCached(set)) { 205 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc)); 206 } 207 return GetError(EXCRegSet, Read); 208 } 209 210 int RegisterContextDarwin_arm64::ReadDBG(bool force) { 211 int set = DBGRegSet; 212 if (force || !RegisterSetIsCached(set)) { 213 SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg)); 214 } 215 return GetError(DBGRegSet, Read); 216 } 217 218 int RegisterContextDarwin_arm64::WriteGPR() { 219 int set = GPRRegSet; 220 if (!RegisterSetIsCached(set)) { 221 SetError(set, Write, -1); 222 return KERN_INVALID_ARGUMENT; 223 } 224 SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr)); 225 SetError(set, Read, -1); 226 return GetError(GPRRegSet, Write); 227 } 228 229 int RegisterContextDarwin_arm64::WriteFPU() { 230 int set = FPURegSet; 231 if (!RegisterSetIsCached(set)) { 232 SetError(set, Write, -1); 233 return KERN_INVALID_ARGUMENT; 234 } 235 SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu)); 236 SetError(set, Read, -1); 237 return GetError(FPURegSet, Write); 238 } 239 240 int RegisterContextDarwin_arm64::WriteEXC() { 241 int set = EXCRegSet; 242 if (!RegisterSetIsCached(set)) { 243 SetError(set, Write, -1); 244 return KERN_INVALID_ARGUMENT; 245 } 246 SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc)); 247 SetError(set, Read, -1); 248 return GetError(EXCRegSet, Write); 249 } 250 251 int RegisterContextDarwin_arm64::WriteDBG() { 252 int set = DBGRegSet; 253 if (!RegisterSetIsCached(set)) { 254 SetError(set, Write, -1); 255 return KERN_INVALID_ARGUMENT; 256 } 257 SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg)); 258 SetError(set, Read, -1); 259 return GetError(DBGRegSet, Write); 260 } 261 262 int RegisterContextDarwin_arm64::ReadRegisterSet(uint32_t set, bool force) { 263 switch (set) { 264 case GPRRegSet: 265 return ReadGPR(force); 266 case FPURegSet: 267 return ReadFPU(force); 268 case EXCRegSet: 269 return ReadEXC(force); 270 case DBGRegSet: 271 return ReadDBG(force); 272 default: 273 break; 274 } 275 return KERN_INVALID_ARGUMENT; 276 } 277 278 int RegisterContextDarwin_arm64::WriteRegisterSet(uint32_t set) { 279 // Make sure we have a valid context to set. 280 if (RegisterSetIsCached(set)) { 281 switch (set) { 282 case GPRRegSet: 283 return WriteGPR(); 284 case FPURegSet: 285 return WriteFPU(); 286 case EXCRegSet: 287 return WriteEXC(); 288 case DBGRegSet: 289 return WriteDBG(); 290 default: 291 break; 292 } 293 } 294 return KERN_INVALID_ARGUMENT; 295 } 296 297 void RegisterContextDarwin_arm64::LogDBGRegisters(Log *log, const DBG &dbg) { 298 if (log) { 299 for (uint32_t i = 0; i < 16; i++) 300 log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8llx, 0x%8.8llx } WVR%-2u/WCR%-2u " 301 "= { 0x%8.8llx, 0x%8.8llx }", 302 i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]); 303 } 304 } 305 306 bool RegisterContextDarwin_arm64::ReadRegister(const RegisterInfo *reg_info, 307 RegisterValue &value) { 308 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 309 int set = RegisterContextDarwin_arm64::GetSetForNativeRegNum(reg); 310 311 if (set == -1) 312 return false; 313 314 if (ReadRegisterSet(set, false) != KERN_SUCCESS) 315 return false; 316 317 switch (reg) { 318 case gpr_x0: 319 case gpr_x1: 320 case gpr_x2: 321 case gpr_x3: 322 case gpr_x4: 323 case gpr_x5: 324 case gpr_x6: 325 case gpr_x7: 326 case gpr_x8: 327 case gpr_x9: 328 case gpr_x10: 329 case gpr_x11: 330 case gpr_x12: 331 case gpr_x13: 332 case gpr_x14: 333 case gpr_x15: 334 case gpr_x16: 335 case gpr_x17: 336 case gpr_x18: 337 case gpr_x19: 338 case gpr_x20: 339 case gpr_x21: 340 case gpr_x22: 341 case gpr_x23: 342 case gpr_x24: 343 case gpr_x25: 344 case gpr_x26: 345 case gpr_x27: 346 case gpr_x28: 347 case gpr_fp: 348 case gpr_sp: 349 case gpr_lr: 350 case gpr_pc: 351 case gpr_cpsr: 352 value.SetUInt64(gpr.x[reg - gpr_x0]); 353 break; 354 355 case fpu_v0: 356 case fpu_v1: 357 case fpu_v2: 358 case fpu_v3: 359 case fpu_v4: 360 case fpu_v5: 361 case fpu_v6: 362 case fpu_v7: 363 case fpu_v8: 364 case fpu_v9: 365 case fpu_v10: 366 case fpu_v11: 367 case fpu_v12: 368 case fpu_v13: 369 case fpu_v14: 370 case fpu_v15: 371 case fpu_v16: 372 case fpu_v17: 373 case fpu_v18: 374 case fpu_v19: 375 case fpu_v20: 376 case fpu_v21: 377 case fpu_v22: 378 case fpu_v23: 379 case fpu_v24: 380 case fpu_v25: 381 case fpu_v26: 382 case fpu_v27: 383 case fpu_v28: 384 case fpu_v29: 385 case fpu_v30: 386 case fpu_v31: 387 value.SetBytes(fpu.v[reg].bytes, reg_info->byte_size, 388 endian::InlHostByteOrder()); 389 break; 390 391 case fpu_fpsr: 392 value.SetUInt32(fpu.fpsr); 393 break; 394 395 case fpu_fpcr: 396 value.SetUInt32(fpu.fpcr); 397 break; 398 399 case exc_exception: 400 value.SetUInt32(exc.exception); 401 break; 402 case exc_esr: 403 value.SetUInt32(exc.esr); 404 break; 405 case exc_far: 406 value.SetUInt64(exc.far); 407 break; 408 409 default: 410 value.SetValueToInvalid(); 411 return false; 412 } 413 return true; 414 } 415 416 bool RegisterContextDarwin_arm64::WriteRegister(const RegisterInfo *reg_info, 417 const RegisterValue &value) { 418 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 419 int set = GetSetForNativeRegNum(reg); 420 421 if (set == -1) 422 return false; 423 424 if (ReadRegisterSet(set, false) != KERN_SUCCESS) 425 return false; 426 427 switch (reg) { 428 case gpr_x0: 429 case gpr_x1: 430 case gpr_x2: 431 case gpr_x3: 432 case gpr_x4: 433 case gpr_x5: 434 case gpr_x6: 435 case gpr_x7: 436 case gpr_x8: 437 case gpr_x9: 438 case gpr_x10: 439 case gpr_x11: 440 case gpr_x12: 441 case gpr_x13: 442 case gpr_x14: 443 case gpr_x15: 444 case gpr_x16: 445 case gpr_x17: 446 case gpr_x18: 447 case gpr_x19: 448 case gpr_x20: 449 case gpr_x21: 450 case gpr_x22: 451 case gpr_x23: 452 case gpr_x24: 453 case gpr_x25: 454 case gpr_x26: 455 case gpr_x27: 456 case gpr_x28: 457 case gpr_fp: 458 case gpr_sp: 459 case gpr_lr: 460 case gpr_pc: 461 case gpr_cpsr: 462 gpr.x[reg - gpr_x0] = value.GetAsUInt64(); 463 break; 464 465 case fpu_v0: 466 case fpu_v1: 467 case fpu_v2: 468 case fpu_v3: 469 case fpu_v4: 470 case fpu_v5: 471 case fpu_v6: 472 case fpu_v7: 473 case fpu_v8: 474 case fpu_v9: 475 case fpu_v10: 476 case fpu_v11: 477 case fpu_v12: 478 case fpu_v13: 479 case fpu_v14: 480 case fpu_v15: 481 case fpu_v16: 482 case fpu_v17: 483 case fpu_v18: 484 case fpu_v19: 485 case fpu_v20: 486 case fpu_v21: 487 case fpu_v22: 488 case fpu_v23: 489 case fpu_v24: 490 case fpu_v25: 491 case fpu_v26: 492 case fpu_v27: 493 case fpu_v28: 494 case fpu_v29: 495 case fpu_v30: 496 case fpu_v31: 497 ::memcpy(fpu.v[reg].bytes, value.GetBytes(), value.GetByteSize()); 498 break; 499 500 case fpu_fpsr: 501 fpu.fpsr = value.GetAsUInt32(); 502 break; 503 504 case fpu_fpcr: 505 fpu.fpcr = value.GetAsUInt32(); 506 break; 507 508 case exc_exception: 509 exc.exception = value.GetAsUInt32(); 510 break; 511 case exc_esr: 512 exc.esr = value.GetAsUInt32(); 513 break; 514 case exc_far: 515 exc.far = value.GetAsUInt64(); 516 break; 517 518 default: 519 return false; 520 } 521 return WriteRegisterSet(set) == KERN_SUCCESS; 522 } 523 524 bool RegisterContextDarwin_arm64::ReadAllRegisterValues( 525 lldb::DataBufferSP &data_sp) { 526 data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0)); 527 if (data_sp && ReadGPR(false) == KERN_SUCCESS && 528 ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) { 529 uint8_t *dst = data_sp->GetBytes(); 530 ::memcpy(dst, &gpr, sizeof(gpr)); 531 dst += sizeof(gpr); 532 533 ::memcpy(dst, &fpu, sizeof(fpu)); 534 dst += sizeof(gpr); 535 536 ::memcpy(dst, &exc, sizeof(exc)); 537 return true; 538 } 539 return false; 540 } 541 542 bool RegisterContextDarwin_arm64::WriteAllRegisterValues( 543 const lldb::DataBufferSP &data_sp) { 544 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) { 545 const uint8_t *src = data_sp->GetBytes(); 546 ::memcpy(&gpr, src, sizeof(gpr)); 547 src += sizeof(gpr); 548 549 ::memcpy(&fpu, src, sizeof(fpu)); 550 src += sizeof(gpr); 551 552 ::memcpy(&exc, src, sizeof(exc)); 553 uint32_t success_count = 0; 554 if (WriteGPR() == KERN_SUCCESS) 555 ++success_count; 556 if (WriteFPU() == KERN_SUCCESS) 557 ++success_count; 558 if (WriteEXC() == KERN_SUCCESS) 559 ++success_count; 560 return success_count == 3; 561 } 562 return false; 563 } 564 565 uint32_t RegisterContextDarwin_arm64::ConvertRegisterKindToRegisterNumber( 566 RegisterKind kind, uint32_t reg) { 567 if (kind == eRegisterKindGeneric) { 568 switch (reg) { 569 case LLDB_REGNUM_GENERIC_PC: 570 return gpr_pc; 571 case LLDB_REGNUM_GENERIC_SP: 572 return gpr_sp; 573 case LLDB_REGNUM_GENERIC_FP: 574 return gpr_fp; 575 case LLDB_REGNUM_GENERIC_RA: 576 return gpr_lr; 577 case LLDB_REGNUM_GENERIC_FLAGS: 578 return gpr_cpsr; 579 default: 580 break; 581 } 582 } else if (kind == eRegisterKindDWARF) { 583 switch (reg) { 584 case arm64_dwarf::x0: 585 return gpr_x0; 586 case arm64_dwarf::x1: 587 return gpr_x1; 588 case arm64_dwarf::x2: 589 return gpr_x2; 590 case arm64_dwarf::x3: 591 return gpr_x3; 592 case arm64_dwarf::x4: 593 return gpr_x4; 594 case arm64_dwarf::x5: 595 return gpr_x5; 596 case arm64_dwarf::x6: 597 return gpr_x6; 598 case arm64_dwarf::x7: 599 return gpr_x7; 600 case arm64_dwarf::x8: 601 return gpr_x8; 602 case arm64_dwarf::x9: 603 return gpr_x9; 604 case arm64_dwarf::x10: 605 return gpr_x10; 606 case arm64_dwarf::x11: 607 return gpr_x11; 608 case arm64_dwarf::x12: 609 return gpr_x12; 610 case arm64_dwarf::x13: 611 return gpr_x13; 612 case arm64_dwarf::x14: 613 return gpr_x14; 614 case arm64_dwarf::x15: 615 return gpr_x15; 616 case arm64_dwarf::x16: 617 return gpr_x16; 618 case arm64_dwarf::x17: 619 return gpr_x17; 620 case arm64_dwarf::x18: 621 return gpr_x18; 622 case arm64_dwarf::x19: 623 return gpr_x19; 624 case arm64_dwarf::x20: 625 return gpr_x20; 626 case arm64_dwarf::x21: 627 return gpr_x21; 628 case arm64_dwarf::x22: 629 return gpr_x22; 630 case arm64_dwarf::x23: 631 return gpr_x23; 632 case arm64_dwarf::x24: 633 return gpr_x24; 634 case arm64_dwarf::x25: 635 return gpr_x25; 636 case arm64_dwarf::x26: 637 return gpr_x26; 638 case arm64_dwarf::x27: 639 return gpr_x27; 640 case arm64_dwarf::x28: 641 return gpr_x28; 642 643 case arm64_dwarf::fp: 644 return gpr_fp; 645 case arm64_dwarf::sp: 646 return gpr_sp; 647 case arm64_dwarf::lr: 648 return gpr_lr; 649 case arm64_dwarf::pc: 650 return gpr_pc; 651 case arm64_dwarf::cpsr: 652 return gpr_cpsr; 653 654 case arm64_dwarf::v0: 655 return fpu_v0; 656 case arm64_dwarf::v1: 657 return fpu_v1; 658 case arm64_dwarf::v2: 659 return fpu_v2; 660 case arm64_dwarf::v3: 661 return fpu_v3; 662 case arm64_dwarf::v4: 663 return fpu_v4; 664 case arm64_dwarf::v5: 665 return fpu_v5; 666 case arm64_dwarf::v6: 667 return fpu_v6; 668 case arm64_dwarf::v7: 669 return fpu_v7; 670 case arm64_dwarf::v8: 671 return fpu_v8; 672 case arm64_dwarf::v9: 673 return fpu_v9; 674 case arm64_dwarf::v10: 675 return fpu_v10; 676 case arm64_dwarf::v11: 677 return fpu_v11; 678 case arm64_dwarf::v12: 679 return fpu_v12; 680 case arm64_dwarf::v13: 681 return fpu_v13; 682 case arm64_dwarf::v14: 683 return fpu_v14; 684 case arm64_dwarf::v15: 685 return fpu_v15; 686 case arm64_dwarf::v16: 687 return fpu_v16; 688 case arm64_dwarf::v17: 689 return fpu_v17; 690 case arm64_dwarf::v18: 691 return fpu_v18; 692 case arm64_dwarf::v19: 693 return fpu_v19; 694 case arm64_dwarf::v20: 695 return fpu_v20; 696 case arm64_dwarf::v21: 697 return fpu_v21; 698 case arm64_dwarf::v22: 699 return fpu_v22; 700 case arm64_dwarf::v23: 701 return fpu_v23; 702 case arm64_dwarf::v24: 703 return fpu_v24; 704 case arm64_dwarf::v25: 705 return fpu_v25; 706 case arm64_dwarf::v26: 707 return fpu_v26; 708 case arm64_dwarf::v27: 709 return fpu_v27; 710 case arm64_dwarf::v28: 711 return fpu_v28; 712 case arm64_dwarf::v29: 713 return fpu_v29; 714 case arm64_dwarf::v30: 715 return fpu_v30; 716 case arm64_dwarf::v31: 717 return fpu_v31; 718 719 default: 720 break; 721 } 722 } else if (kind == eRegisterKindEHFrame) { 723 switch (reg) { 724 case arm64_ehframe::x0: 725 return gpr_x0; 726 case arm64_ehframe::x1: 727 return gpr_x1; 728 case arm64_ehframe::x2: 729 return gpr_x2; 730 case arm64_ehframe::x3: 731 return gpr_x3; 732 case arm64_ehframe::x4: 733 return gpr_x4; 734 case arm64_ehframe::x5: 735 return gpr_x5; 736 case arm64_ehframe::x6: 737 return gpr_x6; 738 case arm64_ehframe::x7: 739 return gpr_x7; 740 case arm64_ehframe::x8: 741 return gpr_x8; 742 case arm64_ehframe::x9: 743 return gpr_x9; 744 case arm64_ehframe::x10: 745 return gpr_x10; 746 case arm64_ehframe::x11: 747 return gpr_x11; 748 case arm64_ehframe::x12: 749 return gpr_x12; 750 case arm64_ehframe::x13: 751 return gpr_x13; 752 case arm64_ehframe::x14: 753 return gpr_x14; 754 case arm64_ehframe::x15: 755 return gpr_x15; 756 case arm64_ehframe::x16: 757 return gpr_x16; 758 case arm64_ehframe::x17: 759 return gpr_x17; 760 case arm64_ehframe::x18: 761 return gpr_x18; 762 case arm64_ehframe::x19: 763 return gpr_x19; 764 case arm64_ehframe::x20: 765 return gpr_x20; 766 case arm64_ehframe::x21: 767 return gpr_x21; 768 case arm64_ehframe::x22: 769 return gpr_x22; 770 case arm64_ehframe::x23: 771 return gpr_x23; 772 case arm64_ehframe::x24: 773 return gpr_x24; 774 case arm64_ehframe::x25: 775 return gpr_x25; 776 case arm64_ehframe::x26: 777 return gpr_x26; 778 case arm64_ehframe::x27: 779 return gpr_x27; 780 case arm64_ehframe::x28: 781 return gpr_x28; 782 case arm64_ehframe::fp: 783 return gpr_fp; 784 case arm64_ehframe::sp: 785 return gpr_sp; 786 case arm64_ehframe::lr: 787 return gpr_lr; 788 case arm64_ehframe::pc: 789 return gpr_pc; 790 case arm64_ehframe::cpsr: 791 return gpr_cpsr; 792 } 793 } else if (kind == eRegisterKindLLDB) { 794 return reg; 795 } 796 return LLDB_INVALID_REGNUM; 797 } 798 799 uint32_t RegisterContextDarwin_arm64::NumSupportedHardwareWatchpoints() { 800 #if defined(__arm64__) || defined(__aarch64__) 801 // autodetect how many watchpoints are supported dynamically... 802 static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX; 803 if (g_num_supported_hw_watchpoints == UINT32_MAX) { 804 size_t len; 805 uint32_t n = 0; 806 len = sizeof(n); 807 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) { 808 g_num_supported_hw_watchpoints = n; 809 } 810 } 811 return g_num_supported_hw_watchpoints; 812 #else 813 // TODO: figure out remote case here! 814 return 2; 815 #endif 816 } 817 818 uint32_t RegisterContextDarwin_arm64::SetHardwareWatchpoint(lldb::addr_t addr, 819 size_t size, 820 bool read, 821 bool write) { 822 // if (log) log->Printf 823 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint(addr = %8.8p, 824 // size = %u, read = %u, write = %u)", addr, size, read, write); 825 826 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 827 828 // Can't watch zero bytes 829 if (size == 0) 830 return LLDB_INVALID_INDEX32; 831 832 // We must watch for either read or write 833 if (read == false && write == false) 834 return LLDB_INVALID_INDEX32; 835 836 // Can't watch more than 4 bytes per WVR/WCR pair 837 if (size > 4) 838 return LLDB_INVALID_INDEX32; 839 840 // We can only watch up to four bytes that follow a 4 byte aligned address 841 // per watchpoint register pair. Since we have at most so we can only watch 842 // until the next 4 byte boundary and we need to make sure we can properly 843 // encode this. 844 uint32_t addr_word_offset = addr % 4; 845 // if (log) log->Printf 846 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() - 847 // addr_word_offset = 0x%8.8x", addr_word_offset); 848 849 uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset; 850 // if (log) log->Printf 851 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() - byte_mask = 852 // 0x%8.8x", byte_mask); 853 if (byte_mask > 0xfu) 854 return LLDB_INVALID_INDEX32; 855 856 // Read the debug state 857 int kret = ReadDBG(false); 858 859 if (kret == KERN_SUCCESS) { 860 // Check to make sure we have the needed hardware support 861 uint32_t i = 0; 862 863 for (i = 0; i < num_hw_watchpoints; ++i) { 864 if ((dbg.wcr[i] & WCR_ENABLE) == 0) 865 break; // We found an available hw breakpoint slot (in i) 866 } 867 868 // See if we found an available hw breakpoint slot above 869 if (i < num_hw_watchpoints) { 870 // Make the byte_mask into a valid Byte Address Select mask 871 uint32_t byte_address_select = byte_mask << 5; 872 // Make sure bits 1:0 are clear in our address 873 dbg.wvr[i] = addr & ~((lldb::addr_t)3); 874 dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA 875 // that we will watch 876 S_USER | // Stop only in user mode 877 (read ? WCR_LOAD : 0) | // Stop on read access? 878 (write ? WCR_STORE : 0) | // Stop on write access? 879 WCR_ENABLE; // Enable this watchpoint; 880 881 kret = WriteDBG(); 882 // if (log) log->Printf 883 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() 884 // WriteDBG() => 0x%8.8x.", kret); 885 886 if (kret == KERN_SUCCESS) 887 return i; 888 } else { 889 // if (log) log->Printf 890 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint(): 891 // All hardware resources (%u) are in use.", 892 // num_hw_watchpoints); 893 } 894 } 895 return LLDB_INVALID_INDEX32; 896 } 897 898 bool RegisterContextDarwin_arm64::ClearHardwareWatchpoint(uint32_t hw_index) { 899 int kret = ReadDBG(false); 900 901 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 902 if (kret == KERN_SUCCESS) { 903 if (hw_index < num_hw_points) { 904 dbg.wcr[hw_index] = 0; 905 // if (log) log->Printf 906 // ("RegisterContextDarwin_arm64::ClearHardwareWatchpoint( %u ) 907 // - WVR%u = 0x%8.8x WCR%u = 0x%8.8x", 908 // hw_index, 909 // hw_index, 910 // dbg.wvr[hw_index], 911 // hw_index, 912 // dbg.wcr[hw_index]); 913 914 kret = WriteDBG(); 915 916 if (kret == KERN_SUCCESS) 917 return true; 918 } 919 } 920 return false; 921 } 922 923 #endif 924