1 //===-- RegisterContextDarwin_arm64.cpp ---------------------------*- C++ 2 //-*-===// 3 // 4 // The LLVM Compiler Infrastructure 5 // 6 // This file is distributed under the University of Illinois Open Source 7 // License. See LICENSE.TXT for details. 8 // 9 //===----------------------------------------------------------------------===// 10 11 #include "RegisterContextDarwin_arm64.h" 12 #include "RegisterContextDarwinConstants.h" 13 14 #include "lldb/Target/Process.h" 15 #include "lldb/Target/Thread.h" 16 #include "lldb/Utility/DataBufferHeap.h" 17 #include "lldb/Utility/DataExtractor.h" 18 #include "lldb/Utility/Endian.h" 19 #include "lldb/Utility/Log.h" 20 #include "lldb/Utility/RegisterValue.h" 21 #include "lldb/Utility/Scalar.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/Support/Compiler.h" 24 25 #include "Plugins/Process/Utility/InstructionUtils.h" 26 27 // Support building against older versions of LLVM, this macro was added 28 // recently. 29 #ifndef LLVM_EXTENSION 30 #define LLVM_EXTENSION 31 #endif 32 33 #include "Utility/ARM64_DWARF_Registers.h" 34 35 using namespace lldb; 36 using namespace lldb_private; 37 38 #define GPR_OFFSET(idx) ((idx)*8) 39 #define GPR_OFFSET_NAME(reg) \ 40 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::GPR, reg)) 41 42 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterContextDarwin_arm64::GPR)) 43 #define FPU_OFFSET_NAME(reg) \ 44 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::FPU, reg)) 45 46 #define EXC_OFFSET_NAME(reg) \ 47 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::EXC, reg) + \ 48 sizeof(RegisterContextDarwin_arm64::GPR) + \ 49 sizeof(RegisterContextDarwin_arm64::FPU)) 50 #define DBG_OFFSET_NAME(reg) \ 51 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::DBG, reg) + \ 52 sizeof(RegisterContextDarwin_arm64::GPR) + \ 53 sizeof(RegisterContextDarwin_arm64::FPU) + \ 54 sizeof(RegisterContextDarwin_arm64::EXC)) 55 56 #define DEFINE_DBG(reg, i) \ 57 #reg, NULL, \ 58 sizeof(((RegisterContextDarwin_arm64::DBG *) NULL)->reg[i]), \ 59 DBG_OFFSET_NAME(reg[i]), eEncodingUint, eFormatHex, \ 60 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 61 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 62 LLDB_INVALID_REGNUM }, \ 63 NULL, NULL, NULL, 0 64 #define REG_CONTEXT_SIZE \ 65 (sizeof(RegisterContextDarwin_arm64::GPR) + \ 66 sizeof(RegisterContextDarwin_arm64::FPU) + \ 67 sizeof(RegisterContextDarwin_arm64::EXC)) 68 69 //----------------------------------------------------------------------------- 70 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure. 71 //----------------------------------------------------------------------------- 72 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT 73 #include "RegisterInfos_arm64.h" 74 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT 75 76 // General purpose registers 77 static uint32_t g_gpr_regnums[] = { 78 gpr_x0, gpr_x1, gpr_x2, gpr_x3, gpr_x4, gpr_x5, gpr_x6, 79 gpr_x7, gpr_x8, gpr_x9, gpr_x10, gpr_x11, gpr_x12, gpr_x13, 80 gpr_x14, gpr_x15, gpr_x16, gpr_x17, gpr_x18, gpr_x19, gpr_x20, 81 gpr_x21, gpr_x22, gpr_x23, gpr_x24, gpr_x25, gpr_x26, gpr_x27, 82 gpr_x28, gpr_fp, gpr_lr, gpr_sp, gpr_pc, gpr_cpsr}; 83 84 // Floating point registers 85 static uint32_t g_fpu_regnums[] = { 86 fpu_v0, fpu_v1, fpu_v2, fpu_v3, fpu_v4, fpu_v5, fpu_v6, 87 fpu_v7, fpu_v8, fpu_v9, fpu_v10, fpu_v11, fpu_v12, fpu_v13, 88 fpu_v14, fpu_v15, fpu_v16, fpu_v17, fpu_v18, fpu_v19, fpu_v20, 89 fpu_v21, fpu_v22, fpu_v23, fpu_v24, fpu_v25, fpu_v26, fpu_v27, 90 fpu_v28, fpu_v29, fpu_v30, fpu_v31, fpu_fpsr, fpu_fpcr}; 91 92 // Exception registers 93 94 static uint32_t g_exc_regnums[] = {exc_far, exc_esr, exc_exception}; 95 96 static size_t k_num_register_infos = 97 llvm::array_lengthof(g_register_infos_arm64_le); 98 99 RegisterContextDarwin_arm64::RegisterContextDarwin_arm64( 100 Thread &thread, uint32_t concrete_frame_idx) 101 : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() { 102 uint32_t i; 103 for (i = 0; i < kNumErrors; i++) { 104 gpr_errs[i] = -1; 105 fpu_errs[i] = -1; 106 exc_errs[i] = -1; 107 } 108 } 109 110 RegisterContextDarwin_arm64::~RegisterContextDarwin_arm64() {} 111 112 void RegisterContextDarwin_arm64::InvalidateAllRegisters() { 113 InvalidateAllRegisterStates(); 114 } 115 116 size_t RegisterContextDarwin_arm64::GetRegisterCount() { 117 assert(k_num_register_infos == k_num_registers); 118 return k_num_registers; 119 } 120 121 const RegisterInfo * 122 RegisterContextDarwin_arm64::GetRegisterInfoAtIndex(size_t reg) { 123 assert(k_num_register_infos == k_num_registers); 124 if (reg < k_num_registers) 125 return &g_register_infos_arm64_le[reg]; 126 return NULL; 127 } 128 129 size_t RegisterContextDarwin_arm64::GetRegisterInfosCount() { 130 return k_num_register_infos; 131 } 132 133 const RegisterInfo *RegisterContextDarwin_arm64::GetRegisterInfos() { 134 return g_register_infos_arm64_le; 135 } 136 137 // Number of registers in each register set 138 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums); 139 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums); 140 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums); 141 142 //---------------------------------------------------------------------- 143 // Register set definitions. The first definitions at register set index of 144 // zero is for all registers, followed by other registers sets. The register 145 // information for the all register set need not be filled in. 146 //---------------------------------------------------------------------- 147 static const RegisterSet g_reg_sets[] = { 148 { 149 "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, 150 }, 151 {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums}, 152 {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}}; 153 154 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets); 155 156 size_t RegisterContextDarwin_arm64::GetRegisterSetCount() { 157 return k_num_regsets; 158 } 159 160 const RegisterSet *RegisterContextDarwin_arm64::GetRegisterSet(size_t reg_set) { 161 if (reg_set < k_num_regsets) 162 return &g_reg_sets[reg_set]; 163 return NULL; 164 } 165 166 //---------------------------------------------------------------------- 167 // Register information definitions for arm64 168 //---------------------------------------------------------------------- 169 int RegisterContextDarwin_arm64::GetSetForNativeRegNum(int reg) { 170 if (reg < fpu_v0) 171 return GPRRegSet; 172 else if (reg < exc_far) 173 return FPURegSet; 174 else if (reg < k_num_registers) 175 return EXCRegSet; 176 return -1; 177 } 178 179 int RegisterContextDarwin_arm64::ReadGPR(bool force) { 180 int set = GPRRegSet; 181 if (force || !RegisterSetIsCached(set)) { 182 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr)); 183 } 184 return GetError(GPRRegSet, Read); 185 } 186 187 int RegisterContextDarwin_arm64::ReadFPU(bool force) { 188 int set = FPURegSet; 189 if (force || !RegisterSetIsCached(set)) { 190 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu)); 191 } 192 return GetError(FPURegSet, Read); 193 } 194 195 int RegisterContextDarwin_arm64::ReadEXC(bool force) { 196 int set = EXCRegSet; 197 if (force || !RegisterSetIsCached(set)) { 198 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc)); 199 } 200 return GetError(EXCRegSet, Read); 201 } 202 203 int RegisterContextDarwin_arm64::ReadDBG(bool force) { 204 int set = DBGRegSet; 205 if (force || !RegisterSetIsCached(set)) { 206 SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg)); 207 } 208 return GetError(DBGRegSet, Read); 209 } 210 211 int RegisterContextDarwin_arm64::WriteGPR() { 212 int set = GPRRegSet; 213 if (!RegisterSetIsCached(set)) { 214 SetError(set, Write, -1); 215 return KERN_INVALID_ARGUMENT; 216 } 217 SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr)); 218 SetError(set, Read, -1); 219 return GetError(GPRRegSet, Write); 220 } 221 222 int RegisterContextDarwin_arm64::WriteFPU() { 223 int set = FPURegSet; 224 if (!RegisterSetIsCached(set)) { 225 SetError(set, Write, -1); 226 return KERN_INVALID_ARGUMENT; 227 } 228 SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu)); 229 SetError(set, Read, -1); 230 return GetError(FPURegSet, Write); 231 } 232 233 int RegisterContextDarwin_arm64::WriteEXC() { 234 int set = EXCRegSet; 235 if (!RegisterSetIsCached(set)) { 236 SetError(set, Write, -1); 237 return KERN_INVALID_ARGUMENT; 238 } 239 SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc)); 240 SetError(set, Read, -1); 241 return GetError(EXCRegSet, Write); 242 } 243 244 int RegisterContextDarwin_arm64::WriteDBG() { 245 int set = DBGRegSet; 246 if (!RegisterSetIsCached(set)) { 247 SetError(set, Write, -1); 248 return KERN_INVALID_ARGUMENT; 249 } 250 SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg)); 251 SetError(set, Read, -1); 252 return GetError(DBGRegSet, Write); 253 } 254 255 int RegisterContextDarwin_arm64::ReadRegisterSet(uint32_t set, bool force) { 256 switch (set) { 257 case GPRRegSet: 258 return ReadGPR(force); 259 case FPURegSet: 260 return ReadFPU(force); 261 case EXCRegSet: 262 return ReadEXC(force); 263 case DBGRegSet: 264 return ReadDBG(force); 265 default: 266 break; 267 } 268 return KERN_INVALID_ARGUMENT; 269 } 270 271 int RegisterContextDarwin_arm64::WriteRegisterSet(uint32_t set) { 272 // Make sure we have a valid context to set. 273 if (RegisterSetIsCached(set)) { 274 switch (set) { 275 case GPRRegSet: 276 return WriteGPR(); 277 case FPURegSet: 278 return WriteFPU(); 279 case EXCRegSet: 280 return WriteEXC(); 281 case DBGRegSet: 282 return WriteDBG(); 283 default: 284 break; 285 } 286 } 287 return KERN_INVALID_ARGUMENT; 288 } 289 290 void RegisterContextDarwin_arm64::LogDBGRegisters(Log *log, const DBG &dbg) { 291 if (log) { 292 for (uint32_t i = 0; i < 16; i++) 293 log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8" PRIu64 ", 0x%8.8" PRIu64 294 " } WVR%-2u/WCR%-2u " 295 "= { 0x%8.8" PRIu64 ", 0x%8.8" PRIu64 " }", 296 i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]); 297 } 298 } 299 300 bool RegisterContextDarwin_arm64::ReadRegister(const RegisterInfo *reg_info, 301 RegisterValue &value) { 302 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 303 int set = RegisterContextDarwin_arm64::GetSetForNativeRegNum(reg); 304 305 if (set == -1) 306 return false; 307 308 if (ReadRegisterSet(set, false) != KERN_SUCCESS) 309 return false; 310 311 switch (reg) { 312 case gpr_x0: 313 case gpr_x1: 314 case gpr_x2: 315 case gpr_x3: 316 case gpr_x4: 317 case gpr_x5: 318 case gpr_x6: 319 case gpr_x7: 320 case gpr_x8: 321 case gpr_x9: 322 case gpr_x10: 323 case gpr_x11: 324 case gpr_x12: 325 case gpr_x13: 326 case gpr_x14: 327 case gpr_x15: 328 case gpr_x16: 329 case gpr_x17: 330 case gpr_x18: 331 case gpr_x19: 332 case gpr_x20: 333 case gpr_x21: 334 case gpr_x22: 335 case gpr_x23: 336 case gpr_x24: 337 case gpr_x25: 338 case gpr_x26: 339 case gpr_x27: 340 case gpr_x28: 341 case gpr_fp: 342 case gpr_sp: 343 case gpr_lr: 344 case gpr_pc: 345 case gpr_cpsr: 346 value.SetUInt64(gpr.x[reg - gpr_x0]); 347 break; 348 349 case gpr_w0: 350 case gpr_w1: 351 case gpr_w2: 352 case gpr_w3: 353 case gpr_w4: 354 case gpr_w5: 355 case gpr_w6: 356 case gpr_w7: 357 case gpr_w8: 358 case gpr_w9: 359 case gpr_w10: 360 case gpr_w11: 361 case gpr_w12: 362 case gpr_w13: 363 case gpr_w14: 364 case gpr_w15: 365 case gpr_w16: 366 case gpr_w17: 367 case gpr_w18: 368 case gpr_w19: 369 case gpr_w20: 370 case gpr_w21: 371 case gpr_w22: 372 case gpr_w23: 373 case gpr_w24: 374 case gpr_w25: 375 case gpr_w26: 376 case gpr_w27: 377 case gpr_w28: { 378 ProcessSP process_sp(m_thread.GetProcess()); 379 if (process_sp.get()) { 380 DataExtractor regdata(&gpr.x[reg - gpr_w0], 8, process_sp->GetByteOrder(), 381 process_sp->GetAddressByteSize()); 382 offset_t offset = 0; 383 uint64_t retval = regdata.GetMaxU64(&offset, 8); 384 uint32_t retval_lower32 = static_cast<uint32_t>(retval & 0xffffffff); 385 value.SetUInt32(retval_lower32); 386 } 387 } break; 388 389 case fpu_v0: 390 case fpu_v1: 391 case fpu_v2: 392 case fpu_v3: 393 case fpu_v4: 394 case fpu_v5: 395 case fpu_v6: 396 case fpu_v7: 397 case fpu_v8: 398 case fpu_v9: 399 case fpu_v10: 400 case fpu_v11: 401 case fpu_v12: 402 case fpu_v13: 403 case fpu_v14: 404 case fpu_v15: 405 case fpu_v16: 406 case fpu_v17: 407 case fpu_v18: 408 case fpu_v19: 409 case fpu_v20: 410 case fpu_v21: 411 case fpu_v22: 412 case fpu_v23: 413 case fpu_v24: 414 case fpu_v25: 415 case fpu_v26: 416 case fpu_v27: 417 case fpu_v28: 418 case fpu_v29: 419 case fpu_v30: 420 case fpu_v31: 421 value.SetBytes(fpu.v[reg].bytes.buffer, reg_info->byte_size, 422 endian::InlHostByteOrder()); 423 break; 424 425 case fpu_s0: 426 case fpu_s1: 427 case fpu_s2: 428 case fpu_s3: 429 case fpu_s4: 430 case fpu_s5: 431 case fpu_s6: 432 case fpu_s7: 433 case fpu_s8: 434 case fpu_s9: 435 case fpu_s10: 436 case fpu_s11: 437 case fpu_s12: 438 case fpu_s13: 439 case fpu_s14: 440 case fpu_s15: 441 case fpu_s16: 442 case fpu_s17: 443 case fpu_s18: 444 case fpu_s19: 445 case fpu_s20: 446 case fpu_s21: 447 case fpu_s22: 448 case fpu_s23: 449 case fpu_s24: 450 case fpu_s25: 451 case fpu_s26: 452 case fpu_s27: 453 case fpu_s28: 454 case fpu_s29: 455 case fpu_s30: 456 case fpu_s31: { 457 ProcessSP process_sp(m_thread.GetProcess()); 458 if (process_sp.get()) { 459 DataExtractor regdata(&fpu.v[reg - fpu_s0], 4, process_sp->GetByteOrder(), 460 process_sp->GetAddressByteSize()); 461 offset_t offset = 0; 462 value.SetFloat(regdata.GetFloat(&offset)); 463 } 464 } break; 465 466 case fpu_d0: 467 case fpu_d1: 468 case fpu_d2: 469 case fpu_d3: 470 case fpu_d4: 471 case fpu_d5: 472 case fpu_d6: 473 case fpu_d7: 474 case fpu_d8: 475 case fpu_d9: 476 case fpu_d10: 477 case fpu_d11: 478 case fpu_d12: 479 case fpu_d13: 480 case fpu_d14: 481 case fpu_d15: 482 case fpu_d16: 483 case fpu_d17: 484 case fpu_d18: 485 case fpu_d19: 486 case fpu_d20: 487 case fpu_d21: 488 case fpu_d22: 489 case fpu_d23: 490 case fpu_d24: 491 case fpu_d25: 492 case fpu_d26: 493 case fpu_d27: 494 case fpu_d28: 495 case fpu_d29: 496 case fpu_d30: 497 case fpu_d31: { 498 ProcessSP process_sp(m_thread.GetProcess()); 499 if (process_sp.get()) { 500 DataExtractor regdata(&fpu.v[reg - fpu_s0], 8, process_sp->GetByteOrder(), 501 process_sp->GetAddressByteSize()); 502 offset_t offset = 0; 503 value.SetDouble(regdata.GetDouble(&offset)); 504 } 505 } break; 506 507 case fpu_fpsr: 508 value.SetUInt32(fpu.fpsr); 509 break; 510 511 case fpu_fpcr: 512 value.SetUInt32(fpu.fpcr); 513 break; 514 515 case exc_exception: 516 value.SetUInt32(exc.exception); 517 break; 518 case exc_esr: 519 value.SetUInt32(exc.esr); 520 break; 521 case exc_far: 522 value.SetUInt64(exc.far); 523 break; 524 525 default: 526 value.SetValueToInvalid(); 527 return false; 528 } 529 return true; 530 } 531 532 bool RegisterContextDarwin_arm64::WriteRegister(const RegisterInfo *reg_info, 533 const RegisterValue &value) { 534 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 535 int set = GetSetForNativeRegNum(reg); 536 537 if (set == -1) 538 return false; 539 540 if (ReadRegisterSet(set, false) != KERN_SUCCESS) 541 return false; 542 543 switch (reg) { 544 case gpr_x0: 545 case gpr_x1: 546 case gpr_x2: 547 case gpr_x3: 548 case gpr_x4: 549 case gpr_x5: 550 case gpr_x6: 551 case gpr_x7: 552 case gpr_x8: 553 case gpr_x9: 554 case gpr_x10: 555 case gpr_x11: 556 case gpr_x12: 557 case gpr_x13: 558 case gpr_x14: 559 case gpr_x15: 560 case gpr_x16: 561 case gpr_x17: 562 case gpr_x18: 563 case gpr_x19: 564 case gpr_x20: 565 case gpr_x21: 566 case gpr_x22: 567 case gpr_x23: 568 case gpr_x24: 569 case gpr_x25: 570 case gpr_x26: 571 case gpr_x27: 572 case gpr_x28: 573 case gpr_fp: 574 case gpr_sp: 575 case gpr_lr: 576 case gpr_pc: 577 case gpr_cpsr: 578 gpr.x[reg - gpr_x0] = value.GetAsUInt64(); 579 break; 580 581 case fpu_v0: 582 case fpu_v1: 583 case fpu_v2: 584 case fpu_v3: 585 case fpu_v4: 586 case fpu_v5: 587 case fpu_v6: 588 case fpu_v7: 589 case fpu_v8: 590 case fpu_v9: 591 case fpu_v10: 592 case fpu_v11: 593 case fpu_v12: 594 case fpu_v13: 595 case fpu_v14: 596 case fpu_v15: 597 case fpu_v16: 598 case fpu_v17: 599 case fpu_v18: 600 case fpu_v19: 601 case fpu_v20: 602 case fpu_v21: 603 case fpu_v22: 604 case fpu_v23: 605 case fpu_v24: 606 case fpu_v25: 607 case fpu_v26: 608 case fpu_v27: 609 case fpu_v28: 610 case fpu_v29: 611 case fpu_v30: 612 case fpu_v31: 613 ::memcpy(fpu.v[reg].bytes.buffer, value.GetBytes(), value.GetByteSize()); 614 break; 615 616 case fpu_fpsr: 617 fpu.fpsr = value.GetAsUInt32(); 618 break; 619 620 case fpu_fpcr: 621 fpu.fpcr = value.GetAsUInt32(); 622 break; 623 624 case exc_exception: 625 exc.exception = value.GetAsUInt32(); 626 break; 627 case exc_esr: 628 exc.esr = value.GetAsUInt32(); 629 break; 630 case exc_far: 631 exc.far = value.GetAsUInt64(); 632 break; 633 634 default: 635 return false; 636 } 637 return WriteRegisterSet(set) == KERN_SUCCESS; 638 } 639 640 bool RegisterContextDarwin_arm64::ReadAllRegisterValues( 641 lldb::DataBufferSP &data_sp) { 642 data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0)); 643 if (data_sp && ReadGPR(false) == KERN_SUCCESS && 644 ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) { 645 uint8_t *dst = data_sp->GetBytes(); 646 ::memcpy(dst, &gpr, sizeof(gpr)); 647 dst += sizeof(gpr); 648 649 ::memcpy(dst, &fpu, sizeof(fpu)); 650 dst += sizeof(gpr); 651 652 ::memcpy(dst, &exc, sizeof(exc)); 653 return true; 654 } 655 return false; 656 } 657 658 bool RegisterContextDarwin_arm64::WriteAllRegisterValues( 659 const lldb::DataBufferSP &data_sp) { 660 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) { 661 const uint8_t *src = data_sp->GetBytes(); 662 ::memcpy(&gpr, src, sizeof(gpr)); 663 src += sizeof(gpr); 664 665 ::memcpy(&fpu, src, sizeof(fpu)); 666 src += sizeof(gpr); 667 668 ::memcpy(&exc, src, sizeof(exc)); 669 uint32_t success_count = 0; 670 if (WriteGPR() == KERN_SUCCESS) 671 ++success_count; 672 if (WriteFPU() == KERN_SUCCESS) 673 ++success_count; 674 if (WriteEXC() == KERN_SUCCESS) 675 ++success_count; 676 return success_count == 3; 677 } 678 return false; 679 } 680 681 uint32_t RegisterContextDarwin_arm64::ConvertRegisterKindToRegisterNumber( 682 RegisterKind kind, uint32_t reg) { 683 if (kind == eRegisterKindGeneric) { 684 switch (reg) { 685 case LLDB_REGNUM_GENERIC_PC: 686 return gpr_pc; 687 case LLDB_REGNUM_GENERIC_SP: 688 return gpr_sp; 689 case LLDB_REGNUM_GENERIC_FP: 690 return gpr_fp; 691 case LLDB_REGNUM_GENERIC_RA: 692 return gpr_lr; 693 case LLDB_REGNUM_GENERIC_FLAGS: 694 return gpr_cpsr; 695 default: 696 break; 697 } 698 } else if (kind == eRegisterKindDWARF) { 699 switch (reg) { 700 case arm64_dwarf::x0: 701 return gpr_x0; 702 case arm64_dwarf::x1: 703 return gpr_x1; 704 case arm64_dwarf::x2: 705 return gpr_x2; 706 case arm64_dwarf::x3: 707 return gpr_x3; 708 case arm64_dwarf::x4: 709 return gpr_x4; 710 case arm64_dwarf::x5: 711 return gpr_x5; 712 case arm64_dwarf::x6: 713 return gpr_x6; 714 case arm64_dwarf::x7: 715 return gpr_x7; 716 case arm64_dwarf::x8: 717 return gpr_x8; 718 case arm64_dwarf::x9: 719 return gpr_x9; 720 case arm64_dwarf::x10: 721 return gpr_x10; 722 case arm64_dwarf::x11: 723 return gpr_x11; 724 case arm64_dwarf::x12: 725 return gpr_x12; 726 case arm64_dwarf::x13: 727 return gpr_x13; 728 case arm64_dwarf::x14: 729 return gpr_x14; 730 case arm64_dwarf::x15: 731 return gpr_x15; 732 case arm64_dwarf::x16: 733 return gpr_x16; 734 case arm64_dwarf::x17: 735 return gpr_x17; 736 case arm64_dwarf::x18: 737 return gpr_x18; 738 case arm64_dwarf::x19: 739 return gpr_x19; 740 case arm64_dwarf::x20: 741 return gpr_x20; 742 case arm64_dwarf::x21: 743 return gpr_x21; 744 case arm64_dwarf::x22: 745 return gpr_x22; 746 case arm64_dwarf::x23: 747 return gpr_x23; 748 case arm64_dwarf::x24: 749 return gpr_x24; 750 case arm64_dwarf::x25: 751 return gpr_x25; 752 case arm64_dwarf::x26: 753 return gpr_x26; 754 case arm64_dwarf::x27: 755 return gpr_x27; 756 case arm64_dwarf::x28: 757 return gpr_x28; 758 759 case arm64_dwarf::fp: 760 return gpr_fp; 761 case arm64_dwarf::sp: 762 return gpr_sp; 763 case arm64_dwarf::lr: 764 return gpr_lr; 765 case arm64_dwarf::pc: 766 return gpr_pc; 767 case arm64_dwarf::cpsr: 768 return gpr_cpsr; 769 770 case arm64_dwarf::v0: 771 return fpu_v0; 772 case arm64_dwarf::v1: 773 return fpu_v1; 774 case arm64_dwarf::v2: 775 return fpu_v2; 776 case arm64_dwarf::v3: 777 return fpu_v3; 778 case arm64_dwarf::v4: 779 return fpu_v4; 780 case arm64_dwarf::v5: 781 return fpu_v5; 782 case arm64_dwarf::v6: 783 return fpu_v6; 784 case arm64_dwarf::v7: 785 return fpu_v7; 786 case arm64_dwarf::v8: 787 return fpu_v8; 788 case arm64_dwarf::v9: 789 return fpu_v9; 790 case arm64_dwarf::v10: 791 return fpu_v10; 792 case arm64_dwarf::v11: 793 return fpu_v11; 794 case arm64_dwarf::v12: 795 return fpu_v12; 796 case arm64_dwarf::v13: 797 return fpu_v13; 798 case arm64_dwarf::v14: 799 return fpu_v14; 800 case arm64_dwarf::v15: 801 return fpu_v15; 802 case arm64_dwarf::v16: 803 return fpu_v16; 804 case arm64_dwarf::v17: 805 return fpu_v17; 806 case arm64_dwarf::v18: 807 return fpu_v18; 808 case arm64_dwarf::v19: 809 return fpu_v19; 810 case arm64_dwarf::v20: 811 return fpu_v20; 812 case arm64_dwarf::v21: 813 return fpu_v21; 814 case arm64_dwarf::v22: 815 return fpu_v22; 816 case arm64_dwarf::v23: 817 return fpu_v23; 818 case arm64_dwarf::v24: 819 return fpu_v24; 820 case arm64_dwarf::v25: 821 return fpu_v25; 822 case arm64_dwarf::v26: 823 return fpu_v26; 824 case arm64_dwarf::v27: 825 return fpu_v27; 826 case arm64_dwarf::v28: 827 return fpu_v28; 828 case arm64_dwarf::v29: 829 return fpu_v29; 830 case arm64_dwarf::v30: 831 return fpu_v30; 832 case arm64_dwarf::v31: 833 return fpu_v31; 834 835 default: 836 break; 837 } 838 } else if (kind == eRegisterKindEHFrame) { 839 switch (reg) { 840 case arm64_ehframe::x0: 841 return gpr_x0; 842 case arm64_ehframe::x1: 843 return gpr_x1; 844 case arm64_ehframe::x2: 845 return gpr_x2; 846 case arm64_ehframe::x3: 847 return gpr_x3; 848 case arm64_ehframe::x4: 849 return gpr_x4; 850 case arm64_ehframe::x5: 851 return gpr_x5; 852 case arm64_ehframe::x6: 853 return gpr_x6; 854 case arm64_ehframe::x7: 855 return gpr_x7; 856 case arm64_ehframe::x8: 857 return gpr_x8; 858 case arm64_ehframe::x9: 859 return gpr_x9; 860 case arm64_ehframe::x10: 861 return gpr_x10; 862 case arm64_ehframe::x11: 863 return gpr_x11; 864 case arm64_ehframe::x12: 865 return gpr_x12; 866 case arm64_ehframe::x13: 867 return gpr_x13; 868 case arm64_ehframe::x14: 869 return gpr_x14; 870 case arm64_ehframe::x15: 871 return gpr_x15; 872 case arm64_ehframe::x16: 873 return gpr_x16; 874 case arm64_ehframe::x17: 875 return gpr_x17; 876 case arm64_ehframe::x18: 877 return gpr_x18; 878 case arm64_ehframe::x19: 879 return gpr_x19; 880 case arm64_ehframe::x20: 881 return gpr_x20; 882 case arm64_ehframe::x21: 883 return gpr_x21; 884 case arm64_ehframe::x22: 885 return gpr_x22; 886 case arm64_ehframe::x23: 887 return gpr_x23; 888 case arm64_ehframe::x24: 889 return gpr_x24; 890 case arm64_ehframe::x25: 891 return gpr_x25; 892 case arm64_ehframe::x26: 893 return gpr_x26; 894 case arm64_ehframe::x27: 895 return gpr_x27; 896 case arm64_ehframe::x28: 897 return gpr_x28; 898 case arm64_ehframe::fp: 899 return gpr_fp; 900 case arm64_ehframe::sp: 901 return gpr_sp; 902 case arm64_ehframe::lr: 903 return gpr_lr; 904 case arm64_ehframe::pc: 905 return gpr_pc; 906 case arm64_ehframe::cpsr: 907 return gpr_cpsr; 908 } 909 } else if (kind == eRegisterKindLLDB) { 910 return reg; 911 } 912 return LLDB_INVALID_REGNUM; 913 } 914 915 uint32_t RegisterContextDarwin_arm64::NumSupportedHardwareWatchpoints() { 916 #if defined(__APPLE__) && (defined(__arm64__) || defined(__aarch64__)) 917 // autodetect how many watchpoints are supported dynamically... 918 static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX; 919 if (g_num_supported_hw_watchpoints == UINT32_MAX) { 920 size_t len; 921 uint32_t n = 0; 922 len = sizeof(n); 923 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) { 924 g_num_supported_hw_watchpoints = n; 925 } 926 } 927 return g_num_supported_hw_watchpoints; 928 #else 929 // TODO: figure out remote case here! 930 return 2; 931 #endif 932 } 933 934 uint32_t RegisterContextDarwin_arm64::SetHardwareWatchpoint(lldb::addr_t addr, 935 size_t size, 936 bool read, 937 bool write) { 938 // if (log) log->Printf 939 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint(addr = %8.8p, 940 // size = %u, read = %u, write = %u)", addr, size, read, write); 941 942 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 943 944 // Can't watch zero bytes 945 if (size == 0) 946 return LLDB_INVALID_INDEX32; 947 948 // We must watch for either read or write 949 if (read == false && write == false) 950 return LLDB_INVALID_INDEX32; 951 952 // Can't watch more than 4 bytes per WVR/WCR pair 953 if (size > 4) 954 return LLDB_INVALID_INDEX32; 955 956 // We can only watch up to four bytes that follow a 4 byte aligned address 957 // per watchpoint register pair. Since we have at most so we can only watch 958 // until the next 4 byte boundary and we need to make sure we can properly 959 // encode this. 960 uint32_t addr_word_offset = addr % 4; 961 // if (log) log->Printf 962 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() - 963 // addr_word_offset = 0x%8.8x", addr_word_offset); 964 965 uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset; 966 // if (log) log->Printf 967 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() - byte_mask = 968 // 0x%8.8x", byte_mask); 969 if (byte_mask > 0xfu) 970 return LLDB_INVALID_INDEX32; 971 972 // Read the debug state 973 int kret = ReadDBG(false); 974 975 if (kret == KERN_SUCCESS) { 976 // Check to make sure we have the needed hardware support 977 uint32_t i = 0; 978 979 for (i = 0; i < num_hw_watchpoints; ++i) { 980 if ((dbg.wcr[i] & WCR_ENABLE) == 0) 981 break; // We found an available hw breakpoint slot (in i) 982 } 983 984 // See if we found an available hw breakpoint slot above 985 if (i < num_hw_watchpoints) { 986 // Make the byte_mask into a valid Byte Address Select mask 987 uint32_t byte_address_select = byte_mask << 5; 988 // Make sure bits 1:0 are clear in our address 989 dbg.wvr[i] = addr & ~((lldb::addr_t)3); 990 dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA 991 // that we will watch 992 S_USER | // Stop only in user mode 993 (read ? WCR_LOAD : 0) | // Stop on read access? 994 (write ? WCR_STORE : 0) | // Stop on write access? 995 WCR_ENABLE; // Enable this watchpoint; 996 997 kret = WriteDBG(); 998 // if (log) log->Printf 999 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() 1000 // WriteDBG() => 0x%8.8x.", kret); 1001 1002 if (kret == KERN_SUCCESS) 1003 return i; 1004 } else { 1005 // if (log) log->Printf 1006 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint(): 1007 // All hardware resources (%u) are in use.", 1008 // num_hw_watchpoints); 1009 } 1010 } 1011 return LLDB_INVALID_INDEX32; 1012 } 1013 1014 bool RegisterContextDarwin_arm64::ClearHardwareWatchpoint(uint32_t hw_index) { 1015 int kret = ReadDBG(false); 1016 1017 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 1018 if (kret == KERN_SUCCESS) { 1019 if (hw_index < num_hw_points) { 1020 dbg.wcr[hw_index] = 0; 1021 // if (log) log->Printf 1022 // ("RegisterContextDarwin_arm64::ClearHardwareWatchpoint( %u ) 1023 // - WVR%u = 0x%8.8x WCR%u = 0x%8.8x", 1024 // hw_index, 1025 // hw_index, 1026 // dbg.wvr[hw_index], 1027 // hw_index, 1028 // dbg.wcr[hw_index]); 1029 1030 kret = WriteDBG(); 1031 1032 if (kret == KERN_SUCCESS) 1033 return true; 1034 } 1035 } 1036 return false; 1037 } 1038