1a63d08c9SGreg Clayton //===-- RegisterContextDarwin_arm.cpp ---------------------------*- C++ -*-===// 2a63d08c9SGreg Clayton // 3a63d08c9SGreg Clayton // The LLVM Compiler Infrastructure 4a63d08c9SGreg Clayton // 5a63d08c9SGreg Clayton // This file is distributed under the University of Illinois Open Source 6a63d08c9SGreg Clayton // License. See LICENSE.TXT for details. 7a63d08c9SGreg Clayton // 8a63d08c9SGreg Clayton //===----------------------------------------------------------------------===// 9a63d08c9SGreg Clayton 10a63d08c9SGreg Clayton #include "RegisterContextDarwin_arm.h" 11981a34c4SPavel Labath #include "RegisterContextDarwinConstants.h" 12a63d08c9SGreg Clayton 13a63d08c9SGreg Clayton // C++ Includes 14a63d08c9SGreg Clayton // Other libraries and framework includes 15a63d08c9SGreg Clayton #include "lldb/Core/RegisterValue.h" 16a63d08c9SGreg Clayton #include "lldb/Core/Scalar.h" 17666cc0b2SZachary Turner #include "lldb/Utility/DataBufferHeap.h" 18666cc0b2SZachary Turner #include "lldb/Utility/DataExtractor.h" 1901c3243fSZachary Turner #include "lldb/Utility/Endian.h" 206f9e6901SZachary Turner #include "lldb/Utility/Log.h" 2112a19904SDaniel Dunbar #include "llvm/Support/Compiler.h" 2212a19904SDaniel Dunbar 23dce502edSGreg Clayton #include "Plugins/Process/Utility/InstructionUtils.h" 24dce502edSGreg Clayton 2512a19904SDaniel Dunbar // Support building against older versions of LLVM, this macro was added 2612a19904SDaniel Dunbar // recently. 2712a19904SDaniel Dunbar #ifndef LLVM_EXTENSION 2812a19904SDaniel Dunbar #define LLVM_EXTENSION 2912a19904SDaniel Dunbar #endif 30a63d08c9SGreg Clayton 31a63d08c9SGreg Clayton // Project includes 32*ff9c4ff1SEric Liu #include "Utility/ARM_DWARF_Registers.h" 3363bd0db0SJason Molenda #include "Utility/ARM_ehframe_Registers.h" 34a63d08c9SGreg Clayton 3528606954SSaleem Abdulrasool #include "llvm/ADT/STLExtras.h" 3628606954SSaleem Abdulrasool 37a63d08c9SGreg Clayton using namespace lldb; 38a63d08c9SGreg Clayton using namespace lldb_private; 39a63d08c9SGreg Clayton 40b9c1b51eSKate Stone enum { 41a63d08c9SGreg Clayton gpr_r0 = 0, 42a63d08c9SGreg Clayton gpr_r1, 43a63d08c9SGreg Clayton gpr_r2, 44a63d08c9SGreg Clayton gpr_r3, 45a63d08c9SGreg Clayton gpr_r4, 46a63d08c9SGreg Clayton gpr_r5, 47a63d08c9SGreg Clayton gpr_r6, 48a63d08c9SGreg Clayton gpr_r7, 49a63d08c9SGreg Clayton gpr_r8, 50a63d08c9SGreg Clayton gpr_r9, 51a63d08c9SGreg Clayton gpr_r10, 52a63d08c9SGreg Clayton gpr_r11, 53a63d08c9SGreg Clayton gpr_r12, 54b9c1b51eSKate Stone gpr_r13, 55b9c1b51eSKate Stone gpr_sp = gpr_r13, 56b9c1b51eSKate Stone gpr_r14, 57b9c1b51eSKate Stone gpr_lr = gpr_r14, 58b9c1b51eSKate Stone gpr_r15, 59b9c1b51eSKate Stone gpr_pc = gpr_r15, 60a63d08c9SGreg Clayton gpr_cpsr, 61a63d08c9SGreg Clayton 62a63d08c9SGreg Clayton fpu_s0, 63a63d08c9SGreg Clayton fpu_s1, 64a63d08c9SGreg Clayton fpu_s2, 65a63d08c9SGreg Clayton fpu_s3, 66a63d08c9SGreg Clayton fpu_s4, 67a63d08c9SGreg Clayton fpu_s5, 68a63d08c9SGreg Clayton fpu_s6, 69a63d08c9SGreg Clayton fpu_s7, 70a63d08c9SGreg Clayton fpu_s8, 71a63d08c9SGreg Clayton fpu_s9, 72a63d08c9SGreg Clayton fpu_s10, 73a63d08c9SGreg Clayton fpu_s11, 74a63d08c9SGreg Clayton fpu_s12, 75a63d08c9SGreg Clayton fpu_s13, 76a63d08c9SGreg Clayton fpu_s14, 77a63d08c9SGreg Clayton fpu_s15, 78a63d08c9SGreg Clayton fpu_s16, 79a63d08c9SGreg Clayton fpu_s17, 80a63d08c9SGreg Clayton fpu_s18, 81a63d08c9SGreg Clayton fpu_s19, 82a63d08c9SGreg Clayton fpu_s20, 83a63d08c9SGreg Clayton fpu_s21, 84a63d08c9SGreg Clayton fpu_s22, 85a63d08c9SGreg Clayton fpu_s23, 86a63d08c9SGreg Clayton fpu_s24, 87a63d08c9SGreg Clayton fpu_s25, 88a63d08c9SGreg Clayton fpu_s26, 89a63d08c9SGreg Clayton fpu_s27, 90a63d08c9SGreg Clayton fpu_s28, 91a63d08c9SGreg Clayton fpu_s29, 92a63d08c9SGreg Clayton fpu_s30, 93a63d08c9SGreg Clayton fpu_s31, 94a63d08c9SGreg Clayton fpu_fpscr, 95a63d08c9SGreg Clayton 96a63d08c9SGreg Clayton exc_exception, 97a63d08c9SGreg Clayton exc_fsr, 98a63d08c9SGreg Clayton exc_far, 99a63d08c9SGreg Clayton 100a63d08c9SGreg Clayton dbg_bvr0, 101a63d08c9SGreg Clayton dbg_bvr1, 102a63d08c9SGreg Clayton dbg_bvr2, 103a63d08c9SGreg Clayton dbg_bvr3, 104a63d08c9SGreg Clayton dbg_bvr4, 105a63d08c9SGreg Clayton dbg_bvr5, 106a63d08c9SGreg Clayton dbg_bvr6, 107a63d08c9SGreg Clayton dbg_bvr7, 108a63d08c9SGreg Clayton dbg_bvr8, 109a63d08c9SGreg Clayton dbg_bvr9, 110a63d08c9SGreg Clayton dbg_bvr10, 111a63d08c9SGreg Clayton dbg_bvr11, 112a63d08c9SGreg Clayton dbg_bvr12, 113a63d08c9SGreg Clayton dbg_bvr13, 114a63d08c9SGreg Clayton dbg_bvr14, 115a63d08c9SGreg Clayton dbg_bvr15, 116a63d08c9SGreg Clayton 117a63d08c9SGreg Clayton dbg_bcr0, 118a63d08c9SGreg Clayton dbg_bcr1, 119a63d08c9SGreg Clayton dbg_bcr2, 120a63d08c9SGreg Clayton dbg_bcr3, 121a63d08c9SGreg Clayton dbg_bcr4, 122a63d08c9SGreg Clayton dbg_bcr5, 123a63d08c9SGreg Clayton dbg_bcr6, 124a63d08c9SGreg Clayton dbg_bcr7, 125a63d08c9SGreg Clayton dbg_bcr8, 126a63d08c9SGreg Clayton dbg_bcr9, 127a63d08c9SGreg Clayton dbg_bcr10, 128a63d08c9SGreg Clayton dbg_bcr11, 129a63d08c9SGreg Clayton dbg_bcr12, 130a63d08c9SGreg Clayton dbg_bcr13, 131a63d08c9SGreg Clayton dbg_bcr14, 132a63d08c9SGreg Clayton dbg_bcr15, 133a63d08c9SGreg Clayton 134a63d08c9SGreg Clayton dbg_wvr0, 135a63d08c9SGreg Clayton dbg_wvr1, 136a63d08c9SGreg Clayton dbg_wvr2, 137a63d08c9SGreg Clayton dbg_wvr3, 138a63d08c9SGreg Clayton dbg_wvr4, 139a63d08c9SGreg Clayton dbg_wvr5, 140a63d08c9SGreg Clayton dbg_wvr6, 141a63d08c9SGreg Clayton dbg_wvr7, 142a63d08c9SGreg Clayton dbg_wvr8, 143a63d08c9SGreg Clayton dbg_wvr9, 144a63d08c9SGreg Clayton dbg_wvr10, 145a63d08c9SGreg Clayton dbg_wvr11, 146a63d08c9SGreg Clayton dbg_wvr12, 147a63d08c9SGreg Clayton dbg_wvr13, 148a63d08c9SGreg Clayton dbg_wvr14, 149a63d08c9SGreg Clayton dbg_wvr15, 150a63d08c9SGreg Clayton 151a63d08c9SGreg Clayton dbg_wcr0, 152a63d08c9SGreg Clayton dbg_wcr1, 153a63d08c9SGreg Clayton dbg_wcr2, 154a63d08c9SGreg Clayton dbg_wcr3, 155a63d08c9SGreg Clayton dbg_wcr4, 156a63d08c9SGreg Clayton dbg_wcr5, 157a63d08c9SGreg Clayton dbg_wcr6, 158a63d08c9SGreg Clayton dbg_wcr7, 159a63d08c9SGreg Clayton dbg_wcr8, 160a63d08c9SGreg Clayton dbg_wcr9, 161a63d08c9SGreg Clayton dbg_wcr10, 162a63d08c9SGreg Clayton dbg_wcr11, 163a63d08c9SGreg Clayton dbg_wcr12, 164a63d08c9SGreg Clayton dbg_wcr13, 165a63d08c9SGreg Clayton dbg_wcr14, 166a63d08c9SGreg Clayton dbg_wcr15, 167a63d08c9SGreg Clayton 168a63d08c9SGreg Clayton k_num_registers 169a63d08c9SGreg Clayton }; 170a63d08c9SGreg Clayton 171a63d08c9SGreg Clayton #define GPR_OFFSET(idx) ((idx)*4) 172a63d08c9SGreg Clayton #define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR)) 173b9c1b51eSKate Stone #define EXC_OFFSET(idx) \ 174b9c1b51eSKate Stone ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR) + \ 175b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU)) 176b9c1b51eSKate Stone #define DBG_OFFSET(reg) \ 177b9c1b51eSKate Stone ((LLVM_EXTENSION offsetof(RegisterContextDarwin_arm::DBG, reg) + \ 178b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::GPR) + \ 179b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU) + \ 180b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::EXC))) 181a63d08c9SGreg Clayton 182b9c1b51eSKate Stone #define DEFINE_DBG(reg, i) \ 183b9c1b51eSKate Stone #reg, NULL, sizeof(((RegisterContextDarwin_arm::DBG *) NULL)->reg[i]), \ 184b9c1b51eSKate Stone DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, \ 185b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 186b9c1b51eSKate Stone LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 187b9c1b51eSKate Stone LLDB_INVALID_REGNUM }, \ 188b9c1b51eSKate Stone nullptr, nullptr, nullptr, 0 189b9c1b51eSKate Stone #define REG_CONTEXT_SIZE \ 190b9c1b51eSKate Stone (sizeof(RegisterContextDarwin_arm::GPR) + \ 191b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU) + \ 192b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::EXC)) 193a63d08c9SGreg Clayton 194a63d08c9SGreg Clayton static RegisterInfo g_register_infos[] = { 195a63d08c9SGreg Clayton // General purpose registers 196b9c1b51eSKate Stone // NAME ALT SZ OFFSET ENCODING FORMAT 197b9c1b51eSKate Stone // EH_FRAME DWARF GENERIC 198b9c1b51eSKate Stone // PROCESS PLUGIN LLDB NATIVE 199b9c1b51eSKate Stone // ====== ======= == ============= ============= ============ 200b9c1b51eSKate Stone // =============== =============== ========================= 201b9c1b51eSKate Stone // ===================== ============= 202b9c1b51eSKate Stone {"r0", 203b9c1b51eSKate Stone NULL, 204b9c1b51eSKate Stone 4, 205b9c1b51eSKate Stone GPR_OFFSET(0), 206b9c1b51eSKate Stone eEncodingUint, 207b9c1b51eSKate Stone eFormatHex, 208b9c1b51eSKate Stone {ehframe_r0, dwarf_r0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r0}, 209b9c1b51eSKate Stone nullptr, 210b9c1b51eSKate Stone nullptr, 211b9c1b51eSKate Stone nullptr, 212b9c1b51eSKate Stone 0}, 213b9c1b51eSKate Stone {"r1", 214b9c1b51eSKate Stone NULL, 215b9c1b51eSKate Stone 4, 216b9c1b51eSKate Stone GPR_OFFSET(1), 217b9c1b51eSKate Stone eEncodingUint, 218b9c1b51eSKate Stone eFormatHex, 219b9c1b51eSKate Stone {ehframe_r1, dwarf_r1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r1}, 220b9c1b51eSKate Stone nullptr, 221b9c1b51eSKate Stone nullptr, 222b9c1b51eSKate Stone nullptr, 223b9c1b51eSKate Stone 0}, 224b9c1b51eSKate Stone {"r2", 225b9c1b51eSKate Stone NULL, 226b9c1b51eSKate Stone 4, 227b9c1b51eSKate Stone GPR_OFFSET(2), 228b9c1b51eSKate Stone eEncodingUint, 229b9c1b51eSKate Stone eFormatHex, 230b9c1b51eSKate Stone {ehframe_r2, dwarf_r2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r2}, 231b9c1b51eSKate Stone nullptr, 232b9c1b51eSKate Stone nullptr, 233b9c1b51eSKate Stone nullptr, 234b9c1b51eSKate Stone 0}, 235b9c1b51eSKate Stone {"r3", 236b9c1b51eSKate Stone NULL, 237b9c1b51eSKate Stone 4, 238b9c1b51eSKate Stone GPR_OFFSET(3), 239b9c1b51eSKate Stone eEncodingUint, 240b9c1b51eSKate Stone eFormatHex, 241b9c1b51eSKate Stone {ehframe_r3, dwarf_r3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r3}, 242b9c1b51eSKate Stone nullptr, 243b9c1b51eSKate Stone nullptr, 244b9c1b51eSKate Stone nullptr, 245b9c1b51eSKate Stone 0}, 246b9c1b51eSKate Stone {"r4", 247b9c1b51eSKate Stone NULL, 248b9c1b51eSKate Stone 4, 249b9c1b51eSKate Stone GPR_OFFSET(4), 250b9c1b51eSKate Stone eEncodingUint, 251b9c1b51eSKate Stone eFormatHex, 252b9c1b51eSKate Stone {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4}, 253b9c1b51eSKate Stone nullptr, 254b9c1b51eSKate Stone nullptr, 255b9c1b51eSKate Stone nullptr, 256b9c1b51eSKate Stone 0}, 257b9c1b51eSKate Stone {"r5", 258b9c1b51eSKate Stone NULL, 259b9c1b51eSKate Stone 4, 260b9c1b51eSKate Stone GPR_OFFSET(5), 261b9c1b51eSKate Stone eEncodingUint, 262b9c1b51eSKate Stone eFormatHex, 263b9c1b51eSKate Stone {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5}, 264b9c1b51eSKate Stone nullptr, 265b9c1b51eSKate Stone nullptr, 266b9c1b51eSKate Stone nullptr, 267b9c1b51eSKate Stone 0}, 268b9c1b51eSKate Stone {"r6", 269b9c1b51eSKate Stone NULL, 270b9c1b51eSKate Stone 4, 271b9c1b51eSKate Stone GPR_OFFSET(6), 272b9c1b51eSKate Stone eEncodingUint, 273b9c1b51eSKate Stone eFormatHex, 274b9c1b51eSKate Stone {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6}, 275b9c1b51eSKate Stone nullptr, 276b9c1b51eSKate Stone nullptr, 277b9c1b51eSKate Stone nullptr, 278b9c1b51eSKate Stone 0}, 279b9c1b51eSKate Stone {"r7", 280b9c1b51eSKate Stone NULL, 281b9c1b51eSKate Stone 4, 282b9c1b51eSKate Stone GPR_OFFSET(7), 283b9c1b51eSKate Stone eEncodingUint, 284b9c1b51eSKate Stone eFormatHex, 285b9c1b51eSKate Stone {ehframe_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, 286b9c1b51eSKate Stone gpr_r7}, 287b9c1b51eSKate Stone nullptr, 288b9c1b51eSKate Stone nullptr, 289b9c1b51eSKate Stone nullptr, 290b9c1b51eSKate Stone 0}, 291b9c1b51eSKate Stone {"r8", 292b9c1b51eSKate Stone NULL, 293b9c1b51eSKate Stone 4, 294b9c1b51eSKate Stone GPR_OFFSET(8), 295b9c1b51eSKate Stone eEncodingUint, 296b9c1b51eSKate Stone eFormatHex, 297b9c1b51eSKate Stone {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8}, 298b9c1b51eSKate Stone nullptr, 299b9c1b51eSKate Stone nullptr, 300b9c1b51eSKate Stone nullptr, 301b9c1b51eSKate Stone 0}, 302b9c1b51eSKate Stone {"r9", 303b9c1b51eSKate Stone NULL, 304b9c1b51eSKate Stone 4, 305b9c1b51eSKate Stone GPR_OFFSET(9), 306b9c1b51eSKate Stone eEncodingUint, 307b9c1b51eSKate Stone eFormatHex, 308b9c1b51eSKate Stone {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9}, 309b9c1b51eSKate Stone nullptr, 310b9c1b51eSKate Stone nullptr, 311b9c1b51eSKate Stone nullptr, 312b9c1b51eSKate Stone 0}, 313b9c1b51eSKate Stone {"r10", 314b9c1b51eSKate Stone NULL, 315b9c1b51eSKate Stone 4, 316b9c1b51eSKate Stone GPR_OFFSET(10), 317b9c1b51eSKate Stone eEncodingUint, 318b9c1b51eSKate Stone eFormatHex, 319b9c1b51eSKate Stone {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 320b9c1b51eSKate Stone gpr_r10}, 321b9c1b51eSKate Stone nullptr, 322b9c1b51eSKate Stone nullptr, 323b9c1b51eSKate Stone nullptr, 324b9c1b51eSKate Stone 0}, 325b9c1b51eSKate Stone {"r11", 326b9c1b51eSKate Stone NULL, 327b9c1b51eSKate Stone 4, 328b9c1b51eSKate Stone GPR_OFFSET(11), 329b9c1b51eSKate Stone eEncodingUint, 330b9c1b51eSKate Stone eFormatHex, 331b9c1b51eSKate Stone {ehframe_r11, dwarf_r11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 332b9c1b51eSKate Stone gpr_r11}, 333b9c1b51eSKate Stone nullptr, 334b9c1b51eSKate Stone nullptr, 335b9c1b51eSKate Stone nullptr, 336b9c1b51eSKate Stone 0}, 337b9c1b51eSKate Stone {"r12", 338b9c1b51eSKate Stone NULL, 339b9c1b51eSKate Stone 4, 340b9c1b51eSKate Stone GPR_OFFSET(12), 341b9c1b51eSKate Stone eEncodingUint, 342b9c1b51eSKate Stone eFormatHex, 343b9c1b51eSKate Stone {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 344b9c1b51eSKate Stone gpr_r12}, 345b9c1b51eSKate Stone nullptr, 346b9c1b51eSKate Stone nullptr, 347b9c1b51eSKate Stone nullptr, 348b9c1b51eSKate Stone 0}, 349b9c1b51eSKate Stone {"sp", 350b9c1b51eSKate Stone "r13", 351b9c1b51eSKate Stone 4, 352b9c1b51eSKate Stone GPR_OFFSET(13), 353b9c1b51eSKate Stone eEncodingUint, 354b9c1b51eSKate Stone eFormatHex, 355b9c1b51eSKate Stone {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, 356b9c1b51eSKate Stone gpr_sp}, 357b9c1b51eSKate Stone nullptr, 358b9c1b51eSKate Stone nullptr, 359b9c1b51eSKate Stone nullptr, 360b9c1b51eSKate Stone 0}, 361b9c1b51eSKate Stone {"lr", 362b9c1b51eSKate Stone "r14", 363b9c1b51eSKate Stone 4, 364b9c1b51eSKate Stone GPR_OFFSET(14), 365b9c1b51eSKate Stone eEncodingUint, 366b9c1b51eSKate Stone eFormatHex, 367b9c1b51eSKate Stone {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, 368b9c1b51eSKate Stone gpr_lr}, 369b9c1b51eSKate Stone nullptr, 370b9c1b51eSKate Stone nullptr, 371b9c1b51eSKate Stone nullptr, 372b9c1b51eSKate Stone 0}, 373b9c1b51eSKate Stone {"pc", 374b9c1b51eSKate Stone "r15", 375b9c1b51eSKate Stone 4, 376b9c1b51eSKate Stone GPR_OFFSET(15), 377b9c1b51eSKate Stone eEncodingUint, 378b9c1b51eSKate Stone eFormatHex, 379b9c1b51eSKate Stone {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, 380b9c1b51eSKate Stone gpr_pc}, 381b9c1b51eSKate Stone nullptr, 382b9c1b51eSKate Stone nullptr, 383b9c1b51eSKate Stone nullptr, 384b9c1b51eSKate Stone 0}, 385b9c1b51eSKate Stone {"cpsr", 386b9c1b51eSKate Stone "psr", 387b9c1b51eSKate Stone 4, 388b9c1b51eSKate Stone GPR_OFFSET(16), 389b9c1b51eSKate Stone eEncodingUint, 390b9c1b51eSKate Stone eFormatHex, 391b9c1b51eSKate Stone {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM, 392b9c1b51eSKate Stone gpr_cpsr}, 393b9c1b51eSKate Stone nullptr, 394b9c1b51eSKate Stone nullptr, 395b9c1b51eSKate Stone nullptr, 396b9c1b51eSKate Stone 0}, 397a63d08c9SGreg Clayton 398b9c1b51eSKate Stone {"s0", 399b9c1b51eSKate Stone NULL, 400b9c1b51eSKate Stone 4, 401b9c1b51eSKate Stone FPU_OFFSET(0), 402b9c1b51eSKate Stone eEncodingIEEE754, 403b9c1b51eSKate Stone eFormatFloat, 404b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 405b9c1b51eSKate Stone fpu_s0}, 406b9c1b51eSKate Stone nullptr, 407b9c1b51eSKate Stone nullptr, 408b9c1b51eSKate Stone nullptr, 409b9c1b51eSKate Stone 0}, 410b9c1b51eSKate Stone {"s1", 411b9c1b51eSKate Stone NULL, 412b9c1b51eSKate Stone 4, 413b9c1b51eSKate Stone FPU_OFFSET(1), 414b9c1b51eSKate Stone eEncodingIEEE754, 415b9c1b51eSKate Stone eFormatFloat, 416b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 417b9c1b51eSKate Stone fpu_s1}, 418b9c1b51eSKate Stone nullptr, 419b9c1b51eSKate Stone nullptr, 420b9c1b51eSKate Stone nullptr, 421b9c1b51eSKate Stone 0}, 422b9c1b51eSKate Stone {"s2", 423b9c1b51eSKate Stone NULL, 424b9c1b51eSKate Stone 4, 425b9c1b51eSKate Stone FPU_OFFSET(2), 426b9c1b51eSKate Stone eEncodingIEEE754, 427b9c1b51eSKate Stone eFormatFloat, 428b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 429b9c1b51eSKate Stone fpu_s2}, 430b9c1b51eSKate Stone nullptr, 431b9c1b51eSKate Stone nullptr, 432b9c1b51eSKate Stone nullptr, 433b9c1b51eSKate Stone 0}, 434b9c1b51eSKate Stone {"s3", 435b9c1b51eSKate Stone NULL, 436b9c1b51eSKate Stone 4, 437b9c1b51eSKate Stone FPU_OFFSET(3), 438b9c1b51eSKate Stone eEncodingIEEE754, 439b9c1b51eSKate Stone eFormatFloat, 440b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 441b9c1b51eSKate Stone fpu_s3}, 442b9c1b51eSKate Stone nullptr, 443b9c1b51eSKate Stone nullptr, 444b9c1b51eSKate Stone nullptr, 445b9c1b51eSKate Stone 0}, 446b9c1b51eSKate Stone {"s4", 447b9c1b51eSKate Stone NULL, 448b9c1b51eSKate Stone 4, 449b9c1b51eSKate Stone FPU_OFFSET(4), 450b9c1b51eSKate Stone eEncodingIEEE754, 451b9c1b51eSKate Stone eFormatFloat, 452b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 453b9c1b51eSKate Stone fpu_s4}, 454b9c1b51eSKate Stone nullptr, 455b9c1b51eSKate Stone nullptr, 456b9c1b51eSKate Stone nullptr, 457b9c1b51eSKate Stone 0}, 458b9c1b51eSKate Stone {"s5", 459b9c1b51eSKate Stone NULL, 460b9c1b51eSKate Stone 4, 461b9c1b51eSKate Stone FPU_OFFSET(5), 462b9c1b51eSKate Stone eEncodingIEEE754, 463b9c1b51eSKate Stone eFormatFloat, 464b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 465b9c1b51eSKate Stone fpu_s5}, 466b9c1b51eSKate Stone nullptr, 467b9c1b51eSKate Stone nullptr, 468b9c1b51eSKate Stone nullptr, 469b9c1b51eSKate Stone 0}, 470b9c1b51eSKate Stone {"s6", 471b9c1b51eSKate Stone NULL, 472b9c1b51eSKate Stone 4, 473b9c1b51eSKate Stone FPU_OFFSET(6), 474b9c1b51eSKate Stone eEncodingIEEE754, 475b9c1b51eSKate Stone eFormatFloat, 476b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 477b9c1b51eSKate Stone fpu_s6}, 478b9c1b51eSKate Stone nullptr, 479b9c1b51eSKate Stone nullptr, 480b9c1b51eSKate Stone nullptr, 481b9c1b51eSKate Stone 0}, 482b9c1b51eSKate Stone {"s7", 483b9c1b51eSKate Stone NULL, 484b9c1b51eSKate Stone 4, 485b9c1b51eSKate Stone FPU_OFFSET(7), 486b9c1b51eSKate Stone eEncodingIEEE754, 487b9c1b51eSKate Stone eFormatFloat, 488b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 489b9c1b51eSKate Stone fpu_s7}, 490b9c1b51eSKate Stone nullptr, 491b9c1b51eSKate Stone nullptr, 492b9c1b51eSKate Stone nullptr, 493b9c1b51eSKate Stone 0}, 494b9c1b51eSKate Stone {"s8", 495b9c1b51eSKate Stone NULL, 496b9c1b51eSKate Stone 4, 497b9c1b51eSKate Stone FPU_OFFSET(8), 498b9c1b51eSKate Stone eEncodingIEEE754, 499b9c1b51eSKate Stone eFormatFloat, 500b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 501b9c1b51eSKate Stone fpu_s8}, 502b9c1b51eSKate Stone nullptr, 503b9c1b51eSKate Stone nullptr, 504b9c1b51eSKate Stone nullptr, 505b9c1b51eSKate Stone 0}, 506b9c1b51eSKate Stone {"s9", 507b9c1b51eSKate Stone NULL, 508b9c1b51eSKate Stone 4, 509b9c1b51eSKate Stone FPU_OFFSET(9), 510b9c1b51eSKate Stone eEncodingIEEE754, 511b9c1b51eSKate Stone eFormatFloat, 512b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 513b9c1b51eSKate Stone fpu_s9}, 514b9c1b51eSKate Stone nullptr, 515b9c1b51eSKate Stone nullptr, 516b9c1b51eSKate Stone nullptr, 517b9c1b51eSKate Stone 0}, 518b9c1b51eSKate Stone {"s10", 519b9c1b51eSKate Stone NULL, 520b9c1b51eSKate Stone 4, 521b9c1b51eSKate Stone FPU_OFFSET(10), 522b9c1b51eSKate Stone eEncodingIEEE754, 523b9c1b51eSKate Stone eFormatFloat, 524b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 525b9c1b51eSKate Stone fpu_s10}, 526b9c1b51eSKate Stone nullptr, 527b9c1b51eSKate Stone nullptr, 528b9c1b51eSKate Stone nullptr, 529b9c1b51eSKate Stone 0}, 530b9c1b51eSKate Stone {"s11", 531b9c1b51eSKate Stone NULL, 532b9c1b51eSKate Stone 4, 533b9c1b51eSKate Stone FPU_OFFSET(11), 534b9c1b51eSKate Stone eEncodingIEEE754, 535b9c1b51eSKate Stone eFormatFloat, 536b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 537b9c1b51eSKate Stone fpu_s11}, 538b9c1b51eSKate Stone nullptr, 539b9c1b51eSKate Stone nullptr, 540b9c1b51eSKate Stone nullptr, 541b9c1b51eSKate Stone 0}, 542b9c1b51eSKate Stone {"s12", 543b9c1b51eSKate Stone NULL, 544b9c1b51eSKate Stone 4, 545b9c1b51eSKate Stone FPU_OFFSET(12), 546b9c1b51eSKate Stone eEncodingIEEE754, 547b9c1b51eSKate Stone eFormatFloat, 548b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 549b9c1b51eSKate Stone fpu_s12}, 550b9c1b51eSKate Stone nullptr, 551b9c1b51eSKate Stone nullptr, 552b9c1b51eSKate Stone nullptr, 553b9c1b51eSKate Stone 0}, 554b9c1b51eSKate Stone {"s13", 555b9c1b51eSKate Stone NULL, 556b9c1b51eSKate Stone 4, 557b9c1b51eSKate Stone FPU_OFFSET(13), 558b9c1b51eSKate Stone eEncodingIEEE754, 559b9c1b51eSKate Stone eFormatFloat, 560b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 561b9c1b51eSKate Stone fpu_s13}, 562b9c1b51eSKate Stone nullptr, 563b9c1b51eSKate Stone nullptr, 564b9c1b51eSKate Stone nullptr, 565b9c1b51eSKate Stone 0}, 566b9c1b51eSKate Stone {"s14", 567b9c1b51eSKate Stone NULL, 568b9c1b51eSKate Stone 4, 569b9c1b51eSKate Stone FPU_OFFSET(14), 570b9c1b51eSKate Stone eEncodingIEEE754, 571b9c1b51eSKate Stone eFormatFloat, 572b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 573b9c1b51eSKate Stone fpu_s14}, 574b9c1b51eSKate Stone nullptr, 575b9c1b51eSKate Stone nullptr, 576b9c1b51eSKate Stone nullptr, 577b9c1b51eSKate Stone 0}, 578b9c1b51eSKate Stone {"s15", 579b9c1b51eSKate Stone NULL, 580b9c1b51eSKate Stone 4, 581b9c1b51eSKate Stone FPU_OFFSET(15), 582b9c1b51eSKate Stone eEncodingIEEE754, 583b9c1b51eSKate Stone eFormatFloat, 584b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 585b9c1b51eSKate Stone fpu_s15}, 586b9c1b51eSKate Stone nullptr, 587b9c1b51eSKate Stone nullptr, 588b9c1b51eSKate Stone nullptr, 589b9c1b51eSKate Stone 0}, 590b9c1b51eSKate Stone {"s16", 591b9c1b51eSKate Stone NULL, 592b9c1b51eSKate Stone 4, 593b9c1b51eSKate Stone FPU_OFFSET(16), 594b9c1b51eSKate Stone eEncodingIEEE754, 595b9c1b51eSKate Stone eFormatFloat, 596b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 597b9c1b51eSKate Stone fpu_s16}, 598b9c1b51eSKate Stone nullptr, 599b9c1b51eSKate Stone nullptr, 600b9c1b51eSKate Stone nullptr, 601b9c1b51eSKate Stone 0}, 602b9c1b51eSKate Stone {"s17", 603b9c1b51eSKate Stone NULL, 604b9c1b51eSKate Stone 4, 605b9c1b51eSKate Stone FPU_OFFSET(17), 606b9c1b51eSKate Stone eEncodingIEEE754, 607b9c1b51eSKate Stone eFormatFloat, 608b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 609b9c1b51eSKate Stone fpu_s17}, 610b9c1b51eSKate Stone nullptr, 611b9c1b51eSKate Stone nullptr, 612b9c1b51eSKate Stone nullptr, 613b9c1b51eSKate Stone 0}, 614b9c1b51eSKate Stone {"s18", 615b9c1b51eSKate Stone NULL, 616b9c1b51eSKate Stone 4, 617b9c1b51eSKate Stone FPU_OFFSET(18), 618b9c1b51eSKate Stone eEncodingIEEE754, 619b9c1b51eSKate Stone eFormatFloat, 620b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 621b9c1b51eSKate Stone fpu_s18}, 622b9c1b51eSKate Stone nullptr, 623b9c1b51eSKate Stone nullptr, 624b9c1b51eSKate Stone nullptr, 625b9c1b51eSKate Stone 0}, 626b9c1b51eSKate Stone {"s19", 627b9c1b51eSKate Stone NULL, 628b9c1b51eSKate Stone 4, 629b9c1b51eSKate Stone FPU_OFFSET(19), 630b9c1b51eSKate Stone eEncodingIEEE754, 631b9c1b51eSKate Stone eFormatFloat, 632b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 633b9c1b51eSKate Stone fpu_s19}, 634b9c1b51eSKate Stone nullptr, 635b9c1b51eSKate Stone nullptr, 636b9c1b51eSKate Stone nullptr, 637b9c1b51eSKate Stone 0}, 638b9c1b51eSKate Stone {"s20", 639b9c1b51eSKate Stone NULL, 640b9c1b51eSKate Stone 4, 641b9c1b51eSKate Stone FPU_OFFSET(20), 642b9c1b51eSKate Stone eEncodingIEEE754, 643b9c1b51eSKate Stone eFormatFloat, 644b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 645b9c1b51eSKate Stone fpu_s20}, 646b9c1b51eSKate Stone nullptr, 647b9c1b51eSKate Stone nullptr, 648b9c1b51eSKate Stone nullptr, 649b9c1b51eSKate Stone 0}, 650b9c1b51eSKate Stone {"s21", 651b9c1b51eSKate Stone NULL, 652b9c1b51eSKate Stone 4, 653b9c1b51eSKate Stone FPU_OFFSET(21), 654b9c1b51eSKate Stone eEncodingIEEE754, 655b9c1b51eSKate Stone eFormatFloat, 656b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 657b9c1b51eSKate Stone fpu_s21}, 658b9c1b51eSKate Stone nullptr, 659b9c1b51eSKate Stone nullptr, 660b9c1b51eSKate Stone nullptr, 661b9c1b51eSKate Stone 0}, 662b9c1b51eSKate Stone {"s22", 663b9c1b51eSKate Stone NULL, 664b9c1b51eSKate Stone 4, 665b9c1b51eSKate Stone FPU_OFFSET(22), 666b9c1b51eSKate Stone eEncodingIEEE754, 667b9c1b51eSKate Stone eFormatFloat, 668b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 669b9c1b51eSKate Stone fpu_s22}, 670b9c1b51eSKate Stone nullptr, 671b9c1b51eSKate Stone nullptr, 672b9c1b51eSKate Stone nullptr, 673b9c1b51eSKate Stone 0}, 674b9c1b51eSKate Stone {"s23", 675b9c1b51eSKate Stone NULL, 676b9c1b51eSKate Stone 4, 677b9c1b51eSKate Stone FPU_OFFSET(23), 678b9c1b51eSKate Stone eEncodingIEEE754, 679b9c1b51eSKate Stone eFormatFloat, 680b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 681b9c1b51eSKate Stone fpu_s23}, 682b9c1b51eSKate Stone nullptr, 683b9c1b51eSKate Stone nullptr, 684b9c1b51eSKate Stone nullptr, 685b9c1b51eSKate Stone 0}, 686b9c1b51eSKate Stone {"s24", 687b9c1b51eSKate Stone NULL, 688b9c1b51eSKate Stone 4, 689b9c1b51eSKate Stone FPU_OFFSET(24), 690b9c1b51eSKate Stone eEncodingIEEE754, 691b9c1b51eSKate Stone eFormatFloat, 692b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 693b9c1b51eSKate Stone fpu_s24}, 694b9c1b51eSKate Stone nullptr, 695b9c1b51eSKate Stone nullptr, 696b9c1b51eSKate Stone nullptr, 697b9c1b51eSKate Stone 0}, 698b9c1b51eSKate Stone {"s25", 699b9c1b51eSKate Stone NULL, 700b9c1b51eSKate Stone 4, 701b9c1b51eSKate Stone FPU_OFFSET(25), 702b9c1b51eSKate Stone eEncodingIEEE754, 703b9c1b51eSKate Stone eFormatFloat, 704b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 705b9c1b51eSKate Stone fpu_s25}, 706b9c1b51eSKate Stone nullptr, 707b9c1b51eSKate Stone nullptr, 708b9c1b51eSKate Stone nullptr, 709b9c1b51eSKate Stone 0}, 710b9c1b51eSKate Stone {"s26", 711b9c1b51eSKate Stone NULL, 712b9c1b51eSKate Stone 4, 713b9c1b51eSKate Stone FPU_OFFSET(26), 714b9c1b51eSKate Stone eEncodingIEEE754, 715b9c1b51eSKate Stone eFormatFloat, 716b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 717b9c1b51eSKate Stone fpu_s26}, 718b9c1b51eSKate Stone nullptr, 719b9c1b51eSKate Stone nullptr, 720b9c1b51eSKate Stone nullptr, 721b9c1b51eSKate Stone 0}, 722b9c1b51eSKate Stone {"s27", 723b9c1b51eSKate Stone NULL, 724b9c1b51eSKate Stone 4, 725b9c1b51eSKate Stone FPU_OFFSET(27), 726b9c1b51eSKate Stone eEncodingIEEE754, 727b9c1b51eSKate Stone eFormatFloat, 728b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 729b9c1b51eSKate Stone fpu_s27}, 730b9c1b51eSKate Stone nullptr, 731b9c1b51eSKate Stone nullptr, 732b9c1b51eSKate Stone nullptr, 733b9c1b51eSKate Stone 0}, 734b9c1b51eSKate Stone {"s28", 735b9c1b51eSKate Stone NULL, 736b9c1b51eSKate Stone 4, 737b9c1b51eSKate Stone FPU_OFFSET(28), 738b9c1b51eSKate Stone eEncodingIEEE754, 739b9c1b51eSKate Stone eFormatFloat, 740b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 741b9c1b51eSKate Stone fpu_s28}, 742b9c1b51eSKate Stone nullptr, 743b9c1b51eSKate Stone nullptr, 744b9c1b51eSKate Stone nullptr, 745b9c1b51eSKate Stone 0}, 746b9c1b51eSKate Stone {"s29", 747b9c1b51eSKate Stone NULL, 748b9c1b51eSKate Stone 4, 749b9c1b51eSKate Stone FPU_OFFSET(29), 750b9c1b51eSKate Stone eEncodingIEEE754, 751b9c1b51eSKate Stone eFormatFloat, 752b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 753b9c1b51eSKate Stone fpu_s29}, 754b9c1b51eSKate Stone nullptr, 755b9c1b51eSKate Stone nullptr, 756b9c1b51eSKate Stone nullptr, 757b9c1b51eSKate Stone 0}, 758b9c1b51eSKate Stone {"s30", 759b9c1b51eSKate Stone NULL, 760b9c1b51eSKate Stone 4, 761b9c1b51eSKate Stone FPU_OFFSET(30), 762b9c1b51eSKate Stone eEncodingIEEE754, 763b9c1b51eSKate Stone eFormatFloat, 764b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 765b9c1b51eSKate Stone fpu_s30}, 766b9c1b51eSKate Stone nullptr, 767b9c1b51eSKate Stone nullptr, 768b9c1b51eSKate Stone nullptr, 769b9c1b51eSKate Stone 0}, 770b9c1b51eSKate Stone {"s31", 771b9c1b51eSKate Stone NULL, 772b9c1b51eSKate Stone 4, 773b9c1b51eSKate Stone FPU_OFFSET(31), 774b9c1b51eSKate Stone eEncodingIEEE754, 775b9c1b51eSKate Stone eFormatFloat, 776b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 777b9c1b51eSKate Stone fpu_s31}, 778b9c1b51eSKate Stone nullptr, 779b9c1b51eSKate Stone nullptr, 780b9c1b51eSKate Stone nullptr, 781b9c1b51eSKate Stone 0}, 782b9c1b51eSKate Stone {"fpscr", 783b9c1b51eSKate Stone NULL, 784b9c1b51eSKate Stone 4, 785b9c1b51eSKate Stone FPU_OFFSET(32), 786b9c1b51eSKate Stone eEncodingUint, 787b9c1b51eSKate Stone eFormatHex, 788b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 789b9c1b51eSKate Stone LLDB_INVALID_REGNUM, fpu_fpscr}, 790b9c1b51eSKate Stone nullptr, 791b9c1b51eSKate Stone nullptr, 792b9c1b51eSKate Stone nullptr, 793b9c1b51eSKate Stone 0}, 794a63d08c9SGreg Clayton 795b9c1b51eSKate Stone {"exception", 796b9c1b51eSKate Stone NULL, 797b9c1b51eSKate Stone 4, 798b9c1b51eSKate Stone EXC_OFFSET(0), 799b9c1b51eSKate Stone eEncodingUint, 800b9c1b51eSKate Stone eFormatHex, 801b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 802b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_exception}, 803b9c1b51eSKate Stone nullptr, 804b9c1b51eSKate Stone nullptr, 805b9c1b51eSKate Stone nullptr, 806b9c1b51eSKate Stone 0}, 807b9c1b51eSKate Stone {"fsr", 808b9c1b51eSKate Stone NULL, 809b9c1b51eSKate Stone 4, 810b9c1b51eSKate Stone EXC_OFFSET(1), 811b9c1b51eSKate Stone eEncodingUint, 812b9c1b51eSKate Stone eFormatHex, 813b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 814b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_fsr}, 815b9c1b51eSKate Stone nullptr, 816b9c1b51eSKate Stone nullptr, 817b9c1b51eSKate Stone nullptr, 818b9c1b51eSKate Stone 0}, 819b9c1b51eSKate Stone {"far", 820b9c1b51eSKate Stone NULL, 821b9c1b51eSKate Stone 4, 822b9c1b51eSKate Stone EXC_OFFSET(2), 823b9c1b51eSKate Stone eEncodingUint, 824b9c1b51eSKate Stone eFormatHex, 825b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 826b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_far}, 827b9c1b51eSKate Stone nullptr, 828b9c1b51eSKate Stone nullptr, 829b9c1b51eSKate Stone nullptr, 830b9c1b51eSKate Stone 0}, 831a63d08c9SGreg Clayton 832a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 0)}, 833a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 1)}, 834a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 2)}, 835a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 3)}, 836a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 4)}, 837a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 5)}, 838a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 6)}, 839a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 7)}, 840a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 8)}, 841a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 9)}, 842a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 10)}, 843a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 11)}, 844a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 12)}, 845a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 13)}, 846a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 14)}, 847a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 15)}, 848a63d08c9SGreg Clayton 849a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 0)}, 850a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 1)}, 851a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 2)}, 852a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 3)}, 853a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 4)}, 854a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 5)}, 855a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 6)}, 856a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 7)}, 857a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 8)}, 858a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 9)}, 859a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 10)}, 860a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 11)}, 861a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 12)}, 862a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 13)}, 863a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 14)}, 864a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 15)}, 865a63d08c9SGreg Clayton 866a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 0)}, 867a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 1)}, 868a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 2)}, 869a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 3)}, 870a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 4)}, 871a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 5)}, 872a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 6)}, 873a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 7)}, 874a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 8)}, 875a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 9)}, 876a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 10)}, 877a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 11)}, 878a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 12)}, 879a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 13)}, 880a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 14)}, 881a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 15)}, 882a63d08c9SGreg Clayton 883a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 0)}, 884a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 1)}, 885a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 2)}, 886a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 3)}, 887a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 4)}, 888a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 5)}, 889a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 6)}, 890a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 7)}, 891a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 8)}, 892a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 9)}, 893a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 10)}, 894a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 11)}, 895a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 12)}, 896a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 13)}, 897a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 14)}, 898b9c1b51eSKate Stone {DEFINE_DBG(wcr, 15)}}; 899a63d08c9SGreg Clayton 900a63d08c9SGreg Clayton // General purpose registers 901b9c1b51eSKate Stone static uint32_t g_gpr_regnums[] = { 902b9c1b51eSKate Stone gpr_r0, gpr_r1, gpr_r2, gpr_r3, gpr_r4, gpr_r5, gpr_r6, gpr_r7, gpr_r8, 903b9c1b51eSKate Stone gpr_r9, gpr_r10, gpr_r11, gpr_r12, gpr_sp, gpr_lr, gpr_pc, gpr_cpsr}; 904a63d08c9SGreg Clayton 905a63d08c9SGreg Clayton // Floating point registers 906b9c1b51eSKate Stone static uint32_t g_fpu_regnums[] = { 907b9c1b51eSKate Stone fpu_s0, fpu_s1, fpu_s2, fpu_s3, fpu_s4, fpu_s5, fpu_s6, 908b9c1b51eSKate Stone fpu_s7, fpu_s8, fpu_s9, fpu_s10, fpu_s11, fpu_s12, fpu_s13, 909b9c1b51eSKate Stone fpu_s14, fpu_s15, fpu_s16, fpu_s17, fpu_s18, fpu_s19, fpu_s20, 910b9c1b51eSKate Stone fpu_s21, fpu_s22, fpu_s23, fpu_s24, fpu_s25, fpu_s26, fpu_s27, 911b9c1b51eSKate Stone fpu_s28, fpu_s29, fpu_s30, fpu_s31, fpu_fpscr, 912a63d08c9SGreg Clayton }; 913a63d08c9SGreg Clayton 914a63d08c9SGreg Clayton // Exception registers 915a63d08c9SGreg Clayton 916b9c1b51eSKate Stone static uint32_t g_exc_regnums[] = { 917b9c1b51eSKate Stone exc_exception, exc_fsr, exc_far, 918a63d08c9SGreg Clayton }; 919a63d08c9SGreg Clayton 92028606954SSaleem Abdulrasool static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos); 921a63d08c9SGreg Clayton 922b9c1b51eSKate Stone RegisterContextDarwin_arm::RegisterContextDarwin_arm( 923b9c1b51eSKate Stone Thread &thread, uint32_t concrete_frame_idx) 924b9c1b51eSKate Stone : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() { 92563bd0db0SJason Molenda uint32_t i; 926b9c1b51eSKate Stone for (i = 0; i < kNumErrors; i++) { 92763bd0db0SJason Molenda gpr_errs[i] = -1; 92863bd0db0SJason Molenda fpu_errs[i] = -1; 92963bd0db0SJason Molenda exc_errs[i] = -1; 93063bd0db0SJason Molenda } 93163bd0db0SJason Molenda } 93263bd0db0SJason Molenda 933b9c1b51eSKate Stone RegisterContextDarwin_arm::~RegisterContextDarwin_arm() {} 93463bd0db0SJason Molenda 935b9c1b51eSKate Stone void RegisterContextDarwin_arm::InvalidateAllRegisters() { 936a63d08c9SGreg Clayton InvalidateAllRegisterStates(); 937a63d08c9SGreg Clayton } 938a63d08c9SGreg Clayton 939b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterCount() { 940a63d08c9SGreg Clayton assert(k_num_register_infos == k_num_registers); 941a63d08c9SGreg Clayton return k_num_registers; 942a63d08c9SGreg Clayton } 943a63d08c9SGreg Clayton 944a63d08c9SGreg Clayton const RegisterInfo * 945b9c1b51eSKate Stone RegisterContextDarwin_arm::GetRegisterInfoAtIndex(size_t reg) { 946a63d08c9SGreg Clayton assert(k_num_register_infos == k_num_registers); 947a63d08c9SGreg Clayton if (reg < k_num_registers) 948a63d08c9SGreg Clayton return &g_register_infos[reg]; 949a63d08c9SGreg Clayton return NULL; 950a63d08c9SGreg Clayton } 951a63d08c9SGreg Clayton 952b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterInfosCount() { 953a63d08c9SGreg Clayton return k_num_register_infos; 954a63d08c9SGreg Clayton } 955a63d08c9SGreg Clayton 956b9c1b51eSKate Stone const RegisterInfo *RegisterContextDarwin_arm::GetRegisterInfos() { 957a63d08c9SGreg Clayton return g_register_infos; 958a63d08c9SGreg Clayton } 959a63d08c9SGreg Clayton 960a63d08c9SGreg Clayton // Number of registers in each register set 96128606954SSaleem Abdulrasool const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums); 96228606954SSaleem Abdulrasool const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums); 96328606954SSaleem Abdulrasool const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums); 964a63d08c9SGreg Clayton 965a63d08c9SGreg Clayton //---------------------------------------------------------------------- 96605097246SAdrian Prantl // Register set definitions. The first definitions at register set index of 96705097246SAdrian Prantl // zero is for all registers, followed by other registers sets. The register 96805097246SAdrian Prantl // information for the all register set need not be filled in. 969a63d08c9SGreg Clayton //---------------------------------------------------------------------- 970b9c1b51eSKate Stone static const RegisterSet g_reg_sets[] = { 971a63d08c9SGreg Clayton { 972b9c1b51eSKate Stone "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, 973b9c1b51eSKate Stone }, 974a63d08c9SGreg Clayton {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums}, 975b9c1b51eSKate Stone {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}}; 976a63d08c9SGreg Clayton 97728606954SSaleem Abdulrasool const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets); 978a63d08c9SGreg Clayton 979b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterSetCount() { 980a63d08c9SGreg Clayton return k_num_regsets; 981a63d08c9SGreg Clayton } 982a63d08c9SGreg Clayton 983b9c1b51eSKate Stone const RegisterSet *RegisterContextDarwin_arm::GetRegisterSet(size_t reg_set) { 984a63d08c9SGreg Clayton if (reg_set < k_num_regsets) 985a63d08c9SGreg Clayton return &g_reg_sets[reg_set]; 986a63d08c9SGreg Clayton return NULL; 987a63d08c9SGreg Clayton } 988a63d08c9SGreg Clayton 989a63d08c9SGreg Clayton //---------------------------------------------------------------------- 990aaa0ba31SBruce Mitchener // Register information definitions for 32 bit i386. 991a63d08c9SGreg Clayton //---------------------------------------------------------------------- 992b9c1b51eSKate Stone int RegisterContextDarwin_arm::GetSetForNativeRegNum(int reg) { 993a63d08c9SGreg Clayton if (reg < fpu_s0) 994a63d08c9SGreg Clayton return GPRRegSet; 995a63d08c9SGreg Clayton else if (reg < exc_exception) 996a63d08c9SGreg Clayton return FPURegSet; 997a63d08c9SGreg Clayton else if (reg < k_num_registers) 998a63d08c9SGreg Clayton return EXCRegSet; 999a63d08c9SGreg Clayton return -1; 1000a63d08c9SGreg Clayton } 1001a63d08c9SGreg Clayton 1002b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadGPR(bool force) { 1003a63d08c9SGreg Clayton int set = GPRRegSet; 1004b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1005a63d08c9SGreg Clayton SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr)); 1006a63d08c9SGreg Clayton } 1007a63d08c9SGreg Clayton return GetError(GPRRegSet, Read); 1008a63d08c9SGreg Clayton } 1009a63d08c9SGreg Clayton 1010b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadFPU(bool force) { 1011a63d08c9SGreg Clayton int set = FPURegSet; 1012b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1013a63d08c9SGreg Clayton SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu)); 1014a63d08c9SGreg Clayton } 1015a63d08c9SGreg Clayton return GetError(FPURegSet, Read); 1016a63d08c9SGreg Clayton } 1017a63d08c9SGreg Clayton 1018b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadEXC(bool force) { 1019a63d08c9SGreg Clayton int set = EXCRegSet; 1020b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1021a63d08c9SGreg Clayton SetError(set, Read, DoReadEXC(GetThreadID(), set, exc)); 1022a63d08c9SGreg Clayton } 1023a63d08c9SGreg Clayton return GetError(EXCRegSet, Read); 1024a63d08c9SGreg Clayton } 1025a63d08c9SGreg Clayton 1026b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadDBG(bool force) { 1027a63d08c9SGreg Clayton int set = DBGRegSet; 1028b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1029a63d08c9SGreg Clayton SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg)); 1030a63d08c9SGreg Clayton } 1031a63d08c9SGreg Clayton return GetError(DBGRegSet, Read); 1032a63d08c9SGreg Clayton } 1033a63d08c9SGreg Clayton 1034b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteGPR() { 1035a63d08c9SGreg Clayton int set = GPRRegSet; 1036b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1037a63d08c9SGreg Clayton SetError(set, Write, -1); 1038a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1039a63d08c9SGreg Clayton } 1040a63d08c9SGreg Clayton SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr)); 1041a63d08c9SGreg Clayton SetError(set, Read, -1); 1042a63d08c9SGreg Clayton return GetError(GPRRegSet, Write); 1043a63d08c9SGreg Clayton } 1044a63d08c9SGreg Clayton 1045b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteFPU() { 1046a63d08c9SGreg Clayton int set = FPURegSet; 1047b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1048a63d08c9SGreg Clayton SetError(set, Write, -1); 1049a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1050a63d08c9SGreg Clayton } 1051a63d08c9SGreg Clayton SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu)); 1052a63d08c9SGreg Clayton SetError(set, Read, -1); 1053a63d08c9SGreg Clayton return GetError(FPURegSet, Write); 1054a63d08c9SGreg Clayton } 1055a63d08c9SGreg Clayton 1056b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteEXC() { 1057a63d08c9SGreg Clayton int set = EXCRegSet; 1058b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1059a63d08c9SGreg Clayton SetError(set, Write, -1); 1060a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1061a63d08c9SGreg Clayton } 1062a63d08c9SGreg Clayton SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc)); 1063a63d08c9SGreg Clayton SetError(set, Read, -1); 1064a63d08c9SGreg Clayton return GetError(EXCRegSet, Write); 1065a63d08c9SGreg Clayton } 1066a63d08c9SGreg Clayton 1067b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteDBG() { 1068a63d08c9SGreg Clayton int set = DBGRegSet; 1069b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1070a63d08c9SGreg Clayton SetError(set, Write, -1); 1071a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1072a63d08c9SGreg Clayton } 1073a63d08c9SGreg Clayton SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg)); 1074a63d08c9SGreg Clayton SetError(set, Read, -1); 1075a63d08c9SGreg Clayton return GetError(DBGRegSet, Write); 1076a63d08c9SGreg Clayton } 1077a63d08c9SGreg Clayton 1078b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadRegisterSet(uint32_t set, bool force) { 1079b9c1b51eSKate Stone switch (set) { 1080b9c1b51eSKate Stone case GPRRegSet: 1081b9c1b51eSKate Stone return ReadGPR(force); 1082b9c1b51eSKate Stone case GPRAltRegSet: 1083b9c1b51eSKate Stone return ReadGPR(force); 1084b9c1b51eSKate Stone case FPURegSet: 1085b9c1b51eSKate Stone return ReadFPU(force); 1086b9c1b51eSKate Stone case EXCRegSet: 1087b9c1b51eSKate Stone return ReadEXC(force); 1088b9c1b51eSKate Stone case DBGRegSet: 1089b9c1b51eSKate Stone return ReadDBG(force); 1090b9c1b51eSKate Stone default: 1091b9c1b51eSKate Stone break; 1092a63d08c9SGreg Clayton } 1093a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1094a63d08c9SGreg Clayton } 1095a63d08c9SGreg Clayton 1096b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteRegisterSet(uint32_t set) { 1097a63d08c9SGreg Clayton // Make sure we have a valid context to set. 1098b9c1b51eSKate Stone if (RegisterSetIsCached(set)) { 1099b9c1b51eSKate Stone switch (set) { 1100b9c1b51eSKate Stone case GPRRegSet: 1101b9c1b51eSKate Stone return WriteGPR(); 1102b9c1b51eSKate Stone case GPRAltRegSet: 1103b9c1b51eSKate Stone return WriteGPR(); 1104b9c1b51eSKate Stone case FPURegSet: 1105b9c1b51eSKate Stone return WriteFPU(); 1106b9c1b51eSKate Stone case EXCRegSet: 1107b9c1b51eSKate Stone return WriteEXC(); 1108b9c1b51eSKate Stone case DBGRegSet: 1109b9c1b51eSKate Stone return WriteDBG(); 1110b9c1b51eSKate Stone default: 1111b9c1b51eSKate Stone break; 1112a63d08c9SGreg Clayton } 1113a63d08c9SGreg Clayton } 1114a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1115a63d08c9SGreg Clayton } 1116a63d08c9SGreg Clayton 1117b9c1b51eSKate Stone void RegisterContextDarwin_arm::LogDBGRegisters(Log *log, const DBG &dbg) { 1118b9c1b51eSKate Stone if (log) { 1119a63d08c9SGreg Clayton for (uint32_t i = 0; i < 16; i++) 1120b9c1b51eSKate Stone log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { " 1121b9c1b51eSKate Stone "0x%8.8x, 0x%8.8x }", 1122b9c1b51eSKate Stone i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]); 1123a63d08c9SGreg Clayton } 1124a63d08c9SGreg Clayton } 1125a63d08c9SGreg Clayton 1126b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ReadRegister(const RegisterInfo *reg_info, 1127b9c1b51eSKate Stone RegisterValue &value) { 1128a63d08c9SGreg Clayton const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 1129a63d08c9SGreg Clayton int set = RegisterContextDarwin_arm::GetSetForNativeRegNum(reg); 1130a63d08c9SGreg Clayton 1131a63d08c9SGreg Clayton if (set == -1) 1132a63d08c9SGreg Clayton return false; 1133a63d08c9SGreg Clayton 1134a63d08c9SGreg Clayton if (ReadRegisterSet(set, false) != KERN_SUCCESS) 1135a63d08c9SGreg Clayton return false; 1136a63d08c9SGreg Clayton 1137b9c1b51eSKate Stone switch (reg) { 1138a63d08c9SGreg Clayton case gpr_r0: 1139a63d08c9SGreg Clayton case gpr_r1: 1140a63d08c9SGreg Clayton case gpr_r2: 1141a63d08c9SGreg Clayton case gpr_r3: 1142a63d08c9SGreg Clayton case gpr_r4: 1143a63d08c9SGreg Clayton case gpr_r5: 1144a63d08c9SGreg Clayton case gpr_r6: 1145a63d08c9SGreg Clayton case gpr_r7: 1146a63d08c9SGreg Clayton case gpr_r8: 1147a63d08c9SGreg Clayton case gpr_r9: 1148a63d08c9SGreg Clayton case gpr_r10: 1149a63d08c9SGreg Clayton case gpr_r11: 1150a63d08c9SGreg Clayton case gpr_r12: 1151a63d08c9SGreg Clayton case gpr_sp: 1152a63d08c9SGreg Clayton case gpr_lr: 1153a63d08c9SGreg Clayton case gpr_pc: 1154a63d08c9SGreg Clayton case gpr_cpsr: 1155a63d08c9SGreg Clayton value.SetUInt32(gpr.r[reg - gpr_r0]); 1156a63d08c9SGreg Clayton break; 1157a63d08c9SGreg Clayton 1158a63d08c9SGreg Clayton case fpu_s0: 1159a63d08c9SGreg Clayton case fpu_s1: 1160a63d08c9SGreg Clayton case fpu_s2: 1161a63d08c9SGreg Clayton case fpu_s3: 1162a63d08c9SGreg Clayton case fpu_s4: 1163a63d08c9SGreg Clayton case fpu_s5: 1164a63d08c9SGreg Clayton case fpu_s6: 1165a63d08c9SGreg Clayton case fpu_s7: 1166a63d08c9SGreg Clayton case fpu_s8: 1167a63d08c9SGreg Clayton case fpu_s9: 1168a63d08c9SGreg Clayton case fpu_s10: 1169a63d08c9SGreg Clayton case fpu_s11: 1170a63d08c9SGreg Clayton case fpu_s12: 1171a63d08c9SGreg Clayton case fpu_s13: 1172a63d08c9SGreg Clayton case fpu_s14: 1173a63d08c9SGreg Clayton case fpu_s15: 1174a63d08c9SGreg Clayton case fpu_s16: 1175a63d08c9SGreg Clayton case fpu_s17: 1176a63d08c9SGreg Clayton case fpu_s18: 1177a63d08c9SGreg Clayton case fpu_s19: 1178a63d08c9SGreg Clayton case fpu_s20: 1179a63d08c9SGreg Clayton case fpu_s21: 1180a63d08c9SGreg Clayton case fpu_s22: 1181a63d08c9SGreg Clayton case fpu_s23: 1182a63d08c9SGreg Clayton case fpu_s24: 1183a63d08c9SGreg Clayton case fpu_s25: 1184a63d08c9SGreg Clayton case fpu_s26: 1185a63d08c9SGreg Clayton case fpu_s27: 1186a63d08c9SGreg Clayton case fpu_s28: 1187a63d08c9SGreg Clayton case fpu_s29: 1188a63d08c9SGreg Clayton case fpu_s30: 1189a63d08c9SGreg Clayton case fpu_s31: 1190a63d08c9SGreg Clayton value.SetUInt32(fpu.floats.s[reg], RegisterValue::eTypeFloat); 1191a63d08c9SGreg Clayton break; 1192a63d08c9SGreg Clayton 1193a63d08c9SGreg Clayton case fpu_fpscr: 1194a63d08c9SGreg Clayton value.SetUInt32(fpu.fpscr); 1195a63d08c9SGreg Clayton break; 1196a63d08c9SGreg Clayton 1197a63d08c9SGreg Clayton case exc_exception: 1198a63d08c9SGreg Clayton value.SetUInt32(exc.exception); 1199a63d08c9SGreg Clayton break; 1200a63d08c9SGreg Clayton case exc_fsr: 1201a63d08c9SGreg Clayton value.SetUInt32(exc.fsr); 1202a63d08c9SGreg Clayton break; 1203a63d08c9SGreg Clayton case exc_far: 1204a63d08c9SGreg Clayton value.SetUInt32(exc.far); 1205a63d08c9SGreg Clayton break; 1206a63d08c9SGreg Clayton 1207a63d08c9SGreg Clayton default: 1208a63d08c9SGreg Clayton value.SetValueToInvalid(); 1209a63d08c9SGreg Clayton return false; 1210a63d08c9SGreg Clayton } 1211a63d08c9SGreg Clayton return true; 1212a63d08c9SGreg Clayton } 1213a63d08c9SGreg Clayton 1214b9c1b51eSKate Stone bool RegisterContextDarwin_arm::WriteRegister(const RegisterInfo *reg_info, 1215b9c1b51eSKate Stone const RegisterValue &value) { 1216a63d08c9SGreg Clayton const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 1217a63d08c9SGreg Clayton int set = GetSetForNativeRegNum(reg); 1218a63d08c9SGreg Clayton 1219a63d08c9SGreg Clayton if (set == -1) 1220a63d08c9SGreg Clayton return false; 1221a63d08c9SGreg Clayton 1222a63d08c9SGreg Clayton if (ReadRegisterSet(set, false) != KERN_SUCCESS) 1223a63d08c9SGreg Clayton return false; 1224a63d08c9SGreg Clayton 1225b9c1b51eSKate Stone switch (reg) { 1226a63d08c9SGreg Clayton case gpr_r0: 1227a63d08c9SGreg Clayton case gpr_r1: 1228a63d08c9SGreg Clayton case gpr_r2: 1229a63d08c9SGreg Clayton case gpr_r3: 1230a63d08c9SGreg Clayton case gpr_r4: 1231a63d08c9SGreg Clayton case gpr_r5: 1232a63d08c9SGreg Clayton case gpr_r6: 1233a63d08c9SGreg Clayton case gpr_r7: 1234a63d08c9SGreg Clayton case gpr_r8: 1235a63d08c9SGreg Clayton case gpr_r9: 1236a63d08c9SGreg Clayton case gpr_r10: 1237a63d08c9SGreg Clayton case gpr_r11: 1238a63d08c9SGreg Clayton case gpr_r12: 1239a63d08c9SGreg Clayton case gpr_sp: 1240a63d08c9SGreg Clayton case gpr_lr: 1241a63d08c9SGreg Clayton case gpr_pc: 1242a63d08c9SGreg Clayton case gpr_cpsr: 1243a63d08c9SGreg Clayton gpr.r[reg - gpr_r0] = value.GetAsUInt32(); 1244a63d08c9SGreg Clayton break; 1245a63d08c9SGreg Clayton 1246a63d08c9SGreg Clayton case fpu_s0: 1247a63d08c9SGreg Clayton case fpu_s1: 1248a63d08c9SGreg Clayton case fpu_s2: 1249a63d08c9SGreg Clayton case fpu_s3: 1250a63d08c9SGreg Clayton case fpu_s4: 1251a63d08c9SGreg Clayton case fpu_s5: 1252a63d08c9SGreg Clayton case fpu_s6: 1253a63d08c9SGreg Clayton case fpu_s7: 1254a63d08c9SGreg Clayton case fpu_s8: 1255a63d08c9SGreg Clayton case fpu_s9: 1256a63d08c9SGreg Clayton case fpu_s10: 1257a63d08c9SGreg Clayton case fpu_s11: 1258a63d08c9SGreg Clayton case fpu_s12: 1259a63d08c9SGreg Clayton case fpu_s13: 1260a63d08c9SGreg Clayton case fpu_s14: 1261a63d08c9SGreg Clayton case fpu_s15: 1262a63d08c9SGreg Clayton case fpu_s16: 1263a63d08c9SGreg Clayton case fpu_s17: 1264a63d08c9SGreg Clayton case fpu_s18: 1265a63d08c9SGreg Clayton case fpu_s19: 1266a63d08c9SGreg Clayton case fpu_s20: 1267a63d08c9SGreg Clayton case fpu_s21: 1268a63d08c9SGreg Clayton case fpu_s22: 1269a63d08c9SGreg Clayton case fpu_s23: 1270a63d08c9SGreg Clayton case fpu_s24: 1271a63d08c9SGreg Clayton case fpu_s25: 1272a63d08c9SGreg Clayton case fpu_s26: 1273a63d08c9SGreg Clayton case fpu_s27: 1274a63d08c9SGreg Clayton case fpu_s28: 1275a63d08c9SGreg Clayton case fpu_s29: 1276a63d08c9SGreg Clayton case fpu_s30: 1277a63d08c9SGreg Clayton case fpu_s31: 1278a63d08c9SGreg Clayton fpu.floats.s[reg] = value.GetAsUInt32(); 1279a63d08c9SGreg Clayton break; 1280a63d08c9SGreg Clayton 1281a63d08c9SGreg Clayton case fpu_fpscr: 1282a63d08c9SGreg Clayton fpu.fpscr = value.GetAsUInt32(); 1283a63d08c9SGreg Clayton break; 1284a63d08c9SGreg Clayton 1285a63d08c9SGreg Clayton case exc_exception: 1286a63d08c9SGreg Clayton exc.exception = value.GetAsUInt32(); 1287a63d08c9SGreg Clayton break; 1288a63d08c9SGreg Clayton case exc_fsr: 1289a63d08c9SGreg Clayton exc.fsr = value.GetAsUInt32(); 1290a63d08c9SGreg Clayton break; 1291a63d08c9SGreg Clayton case exc_far: 1292a63d08c9SGreg Clayton exc.far = value.GetAsUInt32(); 1293a63d08c9SGreg Clayton break; 1294a63d08c9SGreg Clayton 1295a63d08c9SGreg Clayton default: 1296a63d08c9SGreg Clayton return false; 1297a63d08c9SGreg Clayton } 1298a63d08c9SGreg Clayton return WriteRegisterSet(set) == KERN_SUCCESS; 1299a63d08c9SGreg Clayton } 1300a63d08c9SGreg Clayton 1301b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ReadAllRegisterValues( 1302b9c1b51eSKate Stone lldb::DataBufferSP &data_sp) { 1303a63d08c9SGreg Clayton data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0)); 1304b9c1b51eSKate Stone if (data_sp && ReadGPR(false) == KERN_SUCCESS && 1305b9c1b51eSKate Stone ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) { 1306a63d08c9SGreg Clayton uint8_t *dst = data_sp->GetBytes(); 1307a63d08c9SGreg Clayton ::memcpy(dst, &gpr, sizeof(gpr)); 1308a63d08c9SGreg Clayton dst += sizeof(gpr); 1309a63d08c9SGreg Clayton 1310a63d08c9SGreg Clayton ::memcpy(dst, &fpu, sizeof(fpu)); 1311a63d08c9SGreg Clayton dst += sizeof(gpr); 1312a63d08c9SGreg Clayton 1313a63d08c9SGreg Clayton ::memcpy(dst, &exc, sizeof(exc)); 1314a63d08c9SGreg Clayton return true; 1315a63d08c9SGreg Clayton } 1316a63d08c9SGreg Clayton return false; 1317a63d08c9SGreg Clayton } 1318a63d08c9SGreg Clayton 1319b9c1b51eSKate Stone bool RegisterContextDarwin_arm::WriteAllRegisterValues( 1320b9c1b51eSKate Stone const lldb::DataBufferSP &data_sp) { 1321b9c1b51eSKate Stone if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) { 1322a63d08c9SGreg Clayton const uint8_t *src = data_sp->GetBytes(); 1323a63d08c9SGreg Clayton ::memcpy(&gpr, src, sizeof(gpr)); 1324a63d08c9SGreg Clayton src += sizeof(gpr); 1325a63d08c9SGreg Clayton 1326a63d08c9SGreg Clayton ::memcpy(&fpu, src, sizeof(fpu)); 1327a63d08c9SGreg Clayton src += sizeof(gpr); 1328a63d08c9SGreg Clayton 1329a63d08c9SGreg Clayton ::memcpy(&exc, src, sizeof(exc)); 1330a63d08c9SGreg Clayton uint32_t success_count = 0; 1331a63d08c9SGreg Clayton if (WriteGPR() == KERN_SUCCESS) 1332a63d08c9SGreg Clayton ++success_count; 1333a63d08c9SGreg Clayton if (WriteFPU() == KERN_SUCCESS) 1334a63d08c9SGreg Clayton ++success_count; 1335a63d08c9SGreg Clayton if (WriteEXC() == KERN_SUCCESS) 1336a63d08c9SGreg Clayton ++success_count; 1337a63d08c9SGreg Clayton return success_count == 3; 1338a63d08c9SGreg Clayton } 1339a63d08c9SGreg Clayton return false; 1340a63d08c9SGreg Clayton } 1341a63d08c9SGreg Clayton 1342b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::ConvertRegisterKindToRegisterNumber( 1343b9c1b51eSKate Stone lldb::RegisterKind kind, uint32_t reg) { 1344b9c1b51eSKate Stone if (kind == eRegisterKindGeneric) { 1345b9c1b51eSKate Stone switch (reg) { 1346b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_PC: 1347b9c1b51eSKate Stone return gpr_pc; 1348b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_SP: 1349b9c1b51eSKate Stone return gpr_sp; 1350b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_FP: 1351b9c1b51eSKate Stone return gpr_r7; 1352b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_RA: 1353b9c1b51eSKate Stone return gpr_lr; 1354b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_FLAGS: 1355b9c1b51eSKate Stone return gpr_cpsr; 1356a63d08c9SGreg Clayton default: 1357a63d08c9SGreg Clayton break; 1358a63d08c9SGreg Clayton } 1359b9c1b51eSKate Stone } else if (kind == eRegisterKindDWARF) { 1360b9c1b51eSKate Stone switch (reg) { 1361b9c1b51eSKate Stone case dwarf_r0: 1362b9c1b51eSKate Stone return gpr_r0; 1363b9c1b51eSKate Stone case dwarf_r1: 1364b9c1b51eSKate Stone return gpr_r1; 1365b9c1b51eSKate Stone case dwarf_r2: 1366b9c1b51eSKate Stone return gpr_r2; 1367b9c1b51eSKate Stone case dwarf_r3: 1368b9c1b51eSKate Stone return gpr_r3; 1369b9c1b51eSKate Stone case dwarf_r4: 1370b9c1b51eSKate Stone return gpr_r4; 1371b9c1b51eSKate Stone case dwarf_r5: 1372b9c1b51eSKate Stone return gpr_r5; 1373b9c1b51eSKate Stone case dwarf_r6: 1374b9c1b51eSKate Stone return gpr_r6; 1375b9c1b51eSKate Stone case dwarf_r7: 1376b9c1b51eSKate Stone return gpr_r7; 1377b9c1b51eSKate Stone case dwarf_r8: 1378b9c1b51eSKate Stone return gpr_r8; 1379b9c1b51eSKate Stone case dwarf_r9: 1380b9c1b51eSKate Stone return gpr_r9; 1381b9c1b51eSKate Stone case dwarf_r10: 1382b9c1b51eSKate Stone return gpr_r10; 1383b9c1b51eSKate Stone case dwarf_r11: 1384b9c1b51eSKate Stone return gpr_r11; 1385b9c1b51eSKate Stone case dwarf_r12: 1386b9c1b51eSKate Stone return gpr_r12; 1387b9c1b51eSKate Stone case dwarf_sp: 1388b9c1b51eSKate Stone return gpr_sp; 1389b9c1b51eSKate Stone case dwarf_lr: 1390b9c1b51eSKate Stone return gpr_lr; 1391b9c1b51eSKate Stone case dwarf_pc: 1392b9c1b51eSKate Stone return gpr_pc; 1393b9c1b51eSKate Stone case dwarf_spsr: 1394b9c1b51eSKate Stone return gpr_cpsr; 1395a63d08c9SGreg Clayton 1396b9c1b51eSKate Stone case dwarf_s0: 1397b9c1b51eSKate Stone return fpu_s0; 1398b9c1b51eSKate Stone case dwarf_s1: 1399b9c1b51eSKate Stone return fpu_s1; 1400b9c1b51eSKate Stone case dwarf_s2: 1401b9c1b51eSKate Stone return fpu_s2; 1402b9c1b51eSKate Stone case dwarf_s3: 1403b9c1b51eSKate Stone return fpu_s3; 1404b9c1b51eSKate Stone case dwarf_s4: 1405b9c1b51eSKate Stone return fpu_s4; 1406b9c1b51eSKate Stone case dwarf_s5: 1407b9c1b51eSKate Stone return fpu_s5; 1408b9c1b51eSKate Stone case dwarf_s6: 1409b9c1b51eSKate Stone return fpu_s6; 1410b9c1b51eSKate Stone case dwarf_s7: 1411b9c1b51eSKate Stone return fpu_s7; 1412b9c1b51eSKate Stone case dwarf_s8: 1413b9c1b51eSKate Stone return fpu_s8; 1414b9c1b51eSKate Stone case dwarf_s9: 1415b9c1b51eSKate Stone return fpu_s9; 1416b9c1b51eSKate Stone case dwarf_s10: 1417b9c1b51eSKate Stone return fpu_s10; 1418b9c1b51eSKate Stone case dwarf_s11: 1419b9c1b51eSKate Stone return fpu_s11; 1420b9c1b51eSKate Stone case dwarf_s12: 1421b9c1b51eSKate Stone return fpu_s12; 1422b9c1b51eSKate Stone case dwarf_s13: 1423b9c1b51eSKate Stone return fpu_s13; 1424b9c1b51eSKate Stone case dwarf_s14: 1425b9c1b51eSKate Stone return fpu_s14; 1426b9c1b51eSKate Stone case dwarf_s15: 1427b9c1b51eSKate Stone return fpu_s15; 1428b9c1b51eSKate Stone case dwarf_s16: 1429b9c1b51eSKate Stone return fpu_s16; 1430b9c1b51eSKate Stone case dwarf_s17: 1431b9c1b51eSKate Stone return fpu_s17; 1432b9c1b51eSKate Stone case dwarf_s18: 1433b9c1b51eSKate Stone return fpu_s18; 1434b9c1b51eSKate Stone case dwarf_s19: 1435b9c1b51eSKate Stone return fpu_s19; 1436b9c1b51eSKate Stone case dwarf_s20: 1437b9c1b51eSKate Stone return fpu_s20; 1438b9c1b51eSKate Stone case dwarf_s21: 1439b9c1b51eSKate Stone return fpu_s21; 1440b9c1b51eSKate Stone case dwarf_s22: 1441b9c1b51eSKate Stone return fpu_s22; 1442b9c1b51eSKate Stone case dwarf_s23: 1443b9c1b51eSKate Stone return fpu_s23; 1444b9c1b51eSKate Stone case dwarf_s24: 1445b9c1b51eSKate Stone return fpu_s24; 1446b9c1b51eSKate Stone case dwarf_s25: 1447b9c1b51eSKate Stone return fpu_s25; 1448b9c1b51eSKate Stone case dwarf_s26: 1449b9c1b51eSKate Stone return fpu_s26; 1450b9c1b51eSKate Stone case dwarf_s27: 1451b9c1b51eSKate Stone return fpu_s27; 1452b9c1b51eSKate Stone case dwarf_s28: 1453b9c1b51eSKate Stone return fpu_s28; 1454b9c1b51eSKate Stone case dwarf_s29: 1455b9c1b51eSKate Stone return fpu_s29; 1456b9c1b51eSKate Stone case dwarf_s30: 1457b9c1b51eSKate Stone return fpu_s30; 1458b9c1b51eSKate Stone case dwarf_s31: 1459b9c1b51eSKate Stone return fpu_s31; 1460a63d08c9SGreg Clayton 1461a63d08c9SGreg Clayton default: 1462a63d08c9SGreg Clayton break; 1463a63d08c9SGreg Clayton } 1464b9c1b51eSKate Stone } else if (kind == eRegisterKindEHFrame) { 1465b9c1b51eSKate Stone switch (reg) { 1466b9c1b51eSKate Stone case ehframe_r0: 1467b9c1b51eSKate Stone return gpr_r0; 1468b9c1b51eSKate Stone case ehframe_r1: 1469b9c1b51eSKate Stone return gpr_r1; 1470b9c1b51eSKate Stone case ehframe_r2: 1471b9c1b51eSKate Stone return gpr_r2; 1472b9c1b51eSKate Stone case ehframe_r3: 1473b9c1b51eSKate Stone return gpr_r3; 1474b9c1b51eSKate Stone case ehframe_r4: 1475b9c1b51eSKate Stone return gpr_r4; 1476b9c1b51eSKate Stone case ehframe_r5: 1477b9c1b51eSKate Stone return gpr_r5; 1478b9c1b51eSKate Stone case ehframe_r6: 1479b9c1b51eSKate Stone return gpr_r6; 1480b9c1b51eSKate Stone case ehframe_r7: 1481b9c1b51eSKate Stone return gpr_r7; 1482b9c1b51eSKate Stone case ehframe_r8: 1483b9c1b51eSKate Stone return gpr_r8; 1484b9c1b51eSKate Stone case ehframe_r9: 1485b9c1b51eSKate Stone return gpr_r9; 1486b9c1b51eSKate Stone case ehframe_r10: 1487b9c1b51eSKate Stone return gpr_r10; 1488b9c1b51eSKate Stone case ehframe_r11: 1489b9c1b51eSKate Stone return gpr_r11; 1490b9c1b51eSKate Stone case ehframe_r12: 1491b9c1b51eSKate Stone return gpr_r12; 1492b9c1b51eSKate Stone case ehframe_sp: 1493b9c1b51eSKate Stone return gpr_sp; 1494b9c1b51eSKate Stone case ehframe_lr: 1495b9c1b51eSKate Stone return gpr_lr; 1496b9c1b51eSKate Stone case ehframe_pc: 1497b9c1b51eSKate Stone return gpr_pc; 1498b9c1b51eSKate Stone case ehframe_cpsr: 1499b9c1b51eSKate Stone return gpr_cpsr; 1500a63d08c9SGreg Clayton } 1501b9c1b51eSKate Stone } else if (kind == eRegisterKindLLDB) { 1502a63d08c9SGreg Clayton return reg; 1503a63d08c9SGreg Clayton } 1504a63d08c9SGreg Clayton return LLDB_INVALID_REGNUM; 1505a63d08c9SGreg Clayton } 1506a63d08c9SGreg Clayton 1507b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::NumSupportedHardwareBreakpoints() { 150890da3ce3SPavel Labath #if defined(__APPLE__) && defined(__arm__) 1509a63d08c9SGreg Clayton // Set the init value to something that will let us know that we need to 1510a63d08c9SGreg Clayton // autodetect how many breakpoints are supported dynamically... 1511a63d08c9SGreg Clayton static uint32_t g_num_supported_hw_breakpoints = UINT32_MAX; 1512b9c1b51eSKate Stone if (g_num_supported_hw_breakpoints == UINT32_MAX) { 1513a63d08c9SGreg Clayton // Set this to zero in case we can't tell if there are any HW breakpoints 1514a63d08c9SGreg Clayton g_num_supported_hw_breakpoints = 0; 1515a63d08c9SGreg Clayton 1516a63d08c9SGreg Clayton uint32_t register_DBGDIDR; 1517a63d08c9SGreg Clayton 1518a63d08c9SGreg Clayton asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 1519dce502edSGreg Clayton g_num_supported_hw_breakpoints = Bits32(register_DBGDIDR, 27, 24); 1520a63d08c9SGreg Clayton // Zero is reserved for the BRP count, so don't increment it if it is zero 1521a63d08c9SGreg Clayton if (g_num_supported_hw_breakpoints > 0) 1522a63d08c9SGreg Clayton g_num_supported_hw_breakpoints++; 1523b9c1b51eSKate Stone // if (log) log->Printf ("DBGDIDR=0x%8.8x (number BRP pairs = %u)", 1524b9c1b51eSKate Stone // register_DBGDIDR, g_num_supported_hw_breakpoints); 1525a63d08c9SGreg Clayton } 1526a63d08c9SGreg Clayton return g_num_supported_hw_breakpoints; 1527a63d08c9SGreg Clayton #else 1528a63d08c9SGreg Clayton // TODO: figure out remote case here! 1529a63d08c9SGreg Clayton return 6; 1530a63d08c9SGreg Clayton #endif 1531a63d08c9SGreg Clayton } 1532a63d08c9SGreg Clayton 1533b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::SetHardwareBreakpoint(lldb::addr_t addr, 1534b9c1b51eSKate Stone size_t size) { 1535a63d08c9SGreg Clayton // Make sure our address isn't bogus 1536a63d08c9SGreg Clayton if (addr & 1) 1537a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1538a63d08c9SGreg Clayton 1539a63d08c9SGreg Clayton int kret = ReadDBG(false); 1540a63d08c9SGreg Clayton 1541b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1542a63d08c9SGreg Clayton const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints(); 1543a63d08c9SGreg Clayton uint32_t i; 1544b9c1b51eSKate Stone for (i = 0; i < num_hw_breakpoints; ++i) { 1545a63d08c9SGreg Clayton if ((dbg.bcr[i] & BCR_ENABLE) == 0) 1546a63d08c9SGreg Clayton break; // We found an available hw breakpoint slot (in i) 1547a63d08c9SGreg Clayton } 1548a63d08c9SGreg Clayton 1549a63d08c9SGreg Clayton // See if we found an available hw breakpoint slot above 1550b9c1b51eSKate Stone if (i < num_hw_breakpoints) { 1551a63d08c9SGreg Clayton // Make sure bits 1:0 are clear in our address 1552a63d08c9SGreg Clayton dbg.bvr[i] = addr & ~((lldb::addr_t)3); 1553a63d08c9SGreg Clayton 1554b9c1b51eSKate Stone if (size == 2 || addr & 2) { 1555a63d08c9SGreg Clayton uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1; 1556a63d08c9SGreg Clayton 1557a63d08c9SGreg Clayton // We have a thumb breakpoint 1558a63d08c9SGreg Clayton // We have an ARM breakpoint 1559a63d08c9SGreg Clayton dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch 1560b9c1b51eSKate Stone byte_addr_select | // Set the correct byte address select 1561b9c1b51eSKate Stone // so we only trigger on the correct 1562b9c1b51eSKate Stone // opcode 1563a63d08c9SGreg Clayton S_USER | // Which modes should this breakpoint stop in? 1564a63d08c9SGreg Clayton BCR_ENABLE; // Enable this hardware breakpoint 1565b9c1b51eSKate Stone // if (log) log->Printf 1566b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 1567b9c1b51eSKate Stone // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 1568b9c1b51eSKate Stone // 0x%8.8x (Thumb)", 156989f138aeSGreg Clayton // addr, 157089f138aeSGreg Clayton // size, 157189f138aeSGreg Clayton // i, 157289f138aeSGreg Clayton // i, 157389f138aeSGreg Clayton // dbg.bvr[i], 157489f138aeSGreg Clayton // dbg.bcr[i]); 1575b9c1b51eSKate Stone } else if (size == 4) { 1576a63d08c9SGreg Clayton // We have an ARM breakpoint 1577b9c1b51eSKate Stone dbg.bcr[i] = 1578b9c1b51eSKate Stone BCR_M_IMVA_MATCH | // Stop on address mismatch 1579a63d08c9SGreg Clayton BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA 1580a63d08c9SGreg Clayton S_USER | // Which modes should this breakpoint stop in? 1581a63d08c9SGreg Clayton BCR_ENABLE; // Enable this hardware breakpoint 1582b9c1b51eSKate Stone // if (log) log->Printf 1583b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 1584b9c1b51eSKate Stone // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 1585b9c1b51eSKate Stone // 0x%8.8x (ARM)", 158689f138aeSGreg Clayton // addr, 158789f138aeSGreg Clayton // size, 158889f138aeSGreg Clayton // i, 158989f138aeSGreg Clayton // i, 159089f138aeSGreg Clayton // dbg.bvr[i], 159189f138aeSGreg Clayton // dbg.bcr[i]); 1592a63d08c9SGreg Clayton } 1593a63d08c9SGreg Clayton 1594a63d08c9SGreg Clayton kret = WriteDBG(); 1595b9c1b51eSKate Stone // if (log) log->Printf 1596b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint() 1597b9c1b51eSKate Stone // WriteDBG() => 0x%8.8x.", kret); 1598a63d08c9SGreg Clayton 1599a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1600a63d08c9SGreg Clayton return i; 1601a63d08c9SGreg Clayton } 160289f138aeSGreg Clayton // else 160389f138aeSGreg Clayton // { 1604b9c1b51eSKate Stone // if (log) log->Printf 1605b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(addr = 1606b9c1b51eSKate Stone // %8.8p, size = %u) => all hardware breakpoint resources are 1607b9c1b51eSKate Stone // being used.", addr, size); 160889f138aeSGreg Clayton // } 1609a63d08c9SGreg Clayton } 1610a63d08c9SGreg Clayton 1611a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1612a63d08c9SGreg Clayton } 1613a63d08c9SGreg Clayton 1614b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ClearHardwareBreakpoint(uint32_t hw_index) { 1615a63d08c9SGreg Clayton int kret = ReadDBG(false); 1616a63d08c9SGreg Clayton 1617a63d08c9SGreg Clayton const uint32_t num_hw_points = NumSupportedHardwareBreakpoints(); 1618b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1619b9c1b51eSKate Stone if (hw_index < num_hw_points) { 1620a63d08c9SGreg Clayton dbg.bcr[hw_index] = 0; 1621b9c1b51eSKate Stone // if (log) log->Printf 1622b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::SetHardwareBreakpoint( %u ) - 1623b9c1b51eSKate Stone // BVR%u = 0x%8.8x BCR%u = 0x%8.8x", 162489f138aeSGreg Clayton // hw_index, 162589f138aeSGreg Clayton // hw_index, 162689f138aeSGreg Clayton // dbg.bvr[hw_index], 162789f138aeSGreg Clayton // hw_index, 162889f138aeSGreg Clayton // dbg.bcr[hw_index]); 1629a63d08c9SGreg Clayton 1630a63d08c9SGreg Clayton kret = WriteDBG(); 1631a63d08c9SGreg Clayton 1632a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1633a63d08c9SGreg Clayton return true; 1634a63d08c9SGreg Clayton } 1635a63d08c9SGreg Clayton } 1636a63d08c9SGreg Clayton return false; 1637a63d08c9SGreg Clayton } 1638a63d08c9SGreg Clayton 1639b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::NumSupportedHardwareWatchpoints() { 164090da3ce3SPavel Labath #if defined(__APPLE__) && defined(__arm__) 1641a63d08c9SGreg Clayton // Set the init value to something that will let us know that we need to 1642a63d08c9SGreg Clayton // autodetect how many watchpoints are supported dynamically... 1643a63d08c9SGreg Clayton static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX; 1644b9c1b51eSKate Stone if (g_num_supported_hw_watchpoints == UINT32_MAX) { 1645a63d08c9SGreg Clayton // Set this to zero in case we can't tell if there are any HW breakpoints 1646a63d08c9SGreg Clayton g_num_supported_hw_watchpoints = 0; 1647a63d08c9SGreg Clayton 1648a63d08c9SGreg Clayton uint32_t register_DBGDIDR; 1649a63d08c9SGreg Clayton asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 1650dce502edSGreg Clayton g_num_supported_hw_watchpoints = Bits32(register_DBGDIDR, 31, 28) + 1; 1651b9c1b51eSKate Stone // if (log) log->Printf ("DBGDIDR=0x%8.8x (number WRP pairs = %u)", 1652b9c1b51eSKate Stone // register_DBGDIDR, g_num_supported_hw_watchpoints); 1653a63d08c9SGreg Clayton } 1654a63d08c9SGreg Clayton return g_num_supported_hw_watchpoints; 1655a63d08c9SGreg Clayton #else 1656a63d08c9SGreg Clayton // TODO: figure out remote case here! 1657a63d08c9SGreg Clayton return 2; 1658a63d08c9SGreg Clayton #endif 1659a63d08c9SGreg Clayton } 1660a63d08c9SGreg Clayton 1661b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::SetHardwareWatchpoint(lldb::addr_t addr, 1662b9c1b51eSKate Stone size_t size, 1663b9c1b51eSKate Stone bool read, 1664b9c1b51eSKate Stone bool write) { 1665b9c1b51eSKate Stone // if (log) log->Printf 1666b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(addr = %8.8p, size 1667b9c1b51eSKate Stone // = %u, read = %u, write = %u)", addr, size, read, write); 1668a63d08c9SGreg Clayton 1669a63d08c9SGreg Clayton const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 1670a63d08c9SGreg Clayton 1671a63d08c9SGreg Clayton // Can't watch zero bytes 1672a63d08c9SGreg Clayton if (size == 0) 1673a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1674a63d08c9SGreg Clayton 1675a63d08c9SGreg Clayton // We must watch for either read or write 1676a63d08c9SGreg Clayton if (read == false && write == false) 1677a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1678a63d08c9SGreg Clayton 1679a63d08c9SGreg Clayton // Can't watch more than 4 bytes per WVR/WCR pair 1680a63d08c9SGreg Clayton if (size > 4) 1681a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1682a63d08c9SGreg Clayton 1683a63d08c9SGreg Clayton // We can only watch up to four bytes that follow a 4 byte aligned address 1684a63d08c9SGreg Clayton // per watchpoint register pair. Since we have at most so we can only watch 1685a63d08c9SGreg Clayton // until the next 4 byte boundary and we need to make sure we can properly 1686a63d08c9SGreg Clayton // encode this. 1687a63d08c9SGreg Clayton uint32_t addr_word_offset = addr % 4; 1688b9c1b51eSKate Stone // if (log) log->Printf 1689b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - 1690b9c1b51eSKate Stone // addr_word_offset = 0x%8.8x", addr_word_offset); 1691a63d08c9SGreg Clayton 1692a63d08c9SGreg Clayton uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset; 1693b9c1b51eSKate Stone // if (log) log->Printf 1694b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - byte_mask = 1695b9c1b51eSKate Stone // 0x%8.8x", byte_mask); 1696a63d08c9SGreg Clayton if (byte_mask > 0xfu) 1697a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1698a63d08c9SGreg Clayton 1699a63d08c9SGreg Clayton // Read the debug state 1700a63d08c9SGreg Clayton int kret = ReadDBG(false); 1701a63d08c9SGreg Clayton 1702b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1703a63d08c9SGreg Clayton // Check to make sure we have the needed hardware support 1704a63d08c9SGreg Clayton uint32_t i = 0; 1705a63d08c9SGreg Clayton 1706b9c1b51eSKate Stone for (i = 0; i < num_hw_watchpoints; ++i) { 1707a63d08c9SGreg Clayton if ((dbg.wcr[i] & WCR_ENABLE) == 0) 1708a63d08c9SGreg Clayton break; // We found an available hw breakpoint slot (in i) 1709a63d08c9SGreg Clayton } 1710a63d08c9SGreg Clayton 1711a63d08c9SGreg Clayton // See if we found an available hw breakpoint slot above 1712b9c1b51eSKate Stone if (i < num_hw_watchpoints) { 1713a63d08c9SGreg Clayton // Make the byte_mask into a valid Byte Address Select mask 1714a63d08c9SGreg Clayton uint32_t byte_address_select = byte_mask << 5; 1715a63d08c9SGreg Clayton // Make sure bits 1:0 are clear in our address 1716a63d08c9SGreg Clayton dbg.wvr[i] = addr & ~((lldb::addr_t)3); 1717b9c1b51eSKate Stone dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA 1718b9c1b51eSKate Stone // that we will watch 1719a63d08c9SGreg Clayton S_USER | // Stop only in user mode 1720a63d08c9SGreg Clayton (read ? WCR_LOAD : 0) | // Stop on read access? 1721a63d08c9SGreg Clayton (write ? WCR_STORE : 0) | // Stop on write access? 1722a63d08c9SGreg Clayton WCR_ENABLE; // Enable this watchpoint; 1723a63d08c9SGreg Clayton 1724a63d08c9SGreg Clayton kret = WriteDBG(); 1725b9c1b51eSKate Stone // if (log) log->Printf 1726b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() 1727b9c1b51eSKate Stone // WriteDBG() => 0x%8.8x.", kret); 1728a63d08c9SGreg Clayton 1729a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1730a63d08c9SGreg Clayton return i; 1731b9c1b51eSKate Stone } else { 1732b9c1b51eSKate Stone // if (log) log->Printf 1733b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(): All 1734b9c1b51eSKate Stone // hardware resources (%u) are in use.", num_hw_watchpoints); 1735a63d08c9SGreg Clayton } 1736a63d08c9SGreg Clayton } 1737a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1738a63d08c9SGreg Clayton } 1739a63d08c9SGreg Clayton 1740b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ClearHardwareWatchpoint(uint32_t hw_index) { 1741a63d08c9SGreg Clayton int kret = ReadDBG(false); 1742a63d08c9SGreg Clayton 1743a63d08c9SGreg Clayton const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 1744b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1745b9c1b51eSKate Stone if (hw_index < num_hw_points) { 1746a63d08c9SGreg Clayton dbg.wcr[hw_index] = 0; 1747b9c1b51eSKate Stone // if (log) log->Printf 1748b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::ClearHardwareWatchpoint( %u ) - 1749b9c1b51eSKate Stone // WVR%u = 0x%8.8x WCR%u = 0x%8.8x", 175089f138aeSGreg Clayton // hw_index, 175189f138aeSGreg Clayton // hw_index, 175289f138aeSGreg Clayton // dbg.wvr[hw_index], 175389f138aeSGreg Clayton // hw_index, 175489f138aeSGreg Clayton // dbg.wcr[hw_index]); 1755a63d08c9SGreg Clayton 1756a63d08c9SGreg Clayton kret = WriteDBG(); 1757a63d08c9SGreg Clayton 1758a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1759a63d08c9SGreg Clayton return true; 1760a63d08c9SGreg Clayton } 1761a63d08c9SGreg Clayton } 1762a63d08c9SGreg Clayton return false; 1763a63d08c9SGreg Clayton } 1764