180814287SRaphael Isemann //===-- RegisterContextDarwin_arm.cpp -------------------------------------===// 2a63d08c9SGreg Clayton // 32946cd70SChandler Carruth // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 42946cd70SChandler Carruth // See https://llvm.org/LICENSE.txt for license information. 52946cd70SChandler Carruth // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6a63d08c9SGreg Clayton // 7a63d08c9SGreg Clayton //===----------------------------------------------------------------------===// 8a63d08c9SGreg Clayton 9a63d08c9SGreg Clayton #include "RegisterContextDarwin_arm.h" 10981a34c4SPavel Labath #include "RegisterContextDarwinConstants.h" 11a63d08c9SGreg Clayton 12666cc0b2SZachary Turner #include "lldb/Utility/DataBufferHeap.h" 13666cc0b2SZachary Turner #include "lldb/Utility/DataExtractor.h" 1401c3243fSZachary Turner #include "lldb/Utility/Endian.h" 156f9e6901SZachary Turner #include "lldb/Utility/Log.h" 16d821c997SPavel Labath #include "lldb/Utility/RegisterValue.h" 17d821c997SPavel Labath #include "lldb/Utility/Scalar.h" 1812a19904SDaniel Dunbar #include "llvm/Support/Compiler.h" 1912a19904SDaniel Dunbar 20dce502edSGreg Clayton #include "Plugins/Process/Utility/InstructionUtils.h" 21dce502edSGreg Clayton 22796ac80bSJonas Devlieghere #include <memory> 23796ac80bSJonas Devlieghere 24ff9c4ff1SEric Liu #include "Utility/ARM_DWARF_Registers.h" 2563bd0db0SJason Molenda #include "Utility/ARM_ehframe_Registers.h" 26a63d08c9SGreg Clayton 2728606954SSaleem Abdulrasool #include "llvm/ADT/STLExtras.h" 2828606954SSaleem Abdulrasool 29a63d08c9SGreg Clayton using namespace lldb; 30a63d08c9SGreg Clayton using namespace lldb_private; 31a63d08c9SGreg Clayton 32b9c1b51eSKate Stone enum { 33a63d08c9SGreg Clayton gpr_r0 = 0, 34a63d08c9SGreg Clayton gpr_r1, 35a63d08c9SGreg Clayton gpr_r2, 36a63d08c9SGreg Clayton gpr_r3, 37a63d08c9SGreg Clayton gpr_r4, 38a63d08c9SGreg Clayton gpr_r5, 39a63d08c9SGreg Clayton gpr_r6, 40a63d08c9SGreg Clayton gpr_r7, 41a63d08c9SGreg Clayton gpr_r8, 42a63d08c9SGreg Clayton gpr_r9, 43a63d08c9SGreg Clayton gpr_r10, 44a63d08c9SGreg Clayton gpr_r11, 45a63d08c9SGreg Clayton gpr_r12, 46b9c1b51eSKate Stone gpr_r13, 47b9c1b51eSKate Stone gpr_sp = gpr_r13, 48b9c1b51eSKate Stone gpr_r14, 49b9c1b51eSKate Stone gpr_lr = gpr_r14, 50b9c1b51eSKate Stone gpr_r15, 51b9c1b51eSKate Stone gpr_pc = gpr_r15, 52a63d08c9SGreg Clayton gpr_cpsr, 53a63d08c9SGreg Clayton 54a63d08c9SGreg Clayton fpu_s0, 55a63d08c9SGreg Clayton fpu_s1, 56a63d08c9SGreg Clayton fpu_s2, 57a63d08c9SGreg Clayton fpu_s3, 58a63d08c9SGreg Clayton fpu_s4, 59a63d08c9SGreg Clayton fpu_s5, 60a63d08c9SGreg Clayton fpu_s6, 61a63d08c9SGreg Clayton fpu_s7, 62a63d08c9SGreg Clayton fpu_s8, 63a63d08c9SGreg Clayton fpu_s9, 64a63d08c9SGreg Clayton fpu_s10, 65a63d08c9SGreg Clayton fpu_s11, 66a63d08c9SGreg Clayton fpu_s12, 67a63d08c9SGreg Clayton fpu_s13, 68a63d08c9SGreg Clayton fpu_s14, 69a63d08c9SGreg Clayton fpu_s15, 70a63d08c9SGreg Clayton fpu_s16, 71a63d08c9SGreg Clayton fpu_s17, 72a63d08c9SGreg Clayton fpu_s18, 73a63d08c9SGreg Clayton fpu_s19, 74a63d08c9SGreg Clayton fpu_s20, 75a63d08c9SGreg Clayton fpu_s21, 76a63d08c9SGreg Clayton fpu_s22, 77a63d08c9SGreg Clayton fpu_s23, 78a63d08c9SGreg Clayton fpu_s24, 79a63d08c9SGreg Clayton fpu_s25, 80a63d08c9SGreg Clayton fpu_s26, 81a63d08c9SGreg Clayton fpu_s27, 82a63d08c9SGreg Clayton fpu_s28, 83a63d08c9SGreg Clayton fpu_s29, 84a63d08c9SGreg Clayton fpu_s30, 85a63d08c9SGreg Clayton fpu_s31, 86a63d08c9SGreg Clayton fpu_fpscr, 87a63d08c9SGreg Clayton 88a63d08c9SGreg Clayton exc_exception, 89a63d08c9SGreg Clayton exc_fsr, 90a63d08c9SGreg Clayton exc_far, 91a63d08c9SGreg Clayton 92a63d08c9SGreg Clayton dbg_bvr0, 93a63d08c9SGreg Clayton dbg_bvr1, 94a63d08c9SGreg Clayton dbg_bvr2, 95a63d08c9SGreg Clayton dbg_bvr3, 96a63d08c9SGreg Clayton dbg_bvr4, 97a63d08c9SGreg Clayton dbg_bvr5, 98a63d08c9SGreg Clayton dbg_bvr6, 99a63d08c9SGreg Clayton dbg_bvr7, 100a63d08c9SGreg Clayton dbg_bvr8, 101a63d08c9SGreg Clayton dbg_bvr9, 102a63d08c9SGreg Clayton dbg_bvr10, 103a63d08c9SGreg Clayton dbg_bvr11, 104a63d08c9SGreg Clayton dbg_bvr12, 105a63d08c9SGreg Clayton dbg_bvr13, 106a63d08c9SGreg Clayton dbg_bvr14, 107a63d08c9SGreg Clayton dbg_bvr15, 108a63d08c9SGreg Clayton 109a63d08c9SGreg Clayton dbg_bcr0, 110a63d08c9SGreg Clayton dbg_bcr1, 111a63d08c9SGreg Clayton dbg_bcr2, 112a63d08c9SGreg Clayton dbg_bcr3, 113a63d08c9SGreg Clayton dbg_bcr4, 114a63d08c9SGreg Clayton dbg_bcr5, 115a63d08c9SGreg Clayton dbg_bcr6, 116a63d08c9SGreg Clayton dbg_bcr7, 117a63d08c9SGreg Clayton dbg_bcr8, 118a63d08c9SGreg Clayton dbg_bcr9, 119a63d08c9SGreg Clayton dbg_bcr10, 120a63d08c9SGreg Clayton dbg_bcr11, 121a63d08c9SGreg Clayton dbg_bcr12, 122a63d08c9SGreg Clayton dbg_bcr13, 123a63d08c9SGreg Clayton dbg_bcr14, 124a63d08c9SGreg Clayton dbg_bcr15, 125a63d08c9SGreg Clayton 126a63d08c9SGreg Clayton dbg_wvr0, 127a63d08c9SGreg Clayton dbg_wvr1, 128a63d08c9SGreg Clayton dbg_wvr2, 129a63d08c9SGreg Clayton dbg_wvr3, 130a63d08c9SGreg Clayton dbg_wvr4, 131a63d08c9SGreg Clayton dbg_wvr5, 132a63d08c9SGreg Clayton dbg_wvr6, 133a63d08c9SGreg Clayton dbg_wvr7, 134a63d08c9SGreg Clayton dbg_wvr8, 135a63d08c9SGreg Clayton dbg_wvr9, 136a63d08c9SGreg Clayton dbg_wvr10, 137a63d08c9SGreg Clayton dbg_wvr11, 138a63d08c9SGreg Clayton dbg_wvr12, 139a63d08c9SGreg Clayton dbg_wvr13, 140a63d08c9SGreg Clayton dbg_wvr14, 141a63d08c9SGreg Clayton dbg_wvr15, 142a63d08c9SGreg Clayton 143a63d08c9SGreg Clayton dbg_wcr0, 144a63d08c9SGreg Clayton dbg_wcr1, 145a63d08c9SGreg Clayton dbg_wcr2, 146a63d08c9SGreg Clayton dbg_wcr3, 147a63d08c9SGreg Clayton dbg_wcr4, 148a63d08c9SGreg Clayton dbg_wcr5, 149a63d08c9SGreg Clayton dbg_wcr6, 150a63d08c9SGreg Clayton dbg_wcr7, 151a63d08c9SGreg Clayton dbg_wcr8, 152a63d08c9SGreg Clayton dbg_wcr9, 153a63d08c9SGreg Clayton dbg_wcr10, 154a63d08c9SGreg Clayton dbg_wcr11, 155a63d08c9SGreg Clayton dbg_wcr12, 156a63d08c9SGreg Clayton dbg_wcr13, 157a63d08c9SGreg Clayton dbg_wcr14, 158a63d08c9SGreg Clayton dbg_wcr15, 159a63d08c9SGreg Clayton 160a63d08c9SGreg Clayton k_num_registers 161a63d08c9SGreg Clayton }; 162a63d08c9SGreg Clayton 163a63d08c9SGreg Clayton #define GPR_OFFSET(idx) ((idx)*4) 164a63d08c9SGreg Clayton #define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR)) 165b9c1b51eSKate Stone #define EXC_OFFSET(idx) \ 166b9c1b51eSKate Stone ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR) + \ 167b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU)) 168b9c1b51eSKate Stone #define DBG_OFFSET(reg) \ 169b9c1b51eSKate Stone ((LLVM_EXTENSION offsetof(RegisterContextDarwin_arm::DBG, reg) + \ 170b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::GPR) + \ 171b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU) + \ 172b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::EXC))) 173a63d08c9SGreg Clayton 174b9c1b51eSKate Stone #define DEFINE_DBG(reg, i) \ 175b9c1b51eSKate Stone #reg, NULL, sizeof(((RegisterContextDarwin_arm::DBG *) NULL)->reg[i]), \ 176b9c1b51eSKate Stone DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, \ 177b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 178b9c1b51eSKate Stone LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 179b9c1b51eSKate Stone LLDB_INVALID_REGNUM }, \ 180b9c1b51eSKate Stone nullptr, nullptr, nullptr, 0 181b9c1b51eSKate Stone #define REG_CONTEXT_SIZE \ 182b9c1b51eSKate Stone (sizeof(RegisterContextDarwin_arm::GPR) + \ 183b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU) + \ 184b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::EXC)) 185a63d08c9SGreg Clayton 186a63d08c9SGreg Clayton static RegisterInfo g_register_infos[] = { 187a63d08c9SGreg Clayton // General purpose registers 188b9c1b51eSKate Stone // NAME ALT SZ OFFSET ENCODING FORMAT 189b9c1b51eSKate Stone // EH_FRAME DWARF GENERIC 190b9c1b51eSKate Stone // PROCESS PLUGIN LLDB NATIVE 191b9c1b51eSKate Stone // ====== ======= == ============= ============= ============ 192b9c1b51eSKate Stone // =============== =============== ========================= 193b9c1b51eSKate Stone // ===================== ============= 194b9c1b51eSKate Stone {"r0", 195248a1305SKonrad Kleine nullptr, 196b9c1b51eSKate Stone 4, 197b9c1b51eSKate Stone GPR_OFFSET(0), 198b9c1b51eSKate Stone eEncodingUint, 199b9c1b51eSKate Stone eFormatHex, 200b9c1b51eSKate Stone {ehframe_r0, dwarf_r0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r0}, 201b9c1b51eSKate Stone nullptr, 202b9c1b51eSKate Stone nullptr, 203b9c1b51eSKate Stone nullptr, 204b9c1b51eSKate Stone 0}, 205b9c1b51eSKate Stone {"r1", 206248a1305SKonrad Kleine nullptr, 207b9c1b51eSKate Stone 4, 208b9c1b51eSKate Stone GPR_OFFSET(1), 209b9c1b51eSKate Stone eEncodingUint, 210b9c1b51eSKate Stone eFormatHex, 211b9c1b51eSKate Stone {ehframe_r1, dwarf_r1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r1}, 212b9c1b51eSKate Stone nullptr, 213b9c1b51eSKate Stone nullptr, 214b9c1b51eSKate Stone nullptr, 215b9c1b51eSKate Stone 0}, 216b9c1b51eSKate Stone {"r2", 217248a1305SKonrad Kleine nullptr, 218b9c1b51eSKate Stone 4, 219b9c1b51eSKate Stone GPR_OFFSET(2), 220b9c1b51eSKate Stone eEncodingUint, 221b9c1b51eSKate Stone eFormatHex, 222b9c1b51eSKate Stone {ehframe_r2, dwarf_r2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r2}, 223b9c1b51eSKate Stone nullptr, 224b9c1b51eSKate Stone nullptr, 225b9c1b51eSKate Stone nullptr, 226b9c1b51eSKate Stone 0}, 227b9c1b51eSKate Stone {"r3", 228248a1305SKonrad Kleine nullptr, 229b9c1b51eSKate Stone 4, 230b9c1b51eSKate Stone GPR_OFFSET(3), 231b9c1b51eSKate Stone eEncodingUint, 232b9c1b51eSKate Stone eFormatHex, 233b9c1b51eSKate Stone {ehframe_r3, dwarf_r3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r3}, 234b9c1b51eSKate Stone nullptr, 235b9c1b51eSKate Stone nullptr, 236b9c1b51eSKate Stone nullptr, 237b9c1b51eSKate Stone 0}, 238b9c1b51eSKate Stone {"r4", 239248a1305SKonrad Kleine nullptr, 240b9c1b51eSKate Stone 4, 241b9c1b51eSKate Stone GPR_OFFSET(4), 242b9c1b51eSKate Stone eEncodingUint, 243b9c1b51eSKate Stone eFormatHex, 244b9c1b51eSKate Stone {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4}, 245b9c1b51eSKate Stone nullptr, 246b9c1b51eSKate Stone nullptr, 247b9c1b51eSKate Stone nullptr, 248b9c1b51eSKate Stone 0}, 249b9c1b51eSKate Stone {"r5", 250248a1305SKonrad Kleine nullptr, 251b9c1b51eSKate Stone 4, 252b9c1b51eSKate Stone GPR_OFFSET(5), 253b9c1b51eSKate Stone eEncodingUint, 254b9c1b51eSKate Stone eFormatHex, 255b9c1b51eSKate Stone {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5}, 256b9c1b51eSKate Stone nullptr, 257b9c1b51eSKate Stone nullptr, 258b9c1b51eSKate Stone nullptr, 259b9c1b51eSKate Stone 0}, 260b9c1b51eSKate Stone {"r6", 261248a1305SKonrad Kleine nullptr, 262b9c1b51eSKate Stone 4, 263b9c1b51eSKate Stone GPR_OFFSET(6), 264b9c1b51eSKate Stone eEncodingUint, 265b9c1b51eSKate Stone eFormatHex, 266b9c1b51eSKate Stone {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6}, 267b9c1b51eSKate Stone nullptr, 268b9c1b51eSKate Stone nullptr, 269b9c1b51eSKate Stone nullptr, 270b9c1b51eSKate Stone 0}, 271b9c1b51eSKate Stone {"r7", 272248a1305SKonrad Kleine nullptr, 273b9c1b51eSKate Stone 4, 274b9c1b51eSKate Stone GPR_OFFSET(7), 275b9c1b51eSKate Stone eEncodingUint, 276b9c1b51eSKate Stone eFormatHex, 277b9c1b51eSKate Stone {ehframe_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, 278b9c1b51eSKate Stone gpr_r7}, 279b9c1b51eSKate Stone nullptr, 280b9c1b51eSKate Stone nullptr, 281b9c1b51eSKate Stone nullptr, 282b9c1b51eSKate Stone 0}, 283b9c1b51eSKate Stone {"r8", 284248a1305SKonrad Kleine nullptr, 285b9c1b51eSKate Stone 4, 286b9c1b51eSKate Stone GPR_OFFSET(8), 287b9c1b51eSKate Stone eEncodingUint, 288b9c1b51eSKate Stone eFormatHex, 289b9c1b51eSKate Stone {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8}, 290b9c1b51eSKate Stone nullptr, 291b9c1b51eSKate Stone nullptr, 292b9c1b51eSKate Stone nullptr, 293b9c1b51eSKate Stone 0}, 294b9c1b51eSKate Stone {"r9", 295248a1305SKonrad Kleine nullptr, 296b9c1b51eSKate Stone 4, 297b9c1b51eSKate Stone GPR_OFFSET(9), 298b9c1b51eSKate Stone eEncodingUint, 299b9c1b51eSKate Stone eFormatHex, 300b9c1b51eSKate Stone {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9}, 301b9c1b51eSKate Stone nullptr, 302b9c1b51eSKate Stone nullptr, 303b9c1b51eSKate Stone nullptr, 304b9c1b51eSKate Stone 0}, 305b9c1b51eSKate Stone {"r10", 306248a1305SKonrad Kleine nullptr, 307b9c1b51eSKate Stone 4, 308b9c1b51eSKate Stone GPR_OFFSET(10), 309b9c1b51eSKate Stone eEncodingUint, 310b9c1b51eSKate Stone eFormatHex, 311b9c1b51eSKate Stone {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 312b9c1b51eSKate Stone gpr_r10}, 313b9c1b51eSKate Stone nullptr, 314b9c1b51eSKate Stone nullptr, 315b9c1b51eSKate Stone nullptr, 316b9c1b51eSKate Stone 0}, 317b9c1b51eSKate Stone {"r11", 318248a1305SKonrad Kleine nullptr, 319b9c1b51eSKate Stone 4, 320b9c1b51eSKate Stone GPR_OFFSET(11), 321b9c1b51eSKate Stone eEncodingUint, 322b9c1b51eSKate Stone eFormatHex, 323b9c1b51eSKate Stone {ehframe_r11, dwarf_r11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 324b9c1b51eSKate Stone gpr_r11}, 325b9c1b51eSKate Stone nullptr, 326b9c1b51eSKate Stone nullptr, 327b9c1b51eSKate Stone nullptr, 328b9c1b51eSKate Stone 0}, 329b9c1b51eSKate Stone {"r12", 330248a1305SKonrad Kleine nullptr, 331b9c1b51eSKate Stone 4, 332b9c1b51eSKate Stone GPR_OFFSET(12), 333b9c1b51eSKate Stone eEncodingUint, 334b9c1b51eSKate Stone eFormatHex, 335b9c1b51eSKate Stone {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 336b9c1b51eSKate Stone gpr_r12}, 337b9c1b51eSKate Stone nullptr, 338b9c1b51eSKate Stone nullptr, 339b9c1b51eSKate Stone nullptr, 340b9c1b51eSKate Stone 0}, 341b9c1b51eSKate Stone {"sp", 342b9c1b51eSKate Stone "r13", 343b9c1b51eSKate Stone 4, 344b9c1b51eSKate Stone GPR_OFFSET(13), 345b9c1b51eSKate Stone eEncodingUint, 346b9c1b51eSKate Stone eFormatHex, 347b9c1b51eSKate Stone {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, 348b9c1b51eSKate Stone gpr_sp}, 349b9c1b51eSKate Stone nullptr, 350b9c1b51eSKate Stone nullptr, 351b9c1b51eSKate Stone nullptr, 352b9c1b51eSKate Stone 0}, 353b9c1b51eSKate Stone {"lr", 354b9c1b51eSKate Stone "r14", 355b9c1b51eSKate Stone 4, 356b9c1b51eSKate Stone GPR_OFFSET(14), 357b9c1b51eSKate Stone eEncodingUint, 358b9c1b51eSKate Stone eFormatHex, 359b9c1b51eSKate Stone {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, 360b9c1b51eSKate Stone gpr_lr}, 361b9c1b51eSKate Stone nullptr, 362b9c1b51eSKate Stone nullptr, 363b9c1b51eSKate Stone nullptr, 364b9c1b51eSKate Stone 0}, 365b9c1b51eSKate Stone {"pc", 366b9c1b51eSKate Stone "r15", 367b9c1b51eSKate Stone 4, 368b9c1b51eSKate Stone GPR_OFFSET(15), 369b9c1b51eSKate Stone eEncodingUint, 370b9c1b51eSKate Stone eFormatHex, 371b9c1b51eSKate Stone {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, 372b9c1b51eSKate Stone gpr_pc}, 373b9c1b51eSKate Stone nullptr, 374b9c1b51eSKate Stone nullptr, 375b9c1b51eSKate Stone nullptr, 376b9c1b51eSKate Stone 0}, 377b9c1b51eSKate Stone {"cpsr", 378b9c1b51eSKate Stone "psr", 379b9c1b51eSKate Stone 4, 380b9c1b51eSKate Stone GPR_OFFSET(16), 381b9c1b51eSKate Stone eEncodingUint, 382b9c1b51eSKate Stone eFormatHex, 383b9c1b51eSKate Stone {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM, 384b9c1b51eSKate Stone gpr_cpsr}, 385b9c1b51eSKate Stone nullptr, 386b9c1b51eSKate Stone nullptr, 387b9c1b51eSKate Stone nullptr, 388b9c1b51eSKate Stone 0}, 389a63d08c9SGreg Clayton 390b9c1b51eSKate Stone {"s0", 391248a1305SKonrad Kleine nullptr, 392b9c1b51eSKate Stone 4, 393b9c1b51eSKate Stone FPU_OFFSET(0), 394b9c1b51eSKate Stone eEncodingIEEE754, 395b9c1b51eSKate Stone eFormatFloat, 396b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 397b9c1b51eSKate Stone fpu_s0}, 398b9c1b51eSKate Stone nullptr, 399b9c1b51eSKate Stone nullptr, 400b9c1b51eSKate Stone nullptr, 401b9c1b51eSKate Stone 0}, 402b9c1b51eSKate Stone {"s1", 403248a1305SKonrad Kleine nullptr, 404b9c1b51eSKate Stone 4, 405b9c1b51eSKate Stone FPU_OFFSET(1), 406b9c1b51eSKate Stone eEncodingIEEE754, 407b9c1b51eSKate Stone eFormatFloat, 408b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 409b9c1b51eSKate Stone fpu_s1}, 410b9c1b51eSKate Stone nullptr, 411b9c1b51eSKate Stone nullptr, 412b9c1b51eSKate Stone nullptr, 413b9c1b51eSKate Stone 0}, 414b9c1b51eSKate Stone {"s2", 415248a1305SKonrad Kleine nullptr, 416b9c1b51eSKate Stone 4, 417b9c1b51eSKate Stone FPU_OFFSET(2), 418b9c1b51eSKate Stone eEncodingIEEE754, 419b9c1b51eSKate Stone eFormatFloat, 420b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 421b9c1b51eSKate Stone fpu_s2}, 422b9c1b51eSKate Stone nullptr, 423b9c1b51eSKate Stone nullptr, 424b9c1b51eSKate Stone nullptr, 425b9c1b51eSKate Stone 0}, 426b9c1b51eSKate Stone {"s3", 427248a1305SKonrad Kleine nullptr, 428b9c1b51eSKate Stone 4, 429b9c1b51eSKate Stone FPU_OFFSET(3), 430b9c1b51eSKate Stone eEncodingIEEE754, 431b9c1b51eSKate Stone eFormatFloat, 432b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 433b9c1b51eSKate Stone fpu_s3}, 434b9c1b51eSKate Stone nullptr, 435b9c1b51eSKate Stone nullptr, 436b9c1b51eSKate Stone nullptr, 437b9c1b51eSKate Stone 0}, 438b9c1b51eSKate Stone {"s4", 439248a1305SKonrad Kleine nullptr, 440b9c1b51eSKate Stone 4, 441b9c1b51eSKate Stone FPU_OFFSET(4), 442b9c1b51eSKate Stone eEncodingIEEE754, 443b9c1b51eSKate Stone eFormatFloat, 444b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 445b9c1b51eSKate Stone fpu_s4}, 446b9c1b51eSKate Stone nullptr, 447b9c1b51eSKate Stone nullptr, 448b9c1b51eSKate Stone nullptr, 449b9c1b51eSKate Stone 0}, 450b9c1b51eSKate Stone {"s5", 451248a1305SKonrad Kleine nullptr, 452b9c1b51eSKate Stone 4, 453b9c1b51eSKate Stone FPU_OFFSET(5), 454b9c1b51eSKate Stone eEncodingIEEE754, 455b9c1b51eSKate Stone eFormatFloat, 456b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 457b9c1b51eSKate Stone fpu_s5}, 458b9c1b51eSKate Stone nullptr, 459b9c1b51eSKate Stone nullptr, 460b9c1b51eSKate Stone nullptr, 461b9c1b51eSKate Stone 0}, 462b9c1b51eSKate Stone {"s6", 463248a1305SKonrad Kleine nullptr, 464b9c1b51eSKate Stone 4, 465b9c1b51eSKate Stone FPU_OFFSET(6), 466b9c1b51eSKate Stone eEncodingIEEE754, 467b9c1b51eSKate Stone eFormatFloat, 468b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 469b9c1b51eSKate Stone fpu_s6}, 470b9c1b51eSKate Stone nullptr, 471b9c1b51eSKate Stone nullptr, 472b9c1b51eSKate Stone nullptr, 473b9c1b51eSKate Stone 0}, 474b9c1b51eSKate Stone {"s7", 475248a1305SKonrad Kleine nullptr, 476b9c1b51eSKate Stone 4, 477b9c1b51eSKate Stone FPU_OFFSET(7), 478b9c1b51eSKate Stone eEncodingIEEE754, 479b9c1b51eSKate Stone eFormatFloat, 480b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 481b9c1b51eSKate Stone fpu_s7}, 482b9c1b51eSKate Stone nullptr, 483b9c1b51eSKate Stone nullptr, 484b9c1b51eSKate Stone nullptr, 485b9c1b51eSKate Stone 0}, 486b9c1b51eSKate Stone {"s8", 487248a1305SKonrad Kleine nullptr, 488b9c1b51eSKate Stone 4, 489b9c1b51eSKate Stone FPU_OFFSET(8), 490b9c1b51eSKate Stone eEncodingIEEE754, 491b9c1b51eSKate Stone eFormatFloat, 492b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 493b9c1b51eSKate Stone fpu_s8}, 494b9c1b51eSKate Stone nullptr, 495b9c1b51eSKate Stone nullptr, 496b9c1b51eSKate Stone nullptr, 497b9c1b51eSKate Stone 0}, 498b9c1b51eSKate Stone {"s9", 499248a1305SKonrad Kleine nullptr, 500b9c1b51eSKate Stone 4, 501b9c1b51eSKate Stone FPU_OFFSET(9), 502b9c1b51eSKate Stone eEncodingIEEE754, 503b9c1b51eSKate Stone eFormatFloat, 504b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 505b9c1b51eSKate Stone fpu_s9}, 506b9c1b51eSKate Stone nullptr, 507b9c1b51eSKate Stone nullptr, 508b9c1b51eSKate Stone nullptr, 509b9c1b51eSKate Stone 0}, 510b9c1b51eSKate Stone {"s10", 511248a1305SKonrad Kleine nullptr, 512b9c1b51eSKate Stone 4, 513b9c1b51eSKate Stone FPU_OFFSET(10), 514b9c1b51eSKate Stone eEncodingIEEE754, 515b9c1b51eSKate Stone eFormatFloat, 516b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 517b9c1b51eSKate Stone fpu_s10}, 518b9c1b51eSKate Stone nullptr, 519b9c1b51eSKate Stone nullptr, 520b9c1b51eSKate Stone nullptr, 521b9c1b51eSKate Stone 0}, 522b9c1b51eSKate Stone {"s11", 523248a1305SKonrad Kleine nullptr, 524b9c1b51eSKate Stone 4, 525b9c1b51eSKate Stone FPU_OFFSET(11), 526b9c1b51eSKate Stone eEncodingIEEE754, 527b9c1b51eSKate Stone eFormatFloat, 528b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 529b9c1b51eSKate Stone fpu_s11}, 530b9c1b51eSKate Stone nullptr, 531b9c1b51eSKate Stone nullptr, 532b9c1b51eSKate Stone nullptr, 533b9c1b51eSKate Stone 0}, 534b9c1b51eSKate Stone {"s12", 535248a1305SKonrad Kleine nullptr, 536b9c1b51eSKate Stone 4, 537b9c1b51eSKate Stone FPU_OFFSET(12), 538b9c1b51eSKate Stone eEncodingIEEE754, 539b9c1b51eSKate Stone eFormatFloat, 540b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 541b9c1b51eSKate Stone fpu_s12}, 542b9c1b51eSKate Stone nullptr, 543b9c1b51eSKate Stone nullptr, 544b9c1b51eSKate Stone nullptr, 545b9c1b51eSKate Stone 0}, 546b9c1b51eSKate Stone {"s13", 547248a1305SKonrad Kleine nullptr, 548b9c1b51eSKate Stone 4, 549b9c1b51eSKate Stone FPU_OFFSET(13), 550b9c1b51eSKate Stone eEncodingIEEE754, 551b9c1b51eSKate Stone eFormatFloat, 552b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 553b9c1b51eSKate Stone fpu_s13}, 554b9c1b51eSKate Stone nullptr, 555b9c1b51eSKate Stone nullptr, 556b9c1b51eSKate Stone nullptr, 557b9c1b51eSKate Stone 0}, 558b9c1b51eSKate Stone {"s14", 559248a1305SKonrad Kleine nullptr, 560b9c1b51eSKate Stone 4, 561b9c1b51eSKate Stone FPU_OFFSET(14), 562b9c1b51eSKate Stone eEncodingIEEE754, 563b9c1b51eSKate Stone eFormatFloat, 564b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 565b9c1b51eSKate Stone fpu_s14}, 566b9c1b51eSKate Stone nullptr, 567b9c1b51eSKate Stone nullptr, 568b9c1b51eSKate Stone nullptr, 569b9c1b51eSKate Stone 0}, 570b9c1b51eSKate Stone {"s15", 571248a1305SKonrad Kleine nullptr, 572b9c1b51eSKate Stone 4, 573b9c1b51eSKate Stone FPU_OFFSET(15), 574b9c1b51eSKate Stone eEncodingIEEE754, 575b9c1b51eSKate Stone eFormatFloat, 576b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 577b9c1b51eSKate Stone fpu_s15}, 578b9c1b51eSKate Stone nullptr, 579b9c1b51eSKate Stone nullptr, 580b9c1b51eSKate Stone nullptr, 581b9c1b51eSKate Stone 0}, 582b9c1b51eSKate Stone {"s16", 583248a1305SKonrad Kleine nullptr, 584b9c1b51eSKate Stone 4, 585b9c1b51eSKate Stone FPU_OFFSET(16), 586b9c1b51eSKate Stone eEncodingIEEE754, 587b9c1b51eSKate Stone eFormatFloat, 588b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 589b9c1b51eSKate Stone fpu_s16}, 590b9c1b51eSKate Stone nullptr, 591b9c1b51eSKate Stone nullptr, 592b9c1b51eSKate Stone nullptr, 593b9c1b51eSKate Stone 0}, 594b9c1b51eSKate Stone {"s17", 595248a1305SKonrad Kleine nullptr, 596b9c1b51eSKate Stone 4, 597b9c1b51eSKate Stone FPU_OFFSET(17), 598b9c1b51eSKate Stone eEncodingIEEE754, 599b9c1b51eSKate Stone eFormatFloat, 600b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 601b9c1b51eSKate Stone fpu_s17}, 602b9c1b51eSKate Stone nullptr, 603b9c1b51eSKate Stone nullptr, 604b9c1b51eSKate Stone nullptr, 605b9c1b51eSKate Stone 0}, 606b9c1b51eSKate Stone {"s18", 607248a1305SKonrad Kleine nullptr, 608b9c1b51eSKate Stone 4, 609b9c1b51eSKate Stone FPU_OFFSET(18), 610b9c1b51eSKate Stone eEncodingIEEE754, 611b9c1b51eSKate Stone eFormatFloat, 612b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 613b9c1b51eSKate Stone fpu_s18}, 614b9c1b51eSKate Stone nullptr, 615b9c1b51eSKate Stone nullptr, 616b9c1b51eSKate Stone nullptr, 617b9c1b51eSKate Stone 0}, 618b9c1b51eSKate Stone {"s19", 619248a1305SKonrad Kleine nullptr, 620b9c1b51eSKate Stone 4, 621b9c1b51eSKate Stone FPU_OFFSET(19), 622b9c1b51eSKate Stone eEncodingIEEE754, 623b9c1b51eSKate Stone eFormatFloat, 624b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 625b9c1b51eSKate Stone fpu_s19}, 626b9c1b51eSKate Stone nullptr, 627b9c1b51eSKate Stone nullptr, 628b9c1b51eSKate Stone nullptr, 629b9c1b51eSKate Stone 0}, 630b9c1b51eSKate Stone {"s20", 631248a1305SKonrad Kleine nullptr, 632b9c1b51eSKate Stone 4, 633b9c1b51eSKate Stone FPU_OFFSET(20), 634b9c1b51eSKate Stone eEncodingIEEE754, 635b9c1b51eSKate Stone eFormatFloat, 636b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 637b9c1b51eSKate Stone fpu_s20}, 638b9c1b51eSKate Stone nullptr, 639b9c1b51eSKate Stone nullptr, 640b9c1b51eSKate Stone nullptr, 641b9c1b51eSKate Stone 0}, 642b9c1b51eSKate Stone {"s21", 643248a1305SKonrad Kleine nullptr, 644b9c1b51eSKate Stone 4, 645b9c1b51eSKate Stone FPU_OFFSET(21), 646b9c1b51eSKate Stone eEncodingIEEE754, 647b9c1b51eSKate Stone eFormatFloat, 648b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 649b9c1b51eSKate Stone fpu_s21}, 650b9c1b51eSKate Stone nullptr, 651b9c1b51eSKate Stone nullptr, 652b9c1b51eSKate Stone nullptr, 653b9c1b51eSKate Stone 0}, 654b9c1b51eSKate Stone {"s22", 655248a1305SKonrad Kleine nullptr, 656b9c1b51eSKate Stone 4, 657b9c1b51eSKate Stone FPU_OFFSET(22), 658b9c1b51eSKate Stone eEncodingIEEE754, 659b9c1b51eSKate Stone eFormatFloat, 660b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 661b9c1b51eSKate Stone fpu_s22}, 662b9c1b51eSKate Stone nullptr, 663b9c1b51eSKate Stone nullptr, 664b9c1b51eSKate Stone nullptr, 665b9c1b51eSKate Stone 0}, 666b9c1b51eSKate Stone {"s23", 667248a1305SKonrad Kleine nullptr, 668b9c1b51eSKate Stone 4, 669b9c1b51eSKate Stone FPU_OFFSET(23), 670b9c1b51eSKate Stone eEncodingIEEE754, 671b9c1b51eSKate Stone eFormatFloat, 672b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 673b9c1b51eSKate Stone fpu_s23}, 674b9c1b51eSKate Stone nullptr, 675b9c1b51eSKate Stone nullptr, 676b9c1b51eSKate Stone nullptr, 677b9c1b51eSKate Stone 0}, 678b9c1b51eSKate Stone {"s24", 679248a1305SKonrad Kleine nullptr, 680b9c1b51eSKate Stone 4, 681b9c1b51eSKate Stone FPU_OFFSET(24), 682b9c1b51eSKate Stone eEncodingIEEE754, 683b9c1b51eSKate Stone eFormatFloat, 684b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 685b9c1b51eSKate Stone fpu_s24}, 686b9c1b51eSKate Stone nullptr, 687b9c1b51eSKate Stone nullptr, 688b9c1b51eSKate Stone nullptr, 689b9c1b51eSKate Stone 0}, 690b9c1b51eSKate Stone {"s25", 691248a1305SKonrad Kleine nullptr, 692b9c1b51eSKate Stone 4, 693b9c1b51eSKate Stone FPU_OFFSET(25), 694b9c1b51eSKate Stone eEncodingIEEE754, 695b9c1b51eSKate Stone eFormatFloat, 696b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 697b9c1b51eSKate Stone fpu_s25}, 698b9c1b51eSKate Stone nullptr, 699b9c1b51eSKate Stone nullptr, 700b9c1b51eSKate Stone nullptr, 701b9c1b51eSKate Stone 0}, 702b9c1b51eSKate Stone {"s26", 703248a1305SKonrad Kleine nullptr, 704b9c1b51eSKate Stone 4, 705b9c1b51eSKate Stone FPU_OFFSET(26), 706b9c1b51eSKate Stone eEncodingIEEE754, 707b9c1b51eSKate Stone eFormatFloat, 708b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 709b9c1b51eSKate Stone fpu_s26}, 710b9c1b51eSKate Stone nullptr, 711b9c1b51eSKate Stone nullptr, 712b9c1b51eSKate Stone nullptr, 713b9c1b51eSKate Stone 0}, 714b9c1b51eSKate Stone {"s27", 715248a1305SKonrad Kleine nullptr, 716b9c1b51eSKate Stone 4, 717b9c1b51eSKate Stone FPU_OFFSET(27), 718b9c1b51eSKate Stone eEncodingIEEE754, 719b9c1b51eSKate Stone eFormatFloat, 720b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 721b9c1b51eSKate Stone fpu_s27}, 722b9c1b51eSKate Stone nullptr, 723b9c1b51eSKate Stone nullptr, 724b9c1b51eSKate Stone nullptr, 725b9c1b51eSKate Stone 0}, 726b9c1b51eSKate Stone {"s28", 727248a1305SKonrad Kleine nullptr, 728b9c1b51eSKate Stone 4, 729b9c1b51eSKate Stone FPU_OFFSET(28), 730b9c1b51eSKate Stone eEncodingIEEE754, 731b9c1b51eSKate Stone eFormatFloat, 732b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 733b9c1b51eSKate Stone fpu_s28}, 734b9c1b51eSKate Stone nullptr, 735b9c1b51eSKate Stone nullptr, 736b9c1b51eSKate Stone nullptr, 737b9c1b51eSKate Stone 0}, 738b9c1b51eSKate Stone {"s29", 739248a1305SKonrad Kleine nullptr, 740b9c1b51eSKate Stone 4, 741b9c1b51eSKate Stone FPU_OFFSET(29), 742b9c1b51eSKate Stone eEncodingIEEE754, 743b9c1b51eSKate Stone eFormatFloat, 744b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 745b9c1b51eSKate Stone fpu_s29}, 746b9c1b51eSKate Stone nullptr, 747b9c1b51eSKate Stone nullptr, 748b9c1b51eSKate Stone nullptr, 749b9c1b51eSKate Stone 0}, 750b9c1b51eSKate Stone {"s30", 751248a1305SKonrad Kleine nullptr, 752b9c1b51eSKate Stone 4, 753b9c1b51eSKate Stone FPU_OFFSET(30), 754b9c1b51eSKate Stone eEncodingIEEE754, 755b9c1b51eSKate Stone eFormatFloat, 756b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 757b9c1b51eSKate Stone fpu_s30}, 758b9c1b51eSKate Stone nullptr, 759b9c1b51eSKate Stone nullptr, 760b9c1b51eSKate Stone nullptr, 761b9c1b51eSKate Stone 0}, 762b9c1b51eSKate Stone {"s31", 763248a1305SKonrad Kleine nullptr, 764b9c1b51eSKate Stone 4, 765b9c1b51eSKate Stone FPU_OFFSET(31), 766b9c1b51eSKate Stone eEncodingIEEE754, 767b9c1b51eSKate Stone eFormatFloat, 768b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 769b9c1b51eSKate Stone fpu_s31}, 770b9c1b51eSKate Stone nullptr, 771b9c1b51eSKate Stone nullptr, 772b9c1b51eSKate Stone nullptr, 773b9c1b51eSKate Stone 0}, 774b9c1b51eSKate Stone {"fpscr", 775248a1305SKonrad Kleine nullptr, 776b9c1b51eSKate Stone 4, 777b9c1b51eSKate Stone FPU_OFFSET(32), 778b9c1b51eSKate Stone eEncodingUint, 779b9c1b51eSKate Stone eFormatHex, 780b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 781b9c1b51eSKate Stone LLDB_INVALID_REGNUM, fpu_fpscr}, 782b9c1b51eSKate Stone nullptr, 783b9c1b51eSKate Stone nullptr, 784b9c1b51eSKate Stone nullptr, 785b9c1b51eSKate Stone 0}, 786a63d08c9SGreg Clayton 787b9c1b51eSKate Stone {"exception", 788248a1305SKonrad Kleine nullptr, 789b9c1b51eSKate Stone 4, 790b9c1b51eSKate Stone EXC_OFFSET(0), 791b9c1b51eSKate Stone eEncodingUint, 792b9c1b51eSKate Stone eFormatHex, 793b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 794b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_exception}, 795b9c1b51eSKate Stone nullptr, 796b9c1b51eSKate Stone nullptr, 797b9c1b51eSKate Stone nullptr, 798b9c1b51eSKate Stone 0}, 799b9c1b51eSKate Stone {"fsr", 800248a1305SKonrad Kleine nullptr, 801b9c1b51eSKate Stone 4, 802b9c1b51eSKate Stone EXC_OFFSET(1), 803b9c1b51eSKate Stone eEncodingUint, 804b9c1b51eSKate Stone eFormatHex, 805b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 806b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_fsr}, 807b9c1b51eSKate Stone nullptr, 808b9c1b51eSKate Stone nullptr, 809b9c1b51eSKate Stone nullptr, 810b9c1b51eSKate Stone 0}, 811b9c1b51eSKate Stone {"far", 812248a1305SKonrad Kleine nullptr, 813b9c1b51eSKate Stone 4, 814b9c1b51eSKate Stone EXC_OFFSET(2), 815b9c1b51eSKate Stone eEncodingUint, 816b9c1b51eSKate Stone eFormatHex, 817b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 818b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_far}, 819b9c1b51eSKate Stone nullptr, 820b9c1b51eSKate Stone nullptr, 821b9c1b51eSKate Stone nullptr, 822b9c1b51eSKate Stone 0}, 823a63d08c9SGreg Clayton 824a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 0)}, 825a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 1)}, 826a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 2)}, 827a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 3)}, 828a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 4)}, 829a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 5)}, 830a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 6)}, 831a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 7)}, 832a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 8)}, 833a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 9)}, 834a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 10)}, 835a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 11)}, 836a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 12)}, 837a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 13)}, 838a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 14)}, 839a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 15)}, 840a63d08c9SGreg Clayton 841a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 0)}, 842a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 1)}, 843a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 2)}, 844a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 3)}, 845a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 4)}, 846a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 5)}, 847a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 6)}, 848a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 7)}, 849a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 8)}, 850a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 9)}, 851a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 10)}, 852a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 11)}, 853a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 12)}, 854a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 13)}, 855a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 14)}, 856a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 15)}, 857a63d08c9SGreg Clayton 858a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 0)}, 859a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 1)}, 860a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 2)}, 861a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 3)}, 862a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 4)}, 863a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 5)}, 864a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 6)}, 865a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 7)}, 866a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 8)}, 867a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 9)}, 868a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 10)}, 869a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 11)}, 870a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 12)}, 871a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 13)}, 872a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 14)}, 873a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 15)}, 874a63d08c9SGreg Clayton 875a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 0)}, 876a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 1)}, 877a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 2)}, 878a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 3)}, 879a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 4)}, 880a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 5)}, 881a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 6)}, 882a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 7)}, 883a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 8)}, 884a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 9)}, 885a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 10)}, 886a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 11)}, 887a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 12)}, 888a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 13)}, 889a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 14)}, 890b9c1b51eSKate Stone {DEFINE_DBG(wcr, 15)}}; 891a63d08c9SGreg Clayton 892a63d08c9SGreg Clayton // General purpose registers 893b9c1b51eSKate Stone static uint32_t g_gpr_regnums[] = { 894b9c1b51eSKate Stone gpr_r0, gpr_r1, gpr_r2, gpr_r3, gpr_r4, gpr_r5, gpr_r6, gpr_r7, gpr_r8, 895b9c1b51eSKate Stone gpr_r9, gpr_r10, gpr_r11, gpr_r12, gpr_sp, gpr_lr, gpr_pc, gpr_cpsr}; 896a63d08c9SGreg Clayton 897a63d08c9SGreg Clayton // Floating point registers 898b9c1b51eSKate Stone static uint32_t g_fpu_regnums[] = { 899b9c1b51eSKate Stone fpu_s0, fpu_s1, fpu_s2, fpu_s3, fpu_s4, fpu_s5, fpu_s6, 900b9c1b51eSKate Stone fpu_s7, fpu_s8, fpu_s9, fpu_s10, fpu_s11, fpu_s12, fpu_s13, 901b9c1b51eSKate Stone fpu_s14, fpu_s15, fpu_s16, fpu_s17, fpu_s18, fpu_s19, fpu_s20, 902b9c1b51eSKate Stone fpu_s21, fpu_s22, fpu_s23, fpu_s24, fpu_s25, fpu_s26, fpu_s27, 903b9c1b51eSKate Stone fpu_s28, fpu_s29, fpu_s30, fpu_s31, fpu_fpscr, 904a63d08c9SGreg Clayton }; 905a63d08c9SGreg Clayton 906a63d08c9SGreg Clayton // Exception registers 907a63d08c9SGreg Clayton 908b9c1b51eSKate Stone static uint32_t g_exc_regnums[] = { 909b9c1b51eSKate Stone exc_exception, exc_fsr, exc_far, 910a63d08c9SGreg Clayton }; 911a63d08c9SGreg Clayton 91228606954SSaleem Abdulrasool static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos); 913a63d08c9SGreg Clayton 914b9c1b51eSKate Stone RegisterContextDarwin_arm::RegisterContextDarwin_arm( 915b9c1b51eSKate Stone Thread &thread, uint32_t concrete_frame_idx) 916b9c1b51eSKate Stone : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() { 91763bd0db0SJason Molenda uint32_t i; 918b9c1b51eSKate Stone for (i = 0; i < kNumErrors; i++) { 91963bd0db0SJason Molenda gpr_errs[i] = -1; 92063bd0db0SJason Molenda fpu_errs[i] = -1; 92163bd0db0SJason Molenda exc_errs[i] = -1; 92263bd0db0SJason Molenda } 92363bd0db0SJason Molenda } 92463bd0db0SJason Molenda 925*fd2433e1SJonas Devlieghere RegisterContextDarwin_arm::~RegisterContextDarwin_arm() = default; 92663bd0db0SJason Molenda 927b9c1b51eSKate Stone void RegisterContextDarwin_arm::InvalidateAllRegisters() { 928a63d08c9SGreg Clayton InvalidateAllRegisterStates(); 929a63d08c9SGreg Clayton } 930a63d08c9SGreg Clayton 931b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterCount() { 932a63d08c9SGreg Clayton assert(k_num_register_infos == k_num_registers); 933a63d08c9SGreg Clayton return k_num_registers; 934a63d08c9SGreg Clayton } 935a63d08c9SGreg Clayton 936a63d08c9SGreg Clayton const RegisterInfo * 937b9c1b51eSKate Stone RegisterContextDarwin_arm::GetRegisterInfoAtIndex(size_t reg) { 938a63d08c9SGreg Clayton assert(k_num_register_infos == k_num_registers); 939a63d08c9SGreg Clayton if (reg < k_num_registers) 940a63d08c9SGreg Clayton return &g_register_infos[reg]; 941248a1305SKonrad Kleine return nullptr; 942a63d08c9SGreg Clayton } 943a63d08c9SGreg Clayton 944b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterInfosCount() { 945a63d08c9SGreg Clayton return k_num_register_infos; 946a63d08c9SGreg Clayton } 947a63d08c9SGreg Clayton 948b9c1b51eSKate Stone const RegisterInfo *RegisterContextDarwin_arm::GetRegisterInfos() { 949a63d08c9SGreg Clayton return g_register_infos; 950a63d08c9SGreg Clayton } 951a63d08c9SGreg Clayton 952a63d08c9SGreg Clayton // Number of registers in each register set 95328606954SSaleem Abdulrasool const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums); 95428606954SSaleem Abdulrasool const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums); 95528606954SSaleem Abdulrasool const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums); 956a63d08c9SGreg Clayton 95705097246SAdrian Prantl // Register set definitions. The first definitions at register set index of 95805097246SAdrian Prantl // zero is for all registers, followed by other registers sets. The register 95905097246SAdrian Prantl // information for the all register set need not be filled in. 960b9c1b51eSKate Stone static const RegisterSet g_reg_sets[] = { 961a63d08c9SGreg Clayton { 962b9c1b51eSKate Stone "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, 963b9c1b51eSKate Stone }, 964a63d08c9SGreg Clayton {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums}, 965b9c1b51eSKate Stone {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}}; 966a63d08c9SGreg Clayton 96728606954SSaleem Abdulrasool const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets); 968a63d08c9SGreg Clayton 969b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterSetCount() { 970a63d08c9SGreg Clayton return k_num_regsets; 971a63d08c9SGreg Clayton } 972a63d08c9SGreg Clayton 973b9c1b51eSKate Stone const RegisterSet *RegisterContextDarwin_arm::GetRegisterSet(size_t reg_set) { 974a63d08c9SGreg Clayton if (reg_set < k_num_regsets) 975a63d08c9SGreg Clayton return &g_reg_sets[reg_set]; 976248a1305SKonrad Kleine return nullptr; 977a63d08c9SGreg Clayton } 978a63d08c9SGreg Clayton 979aaa0ba31SBruce Mitchener // Register information definitions for 32 bit i386. 980b9c1b51eSKate Stone int RegisterContextDarwin_arm::GetSetForNativeRegNum(int reg) { 981a63d08c9SGreg Clayton if (reg < fpu_s0) 982a63d08c9SGreg Clayton return GPRRegSet; 983a63d08c9SGreg Clayton else if (reg < exc_exception) 984a63d08c9SGreg Clayton return FPURegSet; 985a63d08c9SGreg Clayton else if (reg < k_num_registers) 986a63d08c9SGreg Clayton return EXCRegSet; 987a63d08c9SGreg Clayton return -1; 988a63d08c9SGreg Clayton } 989a63d08c9SGreg Clayton 990b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadGPR(bool force) { 991a63d08c9SGreg Clayton int set = GPRRegSet; 992b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 993a63d08c9SGreg Clayton SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr)); 994a63d08c9SGreg Clayton } 995a63d08c9SGreg Clayton return GetError(GPRRegSet, Read); 996a63d08c9SGreg Clayton } 997a63d08c9SGreg Clayton 998b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadFPU(bool force) { 999a63d08c9SGreg Clayton int set = FPURegSet; 1000b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1001a63d08c9SGreg Clayton SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu)); 1002a63d08c9SGreg Clayton } 1003a63d08c9SGreg Clayton return GetError(FPURegSet, Read); 1004a63d08c9SGreg Clayton } 1005a63d08c9SGreg Clayton 1006b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadEXC(bool force) { 1007a63d08c9SGreg Clayton int set = EXCRegSet; 1008b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1009a63d08c9SGreg Clayton SetError(set, Read, DoReadEXC(GetThreadID(), set, exc)); 1010a63d08c9SGreg Clayton } 1011a63d08c9SGreg Clayton return GetError(EXCRegSet, Read); 1012a63d08c9SGreg Clayton } 1013a63d08c9SGreg Clayton 1014b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadDBG(bool force) { 1015a63d08c9SGreg Clayton int set = DBGRegSet; 1016b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1017a63d08c9SGreg Clayton SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg)); 1018a63d08c9SGreg Clayton } 1019a63d08c9SGreg Clayton return GetError(DBGRegSet, Read); 1020a63d08c9SGreg Clayton } 1021a63d08c9SGreg Clayton 1022b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteGPR() { 1023a63d08c9SGreg Clayton int set = GPRRegSet; 1024b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1025a63d08c9SGreg Clayton SetError(set, Write, -1); 1026a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1027a63d08c9SGreg Clayton } 1028a63d08c9SGreg Clayton SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr)); 1029a63d08c9SGreg Clayton SetError(set, Read, -1); 1030a63d08c9SGreg Clayton return GetError(GPRRegSet, Write); 1031a63d08c9SGreg Clayton } 1032a63d08c9SGreg Clayton 1033b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteFPU() { 1034a63d08c9SGreg Clayton int set = FPURegSet; 1035b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1036a63d08c9SGreg Clayton SetError(set, Write, -1); 1037a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1038a63d08c9SGreg Clayton } 1039a63d08c9SGreg Clayton SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu)); 1040a63d08c9SGreg Clayton SetError(set, Read, -1); 1041a63d08c9SGreg Clayton return GetError(FPURegSet, Write); 1042a63d08c9SGreg Clayton } 1043a63d08c9SGreg Clayton 1044b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteEXC() { 1045a63d08c9SGreg Clayton int set = EXCRegSet; 1046b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1047a63d08c9SGreg Clayton SetError(set, Write, -1); 1048a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1049a63d08c9SGreg Clayton } 1050a63d08c9SGreg Clayton SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc)); 1051a63d08c9SGreg Clayton SetError(set, Read, -1); 1052a63d08c9SGreg Clayton return GetError(EXCRegSet, Write); 1053a63d08c9SGreg Clayton } 1054a63d08c9SGreg Clayton 1055b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteDBG() { 1056a63d08c9SGreg Clayton int set = DBGRegSet; 1057b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1058a63d08c9SGreg Clayton SetError(set, Write, -1); 1059a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1060a63d08c9SGreg Clayton } 1061a63d08c9SGreg Clayton SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg)); 1062a63d08c9SGreg Clayton SetError(set, Read, -1); 1063a63d08c9SGreg Clayton return GetError(DBGRegSet, Write); 1064a63d08c9SGreg Clayton } 1065a63d08c9SGreg Clayton 1066b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadRegisterSet(uint32_t set, bool force) { 1067b9c1b51eSKate Stone switch (set) { 1068b9c1b51eSKate Stone case GPRRegSet: 1069b9c1b51eSKate Stone return ReadGPR(force); 1070b9c1b51eSKate Stone case GPRAltRegSet: 1071b9c1b51eSKate Stone return ReadGPR(force); 1072b9c1b51eSKate Stone case FPURegSet: 1073b9c1b51eSKate Stone return ReadFPU(force); 1074b9c1b51eSKate Stone case EXCRegSet: 1075b9c1b51eSKate Stone return ReadEXC(force); 1076b9c1b51eSKate Stone case DBGRegSet: 1077b9c1b51eSKate Stone return ReadDBG(force); 1078b9c1b51eSKate Stone default: 1079b9c1b51eSKate Stone break; 1080a63d08c9SGreg Clayton } 1081a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1082a63d08c9SGreg Clayton } 1083a63d08c9SGreg Clayton 1084b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteRegisterSet(uint32_t set) { 1085a63d08c9SGreg Clayton // Make sure we have a valid context to set. 1086b9c1b51eSKate Stone if (RegisterSetIsCached(set)) { 1087b9c1b51eSKate Stone switch (set) { 1088b9c1b51eSKate Stone case GPRRegSet: 1089b9c1b51eSKate Stone return WriteGPR(); 1090b9c1b51eSKate Stone case GPRAltRegSet: 1091b9c1b51eSKate Stone return WriteGPR(); 1092b9c1b51eSKate Stone case FPURegSet: 1093b9c1b51eSKate Stone return WriteFPU(); 1094b9c1b51eSKate Stone case EXCRegSet: 1095b9c1b51eSKate Stone return WriteEXC(); 1096b9c1b51eSKate Stone case DBGRegSet: 1097b9c1b51eSKate Stone return WriteDBG(); 1098b9c1b51eSKate Stone default: 1099b9c1b51eSKate Stone break; 1100a63d08c9SGreg Clayton } 1101a63d08c9SGreg Clayton } 1102a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1103a63d08c9SGreg Clayton } 1104a63d08c9SGreg Clayton 1105b9c1b51eSKate Stone void RegisterContextDarwin_arm::LogDBGRegisters(Log *log, const DBG &dbg) { 1106b9c1b51eSKate Stone if (log) { 1107a63d08c9SGreg Clayton for (uint32_t i = 0; i < 16; i++) 110863e5fb76SJonas Devlieghere LLDB_LOGF(log, 110963e5fb76SJonas Devlieghere "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { " 1110b9c1b51eSKate Stone "0x%8.8x, 0x%8.8x }", 1111b9c1b51eSKate Stone i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]); 1112a63d08c9SGreg Clayton } 1113a63d08c9SGreg Clayton } 1114a63d08c9SGreg Clayton 1115b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ReadRegister(const RegisterInfo *reg_info, 1116b9c1b51eSKate Stone RegisterValue &value) { 1117a63d08c9SGreg Clayton const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 1118a63d08c9SGreg Clayton int set = RegisterContextDarwin_arm::GetSetForNativeRegNum(reg); 1119a63d08c9SGreg Clayton 1120a63d08c9SGreg Clayton if (set == -1) 1121a63d08c9SGreg Clayton return false; 1122a63d08c9SGreg Clayton 1123a63d08c9SGreg Clayton if (ReadRegisterSet(set, false) != KERN_SUCCESS) 1124a63d08c9SGreg Clayton return false; 1125a63d08c9SGreg Clayton 1126b9c1b51eSKate Stone switch (reg) { 1127a63d08c9SGreg Clayton case gpr_r0: 1128a63d08c9SGreg Clayton case gpr_r1: 1129a63d08c9SGreg Clayton case gpr_r2: 1130a63d08c9SGreg Clayton case gpr_r3: 1131a63d08c9SGreg Clayton case gpr_r4: 1132a63d08c9SGreg Clayton case gpr_r5: 1133a63d08c9SGreg Clayton case gpr_r6: 1134a63d08c9SGreg Clayton case gpr_r7: 1135a63d08c9SGreg Clayton case gpr_r8: 1136a63d08c9SGreg Clayton case gpr_r9: 1137a63d08c9SGreg Clayton case gpr_r10: 1138a63d08c9SGreg Clayton case gpr_r11: 1139a63d08c9SGreg Clayton case gpr_r12: 1140a63d08c9SGreg Clayton case gpr_sp: 1141a63d08c9SGreg Clayton case gpr_lr: 1142a63d08c9SGreg Clayton case gpr_pc: 1143a63d08c9SGreg Clayton value.SetUInt32(gpr.r[reg - gpr_r0]); 1144a63d08c9SGreg Clayton break; 1145e194d890SJonas Devlieghere case gpr_cpsr: 1146e194d890SJonas Devlieghere value.SetUInt32(gpr.cpsr); 1147e194d890SJonas Devlieghere break; 1148a63d08c9SGreg Clayton case fpu_s0: 1149a63d08c9SGreg Clayton case fpu_s1: 1150a63d08c9SGreg Clayton case fpu_s2: 1151a63d08c9SGreg Clayton case fpu_s3: 1152a63d08c9SGreg Clayton case fpu_s4: 1153a63d08c9SGreg Clayton case fpu_s5: 1154a63d08c9SGreg Clayton case fpu_s6: 1155a63d08c9SGreg Clayton case fpu_s7: 1156a63d08c9SGreg Clayton case fpu_s8: 1157a63d08c9SGreg Clayton case fpu_s9: 1158a63d08c9SGreg Clayton case fpu_s10: 1159a63d08c9SGreg Clayton case fpu_s11: 1160a63d08c9SGreg Clayton case fpu_s12: 1161a63d08c9SGreg Clayton case fpu_s13: 1162a63d08c9SGreg Clayton case fpu_s14: 1163a63d08c9SGreg Clayton case fpu_s15: 1164a63d08c9SGreg Clayton case fpu_s16: 1165a63d08c9SGreg Clayton case fpu_s17: 1166a63d08c9SGreg Clayton case fpu_s18: 1167a63d08c9SGreg Clayton case fpu_s19: 1168a63d08c9SGreg Clayton case fpu_s20: 1169a63d08c9SGreg Clayton case fpu_s21: 1170a63d08c9SGreg Clayton case fpu_s22: 1171a63d08c9SGreg Clayton case fpu_s23: 1172a63d08c9SGreg Clayton case fpu_s24: 1173a63d08c9SGreg Clayton case fpu_s25: 1174a63d08c9SGreg Clayton case fpu_s26: 1175a63d08c9SGreg Clayton case fpu_s27: 1176a63d08c9SGreg Clayton case fpu_s28: 1177a63d08c9SGreg Clayton case fpu_s29: 1178a63d08c9SGreg Clayton case fpu_s30: 1179a63d08c9SGreg Clayton case fpu_s31: 1180a63d08c9SGreg Clayton value.SetUInt32(fpu.floats.s[reg], RegisterValue::eTypeFloat); 1181a63d08c9SGreg Clayton break; 1182a63d08c9SGreg Clayton 1183a63d08c9SGreg Clayton case fpu_fpscr: 1184a63d08c9SGreg Clayton value.SetUInt32(fpu.fpscr); 1185a63d08c9SGreg Clayton break; 1186a63d08c9SGreg Clayton 1187a63d08c9SGreg Clayton case exc_exception: 1188a63d08c9SGreg Clayton value.SetUInt32(exc.exception); 1189a63d08c9SGreg Clayton break; 1190a63d08c9SGreg Clayton case exc_fsr: 1191a63d08c9SGreg Clayton value.SetUInt32(exc.fsr); 1192a63d08c9SGreg Clayton break; 1193a63d08c9SGreg Clayton case exc_far: 1194a63d08c9SGreg Clayton value.SetUInt32(exc.far); 1195a63d08c9SGreg Clayton break; 1196a63d08c9SGreg Clayton 1197a63d08c9SGreg Clayton default: 1198a63d08c9SGreg Clayton value.SetValueToInvalid(); 1199a63d08c9SGreg Clayton return false; 1200a63d08c9SGreg Clayton } 1201a63d08c9SGreg Clayton return true; 1202a63d08c9SGreg Clayton } 1203a63d08c9SGreg Clayton 1204b9c1b51eSKate Stone bool RegisterContextDarwin_arm::WriteRegister(const RegisterInfo *reg_info, 1205b9c1b51eSKate Stone const RegisterValue &value) { 1206a63d08c9SGreg Clayton const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 1207a63d08c9SGreg Clayton int set = GetSetForNativeRegNum(reg); 1208a63d08c9SGreg Clayton 1209a63d08c9SGreg Clayton if (set == -1) 1210a63d08c9SGreg Clayton return false; 1211a63d08c9SGreg Clayton 1212a63d08c9SGreg Clayton if (ReadRegisterSet(set, false) != KERN_SUCCESS) 1213a63d08c9SGreg Clayton return false; 1214a63d08c9SGreg Clayton 1215b9c1b51eSKate Stone switch (reg) { 1216a63d08c9SGreg Clayton case gpr_r0: 1217a63d08c9SGreg Clayton case gpr_r1: 1218a63d08c9SGreg Clayton case gpr_r2: 1219a63d08c9SGreg Clayton case gpr_r3: 1220a63d08c9SGreg Clayton case gpr_r4: 1221a63d08c9SGreg Clayton case gpr_r5: 1222a63d08c9SGreg Clayton case gpr_r6: 1223a63d08c9SGreg Clayton case gpr_r7: 1224a63d08c9SGreg Clayton case gpr_r8: 1225a63d08c9SGreg Clayton case gpr_r9: 1226a63d08c9SGreg Clayton case gpr_r10: 1227a63d08c9SGreg Clayton case gpr_r11: 1228a63d08c9SGreg Clayton case gpr_r12: 1229a63d08c9SGreg Clayton case gpr_sp: 1230a63d08c9SGreg Clayton case gpr_lr: 1231a63d08c9SGreg Clayton case gpr_pc: 1232a63d08c9SGreg Clayton case gpr_cpsr: 1233a63d08c9SGreg Clayton gpr.r[reg - gpr_r0] = value.GetAsUInt32(); 1234a63d08c9SGreg Clayton break; 1235a63d08c9SGreg Clayton 1236a63d08c9SGreg Clayton case fpu_s0: 1237a63d08c9SGreg Clayton case fpu_s1: 1238a63d08c9SGreg Clayton case fpu_s2: 1239a63d08c9SGreg Clayton case fpu_s3: 1240a63d08c9SGreg Clayton case fpu_s4: 1241a63d08c9SGreg Clayton case fpu_s5: 1242a63d08c9SGreg Clayton case fpu_s6: 1243a63d08c9SGreg Clayton case fpu_s7: 1244a63d08c9SGreg Clayton case fpu_s8: 1245a63d08c9SGreg Clayton case fpu_s9: 1246a63d08c9SGreg Clayton case fpu_s10: 1247a63d08c9SGreg Clayton case fpu_s11: 1248a63d08c9SGreg Clayton case fpu_s12: 1249a63d08c9SGreg Clayton case fpu_s13: 1250a63d08c9SGreg Clayton case fpu_s14: 1251a63d08c9SGreg Clayton case fpu_s15: 1252a63d08c9SGreg Clayton case fpu_s16: 1253a63d08c9SGreg Clayton case fpu_s17: 1254a63d08c9SGreg Clayton case fpu_s18: 1255a63d08c9SGreg Clayton case fpu_s19: 1256a63d08c9SGreg Clayton case fpu_s20: 1257a63d08c9SGreg Clayton case fpu_s21: 1258a63d08c9SGreg Clayton case fpu_s22: 1259a63d08c9SGreg Clayton case fpu_s23: 1260a63d08c9SGreg Clayton case fpu_s24: 1261a63d08c9SGreg Clayton case fpu_s25: 1262a63d08c9SGreg Clayton case fpu_s26: 1263a63d08c9SGreg Clayton case fpu_s27: 1264a63d08c9SGreg Clayton case fpu_s28: 1265a63d08c9SGreg Clayton case fpu_s29: 1266a63d08c9SGreg Clayton case fpu_s30: 1267a63d08c9SGreg Clayton case fpu_s31: 1268a63d08c9SGreg Clayton fpu.floats.s[reg] = value.GetAsUInt32(); 1269a63d08c9SGreg Clayton break; 1270a63d08c9SGreg Clayton 1271a63d08c9SGreg Clayton case fpu_fpscr: 1272a63d08c9SGreg Clayton fpu.fpscr = value.GetAsUInt32(); 1273a63d08c9SGreg Clayton break; 1274a63d08c9SGreg Clayton 1275a63d08c9SGreg Clayton case exc_exception: 1276a63d08c9SGreg Clayton exc.exception = value.GetAsUInt32(); 1277a63d08c9SGreg Clayton break; 1278a63d08c9SGreg Clayton case exc_fsr: 1279a63d08c9SGreg Clayton exc.fsr = value.GetAsUInt32(); 1280a63d08c9SGreg Clayton break; 1281a63d08c9SGreg Clayton case exc_far: 1282a63d08c9SGreg Clayton exc.far = value.GetAsUInt32(); 1283a63d08c9SGreg Clayton break; 1284a63d08c9SGreg Clayton 1285a63d08c9SGreg Clayton default: 1286a63d08c9SGreg Clayton return false; 1287a63d08c9SGreg Clayton } 1288a63d08c9SGreg Clayton return WriteRegisterSet(set) == KERN_SUCCESS; 1289a63d08c9SGreg Clayton } 1290a63d08c9SGreg Clayton 1291b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ReadAllRegisterValues( 1292b9c1b51eSKate Stone lldb::DataBufferSP &data_sp) { 1293796ac80bSJonas Devlieghere data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0); 1294b9c1b51eSKate Stone if (data_sp && ReadGPR(false) == KERN_SUCCESS && 1295b9c1b51eSKate Stone ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) { 1296a63d08c9SGreg Clayton uint8_t *dst = data_sp->GetBytes(); 1297a63d08c9SGreg Clayton ::memcpy(dst, &gpr, sizeof(gpr)); 1298a63d08c9SGreg Clayton dst += sizeof(gpr); 1299a63d08c9SGreg Clayton 1300a63d08c9SGreg Clayton ::memcpy(dst, &fpu, sizeof(fpu)); 1301a63d08c9SGreg Clayton dst += sizeof(gpr); 1302a63d08c9SGreg Clayton 1303a63d08c9SGreg Clayton ::memcpy(dst, &exc, sizeof(exc)); 1304a63d08c9SGreg Clayton return true; 1305a63d08c9SGreg Clayton } 1306a63d08c9SGreg Clayton return false; 1307a63d08c9SGreg Clayton } 1308a63d08c9SGreg Clayton 1309b9c1b51eSKate Stone bool RegisterContextDarwin_arm::WriteAllRegisterValues( 1310b9c1b51eSKate Stone const lldb::DataBufferSP &data_sp) { 1311b9c1b51eSKate Stone if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) { 1312a63d08c9SGreg Clayton const uint8_t *src = data_sp->GetBytes(); 1313a63d08c9SGreg Clayton ::memcpy(&gpr, src, sizeof(gpr)); 1314a63d08c9SGreg Clayton src += sizeof(gpr); 1315a63d08c9SGreg Clayton 1316a63d08c9SGreg Clayton ::memcpy(&fpu, src, sizeof(fpu)); 1317a63d08c9SGreg Clayton src += sizeof(gpr); 1318a63d08c9SGreg Clayton 1319a63d08c9SGreg Clayton ::memcpy(&exc, src, sizeof(exc)); 1320a63d08c9SGreg Clayton uint32_t success_count = 0; 1321a63d08c9SGreg Clayton if (WriteGPR() == KERN_SUCCESS) 1322a63d08c9SGreg Clayton ++success_count; 1323a63d08c9SGreg Clayton if (WriteFPU() == KERN_SUCCESS) 1324a63d08c9SGreg Clayton ++success_count; 1325a63d08c9SGreg Clayton if (WriteEXC() == KERN_SUCCESS) 1326a63d08c9SGreg Clayton ++success_count; 1327a63d08c9SGreg Clayton return success_count == 3; 1328a63d08c9SGreg Clayton } 1329a63d08c9SGreg Clayton return false; 1330a63d08c9SGreg Clayton } 1331a63d08c9SGreg Clayton 1332b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::ConvertRegisterKindToRegisterNumber( 1333b9c1b51eSKate Stone lldb::RegisterKind kind, uint32_t reg) { 1334b9c1b51eSKate Stone if (kind == eRegisterKindGeneric) { 1335b9c1b51eSKate Stone switch (reg) { 1336b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_PC: 1337b9c1b51eSKate Stone return gpr_pc; 1338b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_SP: 1339b9c1b51eSKate Stone return gpr_sp; 1340b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_FP: 1341b9c1b51eSKate Stone return gpr_r7; 1342b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_RA: 1343b9c1b51eSKate Stone return gpr_lr; 1344b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_FLAGS: 1345b9c1b51eSKate Stone return gpr_cpsr; 1346a63d08c9SGreg Clayton default: 1347a63d08c9SGreg Clayton break; 1348a63d08c9SGreg Clayton } 1349b9c1b51eSKate Stone } else if (kind == eRegisterKindDWARF) { 1350b9c1b51eSKate Stone switch (reg) { 1351b9c1b51eSKate Stone case dwarf_r0: 1352b9c1b51eSKate Stone return gpr_r0; 1353b9c1b51eSKate Stone case dwarf_r1: 1354b9c1b51eSKate Stone return gpr_r1; 1355b9c1b51eSKate Stone case dwarf_r2: 1356b9c1b51eSKate Stone return gpr_r2; 1357b9c1b51eSKate Stone case dwarf_r3: 1358b9c1b51eSKate Stone return gpr_r3; 1359b9c1b51eSKate Stone case dwarf_r4: 1360b9c1b51eSKate Stone return gpr_r4; 1361b9c1b51eSKate Stone case dwarf_r5: 1362b9c1b51eSKate Stone return gpr_r5; 1363b9c1b51eSKate Stone case dwarf_r6: 1364b9c1b51eSKate Stone return gpr_r6; 1365b9c1b51eSKate Stone case dwarf_r7: 1366b9c1b51eSKate Stone return gpr_r7; 1367b9c1b51eSKate Stone case dwarf_r8: 1368b9c1b51eSKate Stone return gpr_r8; 1369b9c1b51eSKate Stone case dwarf_r9: 1370b9c1b51eSKate Stone return gpr_r9; 1371b9c1b51eSKate Stone case dwarf_r10: 1372b9c1b51eSKate Stone return gpr_r10; 1373b9c1b51eSKate Stone case dwarf_r11: 1374b9c1b51eSKate Stone return gpr_r11; 1375b9c1b51eSKate Stone case dwarf_r12: 1376b9c1b51eSKate Stone return gpr_r12; 1377b9c1b51eSKate Stone case dwarf_sp: 1378b9c1b51eSKate Stone return gpr_sp; 1379b9c1b51eSKate Stone case dwarf_lr: 1380b9c1b51eSKate Stone return gpr_lr; 1381b9c1b51eSKate Stone case dwarf_pc: 1382b9c1b51eSKate Stone return gpr_pc; 1383b9c1b51eSKate Stone case dwarf_spsr: 1384b9c1b51eSKate Stone return gpr_cpsr; 1385a63d08c9SGreg Clayton 1386b9c1b51eSKate Stone case dwarf_s0: 1387b9c1b51eSKate Stone return fpu_s0; 1388b9c1b51eSKate Stone case dwarf_s1: 1389b9c1b51eSKate Stone return fpu_s1; 1390b9c1b51eSKate Stone case dwarf_s2: 1391b9c1b51eSKate Stone return fpu_s2; 1392b9c1b51eSKate Stone case dwarf_s3: 1393b9c1b51eSKate Stone return fpu_s3; 1394b9c1b51eSKate Stone case dwarf_s4: 1395b9c1b51eSKate Stone return fpu_s4; 1396b9c1b51eSKate Stone case dwarf_s5: 1397b9c1b51eSKate Stone return fpu_s5; 1398b9c1b51eSKate Stone case dwarf_s6: 1399b9c1b51eSKate Stone return fpu_s6; 1400b9c1b51eSKate Stone case dwarf_s7: 1401b9c1b51eSKate Stone return fpu_s7; 1402b9c1b51eSKate Stone case dwarf_s8: 1403b9c1b51eSKate Stone return fpu_s8; 1404b9c1b51eSKate Stone case dwarf_s9: 1405b9c1b51eSKate Stone return fpu_s9; 1406b9c1b51eSKate Stone case dwarf_s10: 1407b9c1b51eSKate Stone return fpu_s10; 1408b9c1b51eSKate Stone case dwarf_s11: 1409b9c1b51eSKate Stone return fpu_s11; 1410b9c1b51eSKate Stone case dwarf_s12: 1411b9c1b51eSKate Stone return fpu_s12; 1412b9c1b51eSKate Stone case dwarf_s13: 1413b9c1b51eSKate Stone return fpu_s13; 1414b9c1b51eSKate Stone case dwarf_s14: 1415b9c1b51eSKate Stone return fpu_s14; 1416b9c1b51eSKate Stone case dwarf_s15: 1417b9c1b51eSKate Stone return fpu_s15; 1418b9c1b51eSKate Stone case dwarf_s16: 1419b9c1b51eSKate Stone return fpu_s16; 1420b9c1b51eSKate Stone case dwarf_s17: 1421b9c1b51eSKate Stone return fpu_s17; 1422b9c1b51eSKate Stone case dwarf_s18: 1423b9c1b51eSKate Stone return fpu_s18; 1424b9c1b51eSKate Stone case dwarf_s19: 1425b9c1b51eSKate Stone return fpu_s19; 1426b9c1b51eSKate Stone case dwarf_s20: 1427b9c1b51eSKate Stone return fpu_s20; 1428b9c1b51eSKate Stone case dwarf_s21: 1429b9c1b51eSKate Stone return fpu_s21; 1430b9c1b51eSKate Stone case dwarf_s22: 1431b9c1b51eSKate Stone return fpu_s22; 1432b9c1b51eSKate Stone case dwarf_s23: 1433b9c1b51eSKate Stone return fpu_s23; 1434b9c1b51eSKate Stone case dwarf_s24: 1435b9c1b51eSKate Stone return fpu_s24; 1436b9c1b51eSKate Stone case dwarf_s25: 1437b9c1b51eSKate Stone return fpu_s25; 1438b9c1b51eSKate Stone case dwarf_s26: 1439b9c1b51eSKate Stone return fpu_s26; 1440b9c1b51eSKate Stone case dwarf_s27: 1441b9c1b51eSKate Stone return fpu_s27; 1442b9c1b51eSKate Stone case dwarf_s28: 1443b9c1b51eSKate Stone return fpu_s28; 1444b9c1b51eSKate Stone case dwarf_s29: 1445b9c1b51eSKate Stone return fpu_s29; 1446b9c1b51eSKate Stone case dwarf_s30: 1447b9c1b51eSKate Stone return fpu_s30; 1448b9c1b51eSKate Stone case dwarf_s31: 1449b9c1b51eSKate Stone return fpu_s31; 1450a63d08c9SGreg Clayton 1451a63d08c9SGreg Clayton default: 1452a63d08c9SGreg Clayton break; 1453a63d08c9SGreg Clayton } 1454b9c1b51eSKate Stone } else if (kind == eRegisterKindEHFrame) { 1455b9c1b51eSKate Stone switch (reg) { 1456b9c1b51eSKate Stone case ehframe_r0: 1457b9c1b51eSKate Stone return gpr_r0; 1458b9c1b51eSKate Stone case ehframe_r1: 1459b9c1b51eSKate Stone return gpr_r1; 1460b9c1b51eSKate Stone case ehframe_r2: 1461b9c1b51eSKate Stone return gpr_r2; 1462b9c1b51eSKate Stone case ehframe_r3: 1463b9c1b51eSKate Stone return gpr_r3; 1464b9c1b51eSKate Stone case ehframe_r4: 1465b9c1b51eSKate Stone return gpr_r4; 1466b9c1b51eSKate Stone case ehframe_r5: 1467b9c1b51eSKate Stone return gpr_r5; 1468b9c1b51eSKate Stone case ehframe_r6: 1469b9c1b51eSKate Stone return gpr_r6; 1470b9c1b51eSKate Stone case ehframe_r7: 1471b9c1b51eSKate Stone return gpr_r7; 1472b9c1b51eSKate Stone case ehframe_r8: 1473b9c1b51eSKate Stone return gpr_r8; 1474b9c1b51eSKate Stone case ehframe_r9: 1475b9c1b51eSKate Stone return gpr_r9; 1476b9c1b51eSKate Stone case ehframe_r10: 1477b9c1b51eSKate Stone return gpr_r10; 1478b9c1b51eSKate Stone case ehframe_r11: 1479b9c1b51eSKate Stone return gpr_r11; 1480b9c1b51eSKate Stone case ehframe_r12: 1481b9c1b51eSKate Stone return gpr_r12; 1482b9c1b51eSKate Stone case ehframe_sp: 1483b9c1b51eSKate Stone return gpr_sp; 1484b9c1b51eSKate Stone case ehframe_lr: 1485b9c1b51eSKate Stone return gpr_lr; 1486b9c1b51eSKate Stone case ehframe_pc: 1487b9c1b51eSKate Stone return gpr_pc; 1488b9c1b51eSKate Stone case ehframe_cpsr: 1489b9c1b51eSKate Stone return gpr_cpsr; 1490a63d08c9SGreg Clayton } 1491b9c1b51eSKate Stone } else if (kind == eRegisterKindLLDB) { 1492a63d08c9SGreg Clayton return reg; 1493a63d08c9SGreg Clayton } 1494a63d08c9SGreg Clayton return LLDB_INVALID_REGNUM; 1495a63d08c9SGreg Clayton } 1496a63d08c9SGreg Clayton 1497b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::NumSupportedHardwareBreakpoints() { 149890da3ce3SPavel Labath #if defined(__APPLE__) && defined(__arm__) 1499a63d08c9SGreg Clayton // Set the init value to something that will let us know that we need to 1500a63d08c9SGreg Clayton // autodetect how many breakpoints are supported dynamically... 1501a63d08c9SGreg Clayton static uint32_t g_num_supported_hw_breakpoints = UINT32_MAX; 1502b9c1b51eSKate Stone if (g_num_supported_hw_breakpoints == UINT32_MAX) { 1503a63d08c9SGreg Clayton // Set this to zero in case we can't tell if there are any HW breakpoints 1504a63d08c9SGreg Clayton g_num_supported_hw_breakpoints = 0; 1505a63d08c9SGreg Clayton 1506a63d08c9SGreg Clayton uint32_t register_DBGDIDR; 1507a63d08c9SGreg Clayton 1508a63d08c9SGreg Clayton asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 1509dce502edSGreg Clayton g_num_supported_hw_breakpoints = Bits32(register_DBGDIDR, 27, 24); 1510a63d08c9SGreg Clayton // Zero is reserved for the BRP count, so don't increment it if it is zero 1511a63d08c9SGreg Clayton if (g_num_supported_hw_breakpoints > 0) 1512a63d08c9SGreg Clayton g_num_supported_hw_breakpoints++; 1513a63d08c9SGreg Clayton } 1514a63d08c9SGreg Clayton return g_num_supported_hw_breakpoints; 1515a63d08c9SGreg Clayton #else 1516a63d08c9SGreg Clayton // TODO: figure out remote case here! 1517a63d08c9SGreg Clayton return 6; 1518a63d08c9SGreg Clayton #endif 1519a63d08c9SGreg Clayton } 1520a63d08c9SGreg Clayton 1521b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::SetHardwareBreakpoint(lldb::addr_t addr, 1522b9c1b51eSKate Stone size_t size) { 1523a63d08c9SGreg Clayton // Make sure our address isn't bogus 1524a63d08c9SGreg Clayton if (addr & 1) 1525a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1526a63d08c9SGreg Clayton 1527a63d08c9SGreg Clayton int kret = ReadDBG(false); 1528a63d08c9SGreg Clayton 1529b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1530a63d08c9SGreg Clayton const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints(); 1531a63d08c9SGreg Clayton uint32_t i; 1532b9c1b51eSKate Stone for (i = 0; i < num_hw_breakpoints; ++i) { 1533a63d08c9SGreg Clayton if ((dbg.bcr[i] & BCR_ENABLE) == 0) 1534a63d08c9SGreg Clayton break; // We found an available hw breakpoint slot (in i) 1535a63d08c9SGreg Clayton } 1536a63d08c9SGreg Clayton 1537a63d08c9SGreg Clayton // See if we found an available hw breakpoint slot above 1538b9c1b51eSKate Stone if (i < num_hw_breakpoints) { 1539a63d08c9SGreg Clayton // Make sure bits 1:0 are clear in our address 1540a63d08c9SGreg Clayton dbg.bvr[i] = addr & ~((lldb::addr_t)3); 1541a63d08c9SGreg Clayton 1542b9c1b51eSKate Stone if (size == 2 || addr & 2) { 1543a63d08c9SGreg Clayton uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1; 1544a63d08c9SGreg Clayton 1545a63d08c9SGreg Clayton // We have a thumb breakpoint 1546a63d08c9SGreg Clayton // We have an ARM breakpoint 1547a63d08c9SGreg Clayton dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch 1548b9c1b51eSKate Stone byte_addr_select | // Set the correct byte address select 1549b9c1b51eSKate Stone // so we only trigger on the correct 1550b9c1b51eSKate Stone // opcode 1551a63d08c9SGreg Clayton S_USER | // Which modes should this breakpoint stop in? 1552a63d08c9SGreg Clayton BCR_ENABLE; // Enable this hardware breakpoint 1553b9c1b51eSKate Stone // if (log) log->Printf 1554b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 1555b9c1b51eSKate Stone // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 1556b9c1b51eSKate Stone // 0x%8.8x (Thumb)", 155789f138aeSGreg Clayton // addr, 155889f138aeSGreg Clayton // size, 155989f138aeSGreg Clayton // i, 156089f138aeSGreg Clayton // i, 156189f138aeSGreg Clayton // dbg.bvr[i], 156289f138aeSGreg Clayton // dbg.bcr[i]); 1563b9c1b51eSKate Stone } else if (size == 4) { 1564a63d08c9SGreg Clayton // We have an ARM breakpoint 1565b9c1b51eSKate Stone dbg.bcr[i] = 1566b9c1b51eSKate Stone BCR_M_IMVA_MATCH | // Stop on address mismatch 1567a63d08c9SGreg Clayton BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA 1568a63d08c9SGreg Clayton S_USER | // Which modes should this breakpoint stop in? 1569a63d08c9SGreg Clayton BCR_ENABLE; // Enable this hardware breakpoint 1570b9c1b51eSKate Stone // if (log) log->Printf 1571b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 1572b9c1b51eSKate Stone // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 1573b9c1b51eSKate Stone // 0x%8.8x (ARM)", 157489f138aeSGreg Clayton // addr, 157589f138aeSGreg Clayton // size, 157689f138aeSGreg Clayton // i, 157789f138aeSGreg Clayton // i, 157889f138aeSGreg Clayton // dbg.bvr[i], 157989f138aeSGreg Clayton // dbg.bcr[i]); 1580a63d08c9SGreg Clayton } 1581a63d08c9SGreg Clayton 1582a63d08c9SGreg Clayton kret = WriteDBG(); 1583b9c1b51eSKate Stone // if (log) log->Printf 1584b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint() 1585b9c1b51eSKate Stone // WriteDBG() => 0x%8.8x.", kret); 1586a63d08c9SGreg Clayton 1587a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1588a63d08c9SGreg Clayton return i; 1589a63d08c9SGreg Clayton } 159089f138aeSGreg Clayton // else 159189f138aeSGreg Clayton // { 1592b9c1b51eSKate Stone // if (log) log->Printf 1593b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(addr = 1594b9c1b51eSKate Stone // %8.8p, size = %u) => all hardware breakpoint resources are 1595b9c1b51eSKate Stone // being used.", addr, size); 159689f138aeSGreg Clayton // } 1597a63d08c9SGreg Clayton } 1598a63d08c9SGreg Clayton 1599a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1600a63d08c9SGreg Clayton } 1601a63d08c9SGreg Clayton 1602b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ClearHardwareBreakpoint(uint32_t hw_index) { 1603a63d08c9SGreg Clayton int kret = ReadDBG(false); 1604a63d08c9SGreg Clayton 1605a63d08c9SGreg Clayton const uint32_t num_hw_points = NumSupportedHardwareBreakpoints(); 1606b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1607b9c1b51eSKate Stone if (hw_index < num_hw_points) { 1608a63d08c9SGreg Clayton dbg.bcr[hw_index] = 0; 1609b9c1b51eSKate Stone // if (log) log->Printf 1610b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::SetHardwareBreakpoint( %u ) - 1611b9c1b51eSKate Stone // BVR%u = 0x%8.8x BCR%u = 0x%8.8x", 161289f138aeSGreg Clayton // hw_index, 161389f138aeSGreg Clayton // hw_index, 161489f138aeSGreg Clayton // dbg.bvr[hw_index], 161589f138aeSGreg Clayton // hw_index, 161689f138aeSGreg Clayton // dbg.bcr[hw_index]); 1617a63d08c9SGreg Clayton 1618a63d08c9SGreg Clayton kret = WriteDBG(); 1619a63d08c9SGreg Clayton 1620a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1621a63d08c9SGreg Clayton return true; 1622a63d08c9SGreg Clayton } 1623a63d08c9SGreg Clayton } 1624a63d08c9SGreg Clayton return false; 1625a63d08c9SGreg Clayton } 1626a63d08c9SGreg Clayton 1627b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::NumSupportedHardwareWatchpoints() { 162890da3ce3SPavel Labath #if defined(__APPLE__) && defined(__arm__) 1629a63d08c9SGreg Clayton // Set the init value to something that will let us know that we need to 1630a63d08c9SGreg Clayton // autodetect how many watchpoints are supported dynamically... 1631a63d08c9SGreg Clayton static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX; 1632b9c1b51eSKate Stone if (g_num_supported_hw_watchpoints == UINT32_MAX) { 1633a63d08c9SGreg Clayton // Set this to zero in case we can't tell if there are any HW breakpoints 1634a63d08c9SGreg Clayton g_num_supported_hw_watchpoints = 0; 1635a63d08c9SGreg Clayton 1636a63d08c9SGreg Clayton uint32_t register_DBGDIDR; 1637a63d08c9SGreg Clayton asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 1638dce502edSGreg Clayton g_num_supported_hw_watchpoints = Bits32(register_DBGDIDR, 31, 28) + 1; 1639a63d08c9SGreg Clayton } 1640a63d08c9SGreg Clayton return g_num_supported_hw_watchpoints; 1641a63d08c9SGreg Clayton #else 1642a63d08c9SGreg Clayton // TODO: figure out remote case here! 1643a63d08c9SGreg Clayton return 2; 1644a63d08c9SGreg Clayton #endif 1645a63d08c9SGreg Clayton } 1646a63d08c9SGreg Clayton 1647b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::SetHardwareWatchpoint(lldb::addr_t addr, 1648b9c1b51eSKate Stone size_t size, 1649b9c1b51eSKate Stone bool read, 1650b9c1b51eSKate Stone bool write) { 1651a63d08c9SGreg Clayton const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 1652a63d08c9SGreg Clayton 1653a63d08c9SGreg Clayton // Can't watch zero bytes 1654a63d08c9SGreg Clayton if (size == 0) 1655a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1656a63d08c9SGreg Clayton 1657a63d08c9SGreg Clayton // We must watch for either read or write 1658a6682a41SJonas Devlieghere if (!read && !write) 1659a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1660a63d08c9SGreg Clayton 1661a63d08c9SGreg Clayton // Can't watch more than 4 bytes per WVR/WCR pair 1662a63d08c9SGreg Clayton if (size > 4) 1663a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1664a63d08c9SGreg Clayton 1665a63d08c9SGreg Clayton // We can only watch up to four bytes that follow a 4 byte aligned address 1666a63d08c9SGreg Clayton // per watchpoint register pair. Since we have at most so we can only watch 1667a63d08c9SGreg Clayton // until the next 4 byte boundary and we need to make sure we can properly 1668a63d08c9SGreg Clayton // encode this. 1669a63d08c9SGreg Clayton uint32_t addr_word_offset = addr % 4; 1670b9c1b51eSKate Stone // if (log) log->Printf 1671b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - 1672b9c1b51eSKate Stone // addr_word_offset = 0x%8.8x", addr_word_offset); 1673a63d08c9SGreg Clayton 1674a63d08c9SGreg Clayton uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset; 1675b9c1b51eSKate Stone // if (log) log->Printf 1676b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - byte_mask = 1677b9c1b51eSKate Stone // 0x%8.8x", byte_mask); 1678a63d08c9SGreg Clayton if (byte_mask > 0xfu) 1679a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1680a63d08c9SGreg Clayton 1681a63d08c9SGreg Clayton // Read the debug state 1682a63d08c9SGreg Clayton int kret = ReadDBG(false); 1683a63d08c9SGreg Clayton 1684b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1685a63d08c9SGreg Clayton // Check to make sure we have the needed hardware support 1686a63d08c9SGreg Clayton uint32_t i = 0; 1687a63d08c9SGreg Clayton 1688b9c1b51eSKate Stone for (i = 0; i < num_hw_watchpoints; ++i) { 1689a63d08c9SGreg Clayton if ((dbg.wcr[i] & WCR_ENABLE) == 0) 1690a63d08c9SGreg Clayton break; // We found an available hw breakpoint slot (in i) 1691a63d08c9SGreg Clayton } 1692a63d08c9SGreg Clayton 1693a63d08c9SGreg Clayton // See if we found an available hw breakpoint slot above 1694b9c1b51eSKate Stone if (i < num_hw_watchpoints) { 1695a63d08c9SGreg Clayton // Make the byte_mask into a valid Byte Address Select mask 1696a63d08c9SGreg Clayton uint32_t byte_address_select = byte_mask << 5; 1697a63d08c9SGreg Clayton // Make sure bits 1:0 are clear in our address 1698a63d08c9SGreg Clayton dbg.wvr[i] = addr & ~((lldb::addr_t)3); 1699b9c1b51eSKate Stone dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA 1700b9c1b51eSKate Stone // that we will watch 1701a63d08c9SGreg Clayton S_USER | // Stop only in user mode 1702a63d08c9SGreg Clayton (read ? WCR_LOAD : 0) | // Stop on read access? 1703a63d08c9SGreg Clayton (write ? WCR_STORE : 0) | // Stop on write access? 1704a63d08c9SGreg Clayton WCR_ENABLE; // Enable this watchpoint; 1705a63d08c9SGreg Clayton 1706a63d08c9SGreg Clayton kret = WriteDBG(); 1707b9c1b51eSKate Stone // if (log) log->Printf 1708b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() 1709b9c1b51eSKate Stone // WriteDBG() => 0x%8.8x.", kret); 1710a63d08c9SGreg Clayton 1711a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1712a63d08c9SGreg Clayton return i; 1713b9c1b51eSKate Stone } else { 1714b9c1b51eSKate Stone // if (log) log->Printf 1715b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(): All 1716b9c1b51eSKate Stone // hardware resources (%u) are in use.", num_hw_watchpoints); 1717a63d08c9SGreg Clayton } 1718a63d08c9SGreg Clayton } 1719a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1720a63d08c9SGreg Clayton } 1721a63d08c9SGreg Clayton 1722b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ClearHardwareWatchpoint(uint32_t hw_index) { 1723a63d08c9SGreg Clayton int kret = ReadDBG(false); 1724a63d08c9SGreg Clayton 1725a63d08c9SGreg Clayton const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 1726b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1727b9c1b51eSKate Stone if (hw_index < num_hw_points) { 1728a63d08c9SGreg Clayton dbg.wcr[hw_index] = 0; 1729b9c1b51eSKate Stone // if (log) log->Printf 1730b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::ClearHardwareWatchpoint( %u ) - 1731b9c1b51eSKate Stone // WVR%u = 0x%8.8x WCR%u = 0x%8.8x", 173289f138aeSGreg Clayton // hw_index, 173389f138aeSGreg Clayton // hw_index, 173489f138aeSGreg Clayton // dbg.wvr[hw_index], 173589f138aeSGreg Clayton // hw_index, 173689f138aeSGreg Clayton // dbg.wcr[hw_index]); 1737a63d08c9SGreg Clayton 1738a63d08c9SGreg Clayton kret = WriteDBG(); 1739a63d08c9SGreg Clayton 1740a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1741a63d08c9SGreg Clayton return true; 1742a63d08c9SGreg Clayton } 1743a63d08c9SGreg Clayton } 1744a63d08c9SGreg Clayton return false; 1745a63d08c9SGreg Clayton } 1746