180814287SRaphael Isemann //===-- RegisterContextDarwin_arm.cpp -------------------------------------===// 2a63d08c9SGreg Clayton // 32946cd70SChandler Carruth // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 42946cd70SChandler Carruth // See https://llvm.org/LICENSE.txt for license information. 52946cd70SChandler Carruth // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6a63d08c9SGreg Clayton // 7a63d08c9SGreg Clayton //===----------------------------------------------------------------------===// 8a63d08c9SGreg Clayton 9a63d08c9SGreg Clayton #include "RegisterContextDarwin_arm.h" 10981a34c4SPavel Labath #include "RegisterContextDarwinConstants.h" 11a63d08c9SGreg Clayton 12666cc0b2SZachary Turner #include "lldb/Utility/DataBufferHeap.h" 13666cc0b2SZachary Turner #include "lldb/Utility/DataExtractor.h" 1401c3243fSZachary Turner #include "lldb/Utility/Endian.h" 156f9e6901SZachary Turner #include "lldb/Utility/Log.h" 16d821c997SPavel Labath #include "lldb/Utility/RegisterValue.h" 17d821c997SPavel Labath #include "lldb/Utility/Scalar.h" 1812a19904SDaniel Dunbar #include "llvm/Support/Compiler.h" 1912a19904SDaniel Dunbar 20dce502edSGreg Clayton #include "Plugins/Process/Utility/InstructionUtils.h" 21dce502edSGreg Clayton 22796ac80bSJonas Devlieghere #include <memory> 23796ac80bSJonas Devlieghere 24ff9c4ff1SEric Liu #include "Utility/ARM_DWARF_Registers.h" 2563bd0db0SJason Molenda #include "Utility/ARM_ehframe_Registers.h" 26a63d08c9SGreg Clayton 2728606954SSaleem Abdulrasool #include "llvm/ADT/STLExtras.h" 2828606954SSaleem Abdulrasool 29a63d08c9SGreg Clayton using namespace lldb; 30a63d08c9SGreg Clayton using namespace lldb_private; 31a63d08c9SGreg Clayton 32b9c1b51eSKate Stone enum { 33a63d08c9SGreg Clayton gpr_r0 = 0, 34a63d08c9SGreg Clayton gpr_r1, 35a63d08c9SGreg Clayton gpr_r2, 36a63d08c9SGreg Clayton gpr_r3, 37a63d08c9SGreg Clayton gpr_r4, 38a63d08c9SGreg Clayton gpr_r5, 39a63d08c9SGreg Clayton gpr_r6, 40a63d08c9SGreg Clayton gpr_r7, 41a63d08c9SGreg Clayton gpr_r8, 42a63d08c9SGreg Clayton gpr_r9, 43a63d08c9SGreg Clayton gpr_r10, 44a63d08c9SGreg Clayton gpr_r11, 45a63d08c9SGreg Clayton gpr_r12, 46b9c1b51eSKate Stone gpr_r13, 47b9c1b51eSKate Stone gpr_sp = gpr_r13, 48b9c1b51eSKate Stone gpr_r14, 49b9c1b51eSKate Stone gpr_lr = gpr_r14, 50b9c1b51eSKate Stone gpr_r15, 51b9c1b51eSKate Stone gpr_pc = gpr_r15, 52a63d08c9SGreg Clayton gpr_cpsr, 53a63d08c9SGreg Clayton 54a63d08c9SGreg Clayton fpu_s0, 55a63d08c9SGreg Clayton fpu_s1, 56a63d08c9SGreg Clayton fpu_s2, 57a63d08c9SGreg Clayton fpu_s3, 58a63d08c9SGreg Clayton fpu_s4, 59a63d08c9SGreg Clayton fpu_s5, 60a63d08c9SGreg Clayton fpu_s6, 61a63d08c9SGreg Clayton fpu_s7, 62a63d08c9SGreg Clayton fpu_s8, 63a63d08c9SGreg Clayton fpu_s9, 64a63d08c9SGreg Clayton fpu_s10, 65a63d08c9SGreg Clayton fpu_s11, 66a63d08c9SGreg Clayton fpu_s12, 67a63d08c9SGreg Clayton fpu_s13, 68a63d08c9SGreg Clayton fpu_s14, 69a63d08c9SGreg Clayton fpu_s15, 70a63d08c9SGreg Clayton fpu_s16, 71a63d08c9SGreg Clayton fpu_s17, 72a63d08c9SGreg Clayton fpu_s18, 73a63d08c9SGreg Clayton fpu_s19, 74a63d08c9SGreg Clayton fpu_s20, 75a63d08c9SGreg Clayton fpu_s21, 76a63d08c9SGreg Clayton fpu_s22, 77a63d08c9SGreg Clayton fpu_s23, 78a63d08c9SGreg Clayton fpu_s24, 79a63d08c9SGreg Clayton fpu_s25, 80a63d08c9SGreg Clayton fpu_s26, 81a63d08c9SGreg Clayton fpu_s27, 82a63d08c9SGreg Clayton fpu_s28, 83a63d08c9SGreg Clayton fpu_s29, 84a63d08c9SGreg Clayton fpu_s30, 85a63d08c9SGreg Clayton fpu_s31, 86a63d08c9SGreg Clayton fpu_fpscr, 87a63d08c9SGreg Clayton 88a63d08c9SGreg Clayton exc_exception, 89a63d08c9SGreg Clayton exc_fsr, 90a63d08c9SGreg Clayton exc_far, 91a63d08c9SGreg Clayton 92a63d08c9SGreg Clayton dbg_bvr0, 93a63d08c9SGreg Clayton dbg_bvr1, 94a63d08c9SGreg Clayton dbg_bvr2, 95a63d08c9SGreg Clayton dbg_bvr3, 96a63d08c9SGreg Clayton dbg_bvr4, 97a63d08c9SGreg Clayton dbg_bvr5, 98a63d08c9SGreg Clayton dbg_bvr6, 99a63d08c9SGreg Clayton dbg_bvr7, 100a63d08c9SGreg Clayton dbg_bvr8, 101a63d08c9SGreg Clayton dbg_bvr9, 102a63d08c9SGreg Clayton dbg_bvr10, 103a63d08c9SGreg Clayton dbg_bvr11, 104a63d08c9SGreg Clayton dbg_bvr12, 105a63d08c9SGreg Clayton dbg_bvr13, 106a63d08c9SGreg Clayton dbg_bvr14, 107a63d08c9SGreg Clayton dbg_bvr15, 108a63d08c9SGreg Clayton 109a63d08c9SGreg Clayton dbg_bcr0, 110a63d08c9SGreg Clayton dbg_bcr1, 111a63d08c9SGreg Clayton dbg_bcr2, 112a63d08c9SGreg Clayton dbg_bcr3, 113a63d08c9SGreg Clayton dbg_bcr4, 114a63d08c9SGreg Clayton dbg_bcr5, 115a63d08c9SGreg Clayton dbg_bcr6, 116a63d08c9SGreg Clayton dbg_bcr7, 117a63d08c9SGreg Clayton dbg_bcr8, 118a63d08c9SGreg Clayton dbg_bcr9, 119a63d08c9SGreg Clayton dbg_bcr10, 120a63d08c9SGreg Clayton dbg_bcr11, 121a63d08c9SGreg Clayton dbg_bcr12, 122a63d08c9SGreg Clayton dbg_bcr13, 123a63d08c9SGreg Clayton dbg_bcr14, 124a63d08c9SGreg Clayton dbg_bcr15, 125a63d08c9SGreg Clayton 126a63d08c9SGreg Clayton dbg_wvr0, 127a63d08c9SGreg Clayton dbg_wvr1, 128a63d08c9SGreg Clayton dbg_wvr2, 129a63d08c9SGreg Clayton dbg_wvr3, 130a63d08c9SGreg Clayton dbg_wvr4, 131a63d08c9SGreg Clayton dbg_wvr5, 132a63d08c9SGreg Clayton dbg_wvr6, 133a63d08c9SGreg Clayton dbg_wvr7, 134a63d08c9SGreg Clayton dbg_wvr8, 135a63d08c9SGreg Clayton dbg_wvr9, 136a63d08c9SGreg Clayton dbg_wvr10, 137a63d08c9SGreg Clayton dbg_wvr11, 138a63d08c9SGreg Clayton dbg_wvr12, 139a63d08c9SGreg Clayton dbg_wvr13, 140a63d08c9SGreg Clayton dbg_wvr14, 141a63d08c9SGreg Clayton dbg_wvr15, 142a63d08c9SGreg Clayton 143a63d08c9SGreg Clayton dbg_wcr0, 144a63d08c9SGreg Clayton dbg_wcr1, 145a63d08c9SGreg Clayton dbg_wcr2, 146a63d08c9SGreg Clayton dbg_wcr3, 147a63d08c9SGreg Clayton dbg_wcr4, 148a63d08c9SGreg Clayton dbg_wcr5, 149a63d08c9SGreg Clayton dbg_wcr6, 150a63d08c9SGreg Clayton dbg_wcr7, 151a63d08c9SGreg Clayton dbg_wcr8, 152a63d08c9SGreg Clayton dbg_wcr9, 153a63d08c9SGreg Clayton dbg_wcr10, 154a63d08c9SGreg Clayton dbg_wcr11, 155a63d08c9SGreg Clayton dbg_wcr12, 156a63d08c9SGreg Clayton dbg_wcr13, 157a63d08c9SGreg Clayton dbg_wcr14, 158a63d08c9SGreg Clayton dbg_wcr15, 159a63d08c9SGreg Clayton 160a63d08c9SGreg Clayton k_num_registers 161a63d08c9SGreg Clayton }; 162a63d08c9SGreg Clayton 163a63d08c9SGreg Clayton #define GPR_OFFSET(idx) ((idx)*4) 164a63d08c9SGreg Clayton #define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR)) 165b9c1b51eSKate Stone #define EXC_OFFSET(idx) \ 166b9c1b51eSKate Stone ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR) + \ 167b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU)) 168b9c1b51eSKate Stone #define DBG_OFFSET(reg) \ 169b9c1b51eSKate Stone ((LLVM_EXTENSION offsetof(RegisterContextDarwin_arm::DBG, reg) + \ 170b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::GPR) + \ 171b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU) + \ 172b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::EXC))) 173a63d08c9SGreg Clayton 174b9c1b51eSKate Stone #define DEFINE_DBG(reg, i) \ 175b9c1b51eSKate Stone #reg, NULL, sizeof(((RegisterContextDarwin_arm::DBG *) NULL)->reg[i]), \ 176b9c1b51eSKate Stone DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, \ 177b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 178b9c1b51eSKate Stone LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 179b9c1b51eSKate Stone LLDB_INVALID_REGNUM }, \ 180202af507SPavel Labath nullptr, nullptr, 181b9c1b51eSKate Stone #define REG_CONTEXT_SIZE \ 182b9c1b51eSKate Stone (sizeof(RegisterContextDarwin_arm::GPR) + \ 183b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU) + \ 184b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::EXC)) 185a63d08c9SGreg Clayton 186a63d08c9SGreg Clayton static RegisterInfo g_register_infos[] = { 187a63d08c9SGreg Clayton // General purpose registers 188b9c1b51eSKate Stone // NAME ALT SZ OFFSET ENCODING FORMAT 189b9c1b51eSKate Stone // EH_FRAME DWARF GENERIC 190b9c1b51eSKate Stone // PROCESS PLUGIN LLDB NATIVE 191b9c1b51eSKate Stone // ====== ======= == ============= ============= ============ 192b9c1b51eSKate Stone // =============== =============== ========================= 193b9c1b51eSKate Stone // ===================== ============= 194b9c1b51eSKate Stone {"r0", 195248a1305SKonrad Kleine nullptr, 196b9c1b51eSKate Stone 4, 197b9c1b51eSKate Stone GPR_OFFSET(0), 198b9c1b51eSKate Stone eEncodingUint, 199b9c1b51eSKate Stone eFormatHex, 200b9c1b51eSKate Stone {ehframe_r0, dwarf_r0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r0}, 201b9c1b51eSKate Stone nullptr, 202b9c1b51eSKate Stone nullptr, 203202af507SPavel Labath }, 204b9c1b51eSKate Stone {"r1", 205248a1305SKonrad Kleine nullptr, 206b9c1b51eSKate Stone 4, 207b9c1b51eSKate Stone GPR_OFFSET(1), 208b9c1b51eSKate Stone eEncodingUint, 209b9c1b51eSKate Stone eFormatHex, 210b9c1b51eSKate Stone {ehframe_r1, dwarf_r1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r1}, 211b9c1b51eSKate Stone nullptr, 212b9c1b51eSKate Stone nullptr, 213202af507SPavel Labath }, 214b9c1b51eSKate Stone {"r2", 215248a1305SKonrad Kleine nullptr, 216b9c1b51eSKate Stone 4, 217b9c1b51eSKate Stone GPR_OFFSET(2), 218b9c1b51eSKate Stone eEncodingUint, 219b9c1b51eSKate Stone eFormatHex, 220b9c1b51eSKate Stone {ehframe_r2, dwarf_r2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r2}, 221b9c1b51eSKate Stone nullptr, 222b9c1b51eSKate Stone nullptr, 223202af507SPavel Labath }, 224b9c1b51eSKate Stone {"r3", 225248a1305SKonrad Kleine nullptr, 226b9c1b51eSKate Stone 4, 227b9c1b51eSKate Stone GPR_OFFSET(3), 228b9c1b51eSKate Stone eEncodingUint, 229b9c1b51eSKate Stone eFormatHex, 230b9c1b51eSKate Stone {ehframe_r3, dwarf_r3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r3}, 231b9c1b51eSKate Stone nullptr, 232b9c1b51eSKate Stone nullptr, 233202af507SPavel Labath }, 234b9c1b51eSKate Stone {"r4", 235248a1305SKonrad Kleine nullptr, 236b9c1b51eSKate Stone 4, 237b9c1b51eSKate Stone GPR_OFFSET(4), 238b9c1b51eSKate Stone eEncodingUint, 239b9c1b51eSKate Stone eFormatHex, 240b9c1b51eSKate Stone {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4}, 241b9c1b51eSKate Stone nullptr, 242b9c1b51eSKate Stone nullptr, 243202af507SPavel Labath }, 244b9c1b51eSKate Stone {"r5", 245248a1305SKonrad Kleine nullptr, 246b9c1b51eSKate Stone 4, 247b9c1b51eSKate Stone GPR_OFFSET(5), 248b9c1b51eSKate Stone eEncodingUint, 249b9c1b51eSKate Stone eFormatHex, 250b9c1b51eSKate Stone {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5}, 251b9c1b51eSKate Stone nullptr, 252b9c1b51eSKate Stone nullptr, 253202af507SPavel Labath }, 254b9c1b51eSKate Stone {"r6", 255248a1305SKonrad Kleine nullptr, 256b9c1b51eSKate Stone 4, 257b9c1b51eSKate Stone GPR_OFFSET(6), 258b9c1b51eSKate Stone eEncodingUint, 259b9c1b51eSKate Stone eFormatHex, 260b9c1b51eSKate Stone {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6}, 261b9c1b51eSKate Stone nullptr, 262b9c1b51eSKate Stone nullptr, 263202af507SPavel Labath }, 264b9c1b51eSKate Stone {"r7", 265248a1305SKonrad Kleine nullptr, 266b9c1b51eSKate Stone 4, 267b9c1b51eSKate Stone GPR_OFFSET(7), 268b9c1b51eSKate Stone eEncodingUint, 269b9c1b51eSKate Stone eFormatHex, 270b9c1b51eSKate Stone {ehframe_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, 271b9c1b51eSKate Stone gpr_r7}, 272b9c1b51eSKate Stone nullptr, 273b9c1b51eSKate Stone nullptr, 274202af507SPavel Labath }, 275b9c1b51eSKate Stone {"r8", 276248a1305SKonrad Kleine nullptr, 277b9c1b51eSKate Stone 4, 278b9c1b51eSKate Stone GPR_OFFSET(8), 279b9c1b51eSKate Stone eEncodingUint, 280b9c1b51eSKate Stone eFormatHex, 281b9c1b51eSKate Stone {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8}, 282b9c1b51eSKate Stone nullptr, 283b9c1b51eSKate Stone nullptr, 284202af507SPavel Labath }, 285b9c1b51eSKate Stone {"r9", 286248a1305SKonrad Kleine nullptr, 287b9c1b51eSKate Stone 4, 288b9c1b51eSKate Stone GPR_OFFSET(9), 289b9c1b51eSKate Stone eEncodingUint, 290b9c1b51eSKate Stone eFormatHex, 291b9c1b51eSKate Stone {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9}, 292b9c1b51eSKate Stone nullptr, 293b9c1b51eSKate Stone nullptr, 294202af507SPavel Labath }, 295b9c1b51eSKate Stone {"r10", 296248a1305SKonrad Kleine nullptr, 297b9c1b51eSKate Stone 4, 298b9c1b51eSKate Stone GPR_OFFSET(10), 299b9c1b51eSKate Stone eEncodingUint, 300b9c1b51eSKate Stone eFormatHex, 301b9c1b51eSKate Stone {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 302b9c1b51eSKate Stone gpr_r10}, 303b9c1b51eSKate Stone nullptr, 304b9c1b51eSKate Stone nullptr, 305202af507SPavel Labath }, 306b9c1b51eSKate Stone {"r11", 307248a1305SKonrad Kleine nullptr, 308b9c1b51eSKate Stone 4, 309b9c1b51eSKate Stone GPR_OFFSET(11), 310b9c1b51eSKate Stone eEncodingUint, 311b9c1b51eSKate Stone eFormatHex, 312b9c1b51eSKate Stone {ehframe_r11, dwarf_r11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 313b9c1b51eSKate Stone gpr_r11}, 314b9c1b51eSKate Stone nullptr, 315b9c1b51eSKate Stone nullptr, 316202af507SPavel Labath }, 317b9c1b51eSKate Stone {"r12", 318248a1305SKonrad Kleine nullptr, 319b9c1b51eSKate Stone 4, 320b9c1b51eSKate Stone GPR_OFFSET(12), 321b9c1b51eSKate Stone eEncodingUint, 322b9c1b51eSKate Stone eFormatHex, 323b9c1b51eSKate Stone {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 324b9c1b51eSKate Stone gpr_r12}, 325b9c1b51eSKate Stone nullptr, 326b9c1b51eSKate Stone nullptr, 327202af507SPavel Labath }, 328b9c1b51eSKate Stone {"sp", 329b9c1b51eSKate Stone "r13", 330b9c1b51eSKate Stone 4, 331b9c1b51eSKate Stone GPR_OFFSET(13), 332b9c1b51eSKate Stone eEncodingUint, 333b9c1b51eSKate Stone eFormatHex, 334b9c1b51eSKate Stone {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, 335b9c1b51eSKate Stone gpr_sp}, 336b9c1b51eSKate Stone nullptr, 337b9c1b51eSKate Stone nullptr, 338202af507SPavel Labath }, 339b9c1b51eSKate Stone {"lr", 340b9c1b51eSKate Stone "r14", 341b9c1b51eSKate Stone 4, 342b9c1b51eSKate Stone GPR_OFFSET(14), 343b9c1b51eSKate Stone eEncodingUint, 344b9c1b51eSKate Stone eFormatHex, 345b9c1b51eSKate Stone {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, 346b9c1b51eSKate Stone gpr_lr}, 347b9c1b51eSKate Stone nullptr, 348b9c1b51eSKate Stone nullptr, 349202af507SPavel Labath }, 350b9c1b51eSKate Stone {"pc", 351b9c1b51eSKate Stone "r15", 352b9c1b51eSKate Stone 4, 353b9c1b51eSKate Stone GPR_OFFSET(15), 354b9c1b51eSKate Stone eEncodingUint, 355b9c1b51eSKate Stone eFormatHex, 356b9c1b51eSKate Stone {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, 357b9c1b51eSKate Stone gpr_pc}, 358b9c1b51eSKate Stone nullptr, 359b9c1b51eSKate Stone nullptr, 360202af507SPavel Labath }, 361b9c1b51eSKate Stone {"cpsr", 362b9c1b51eSKate Stone "psr", 363b9c1b51eSKate Stone 4, 364b9c1b51eSKate Stone GPR_OFFSET(16), 365b9c1b51eSKate Stone eEncodingUint, 366b9c1b51eSKate Stone eFormatHex, 367b9c1b51eSKate Stone {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM, 368b9c1b51eSKate Stone gpr_cpsr}, 369b9c1b51eSKate Stone nullptr, 370b9c1b51eSKate Stone nullptr, 371202af507SPavel Labath }, 372a63d08c9SGreg Clayton 373b9c1b51eSKate Stone {"s0", 374248a1305SKonrad Kleine nullptr, 375b9c1b51eSKate Stone 4, 376b9c1b51eSKate Stone FPU_OFFSET(0), 377b9c1b51eSKate Stone eEncodingIEEE754, 378b9c1b51eSKate Stone eFormatFloat, 379b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 380b9c1b51eSKate Stone fpu_s0}, 381b9c1b51eSKate Stone nullptr, 382b9c1b51eSKate Stone nullptr, 383202af507SPavel Labath }, 384b9c1b51eSKate Stone {"s1", 385248a1305SKonrad Kleine nullptr, 386b9c1b51eSKate Stone 4, 387b9c1b51eSKate Stone FPU_OFFSET(1), 388b9c1b51eSKate Stone eEncodingIEEE754, 389b9c1b51eSKate Stone eFormatFloat, 390b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 391b9c1b51eSKate Stone fpu_s1}, 392b9c1b51eSKate Stone nullptr, 393b9c1b51eSKate Stone nullptr, 394202af507SPavel Labath }, 395b9c1b51eSKate Stone {"s2", 396248a1305SKonrad Kleine nullptr, 397b9c1b51eSKate Stone 4, 398b9c1b51eSKate Stone FPU_OFFSET(2), 399b9c1b51eSKate Stone eEncodingIEEE754, 400b9c1b51eSKate Stone eFormatFloat, 401b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 402b9c1b51eSKate Stone fpu_s2}, 403b9c1b51eSKate Stone nullptr, 404b9c1b51eSKate Stone nullptr, 405202af507SPavel Labath }, 406b9c1b51eSKate Stone {"s3", 407248a1305SKonrad Kleine nullptr, 408b9c1b51eSKate Stone 4, 409b9c1b51eSKate Stone FPU_OFFSET(3), 410b9c1b51eSKate Stone eEncodingIEEE754, 411b9c1b51eSKate Stone eFormatFloat, 412b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 413b9c1b51eSKate Stone fpu_s3}, 414b9c1b51eSKate Stone nullptr, 415b9c1b51eSKate Stone nullptr, 416202af507SPavel Labath }, 417b9c1b51eSKate Stone {"s4", 418248a1305SKonrad Kleine nullptr, 419b9c1b51eSKate Stone 4, 420b9c1b51eSKate Stone FPU_OFFSET(4), 421b9c1b51eSKate Stone eEncodingIEEE754, 422b9c1b51eSKate Stone eFormatFloat, 423b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 424b9c1b51eSKate Stone fpu_s4}, 425b9c1b51eSKate Stone nullptr, 426b9c1b51eSKate Stone nullptr, 427202af507SPavel Labath }, 428b9c1b51eSKate Stone {"s5", 429248a1305SKonrad Kleine nullptr, 430b9c1b51eSKate Stone 4, 431b9c1b51eSKate Stone FPU_OFFSET(5), 432b9c1b51eSKate Stone eEncodingIEEE754, 433b9c1b51eSKate Stone eFormatFloat, 434b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 435b9c1b51eSKate Stone fpu_s5}, 436b9c1b51eSKate Stone nullptr, 437b9c1b51eSKate Stone nullptr, 438202af507SPavel Labath }, 439b9c1b51eSKate Stone {"s6", 440248a1305SKonrad Kleine nullptr, 441b9c1b51eSKate Stone 4, 442b9c1b51eSKate Stone FPU_OFFSET(6), 443b9c1b51eSKate Stone eEncodingIEEE754, 444b9c1b51eSKate Stone eFormatFloat, 445b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 446b9c1b51eSKate Stone fpu_s6}, 447b9c1b51eSKate Stone nullptr, 448b9c1b51eSKate Stone nullptr, 449202af507SPavel Labath }, 450b9c1b51eSKate Stone {"s7", 451248a1305SKonrad Kleine nullptr, 452b9c1b51eSKate Stone 4, 453b9c1b51eSKate Stone FPU_OFFSET(7), 454b9c1b51eSKate Stone eEncodingIEEE754, 455b9c1b51eSKate Stone eFormatFloat, 456b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 457b9c1b51eSKate Stone fpu_s7}, 458b9c1b51eSKate Stone nullptr, 459b9c1b51eSKate Stone nullptr, 460202af507SPavel Labath }, 461b9c1b51eSKate Stone {"s8", 462248a1305SKonrad Kleine nullptr, 463b9c1b51eSKate Stone 4, 464b9c1b51eSKate Stone FPU_OFFSET(8), 465b9c1b51eSKate Stone eEncodingIEEE754, 466b9c1b51eSKate Stone eFormatFloat, 467b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 468b9c1b51eSKate Stone fpu_s8}, 469b9c1b51eSKate Stone nullptr, 470b9c1b51eSKate Stone nullptr, 471202af507SPavel Labath }, 472b9c1b51eSKate Stone {"s9", 473248a1305SKonrad Kleine nullptr, 474b9c1b51eSKate Stone 4, 475b9c1b51eSKate Stone FPU_OFFSET(9), 476b9c1b51eSKate Stone eEncodingIEEE754, 477b9c1b51eSKate Stone eFormatFloat, 478b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 479b9c1b51eSKate Stone fpu_s9}, 480b9c1b51eSKate Stone nullptr, 481b9c1b51eSKate Stone nullptr, 482202af507SPavel Labath }, 483b9c1b51eSKate Stone {"s10", 484248a1305SKonrad Kleine nullptr, 485b9c1b51eSKate Stone 4, 486b9c1b51eSKate Stone FPU_OFFSET(10), 487b9c1b51eSKate Stone eEncodingIEEE754, 488b9c1b51eSKate Stone eFormatFloat, 489b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 490b9c1b51eSKate Stone fpu_s10}, 491b9c1b51eSKate Stone nullptr, 492b9c1b51eSKate Stone nullptr, 493202af507SPavel Labath }, 494b9c1b51eSKate Stone {"s11", 495248a1305SKonrad Kleine nullptr, 496b9c1b51eSKate Stone 4, 497b9c1b51eSKate Stone FPU_OFFSET(11), 498b9c1b51eSKate Stone eEncodingIEEE754, 499b9c1b51eSKate Stone eFormatFloat, 500b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 501b9c1b51eSKate Stone fpu_s11}, 502b9c1b51eSKate Stone nullptr, 503b9c1b51eSKate Stone nullptr, 504202af507SPavel Labath }, 505b9c1b51eSKate Stone {"s12", 506248a1305SKonrad Kleine nullptr, 507b9c1b51eSKate Stone 4, 508b9c1b51eSKate Stone FPU_OFFSET(12), 509b9c1b51eSKate Stone eEncodingIEEE754, 510b9c1b51eSKate Stone eFormatFloat, 511b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 512b9c1b51eSKate Stone fpu_s12}, 513b9c1b51eSKate Stone nullptr, 514b9c1b51eSKate Stone nullptr, 515202af507SPavel Labath }, 516b9c1b51eSKate Stone {"s13", 517248a1305SKonrad Kleine nullptr, 518b9c1b51eSKate Stone 4, 519b9c1b51eSKate Stone FPU_OFFSET(13), 520b9c1b51eSKate Stone eEncodingIEEE754, 521b9c1b51eSKate Stone eFormatFloat, 522b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 523b9c1b51eSKate Stone fpu_s13}, 524b9c1b51eSKate Stone nullptr, 525b9c1b51eSKate Stone nullptr, 526202af507SPavel Labath }, 527b9c1b51eSKate Stone {"s14", 528248a1305SKonrad Kleine nullptr, 529b9c1b51eSKate Stone 4, 530b9c1b51eSKate Stone FPU_OFFSET(14), 531b9c1b51eSKate Stone eEncodingIEEE754, 532b9c1b51eSKate Stone eFormatFloat, 533b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 534b9c1b51eSKate Stone fpu_s14}, 535b9c1b51eSKate Stone nullptr, 536b9c1b51eSKate Stone nullptr, 537202af507SPavel Labath }, 538b9c1b51eSKate Stone {"s15", 539248a1305SKonrad Kleine nullptr, 540b9c1b51eSKate Stone 4, 541b9c1b51eSKate Stone FPU_OFFSET(15), 542b9c1b51eSKate Stone eEncodingIEEE754, 543b9c1b51eSKate Stone eFormatFloat, 544b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 545b9c1b51eSKate Stone fpu_s15}, 546b9c1b51eSKate Stone nullptr, 547b9c1b51eSKate Stone nullptr, 548202af507SPavel Labath }, 549b9c1b51eSKate Stone {"s16", 550248a1305SKonrad Kleine nullptr, 551b9c1b51eSKate Stone 4, 552b9c1b51eSKate Stone FPU_OFFSET(16), 553b9c1b51eSKate Stone eEncodingIEEE754, 554b9c1b51eSKate Stone eFormatFloat, 555b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 556b9c1b51eSKate Stone fpu_s16}, 557b9c1b51eSKate Stone nullptr, 558b9c1b51eSKate Stone nullptr, 559202af507SPavel Labath }, 560b9c1b51eSKate Stone {"s17", 561248a1305SKonrad Kleine nullptr, 562b9c1b51eSKate Stone 4, 563b9c1b51eSKate Stone FPU_OFFSET(17), 564b9c1b51eSKate Stone eEncodingIEEE754, 565b9c1b51eSKate Stone eFormatFloat, 566b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 567b9c1b51eSKate Stone fpu_s17}, 568b9c1b51eSKate Stone nullptr, 569b9c1b51eSKate Stone nullptr, 570202af507SPavel Labath }, 571b9c1b51eSKate Stone {"s18", 572248a1305SKonrad Kleine nullptr, 573b9c1b51eSKate Stone 4, 574b9c1b51eSKate Stone FPU_OFFSET(18), 575b9c1b51eSKate Stone eEncodingIEEE754, 576b9c1b51eSKate Stone eFormatFloat, 577b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 578b9c1b51eSKate Stone fpu_s18}, 579b9c1b51eSKate Stone nullptr, 580b9c1b51eSKate Stone nullptr, 581202af507SPavel Labath }, 582b9c1b51eSKate Stone {"s19", 583248a1305SKonrad Kleine nullptr, 584b9c1b51eSKate Stone 4, 585b9c1b51eSKate Stone FPU_OFFSET(19), 586b9c1b51eSKate Stone eEncodingIEEE754, 587b9c1b51eSKate Stone eFormatFloat, 588b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 589b9c1b51eSKate Stone fpu_s19}, 590b9c1b51eSKate Stone nullptr, 591b9c1b51eSKate Stone nullptr, 592202af507SPavel Labath }, 593b9c1b51eSKate Stone {"s20", 594248a1305SKonrad Kleine nullptr, 595b9c1b51eSKate Stone 4, 596b9c1b51eSKate Stone FPU_OFFSET(20), 597b9c1b51eSKate Stone eEncodingIEEE754, 598b9c1b51eSKate Stone eFormatFloat, 599b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 600b9c1b51eSKate Stone fpu_s20}, 601b9c1b51eSKate Stone nullptr, 602b9c1b51eSKate Stone nullptr, 603202af507SPavel Labath }, 604b9c1b51eSKate Stone {"s21", 605248a1305SKonrad Kleine nullptr, 606b9c1b51eSKate Stone 4, 607b9c1b51eSKate Stone FPU_OFFSET(21), 608b9c1b51eSKate Stone eEncodingIEEE754, 609b9c1b51eSKate Stone eFormatFloat, 610b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 611b9c1b51eSKate Stone fpu_s21}, 612b9c1b51eSKate Stone nullptr, 613b9c1b51eSKate Stone nullptr, 614202af507SPavel Labath }, 615b9c1b51eSKate Stone {"s22", 616248a1305SKonrad Kleine nullptr, 617b9c1b51eSKate Stone 4, 618b9c1b51eSKate Stone FPU_OFFSET(22), 619b9c1b51eSKate Stone eEncodingIEEE754, 620b9c1b51eSKate Stone eFormatFloat, 621b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 622b9c1b51eSKate Stone fpu_s22}, 623b9c1b51eSKate Stone nullptr, 624b9c1b51eSKate Stone nullptr, 625202af507SPavel Labath }, 626b9c1b51eSKate Stone {"s23", 627248a1305SKonrad Kleine nullptr, 628b9c1b51eSKate Stone 4, 629b9c1b51eSKate Stone FPU_OFFSET(23), 630b9c1b51eSKate Stone eEncodingIEEE754, 631b9c1b51eSKate Stone eFormatFloat, 632b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 633b9c1b51eSKate Stone fpu_s23}, 634b9c1b51eSKate Stone nullptr, 635b9c1b51eSKate Stone nullptr, 636202af507SPavel Labath }, 637b9c1b51eSKate Stone {"s24", 638248a1305SKonrad Kleine nullptr, 639b9c1b51eSKate Stone 4, 640b9c1b51eSKate Stone FPU_OFFSET(24), 641b9c1b51eSKate Stone eEncodingIEEE754, 642b9c1b51eSKate Stone eFormatFloat, 643b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 644b9c1b51eSKate Stone fpu_s24}, 645b9c1b51eSKate Stone nullptr, 646b9c1b51eSKate Stone nullptr, 647202af507SPavel Labath }, 648b9c1b51eSKate Stone {"s25", 649248a1305SKonrad Kleine nullptr, 650b9c1b51eSKate Stone 4, 651b9c1b51eSKate Stone FPU_OFFSET(25), 652b9c1b51eSKate Stone eEncodingIEEE754, 653b9c1b51eSKate Stone eFormatFloat, 654b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 655b9c1b51eSKate Stone fpu_s25}, 656b9c1b51eSKate Stone nullptr, 657b9c1b51eSKate Stone nullptr, 658202af507SPavel Labath }, 659b9c1b51eSKate Stone {"s26", 660248a1305SKonrad Kleine nullptr, 661b9c1b51eSKate Stone 4, 662b9c1b51eSKate Stone FPU_OFFSET(26), 663b9c1b51eSKate Stone eEncodingIEEE754, 664b9c1b51eSKate Stone eFormatFloat, 665b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 666b9c1b51eSKate Stone fpu_s26}, 667b9c1b51eSKate Stone nullptr, 668b9c1b51eSKate Stone nullptr, 669202af507SPavel Labath }, 670b9c1b51eSKate Stone {"s27", 671248a1305SKonrad Kleine nullptr, 672b9c1b51eSKate Stone 4, 673b9c1b51eSKate Stone FPU_OFFSET(27), 674b9c1b51eSKate Stone eEncodingIEEE754, 675b9c1b51eSKate Stone eFormatFloat, 676b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 677b9c1b51eSKate Stone fpu_s27}, 678b9c1b51eSKate Stone nullptr, 679b9c1b51eSKate Stone nullptr, 680202af507SPavel Labath }, 681b9c1b51eSKate Stone {"s28", 682248a1305SKonrad Kleine nullptr, 683b9c1b51eSKate Stone 4, 684b9c1b51eSKate Stone FPU_OFFSET(28), 685b9c1b51eSKate Stone eEncodingIEEE754, 686b9c1b51eSKate Stone eFormatFloat, 687b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 688b9c1b51eSKate Stone fpu_s28}, 689b9c1b51eSKate Stone nullptr, 690b9c1b51eSKate Stone nullptr, 691202af507SPavel Labath }, 692b9c1b51eSKate Stone {"s29", 693248a1305SKonrad Kleine nullptr, 694b9c1b51eSKate Stone 4, 695b9c1b51eSKate Stone FPU_OFFSET(29), 696b9c1b51eSKate Stone eEncodingIEEE754, 697b9c1b51eSKate Stone eFormatFloat, 698b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 699b9c1b51eSKate Stone fpu_s29}, 700b9c1b51eSKate Stone nullptr, 701b9c1b51eSKate Stone nullptr, 702202af507SPavel Labath }, 703b9c1b51eSKate Stone {"s30", 704248a1305SKonrad Kleine nullptr, 705b9c1b51eSKate Stone 4, 706b9c1b51eSKate Stone FPU_OFFSET(30), 707b9c1b51eSKate Stone eEncodingIEEE754, 708b9c1b51eSKate Stone eFormatFloat, 709b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 710b9c1b51eSKate Stone fpu_s30}, 711b9c1b51eSKate Stone nullptr, 712b9c1b51eSKate Stone nullptr, 713202af507SPavel Labath }, 714b9c1b51eSKate Stone {"s31", 715248a1305SKonrad Kleine nullptr, 716b9c1b51eSKate Stone 4, 717b9c1b51eSKate Stone FPU_OFFSET(31), 718b9c1b51eSKate Stone eEncodingIEEE754, 719b9c1b51eSKate Stone eFormatFloat, 720b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 721b9c1b51eSKate Stone fpu_s31}, 722b9c1b51eSKate Stone nullptr, 723b9c1b51eSKate Stone nullptr, 724202af507SPavel Labath }, 725b9c1b51eSKate Stone {"fpscr", 726248a1305SKonrad Kleine nullptr, 727b9c1b51eSKate Stone 4, 728b9c1b51eSKate Stone FPU_OFFSET(32), 729b9c1b51eSKate Stone eEncodingUint, 730b9c1b51eSKate Stone eFormatHex, 731b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 732b9c1b51eSKate Stone LLDB_INVALID_REGNUM, fpu_fpscr}, 733b9c1b51eSKate Stone nullptr, 734b9c1b51eSKate Stone nullptr, 735202af507SPavel Labath }, 736a63d08c9SGreg Clayton 737b9c1b51eSKate Stone {"exception", 738248a1305SKonrad Kleine nullptr, 739b9c1b51eSKate Stone 4, 740b9c1b51eSKate Stone EXC_OFFSET(0), 741b9c1b51eSKate Stone eEncodingUint, 742b9c1b51eSKate Stone eFormatHex, 743b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 744b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_exception}, 745b9c1b51eSKate Stone nullptr, 746b9c1b51eSKate Stone nullptr, 747202af507SPavel Labath }, 748b9c1b51eSKate Stone {"fsr", 749248a1305SKonrad Kleine nullptr, 750b9c1b51eSKate Stone 4, 751b9c1b51eSKate Stone EXC_OFFSET(1), 752b9c1b51eSKate Stone eEncodingUint, 753b9c1b51eSKate Stone eFormatHex, 754b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 755b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_fsr}, 756b9c1b51eSKate Stone nullptr, 757b9c1b51eSKate Stone nullptr, 758202af507SPavel Labath }, 759b9c1b51eSKate Stone {"far", 760248a1305SKonrad Kleine nullptr, 761b9c1b51eSKate Stone 4, 762b9c1b51eSKate Stone EXC_OFFSET(2), 763b9c1b51eSKate Stone eEncodingUint, 764b9c1b51eSKate Stone eFormatHex, 765b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 766b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_far}, 767b9c1b51eSKate Stone nullptr, 768b9c1b51eSKate Stone nullptr, 769202af507SPavel Labath }, 770a63d08c9SGreg Clayton 771a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 0)}, 772a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 1)}, 773a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 2)}, 774a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 3)}, 775a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 4)}, 776a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 5)}, 777a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 6)}, 778a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 7)}, 779a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 8)}, 780a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 9)}, 781a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 10)}, 782a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 11)}, 783a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 12)}, 784a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 13)}, 785a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 14)}, 786a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 15)}, 787a63d08c9SGreg Clayton 788a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 0)}, 789a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 1)}, 790a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 2)}, 791a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 3)}, 792a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 4)}, 793a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 5)}, 794a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 6)}, 795a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 7)}, 796a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 8)}, 797a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 9)}, 798a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 10)}, 799a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 11)}, 800a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 12)}, 801a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 13)}, 802a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 14)}, 803a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 15)}, 804a63d08c9SGreg Clayton 805a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 0)}, 806a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 1)}, 807a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 2)}, 808a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 3)}, 809a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 4)}, 810a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 5)}, 811a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 6)}, 812a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 7)}, 813a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 8)}, 814a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 9)}, 815a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 10)}, 816a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 11)}, 817a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 12)}, 818a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 13)}, 819a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 14)}, 820a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 15)}, 821a63d08c9SGreg Clayton 822a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 0)}, 823a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 1)}, 824a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 2)}, 825a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 3)}, 826a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 4)}, 827a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 5)}, 828a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 6)}, 829a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 7)}, 830a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 8)}, 831a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 9)}, 832a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 10)}, 833a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 11)}, 834a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 12)}, 835a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 13)}, 836a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 14)}, 837b9c1b51eSKate Stone {DEFINE_DBG(wcr, 15)}}; 838a63d08c9SGreg Clayton 839a63d08c9SGreg Clayton // General purpose registers 840b9c1b51eSKate Stone static uint32_t g_gpr_regnums[] = { 841b9c1b51eSKate Stone gpr_r0, gpr_r1, gpr_r2, gpr_r3, gpr_r4, gpr_r5, gpr_r6, gpr_r7, gpr_r8, 842b9c1b51eSKate Stone gpr_r9, gpr_r10, gpr_r11, gpr_r12, gpr_sp, gpr_lr, gpr_pc, gpr_cpsr}; 843a63d08c9SGreg Clayton 844a63d08c9SGreg Clayton // Floating point registers 845b9c1b51eSKate Stone static uint32_t g_fpu_regnums[] = { 846b9c1b51eSKate Stone fpu_s0, fpu_s1, fpu_s2, fpu_s3, fpu_s4, fpu_s5, fpu_s6, 847b9c1b51eSKate Stone fpu_s7, fpu_s8, fpu_s9, fpu_s10, fpu_s11, fpu_s12, fpu_s13, 848b9c1b51eSKate Stone fpu_s14, fpu_s15, fpu_s16, fpu_s17, fpu_s18, fpu_s19, fpu_s20, 849b9c1b51eSKate Stone fpu_s21, fpu_s22, fpu_s23, fpu_s24, fpu_s25, fpu_s26, fpu_s27, 850b9c1b51eSKate Stone fpu_s28, fpu_s29, fpu_s30, fpu_s31, fpu_fpscr, 851a63d08c9SGreg Clayton }; 852a63d08c9SGreg Clayton 853a63d08c9SGreg Clayton // Exception registers 854a63d08c9SGreg Clayton 855b9c1b51eSKate Stone static uint32_t g_exc_regnums[] = { 856b9c1b51eSKate Stone exc_exception, exc_fsr, exc_far, 857a63d08c9SGreg Clayton }; 858a63d08c9SGreg Clayton 859*f15014ffSBenjamin Kramer static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos); 860a63d08c9SGreg Clayton 861b9c1b51eSKate Stone RegisterContextDarwin_arm::RegisterContextDarwin_arm( 862b9c1b51eSKate Stone Thread &thread, uint32_t concrete_frame_idx) 863b9c1b51eSKate Stone : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() { 86463bd0db0SJason Molenda uint32_t i; 865b9c1b51eSKate Stone for (i = 0; i < kNumErrors; i++) { 86663bd0db0SJason Molenda gpr_errs[i] = -1; 86763bd0db0SJason Molenda fpu_errs[i] = -1; 86863bd0db0SJason Molenda exc_errs[i] = -1; 86963bd0db0SJason Molenda } 87063bd0db0SJason Molenda } 87163bd0db0SJason Molenda 872fd2433e1SJonas Devlieghere RegisterContextDarwin_arm::~RegisterContextDarwin_arm() = default; 87363bd0db0SJason Molenda 874b9c1b51eSKate Stone void RegisterContextDarwin_arm::InvalidateAllRegisters() { 875a63d08c9SGreg Clayton InvalidateAllRegisterStates(); 876a63d08c9SGreg Clayton } 877a63d08c9SGreg Clayton 878b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterCount() { 879a63d08c9SGreg Clayton assert(k_num_register_infos == k_num_registers); 880a63d08c9SGreg Clayton return k_num_registers; 881a63d08c9SGreg Clayton } 882a63d08c9SGreg Clayton 883a63d08c9SGreg Clayton const RegisterInfo * 884b9c1b51eSKate Stone RegisterContextDarwin_arm::GetRegisterInfoAtIndex(size_t reg) { 885a63d08c9SGreg Clayton assert(k_num_register_infos == k_num_registers); 886a63d08c9SGreg Clayton if (reg < k_num_registers) 887a63d08c9SGreg Clayton return &g_register_infos[reg]; 888248a1305SKonrad Kleine return nullptr; 889a63d08c9SGreg Clayton } 890a63d08c9SGreg Clayton 891b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterInfosCount() { 892a63d08c9SGreg Clayton return k_num_register_infos; 893a63d08c9SGreg Clayton } 894a63d08c9SGreg Clayton 895b9c1b51eSKate Stone const RegisterInfo *RegisterContextDarwin_arm::GetRegisterInfos() { 896a63d08c9SGreg Clayton return g_register_infos; 897a63d08c9SGreg Clayton } 898a63d08c9SGreg Clayton 899a63d08c9SGreg Clayton // Number of registers in each register set 900*f15014ffSBenjamin Kramer const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums); 901*f15014ffSBenjamin Kramer const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums); 902*f15014ffSBenjamin Kramer const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums); 903a63d08c9SGreg Clayton 90405097246SAdrian Prantl // Register set definitions. The first definitions at register set index of 90505097246SAdrian Prantl // zero is for all registers, followed by other registers sets. The register 90605097246SAdrian Prantl // information for the all register set need not be filled in. 907b9c1b51eSKate Stone static const RegisterSet g_reg_sets[] = { 908a63d08c9SGreg Clayton { 909b9c1b51eSKate Stone "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, 910b9c1b51eSKate Stone }, 911a63d08c9SGreg Clayton {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums}, 912b9c1b51eSKate Stone {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}}; 913a63d08c9SGreg Clayton 914*f15014ffSBenjamin Kramer const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets); 915a63d08c9SGreg Clayton 916b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterSetCount() { 917a63d08c9SGreg Clayton return k_num_regsets; 918a63d08c9SGreg Clayton } 919a63d08c9SGreg Clayton 920b9c1b51eSKate Stone const RegisterSet *RegisterContextDarwin_arm::GetRegisterSet(size_t reg_set) { 921a63d08c9SGreg Clayton if (reg_set < k_num_regsets) 922a63d08c9SGreg Clayton return &g_reg_sets[reg_set]; 923248a1305SKonrad Kleine return nullptr; 924a63d08c9SGreg Clayton } 925a63d08c9SGreg Clayton 926aaa0ba31SBruce Mitchener // Register information definitions for 32 bit i386. 927b9c1b51eSKate Stone int RegisterContextDarwin_arm::GetSetForNativeRegNum(int reg) { 928a63d08c9SGreg Clayton if (reg < fpu_s0) 929a63d08c9SGreg Clayton return GPRRegSet; 930a63d08c9SGreg Clayton else if (reg < exc_exception) 931a63d08c9SGreg Clayton return FPURegSet; 932a63d08c9SGreg Clayton else if (reg < k_num_registers) 933a63d08c9SGreg Clayton return EXCRegSet; 934a63d08c9SGreg Clayton return -1; 935a63d08c9SGreg Clayton } 936a63d08c9SGreg Clayton 937b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadGPR(bool force) { 938a63d08c9SGreg Clayton int set = GPRRegSet; 939b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 940a63d08c9SGreg Clayton SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr)); 941a63d08c9SGreg Clayton } 942a63d08c9SGreg Clayton return GetError(GPRRegSet, Read); 943a63d08c9SGreg Clayton } 944a63d08c9SGreg Clayton 945b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadFPU(bool force) { 946a63d08c9SGreg Clayton int set = FPURegSet; 947b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 948a63d08c9SGreg Clayton SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu)); 949a63d08c9SGreg Clayton } 950a63d08c9SGreg Clayton return GetError(FPURegSet, Read); 951a63d08c9SGreg Clayton } 952a63d08c9SGreg Clayton 953b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadEXC(bool force) { 954a63d08c9SGreg Clayton int set = EXCRegSet; 955b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 956a63d08c9SGreg Clayton SetError(set, Read, DoReadEXC(GetThreadID(), set, exc)); 957a63d08c9SGreg Clayton } 958a63d08c9SGreg Clayton return GetError(EXCRegSet, Read); 959a63d08c9SGreg Clayton } 960a63d08c9SGreg Clayton 961b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadDBG(bool force) { 962a63d08c9SGreg Clayton int set = DBGRegSet; 963b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 964a63d08c9SGreg Clayton SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg)); 965a63d08c9SGreg Clayton } 966a63d08c9SGreg Clayton return GetError(DBGRegSet, Read); 967a63d08c9SGreg Clayton } 968a63d08c9SGreg Clayton 969b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteGPR() { 970a63d08c9SGreg Clayton int set = GPRRegSet; 971b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 972a63d08c9SGreg Clayton SetError(set, Write, -1); 973a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 974a63d08c9SGreg Clayton } 975a63d08c9SGreg Clayton SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr)); 976a63d08c9SGreg Clayton SetError(set, Read, -1); 977a63d08c9SGreg Clayton return GetError(GPRRegSet, Write); 978a63d08c9SGreg Clayton } 979a63d08c9SGreg Clayton 980b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteFPU() { 981a63d08c9SGreg Clayton int set = FPURegSet; 982b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 983a63d08c9SGreg Clayton SetError(set, Write, -1); 984a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 985a63d08c9SGreg Clayton } 986a63d08c9SGreg Clayton SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu)); 987a63d08c9SGreg Clayton SetError(set, Read, -1); 988a63d08c9SGreg Clayton return GetError(FPURegSet, Write); 989a63d08c9SGreg Clayton } 990a63d08c9SGreg Clayton 991b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteEXC() { 992a63d08c9SGreg Clayton int set = EXCRegSet; 993b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 994a63d08c9SGreg Clayton SetError(set, Write, -1); 995a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 996a63d08c9SGreg Clayton } 997a63d08c9SGreg Clayton SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc)); 998a63d08c9SGreg Clayton SetError(set, Read, -1); 999a63d08c9SGreg Clayton return GetError(EXCRegSet, Write); 1000a63d08c9SGreg Clayton } 1001a63d08c9SGreg Clayton 1002b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteDBG() { 1003a63d08c9SGreg Clayton int set = DBGRegSet; 1004b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1005a63d08c9SGreg Clayton SetError(set, Write, -1); 1006a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1007a63d08c9SGreg Clayton } 1008a63d08c9SGreg Clayton SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg)); 1009a63d08c9SGreg Clayton SetError(set, Read, -1); 1010a63d08c9SGreg Clayton return GetError(DBGRegSet, Write); 1011a63d08c9SGreg Clayton } 1012a63d08c9SGreg Clayton 1013b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadRegisterSet(uint32_t set, bool force) { 1014b9c1b51eSKate Stone switch (set) { 1015b9c1b51eSKate Stone case GPRRegSet: 1016b9c1b51eSKate Stone return ReadGPR(force); 1017b9c1b51eSKate Stone case GPRAltRegSet: 1018b9c1b51eSKate Stone return ReadGPR(force); 1019b9c1b51eSKate Stone case FPURegSet: 1020b9c1b51eSKate Stone return ReadFPU(force); 1021b9c1b51eSKate Stone case EXCRegSet: 1022b9c1b51eSKate Stone return ReadEXC(force); 1023b9c1b51eSKate Stone case DBGRegSet: 1024b9c1b51eSKate Stone return ReadDBG(force); 1025b9c1b51eSKate Stone default: 1026b9c1b51eSKate Stone break; 1027a63d08c9SGreg Clayton } 1028a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1029a63d08c9SGreg Clayton } 1030a63d08c9SGreg Clayton 1031b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteRegisterSet(uint32_t set) { 1032a63d08c9SGreg Clayton // Make sure we have a valid context to set. 1033b9c1b51eSKate Stone if (RegisterSetIsCached(set)) { 1034b9c1b51eSKate Stone switch (set) { 1035b9c1b51eSKate Stone case GPRRegSet: 1036b9c1b51eSKate Stone return WriteGPR(); 1037b9c1b51eSKate Stone case GPRAltRegSet: 1038b9c1b51eSKate Stone return WriteGPR(); 1039b9c1b51eSKate Stone case FPURegSet: 1040b9c1b51eSKate Stone return WriteFPU(); 1041b9c1b51eSKate Stone case EXCRegSet: 1042b9c1b51eSKate Stone return WriteEXC(); 1043b9c1b51eSKate Stone case DBGRegSet: 1044b9c1b51eSKate Stone return WriteDBG(); 1045b9c1b51eSKate Stone default: 1046b9c1b51eSKate Stone break; 1047a63d08c9SGreg Clayton } 1048a63d08c9SGreg Clayton } 1049a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1050a63d08c9SGreg Clayton } 1051a63d08c9SGreg Clayton 1052b9c1b51eSKate Stone void RegisterContextDarwin_arm::LogDBGRegisters(Log *log, const DBG &dbg) { 1053b9c1b51eSKate Stone if (log) { 1054a63d08c9SGreg Clayton for (uint32_t i = 0; i < 16; i++) 105563e5fb76SJonas Devlieghere LLDB_LOGF(log, 105663e5fb76SJonas Devlieghere "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { " 1057b9c1b51eSKate Stone "0x%8.8x, 0x%8.8x }", 1058b9c1b51eSKate Stone i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]); 1059a63d08c9SGreg Clayton } 1060a63d08c9SGreg Clayton } 1061a63d08c9SGreg Clayton 1062b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ReadRegister(const RegisterInfo *reg_info, 1063b9c1b51eSKate Stone RegisterValue &value) { 1064a63d08c9SGreg Clayton const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 1065a63d08c9SGreg Clayton int set = RegisterContextDarwin_arm::GetSetForNativeRegNum(reg); 1066a63d08c9SGreg Clayton 1067a63d08c9SGreg Clayton if (set == -1) 1068a63d08c9SGreg Clayton return false; 1069a63d08c9SGreg Clayton 1070a63d08c9SGreg Clayton if (ReadRegisterSet(set, false) != KERN_SUCCESS) 1071a63d08c9SGreg Clayton return false; 1072a63d08c9SGreg Clayton 1073b9c1b51eSKate Stone switch (reg) { 1074a63d08c9SGreg Clayton case gpr_r0: 1075a63d08c9SGreg Clayton case gpr_r1: 1076a63d08c9SGreg Clayton case gpr_r2: 1077a63d08c9SGreg Clayton case gpr_r3: 1078a63d08c9SGreg Clayton case gpr_r4: 1079a63d08c9SGreg Clayton case gpr_r5: 1080a63d08c9SGreg Clayton case gpr_r6: 1081a63d08c9SGreg Clayton case gpr_r7: 1082a63d08c9SGreg Clayton case gpr_r8: 1083a63d08c9SGreg Clayton case gpr_r9: 1084a63d08c9SGreg Clayton case gpr_r10: 1085a63d08c9SGreg Clayton case gpr_r11: 1086a63d08c9SGreg Clayton case gpr_r12: 1087a63d08c9SGreg Clayton case gpr_sp: 1088a63d08c9SGreg Clayton case gpr_lr: 1089a63d08c9SGreg Clayton case gpr_pc: 1090a63d08c9SGreg Clayton value.SetUInt32(gpr.r[reg - gpr_r0]); 1091a63d08c9SGreg Clayton break; 1092e194d890SJonas Devlieghere case gpr_cpsr: 1093e194d890SJonas Devlieghere value.SetUInt32(gpr.cpsr); 1094e194d890SJonas Devlieghere break; 1095a63d08c9SGreg Clayton case fpu_s0: 1096a63d08c9SGreg Clayton case fpu_s1: 1097a63d08c9SGreg Clayton case fpu_s2: 1098a63d08c9SGreg Clayton case fpu_s3: 1099a63d08c9SGreg Clayton case fpu_s4: 1100a63d08c9SGreg Clayton case fpu_s5: 1101a63d08c9SGreg Clayton case fpu_s6: 1102a63d08c9SGreg Clayton case fpu_s7: 1103a63d08c9SGreg Clayton case fpu_s8: 1104a63d08c9SGreg Clayton case fpu_s9: 1105a63d08c9SGreg Clayton case fpu_s10: 1106a63d08c9SGreg Clayton case fpu_s11: 1107a63d08c9SGreg Clayton case fpu_s12: 1108a63d08c9SGreg Clayton case fpu_s13: 1109a63d08c9SGreg Clayton case fpu_s14: 1110a63d08c9SGreg Clayton case fpu_s15: 1111a63d08c9SGreg Clayton case fpu_s16: 1112a63d08c9SGreg Clayton case fpu_s17: 1113a63d08c9SGreg Clayton case fpu_s18: 1114a63d08c9SGreg Clayton case fpu_s19: 1115a63d08c9SGreg Clayton case fpu_s20: 1116a63d08c9SGreg Clayton case fpu_s21: 1117a63d08c9SGreg Clayton case fpu_s22: 1118a63d08c9SGreg Clayton case fpu_s23: 1119a63d08c9SGreg Clayton case fpu_s24: 1120a63d08c9SGreg Clayton case fpu_s25: 1121a63d08c9SGreg Clayton case fpu_s26: 1122a63d08c9SGreg Clayton case fpu_s27: 1123a63d08c9SGreg Clayton case fpu_s28: 1124a63d08c9SGreg Clayton case fpu_s29: 1125a63d08c9SGreg Clayton case fpu_s30: 1126a63d08c9SGreg Clayton case fpu_s31: 1127a63d08c9SGreg Clayton value.SetUInt32(fpu.floats.s[reg], RegisterValue::eTypeFloat); 1128a63d08c9SGreg Clayton break; 1129a63d08c9SGreg Clayton 1130a63d08c9SGreg Clayton case fpu_fpscr: 1131a63d08c9SGreg Clayton value.SetUInt32(fpu.fpscr); 1132a63d08c9SGreg Clayton break; 1133a63d08c9SGreg Clayton 1134a63d08c9SGreg Clayton case exc_exception: 1135a63d08c9SGreg Clayton value.SetUInt32(exc.exception); 1136a63d08c9SGreg Clayton break; 1137a63d08c9SGreg Clayton case exc_fsr: 1138a63d08c9SGreg Clayton value.SetUInt32(exc.fsr); 1139a63d08c9SGreg Clayton break; 1140a63d08c9SGreg Clayton case exc_far: 1141a63d08c9SGreg Clayton value.SetUInt32(exc.far); 1142a63d08c9SGreg Clayton break; 1143a63d08c9SGreg Clayton 1144a63d08c9SGreg Clayton default: 1145a63d08c9SGreg Clayton value.SetValueToInvalid(); 1146a63d08c9SGreg Clayton return false; 1147a63d08c9SGreg Clayton } 1148a63d08c9SGreg Clayton return true; 1149a63d08c9SGreg Clayton } 1150a63d08c9SGreg Clayton 1151b9c1b51eSKate Stone bool RegisterContextDarwin_arm::WriteRegister(const RegisterInfo *reg_info, 1152b9c1b51eSKate Stone const RegisterValue &value) { 1153a63d08c9SGreg Clayton const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 1154a63d08c9SGreg Clayton int set = GetSetForNativeRegNum(reg); 1155a63d08c9SGreg Clayton 1156a63d08c9SGreg Clayton if (set == -1) 1157a63d08c9SGreg Clayton return false; 1158a63d08c9SGreg Clayton 1159a63d08c9SGreg Clayton if (ReadRegisterSet(set, false) != KERN_SUCCESS) 1160a63d08c9SGreg Clayton return false; 1161a63d08c9SGreg Clayton 1162b9c1b51eSKate Stone switch (reg) { 1163a63d08c9SGreg Clayton case gpr_r0: 1164a63d08c9SGreg Clayton case gpr_r1: 1165a63d08c9SGreg Clayton case gpr_r2: 1166a63d08c9SGreg Clayton case gpr_r3: 1167a63d08c9SGreg Clayton case gpr_r4: 1168a63d08c9SGreg Clayton case gpr_r5: 1169a63d08c9SGreg Clayton case gpr_r6: 1170a63d08c9SGreg Clayton case gpr_r7: 1171a63d08c9SGreg Clayton case gpr_r8: 1172a63d08c9SGreg Clayton case gpr_r9: 1173a63d08c9SGreg Clayton case gpr_r10: 1174a63d08c9SGreg Clayton case gpr_r11: 1175a63d08c9SGreg Clayton case gpr_r12: 1176a63d08c9SGreg Clayton case gpr_sp: 1177a63d08c9SGreg Clayton case gpr_lr: 1178a63d08c9SGreg Clayton case gpr_pc: 1179a63d08c9SGreg Clayton case gpr_cpsr: 1180a63d08c9SGreg Clayton gpr.r[reg - gpr_r0] = value.GetAsUInt32(); 1181a63d08c9SGreg Clayton break; 1182a63d08c9SGreg Clayton 1183a63d08c9SGreg Clayton case fpu_s0: 1184a63d08c9SGreg Clayton case fpu_s1: 1185a63d08c9SGreg Clayton case fpu_s2: 1186a63d08c9SGreg Clayton case fpu_s3: 1187a63d08c9SGreg Clayton case fpu_s4: 1188a63d08c9SGreg Clayton case fpu_s5: 1189a63d08c9SGreg Clayton case fpu_s6: 1190a63d08c9SGreg Clayton case fpu_s7: 1191a63d08c9SGreg Clayton case fpu_s8: 1192a63d08c9SGreg Clayton case fpu_s9: 1193a63d08c9SGreg Clayton case fpu_s10: 1194a63d08c9SGreg Clayton case fpu_s11: 1195a63d08c9SGreg Clayton case fpu_s12: 1196a63d08c9SGreg Clayton case fpu_s13: 1197a63d08c9SGreg Clayton case fpu_s14: 1198a63d08c9SGreg Clayton case fpu_s15: 1199a63d08c9SGreg Clayton case fpu_s16: 1200a63d08c9SGreg Clayton case fpu_s17: 1201a63d08c9SGreg Clayton case fpu_s18: 1202a63d08c9SGreg Clayton case fpu_s19: 1203a63d08c9SGreg Clayton case fpu_s20: 1204a63d08c9SGreg Clayton case fpu_s21: 1205a63d08c9SGreg Clayton case fpu_s22: 1206a63d08c9SGreg Clayton case fpu_s23: 1207a63d08c9SGreg Clayton case fpu_s24: 1208a63d08c9SGreg Clayton case fpu_s25: 1209a63d08c9SGreg Clayton case fpu_s26: 1210a63d08c9SGreg Clayton case fpu_s27: 1211a63d08c9SGreg Clayton case fpu_s28: 1212a63d08c9SGreg Clayton case fpu_s29: 1213a63d08c9SGreg Clayton case fpu_s30: 1214a63d08c9SGreg Clayton case fpu_s31: 1215a63d08c9SGreg Clayton fpu.floats.s[reg] = value.GetAsUInt32(); 1216a63d08c9SGreg Clayton break; 1217a63d08c9SGreg Clayton 1218a63d08c9SGreg Clayton case fpu_fpscr: 1219a63d08c9SGreg Clayton fpu.fpscr = value.GetAsUInt32(); 1220a63d08c9SGreg Clayton break; 1221a63d08c9SGreg Clayton 1222a63d08c9SGreg Clayton case exc_exception: 1223a63d08c9SGreg Clayton exc.exception = value.GetAsUInt32(); 1224a63d08c9SGreg Clayton break; 1225a63d08c9SGreg Clayton case exc_fsr: 1226a63d08c9SGreg Clayton exc.fsr = value.GetAsUInt32(); 1227a63d08c9SGreg Clayton break; 1228a63d08c9SGreg Clayton case exc_far: 1229a63d08c9SGreg Clayton exc.far = value.GetAsUInt32(); 1230a63d08c9SGreg Clayton break; 1231a63d08c9SGreg Clayton 1232a63d08c9SGreg Clayton default: 1233a63d08c9SGreg Clayton return false; 1234a63d08c9SGreg Clayton } 1235a63d08c9SGreg Clayton return WriteRegisterSet(set) == KERN_SUCCESS; 1236a63d08c9SGreg Clayton } 1237a63d08c9SGreg Clayton 1238b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ReadAllRegisterValues( 1239b9c1b51eSKate Stone lldb::DataBufferSP &data_sp) { 1240796ac80bSJonas Devlieghere data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0); 1241b9c1b51eSKate Stone if (data_sp && ReadGPR(false) == KERN_SUCCESS && 1242b9c1b51eSKate Stone ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) { 1243a63d08c9SGreg Clayton uint8_t *dst = data_sp->GetBytes(); 1244a63d08c9SGreg Clayton ::memcpy(dst, &gpr, sizeof(gpr)); 1245a63d08c9SGreg Clayton dst += sizeof(gpr); 1246a63d08c9SGreg Clayton 1247a63d08c9SGreg Clayton ::memcpy(dst, &fpu, sizeof(fpu)); 1248a63d08c9SGreg Clayton dst += sizeof(gpr); 1249a63d08c9SGreg Clayton 1250a63d08c9SGreg Clayton ::memcpy(dst, &exc, sizeof(exc)); 1251a63d08c9SGreg Clayton return true; 1252a63d08c9SGreg Clayton } 1253a63d08c9SGreg Clayton return false; 1254a63d08c9SGreg Clayton } 1255a63d08c9SGreg Clayton 1256b9c1b51eSKate Stone bool RegisterContextDarwin_arm::WriteAllRegisterValues( 1257b9c1b51eSKate Stone const lldb::DataBufferSP &data_sp) { 1258b9c1b51eSKate Stone if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) { 1259a63d08c9SGreg Clayton const uint8_t *src = data_sp->GetBytes(); 1260a63d08c9SGreg Clayton ::memcpy(&gpr, src, sizeof(gpr)); 1261a63d08c9SGreg Clayton src += sizeof(gpr); 1262a63d08c9SGreg Clayton 1263a63d08c9SGreg Clayton ::memcpy(&fpu, src, sizeof(fpu)); 1264a63d08c9SGreg Clayton src += sizeof(gpr); 1265a63d08c9SGreg Clayton 1266a63d08c9SGreg Clayton ::memcpy(&exc, src, sizeof(exc)); 1267a63d08c9SGreg Clayton uint32_t success_count = 0; 1268a63d08c9SGreg Clayton if (WriteGPR() == KERN_SUCCESS) 1269a63d08c9SGreg Clayton ++success_count; 1270a63d08c9SGreg Clayton if (WriteFPU() == KERN_SUCCESS) 1271a63d08c9SGreg Clayton ++success_count; 1272a63d08c9SGreg Clayton if (WriteEXC() == KERN_SUCCESS) 1273a63d08c9SGreg Clayton ++success_count; 1274a63d08c9SGreg Clayton return success_count == 3; 1275a63d08c9SGreg Clayton } 1276a63d08c9SGreg Clayton return false; 1277a63d08c9SGreg Clayton } 1278a63d08c9SGreg Clayton 1279b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::ConvertRegisterKindToRegisterNumber( 1280b9c1b51eSKate Stone lldb::RegisterKind kind, uint32_t reg) { 1281b9c1b51eSKate Stone if (kind == eRegisterKindGeneric) { 1282b9c1b51eSKate Stone switch (reg) { 1283b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_PC: 1284b9c1b51eSKate Stone return gpr_pc; 1285b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_SP: 1286b9c1b51eSKate Stone return gpr_sp; 1287b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_FP: 1288b9c1b51eSKate Stone return gpr_r7; 1289b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_RA: 1290b9c1b51eSKate Stone return gpr_lr; 1291b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_FLAGS: 1292b9c1b51eSKate Stone return gpr_cpsr; 1293a63d08c9SGreg Clayton default: 1294a63d08c9SGreg Clayton break; 1295a63d08c9SGreg Clayton } 1296b9c1b51eSKate Stone } else if (kind == eRegisterKindDWARF) { 1297b9c1b51eSKate Stone switch (reg) { 1298b9c1b51eSKate Stone case dwarf_r0: 1299b9c1b51eSKate Stone return gpr_r0; 1300b9c1b51eSKate Stone case dwarf_r1: 1301b9c1b51eSKate Stone return gpr_r1; 1302b9c1b51eSKate Stone case dwarf_r2: 1303b9c1b51eSKate Stone return gpr_r2; 1304b9c1b51eSKate Stone case dwarf_r3: 1305b9c1b51eSKate Stone return gpr_r3; 1306b9c1b51eSKate Stone case dwarf_r4: 1307b9c1b51eSKate Stone return gpr_r4; 1308b9c1b51eSKate Stone case dwarf_r5: 1309b9c1b51eSKate Stone return gpr_r5; 1310b9c1b51eSKate Stone case dwarf_r6: 1311b9c1b51eSKate Stone return gpr_r6; 1312b9c1b51eSKate Stone case dwarf_r7: 1313b9c1b51eSKate Stone return gpr_r7; 1314b9c1b51eSKate Stone case dwarf_r8: 1315b9c1b51eSKate Stone return gpr_r8; 1316b9c1b51eSKate Stone case dwarf_r9: 1317b9c1b51eSKate Stone return gpr_r9; 1318b9c1b51eSKate Stone case dwarf_r10: 1319b9c1b51eSKate Stone return gpr_r10; 1320b9c1b51eSKate Stone case dwarf_r11: 1321b9c1b51eSKate Stone return gpr_r11; 1322b9c1b51eSKate Stone case dwarf_r12: 1323b9c1b51eSKate Stone return gpr_r12; 1324b9c1b51eSKate Stone case dwarf_sp: 1325b9c1b51eSKate Stone return gpr_sp; 1326b9c1b51eSKate Stone case dwarf_lr: 1327b9c1b51eSKate Stone return gpr_lr; 1328b9c1b51eSKate Stone case dwarf_pc: 1329b9c1b51eSKate Stone return gpr_pc; 1330b9c1b51eSKate Stone case dwarf_spsr: 1331b9c1b51eSKate Stone return gpr_cpsr; 1332a63d08c9SGreg Clayton 1333b9c1b51eSKate Stone case dwarf_s0: 1334b9c1b51eSKate Stone return fpu_s0; 1335b9c1b51eSKate Stone case dwarf_s1: 1336b9c1b51eSKate Stone return fpu_s1; 1337b9c1b51eSKate Stone case dwarf_s2: 1338b9c1b51eSKate Stone return fpu_s2; 1339b9c1b51eSKate Stone case dwarf_s3: 1340b9c1b51eSKate Stone return fpu_s3; 1341b9c1b51eSKate Stone case dwarf_s4: 1342b9c1b51eSKate Stone return fpu_s4; 1343b9c1b51eSKate Stone case dwarf_s5: 1344b9c1b51eSKate Stone return fpu_s5; 1345b9c1b51eSKate Stone case dwarf_s6: 1346b9c1b51eSKate Stone return fpu_s6; 1347b9c1b51eSKate Stone case dwarf_s7: 1348b9c1b51eSKate Stone return fpu_s7; 1349b9c1b51eSKate Stone case dwarf_s8: 1350b9c1b51eSKate Stone return fpu_s8; 1351b9c1b51eSKate Stone case dwarf_s9: 1352b9c1b51eSKate Stone return fpu_s9; 1353b9c1b51eSKate Stone case dwarf_s10: 1354b9c1b51eSKate Stone return fpu_s10; 1355b9c1b51eSKate Stone case dwarf_s11: 1356b9c1b51eSKate Stone return fpu_s11; 1357b9c1b51eSKate Stone case dwarf_s12: 1358b9c1b51eSKate Stone return fpu_s12; 1359b9c1b51eSKate Stone case dwarf_s13: 1360b9c1b51eSKate Stone return fpu_s13; 1361b9c1b51eSKate Stone case dwarf_s14: 1362b9c1b51eSKate Stone return fpu_s14; 1363b9c1b51eSKate Stone case dwarf_s15: 1364b9c1b51eSKate Stone return fpu_s15; 1365b9c1b51eSKate Stone case dwarf_s16: 1366b9c1b51eSKate Stone return fpu_s16; 1367b9c1b51eSKate Stone case dwarf_s17: 1368b9c1b51eSKate Stone return fpu_s17; 1369b9c1b51eSKate Stone case dwarf_s18: 1370b9c1b51eSKate Stone return fpu_s18; 1371b9c1b51eSKate Stone case dwarf_s19: 1372b9c1b51eSKate Stone return fpu_s19; 1373b9c1b51eSKate Stone case dwarf_s20: 1374b9c1b51eSKate Stone return fpu_s20; 1375b9c1b51eSKate Stone case dwarf_s21: 1376b9c1b51eSKate Stone return fpu_s21; 1377b9c1b51eSKate Stone case dwarf_s22: 1378b9c1b51eSKate Stone return fpu_s22; 1379b9c1b51eSKate Stone case dwarf_s23: 1380b9c1b51eSKate Stone return fpu_s23; 1381b9c1b51eSKate Stone case dwarf_s24: 1382b9c1b51eSKate Stone return fpu_s24; 1383b9c1b51eSKate Stone case dwarf_s25: 1384b9c1b51eSKate Stone return fpu_s25; 1385b9c1b51eSKate Stone case dwarf_s26: 1386b9c1b51eSKate Stone return fpu_s26; 1387b9c1b51eSKate Stone case dwarf_s27: 1388b9c1b51eSKate Stone return fpu_s27; 1389b9c1b51eSKate Stone case dwarf_s28: 1390b9c1b51eSKate Stone return fpu_s28; 1391b9c1b51eSKate Stone case dwarf_s29: 1392b9c1b51eSKate Stone return fpu_s29; 1393b9c1b51eSKate Stone case dwarf_s30: 1394b9c1b51eSKate Stone return fpu_s30; 1395b9c1b51eSKate Stone case dwarf_s31: 1396b9c1b51eSKate Stone return fpu_s31; 1397a63d08c9SGreg Clayton 1398a63d08c9SGreg Clayton default: 1399a63d08c9SGreg Clayton break; 1400a63d08c9SGreg Clayton } 1401b9c1b51eSKate Stone } else if (kind == eRegisterKindEHFrame) { 1402b9c1b51eSKate Stone switch (reg) { 1403b9c1b51eSKate Stone case ehframe_r0: 1404b9c1b51eSKate Stone return gpr_r0; 1405b9c1b51eSKate Stone case ehframe_r1: 1406b9c1b51eSKate Stone return gpr_r1; 1407b9c1b51eSKate Stone case ehframe_r2: 1408b9c1b51eSKate Stone return gpr_r2; 1409b9c1b51eSKate Stone case ehframe_r3: 1410b9c1b51eSKate Stone return gpr_r3; 1411b9c1b51eSKate Stone case ehframe_r4: 1412b9c1b51eSKate Stone return gpr_r4; 1413b9c1b51eSKate Stone case ehframe_r5: 1414b9c1b51eSKate Stone return gpr_r5; 1415b9c1b51eSKate Stone case ehframe_r6: 1416b9c1b51eSKate Stone return gpr_r6; 1417b9c1b51eSKate Stone case ehframe_r7: 1418b9c1b51eSKate Stone return gpr_r7; 1419b9c1b51eSKate Stone case ehframe_r8: 1420b9c1b51eSKate Stone return gpr_r8; 1421b9c1b51eSKate Stone case ehframe_r9: 1422b9c1b51eSKate Stone return gpr_r9; 1423b9c1b51eSKate Stone case ehframe_r10: 1424b9c1b51eSKate Stone return gpr_r10; 1425b9c1b51eSKate Stone case ehframe_r11: 1426b9c1b51eSKate Stone return gpr_r11; 1427b9c1b51eSKate Stone case ehframe_r12: 1428b9c1b51eSKate Stone return gpr_r12; 1429b9c1b51eSKate Stone case ehframe_sp: 1430b9c1b51eSKate Stone return gpr_sp; 1431b9c1b51eSKate Stone case ehframe_lr: 1432b9c1b51eSKate Stone return gpr_lr; 1433b9c1b51eSKate Stone case ehframe_pc: 1434b9c1b51eSKate Stone return gpr_pc; 1435b9c1b51eSKate Stone case ehframe_cpsr: 1436b9c1b51eSKate Stone return gpr_cpsr; 1437a63d08c9SGreg Clayton } 1438b9c1b51eSKate Stone } else if (kind == eRegisterKindLLDB) { 1439a63d08c9SGreg Clayton return reg; 1440a63d08c9SGreg Clayton } 1441a63d08c9SGreg Clayton return LLDB_INVALID_REGNUM; 1442a63d08c9SGreg Clayton } 1443a63d08c9SGreg Clayton 1444b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::NumSupportedHardwareBreakpoints() { 144590da3ce3SPavel Labath #if defined(__APPLE__) && defined(__arm__) 1446a63d08c9SGreg Clayton // Set the init value to something that will let us know that we need to 1447a63d08c9SGreg Clayton // autodetect how many breakpoints are supported dynamically... 1448a63d08c9SGreg Clayton static uint32_t g_num_supported_hw_breakpoints = UINT32_MAX; 1449b9c1b51eSKate Stone if (g_num_supported_hw_breakpoints == UINT32_MAX) { 1450a63d08c9SGreg Clayton // Set this to zero in case we can't tell if there are any HW breakpoints 1451a63d08c9SGreg Clayton g_num_supported_hw_breakpoints = 0; 1452a63d08c9SGreg Clayton 1453a63d08c9SGreg Clayton uint32_t register_DBGDIDR; 1454a63d08c9SGreg Clayton 1455a63d08c9SGreg Clayton asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 1456dce502edSGreg Clayton g_num_supported_hw_breakpoints = Bits32(register_DBGDIDR, 27, 24); 1457a63d08c9SGreg Clayton // Zero is reserved for the BRP count, so don't increment it if it is zero 1458a63d08c9SGreg Clayton if (g_num_supported_hw_breakpoints > 0) 1459a63d08c9SGreg Clayton g_num_supported_hw_breakpoints++; 1460a63d08c9SGreg Clayton } 1461a63d08c9SGreg Clayton return g_num_supported_hw_breakpoints; 1462a63d08c9SGreg Clayton #else 1463a63d08c9SGreg Clayton // TODO: figure out remote case here! 1464a63d08c9SGreg Clayton return 6; 1465a63d08c9SGreg Clayton #endif 1466a63d08c9SGreg Clayton } 1467a63d08c9SGreg Clayton 1468b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::SetHardwareBreakpoint(lldb::addr_t addr, 1469b9c1b51eSKate Stone size_t size) { 1470a63d08c9SGreg Clayton // Make sure our address isn't bogus 1471a63d08c9SGreg Clayton if (addr & 1) 1472a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1473a63d08c9SGreg Clayton 1474a63d08c9SGreg Clayton int kret = ReadDBG(false); 1475a63d08c9SGreg Clayton 1476b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1477a63d08c9SGreg Clayton const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints(); 1478a63d08c9SGreg Clayton uint32_t i; 1479b9c1b51eSKate Stone for (i = 0; i < num_hw_breakpoints; ++i) { 1480a63d08c9SGreg Clayton if ((dbg.bcr[i] & BCR_ENABLE) == 0) 1481a63d08c9SGreg Clayton break; // We found an available hw breakpoint slot (in i) 1482a63d08c9SGreg Clayton } 1483a63d08c9SGreg Clayton 1484a63d08c9SGreg Clayton // See if we found an available hw breakpoint slot above 1485b9c1b51eSKate Stone if (i < num_hw_breakpoints) { 1486a63d08c9SGreg Clayton // Make sure bits 1:0 are clear in our address 1487a63d08c9SGreg Clayton dbg.bvr[i] = addr & ~((lldb::addr_t)3); 1488a63d08c9SGreg Clayton 1489b9c1b51eSKate Stone if (size == 2 || addr & 2) { 1490a63d08c9SGreg Clayton uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1; 1491a63d08c9SGreg Clayton 1492a63d08c9SGreg Clayton // We have a thumb breakpoint 1493a63d08c9SGreg Clayton // We have an ARM breakpoint 1494a63d08c9SGreg Clayton dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch 1495b9c1b51eSKate Stone byte_addr_select | // Set the correct byte address select 1496b9c1b51eSKate Stone // so we only trigger on the correct 1497b9c1b51eSKate Stone // opcode 1498a63d08c9SGreg Clayton S_USER | // Which modes should this breakpoint stop in? 1499a63d08c9SGreg Clayton BCR_ENABLE; // Enable this hardware breakpoint 1500b9c1b51eSKate Stone // if (log) log->Printf 1501b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 1502b9c1b51eSKate Stone // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 1503b9c1b51eSKate Stone // 0x%8.8x (Thumb)", 150489f138aeSGreg Clayton // addr, 150589f138aeSGreg Clayton // size, 150689f138aeSGreg Clayton // i, 150789f138aeSGreg Clayton // i, 150889f138aeSGreg Clayton // dbg.bvr[i], 150989f138aeSGreg Clayton // dbg.bcr[i]); 1510b9c1b51eSKate Stone } else if (size == 4) { 1511a63d08c9SGreg Clayton // We have an ARM breakpoint 1512b9c1b51eSKate Stone dbg.bcr[i] = 1513b9c1b51eSKate Stone BCR_M_IMVA_MATCH | // Stop on address mismatch 1514a63d08c9SGreg Clayton BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA 1515a63d08c9SGreg Clayton S_USER | // Which modes should this breakpoint stop in? 1516a63d08c9SGreg Clayton BCR_ENABLE; // Enable this hardware breakpoint 1517b9c1b51eSKate Stone // if (log) log->Printf 1518b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 1519b9c1b51eSKate Stone // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 1520b9c1b51eSKate Stone // 0x%8.8x (ARM)", 152189f138aeSGreg Clayton // addr, 152289f138aeSGreg Clayton // size, 152389f138aeSGreg Clayton // i, 152489f138aeSGreg Clayton // i, 152589f138aeSGreg Clayton // dbg.bvr[i], 152689f138aeSGreg Clayton // dbg.bcr[i]); 1527a63d08c9SGreg Clayton } 1528a63d08c9SGreg Clayton 1529a63d08c9SGreg Clayton kret = WriteDBG(); 1530b9c1b51eSKate Stone // if (log) log->Printf 1531b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint() 1532b9c1b51eSKate Stone // WriteDBG() => 0x%8.8x.", kret); 1533a63d08c9SGreg Clayton 1534a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1535a63d08c9SGreg Clayton return i; 1536a63d08c9SGreg Clayton } 153789f138aeSGreg Clayton // else 153889f138aeSGreg Clayton // { 1539b9c1b51eSKate Stone // if (log) log->Printf 1540b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(addr = 1541b9c1b51eSKate Stone // %8.8p, size = %u) => all hardware breakpoint resources are 1542b9c1b51eSKate Stone // being used.", addr, size); 154389f138aeSGreg Clayton // } 1544a63d08c9SGreg Clayton } 1545a63d08c9SGreg Clayton 1546a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1547a63d08c9SGreg Clayton } 1548a63d08c9SGreg Clayton 1549b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ClearHardwareBreakpoint(uint32_t hw_index) { 1550a63d08c9SGreg Clayton int kret = ReadDBG(false); 1551a63d08c9SGreg Clayton 1552a63d08c9SGreg Clayton const uint32_t num_hw_points = NumSupportedHardwareBreakpoints(); 1553b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1554b9c1b51eSKate Stone if (hw_index < num_hw_points) { 1555a63d08c9SGreg Clayton dbg.bcr[hw_index] = 0; 1556b9c1b51eSKate Stone // if (log) log->Printf 1557b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::SetHardwareBreakpoint( %u ) - 1558b9c1b51eSKate Stone // BVR%u = 0x%8.8x BCR%u = 0x%8.8x", 155989f138aeSGreg Clayton // hw_index, 156089f138aeSGreg Clayton // hw_index, 156189f138aeSGreg Clayton // dbg.bvr[hw_index], 156289f138aeSGreg Clayton // hw_index, 156389f138aeSGreg Clayton // dbg.bcr[hw_index]); 1564a63d08c9SGreg Clayton 1565a63d08c9SGreg Clayton kret = WriteDBG(); 1566a63d08c9SGreg Clayton 1567a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1568a63d08c9SGreg Clayton return true; 1569a63d08c9SGreg Clayton } 1570a63d08c9SGreg Clayton } 1571a63d08c9SGreg Clayton return false; 1572a63d08c9SGreg Clayton } 1573a63d08c9SGreg Clayton 1574b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::NumSupportedHardwareWatchpoints() { 157590da3ce3SPavel Labath #if defined(__APPLE__) && defined(__arm__) 1576a63d08c9SGreg Clayton // Set the init value to something that will let us know that we need to 1577a63d08c9SGreg Clayton // autodetect how many watchpoints are supported dynamically... 1578a63d08c9SGreg Clayton static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX; 1579b9c1b51eSKate Stone if (g_num_supported_hw_watchpoints == UINT32_MAX) { 1580a63d08c9SGreg Clayton // Set this to zero in case we can't tell if there are any HW breakpoints 1581a63d08c9SGreg Clayton g_num_supported_hw_watchpoints = 0; 1582a63d08c9SGreg Clayton 1583a63d08c9SGreg Clayton uint32_t register_DBGDIDR; 1584a63d08c9SGreg Clayton asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 1585dce502edSGreg Clayton g_num_supported_hw_watchpoints = Bits32(register_DBGDIDR, 31, 28) + 1; 1586a63d08c9SGreg Clayton } 1587a63d08c9SGreg Clayton return g_num_supported_hw_watchpoints; 1588a63d08c9SGreg Clayton #else 1589a63d08c9SGreg Clayton // TODO: figure out remote case here! 1590a63d08c9SGreg Clayton return 2; 1591a63d08c9SGreg Clayton #endif 1592a63d08c9SGreg Clayton } 1593a63d08c9SGreg Clayton 1594b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::SetHardwareWatchpoint(lldb::addr_t addr, 1595b9c1b51eSKate Stone size_t size, 1596b9c1b51eSKate Stone bool read, 1597b9c1b51eSKate Stone bool write) { 1598a63d08c9SGreg Clayton const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 1599a63d08c9SGreg Clayton 1600a63d08c9SGreg Clayton // Can't watch zero bytes 1601a63d08c9SGreg Clayton if (size == 0) 1602a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1603a63d08c9SGreg Clayton 1604a63d08c9SGreg Clayton // We must watch for either read or write 1605a6682a41SJonas Devlieghere if (!read && !write) 1606a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1607a63d08c9SGreg Clayton 1608a63d08c9SGreg Clayton // Can't watch more than 4 bytes per WVR/WCR pair 1609a63d08c9SGreg Clayton if (size > 4) 1610a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1611a63d08c9SGreg Clayton 1612a63d08c9SGreg Clayton // We can only watch up to four bytes that follow a 4 byte aligned address 1613a63d08c9SGreg Clayton // per watchpoint register pair. Since we have at most so we can only watch 1614a63d08c9SGreg Clayton // until the next 4 byte boundary and we need to make sure we can properly 1615a63d08c9SGreg Clayton // encode this. 1616a63d08c9SGreg Clayton uint32_t addr_word_offset = addr % 4; 1617b9c1b51eSKate Stone // if (log) log->Printf 1618b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - 1619b9c1b51eSKate Stone // addr_word_offset = 0x%8.8x", addr_word_offset); 1620a63d08c9SGreg Clayton 1621a63d08c9SGreg Clayton uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset; 1622b9c1b51eSKate Stone // if (log) log->Printf 1623b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - byte_mask = 1624b9c1b51eSKate Stone // 0x%8.8x", byte_mask); 1625a63d08c9SGreg Clayton if (byte_mask > 0xfu) 1626a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1627a63d08c9SGreg Clayton 1628a63d08c9SGreg Clayton // Read the debug state 1629a63d08c9SGreg Clayton int kret = ReadDBG(false); 1630a63d08c9SGreg Clayton 1631b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1632a63d08c9SGreg Clayton // Check to make sure we have the needed hardware support 1633a63d08c9SGreg Clayton uint32_t i = 0; 1634a63d08c9SGreg Clayton 1635b9c1b51eSKate Stone for (i = 0; i < num_hw_watchpoints; ++i) { 1636a63d08c9SGreg Clayton if ((dbg.wcr[i] & WCR_ENABLE) == 0) 1637a63d08c9SGreg Clayton break; // We found an available hw breakpoint slot (in i) 1638a63d08c9SGreg Clayton } 1639a63d08c9SGreg Clayton 1640a63d08c9SGreg Clayton // See if we found an available hw breakpoint slot above 1641b9c1b51eSKate Stone if (i < num_hw_watchpoints) { 1642a63d08c9SGreg Clayton // Make the byte_mask into a valid Byte Address Select mask 1643a63d08c9SGreg Clayton uint32_t byte_address_select = byte_mask << 5; 1644a63d08c9SGreg Clayton // Make sure bits 1:0 are clear in our address 1645a63d08c9SGreg Clayton dbg.wvr[i] = addr & ~((lldb::addr_t)3); 1646b9c1b51eSKate Stone dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA 1647b9c1b51eSKate Stone // that we will watch 1648a63d08c9SGreg Clayton S_USER | // Stop only in user mode 1649a63d08c9SGreg Clayton (read ? WCR_LOAD : 0) | // Stop on read access? 1650a63d08c9SGreg Clayton (write ? WCR_STORE : 0) | // Stop on write access? 1651a63d08c9SGreg Clayton WCR_ENABLE; // Enable this watchpoint; 1652a63d08c9SGreg Clayton 1653a63d08c9SGreg Clayton kret = WriteDBG(); 1654b9c1b51eSKate Stone // if (log) log->Printf 1655b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() 1656b9c1b51eSKate Stone // WriteDBG() => 0x%8.8x.", kret); 1657a63d08c9SGreg Clayton 1658a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1659a63d08c9SGreg Clayton return i; 1660b9c1b51eSKate Stone } else { 1661b9c1b51eSKate Stone // if (log) log->Printf 1662b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(): All 1663b9c1b51eSKate Stone // hardware resources (%u) are in use.", num_hw_watchpoints); 1664a63d08c9SGreg Clayton } 1665a63d08c9SGreg Clayton } 1666a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1667a63d08c9SGreg Clayton } 1668a63d08c9SGreg Clayton 1669b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ClearHardwareWatchpoint(uint32_t hw_index) { 1670a63d08c9SGreg Clayton int kret = ReadDBG(false); 1671a63d08c9SGreg Clayton 1672a63d08c9SGreg Clayton const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 1673b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1674b9c1b51eSKate Stone if (hw_index < num_hw_points) { 1675a63d08c9SGreg Clayton dbg.wcr[hw_index] = 0; 1676b9c1b51eSKate Stone // if (log) log->Printf 1677b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::ClearHardwareWatchpoint( %u ) - 1678b9c1b51eSKate Stone // WVR%u = 0x%8.8x WCR%u = 0x%8.8x", 167989f138aeSGreg Clayton // hw_index, 168089f138aeSGreg Clayton // hw_index, 168189f138aeSGreg Clayton // dbg.wvr[hw_index], 168289f138aeSGreg Clayton // hw_index, 168389f138aeSGreg Clayton // dbg.wcr[hw_index]); 1684a63d08c9SGreg Clayton 1685a63d08c9SGreg Clayton kret = WriteDBG(); 1686a63d08c9SGreg Clayton 1687a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1688a63d08c9SGreg Clayton return true; 1689a63d08c9SGreg Clayton } 1690a63d08c9SGreg Clayton } 1691a63d08c9SGreg Clayton return false; 1692a63d08c9SGreg Clayton } 1693