1a63d08c9SGreg Clayton //===-- RegisterContextDarwin_arm.cpp ---------------------------*- C++ -*-===// 2a63d08c9SGreg Clayton // 3a63d08c9SGreg Clayton // The LLVM Compiler Infrastructure 4a63d08c9SGreg Clayton // 5a63d08c9SGreg Clayton // This file is distributed under the University of Illinois Open Source 6a63d08c9SGreg Clayton // License. See LICENSE.TXT for details. 7a63d08c9SGreg Clayton // 8a63d08c9SGreg Clayton //===----------------------------------------------------------------------===// 9a63d08c9SGreg Clayton 10a63d08c9SGreg Clayton #include "RegisterContextDarwin_arm.h" 11981a34c4SPavel Labath #include "RegisterContextDarwinConstants.h" 12a63d08c9SGreg Clayton 13666cc0b2SZachary Turner #include "lldb/Utility/DataBufferHeap.h" 14666cc0b2SZachary Turner #include "lldb/Utility/DataExtractor.h" 1501c3243fSZachary Turner #include "lldb/Utility/Endian.h" 166f9e6901SZachary Turner #include "lldb/Utility/Log.h" 17d821c997SPavel Labath #include "lldb/Utility/RegisterValue.h" 18d821c997SPavel Labath #include "lldb/Utility/Scalar.h" 1912a19904SDaniel Dunbar #include "llvm/Support/Compiler.h" 2012a19904SDaniel Dunbar 21dce502edSGreg Clayton #include "Plugins/Process/Utility/InstructionUtils.h" 22dce502edSGreg Clayton 2312a19904SDaniel Dunbar // Support building against older versions of LLVM, this macro was added 2412a19904SDaniel Dunbar // recently. 2512a19904SDaniel Dunbar #ifndef LLVM_EXTENSION 2612a19904SDaniel Dunbar #define LLVM_EXTENSION 2712a19904SDaniel Dunbar #endif 28a63d08c9SGreg Clayton 29ff9c4ff1SEric Liu #include "Utility/ARM_DWARF_Registers.h" 3063bd0db0SJason Molenda #include "Utility/ARM_ehframe_Registers.h" 31a63d08c9SGreg Clayton 3228606954SSaleem Abdulrasool #include "llvm/ADT/STLExtras.h" 3328606954SSaleem Abdulrasool 34a63d08c9SGreg Clayton using namespace lldb; 35a63d08c9SGreg Clayton using namespace lldb_private; 36a63d08c9SGreg Clayton 37b9c1b51eSKate Stone enum { 38a63d08c9SGreg Clayton gpr_r0 = 0, 39a63d08c9SGreg Clayton gpr_r1, 40a63d08c9SGreg Clayton gpr_r2, 41a63d08c9SGreg Clayton gpr_r3, 42a63d08c9SGreg Clayton gpr_r4, 43a63d08c9SGreg Clayton gpr_r5, 44a63d08c9SGreg Clayton gpr_r6, 45a63d08c9SGreg Clayton gpr_r7, 46a63d08c9SGreg Clayton gpr_r8, 47a63d08c9SGreg Clayton gpr_r9, 48a63d08c9SGreg Clayton gpr_r10, 49a63d08c9SGreg Clayton gpr_r11, 50a63d08c9SGreg Clayton gpr_r12, 51b9c1b51eSKate Stone gpr_r13, 52b9c1b51eSKate Stone gpr_sp = gpr_r13, 53b9c1b51eSKate Stone gpr_r14, 54b9c1b51eSKate Stone gpr_lr = gpr_r14, 55b9c1b51eSKate Stone gpr_r15, 56b9c1b51eSKate Stone gpr_pc = gpr_r15, 57a63d08c9SGreg Clayton gpr_cpsr, 58a63d08c9SGreg Clayton 59a63d08c9SGreg Clayton fpu_s0, 60a63d08c9SGreg Clayton fpu_s1, 61a63d08c9SGreg Clayton fpu_s2, 62a63d08c9SGreg Clayton fpu_s3, 63a63d08c9SGreg Clayton fpu_s4, 64a63d08c9SGreg Clayton fpu_s5, 65a63d08c9SGreg Clayton fpu_s6, 66a63d08c9SGreg Clayton fpu_s7, 67a63d08c9SGreg Clayton fpu_s8, 68a63d08c9SGreg Clayton fpu_s9, 69a63d08c9SGreg Clayton fpu_s10, 70a63d08c9SGreg Clayton fpu_s11, 71a63d08c9SGreg Clayton fpu_s12, 72a63d08c9SGreg Clayton fpu_s13, 73a63d08c9SGreg Clayton fpu_s14, 74a63d08c9SGreg Clayton fpu_s15, 75a63d08c9SGreg Clayton fpu_s16, 76a63d08c9SGreg Clayton fpu_s17, 77a63d08c9SGreg Clayton fpu_s18, 78a63d08c9SGreg Clayton fpu_s19, 79a63d08c9SGreg Clayton fpu_s20, 80a63d08c9SGreg Clayton fpu_s21, 81a63d08c9SGreg Clayton fpu_s22, 82a63d08c9SGreg Clayton fpu_s23, 83a63d08c9SGreg Clayton fpu_s24, 84a63d08c9SGreg Clayton fpu_s25, 85a63d08c9SGreg Clayton fpu_s26, 86a63d08c9SGreg Clayton fpu_s27, 87a63d08c9SGreg Clayton fpu_s28, 88a63d08c9SGreg Clayton fpu_s29, 89a63d08c9SGreg Clayton fpu_s30, 90a63d08c9SGreg Clayton fpu_s31, 91a63d08c9SGreg Clayton fpu_fpscr, 92a63d08c9SGreg Clayton 93a63d08c9SGreg Clayton exc_exception, 94a63d08c9SGreg Clayton exc_fsr, 95a63d08c9SGreg Clayton exc_far, 96a63d08c9SGreg Clayton 97a63d08c9SGreg Clayton dbg_bvr0, 98a63d08c9SGreg Clayton dbg_bvr1, 99a63d08c9SGreg Clayton dbg_bvr2, 100a63d08c9SGreg Clayton dbg_bvr3, 101a63d08c9SGreg Clayton dbg_bvr4, 102a63d08c9SGreg Clayton dbg_bvr5, 103a63d08c9SGreg Clayton dbg_bvr6, 104a63d08c9SGreg Clayton dbg_bvr7, 105a63d08c9SGreg Clayton dbg_bvr8, 106a63d08c9SGreg Clayton dbg_bvr9, 107a63d08c9SGreg Clayton dbg_bvr10, 108a63d08c9SGreg Clayton dbg_bvr11, 109a63d08c9SGreg Clayton dbg_bvr12, 110a63d08c9SGreg Clayton dbg_bvr13, 111a63d08c9SGreg Clayton dbg_bvr14, 112a63d08c9SGreg Clayton dbg_bvr15, 113a63d08c9SGreg Clayton 114a63d08c9SGreg Clayton dbg_bcr0, 115a63d08c9SGreg Clayton dbg_bcr1, 116a63d08c9SGreg Clayton dbg_bcr2, 117a63d08c9SGreg Clayton dbg_bcr3, 118a63d08c9SGreg Clayton dbg_bcr4, 119a63d08c9SGreg Clayton dbg_bcr5, 120a63d08c9SGreg Clayton dbg_bcr6, 121a63d08c9SGreg Clayton dbg_bcr7, 122a63d08c9SGreg Clayton dbg_bcr8, 123a63d08c9SGreg Clayton dbg_bcr9, 124a63d08c9SGreg Clayton dbg_bcr10, 125a63d08c9SGreg Clayton dbg_bcr11, 126a63d08c9SGreg Clayton dbg_bcr12, 127a63d08c9SGreg Clayton dbg_bcr13, 128a63d08c9SGreg Clayton dbg_bcr14, 129a63d08c9SGreg Clayton dbg_bcr15, 130a63d08c9SGreg Clayton 131a63d08c9SGreg Clayton dbg_wvr0, 132a63d08c9SGreg Clayton dbg_wvr1, 133a63d08c9SGreg Clayton dbg_wvr2, 134a63d08c9SGreg Clayton dbg_wvr3, 135a63d08c9SGreg Clayton dbg_wvr4, 136a63d08c9SGreg Clayton dbg_wvr5, 137a63d08c9SGreg Clayton dbg_wvr6, 138a63d08c9SGreg Clayton dbg_wvr7, 139a63d08c9SGreg Clayton dbg_wvr8, 140a63d08c9SGreg Clayton dbg_wvr9, 141a63d08c9SGreg Clayton dbg_wvr10, 142a63d08c9SGreg Clayton dbg_wvr11, 143a63d08c9SGreg Clayton dbg_wvr12, 144a63d08c9SGreg Clayton dbg_wvr13, 145a63d08c9SGreg Clayton dbg_wvr14, 146a63d08c9SGreg Clayton dbg_wvr15, 147a63d08c9SGreg Clayton 148a63d08c9SGreg Clayton dbg_wcr0, 149a63d08c9SGreg Clayton dbg_wcr1, 150a63d08c9SGreg Clayton dbg_wcr2, 151a63d08c9SGreg Clayton dbg_wcr3, 152a63d08c9SGreg Clayton dbg_wcr4, 153a63d08c9SGreg Clayton dbg_wcr5, 154a63d08c9SGreg Clayton dbg_wcr6, 155a63d08c9SGreg Clayton dbg_wcr7, 156a63d08c9SGreg Clayton dbg_wcr8, 157a63d08c9SGreg Clayton dbg_wcr9, 158a63d08c9SGreg Clayton dbg_wcr10, 159a63d08c9SGreg Clayton dbg_wcr11, 160a63d08c9SGreg Clayton dbg_wcr12, 161a63d08c9SGreg Clayton dbg_wcr13, 162a63d08c9SGreg Clayton dbg_wcr14, 163a63d08c9SGreg Clayton dbg_wcr15, 164a63d08c9SGreg Clayton 165a63d08c9SGreg Clayton k_num_registers 166a63d08c9SGreg Clayton }; 167a63d08c9SGreg Clayton 168a63d08c9SGreg Clayton #define GPR_OFFSET(idx) ((idx)*4) 169a63d08c9SGreg Clayton #define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR)) 170b9c1b51eSKate Stone #define EXC_OFFSET(idx) \ 171b9c1b51eSKate Stone ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR) + \ 172b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU)) 173b9c1b51eSKate Stone #define DBG_OFFSET(reg) \ 174b9c1b51eSKate Stone ((LLVM_EXTENSION offsetof(RegisterContextDarwin_arm::DBG, reg) + \ 175b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::GPR) + \ 176b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU) + \ 177b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::EXC))) 178a63d08c9SGreg Clayton 179b9c1b51eSKate Stone #define DEFINE_DBG(reg, i) \ 180b9c1b51eSKate Stone #reg, NULL, sizeof(((RegisterContextDarwin_arm::DBG *) NULL)->reg[i]), \ 181b9c1b51eSKate Stone DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, \ 182b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 183b9c1b51eSKate Stone LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 184b9c1b51eSKate Stone LLDB_INVALID_REGNUM }, \ 185b9c1b51eSKate Stone nullptr, nullptr, nullptr, 0 186b9c1b51eSKate Stone #define REG_CONTEXT_SIZE \ 187b9c1b51eSKate Stone (sizeof(RegisterContextDarwin_arm::GPR) + \ 188b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU) + \ 189b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::EXC)) 190a63d08c9SGreg Clayton 191a63d08c9SGreg Clayton static RegisterInfo g_register_infos[] = { 192a63d08c9SGreg Clayton // General purpose registers 193b9c1b51eSKate Stone // NAME ALT SZ OFFSET ENCODING FORMAT 194b9c1b51eSKate Stone // EH_FRAME DWARF GENERIC 195b9c1b51eSKate Stone // PROCESS PLUGIN LLDB NATIVE 196b9c1b51eSKate Stone // ====== ======= == ============= ============= ============ 197b9c1b51eSKate Stone // =============== =============== ========================= 198b9c1b51eSKate Stone // ===================== ============= 199b9c1b51eSKate Stone {"r0", 200b9c1b51eSKate Stone NULL, 201b9c1b51eSKate Stone 4, 202b9c1b51eSKate Stone GPR_OFFSET(0), 203b9c1b51eSKate Stone eEncodingUint, 204b9c1b51eSKate Stone eFormatHex, 205b9c1b51eSKate Stone {ehframe_r0, dwarf_r0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r0}, 206b9c1b51eSKate Stone nullptr, 207b9c1b51eSKate Stone nullptr, 208b9c1b51eSKate Stone nullptr, 209b9c1b51eSKate Stone 0}, 210b9c1b51eSKate Stone {"r1", 211b9c1b51eSKate Stone NULL, 212b9c1b51eSKate Stone 4, 213b9c1b51eSKate Stone GPR_OFFSET(1), 214b9c1b51eSKate Stone eEncodingUint, 215b9c1b51eSKate Stone eFormatHex, 216b9c1b51eSKate Stone {ehframe_r1, dwarf_r1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r1}, 217b9c1b51eSKate Stone nullptr, 218b9c1b51eSKate Stone nullptr, 219b9c1b51eSKate Stone nullptr, 220b9c1b51eSKate Stone 0}, 221b9c1b51eSKate Stone {"r2", 222b9c1b51eSKate Stone NULL, 223b9c1b51eSKate Stone 4, 224b9c1b51eSKate Stone GPR_OFFSET(2), 225b9c1b51eSKate Stone eEncodingUint, 226b9c1b51eSKate Stone eFormatHex, 227b9c1b51eSKate Stone {ehframe_r2, dwarf_r2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r2}, 228b9c1b51eSKate Stone nullptr, 229b9c1b51eSKate Stone nullptr, 230b9c1b51eSKate Stone nullptr, 231b9c1b51eSKate Stone 0}, 232b9c1b51eSKate Stone {"r3", 233b9c1b51eSKate Stone NULL, 234b9c1b51eSKate Stone 4, 235b9c1b51eSKate Stone GPR_OFFSET(3), 236b9c1b51eSKate Stone eEncodingUint, 237b9c1b51eSKate Stone eFormatHex, 238b9c1b51eSKate Stone {ehframe_r3, dwarf_r3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r3}, 239b9c1b51eSKate Stone nullptr, 240b9c1b51eSKate Stone nullptr, 241b9c1b51eSKate Stone nullptr, 242b9c1b51eSKate Stone 0}, 243b9c1b51eSKate Stone {"r4", 244b9c1b51eSKate Stone NULL, 245b9c1b51eSKate Stone 4, 246b9c1b51eSKate Stone GPR_OFFSET(4), 247b9c1b51eSKate Stone eEncodingUint, 248b9c1b51eSKate Stone eFormatHex, 249b9c1b51eSKate Stone {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4}, 250b9c1b51eSKate Stone nullptr, 251b9c1b51eSKate Stone nullptr, 252b9c1b51eSKate Stone nullptr, 253b9c1b51eSKate Stone 0}, 254b9c1b51eSKate Stone {"r5", 255b9c1b51eSKate Stone NULL, 256b9c1b51eSKate Stone 4, 257b9c1b51eSKate Stone GPR_OFFSET(5), 258b9c1b51eSKate Stone eEncodingUint, 259b9c1b51eSKate Stone eFormatHex, 260b9c1b51eSKate Stone {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5}, 261b9c1b51eSKate Stone nullptr, 262b9c1b51eSKate Stone nullptr, 263b9c1b51eSKate Stone nullptr, 264b9c1b51eSKate Stone 0}, 265b9c1b51eSKate Stone {"r6", 266b9c1b51eSKate Stone NULL, 267b9c1b51eSKate Stone 4, 268b9c1b51eSKate Stone GPR_OFFSET(6), 269b9c1b51eSKate Stone eEncodingUint, 270b9c1b51eSKate Stone eFormatHex, 271b9c1b51eSKate Stone {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6}, 272b9c1b51eSKate Stone nullptr, 273b9c1b51eSKate Stone nullptr, 274b9c1b51eSKate Stone nullptr, 275b9c1b51eSKate Stone 0}, 276b9c1b51eSKate Stone {"r7", 277b9c1b51eSKate Stone NULL, 278b9c1b51eSKate Stone 4, 279b9c1b51eSKate Stone GPR_OFFSET(7), 280b9c1b51eSKate Stone eEncodingUint, 281b9c1b51eSKate Stone eFormatHex, 282b9c1b51eSKate Stone {ehframe_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, 283b9c1b51eSKate Stone gpr_r7}, 284b9c1b51eSKate Stone nullptr, 285b9c1b51eSKate Stone nullptr, 286b9c1b51eSKate Stone nullptr, 287b9c1b51eSKate Stone 0}, 288b9c1b51eSKate Stone {"r8", 289b9c1b51eSKate Stone NULL, 290b9c1b51eSKate Stone 4, 291b9c1b51eSKate Stone GPR_OFFSET(8), 292b9c1b51eSKate Stone eEncodingUint, 293b9c1b51eSKate Stone eFormatHex, 294b9c1b51eSKate Stone {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8}, 295b9c1b51eSKate Stone nullptr, 296b9c1b51eSKate Stone nullptr, 297b9c1b51eSKate Stone nullptr, 298b9c1b51eSKate Stone 0}, 299b9c1b51eSKate Stone {"r9", 300b9c1b51eSKate Stone NULL, 301b9c1b51eSKate Stone 4, 302b9c1b51eSKate Stone GPR_OFFSET(9), 303b9c1b51eSKate Stone eEncodingUint, 304b9c1b51eSKate Stone eFormatHex, 305b9c1b51eSKate Stone {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9}, 306b9c1b51eSKate Stone nullptr, 307b9c1b51eSKate Stone nullptr, 308b9c1b51eSKate Stone nullptr, 309b9c1b51eSKate Stone 0}, 310b9c1b51eSKate Stone {"r10", 311b9c1b51eSKate Stone NULL, 312b9c1b51eSKate Stone 4, 313b9c1b51eSKate Stone GPR_OFFSET(10), 314b9c1b51eSKate Stone eEncodingUint, 315b9c1b51eSKate Stone eFormatHex, 316b9c1b51eSKate Stone {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 317b9c1b51eSKate Stone gpr_r10}, 318b9c1b51eSKate Stone nullptr, 319b9c1b51eSKate Stone nullptr, 320b9c1b51eSKate Stone nullptr, 321b9c1b51eSKate Stone 0}, 322b9c1b51eSKate Stone {"r11", 323b9c1b51eSKate Stone NULL, 324b9c1b51eSKate Stone 4, 325b9c1b51eSKate Stone GPR_OFFSET(11), 326b9c1b51eSKate Stone eEncodingUint, 327b9c1b51eSKate Stone eFormatHex, 328b9c1b51eSKate Stone {ehframe_r11, dwarf_r11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 329b9c1b51eSKate Stone gpr_r11}, 330b9c1b51eSKate Stone nullptr, 331b9c1b51eSKate Stone nullptr, 332b9c1b51eSKate Stone nullptr, 333b9c1b51eSKate Stone 0}, 334b9c1b51eSKate Stone {"r12", 335b9c1b51eSKate Stone NULL, 336b9c1b51eSKate Stone 4, 337b9c1b51eSKate Stone GPR_OFFSET(12), 338b9c1b51eSKate Stone eEncodingUint, 339b9c1b51eSKate Stone eFormatHex, 340b9c1b51eSKate Stone {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 341b9c1b51eSKate Stone gpr_r12}, 342b9c1b51eSKate Stone nullptr, 343b9c1b51eSKate Stone nullptr, 344b9c1b51eSKate Stone nullptr, 345b9c1b51eSKate Stone 0}, 346b9c1b51eSKate Stone {"sp", 347b9c1b51eSKate Stone "r13", 348b9c1b51eSKate Stone 4, 349b9c1b51eSKate Stone GPR_OFFSET(13), 350b9c1b51eSKate Stone eEncodingUint, 351b9c1b51eSKate Stone eFormatHex, 352b9c1b51eSKate Stone {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, 353b9c1b51eSKate Stone gpr_sp}, 354b9c1b51eSKate Stone nullptr, 355b9c1b51eSKate Stone nullptr, 356b9c1b51eSKate Stone nullptr, 357b9c1b51eSKate Stone 0}, 358b9c1b51eSKate Stone {"lr", 359b9c1b51eSKate Stone "r14", 360b9c1b51eSKate Stone 4, 361b9c1b51eSKate Stone GPR_OFFSET(14), 362b9c1b51eSKate Stone eEncodingUint, 363b9c1b51eSKate Stone eFormatHex, 364b9c1b51eSKate Stone {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, 365b9c1b51eSKate Stone gpr_lr}, 366b9c1b51eSKate Stone nullptr, 367b9c1b51eSKate Stone nullptr, 368b9c1b51eSKate Stone nullptr, 369b9c1b51eSKate Stone 0}, 370b9c1b51eSKate Stone {"pc", 371b9c1b51eSKate Stone "r15", 372b9c1b51eSKate Stone 4, 373b9c1b51eSKate Stone GPR_OFFSET(15), 374b9c1b51eSKate Stone eEncodingUint, 375b9c1b51eSKate Stone eFormatHex, 376b9c1b51eSKate Stone {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, 377b9c1b51eSKate Stone gpr_pc}, 378b9c1b51eSKate Stone nullptr, 379b9c1b51eSKate Stone nullptr, 380b9c1b51eSKate Stone nullptr, 381b9c1b51eSKate Stone 0}, 382b9c1b51eSKate Stone {"cpsr", 383b9c1b51eSKate Stone "psr", 384b9c1b51eSKate Stone 4, 385b9c1b51eSKate Stone GPR_OFFSET(16), 386b9c1b51eSKate Stone eEncodingUint, 387b9c1b51eSKate Stone eFormatHex, 388b9c1b51eSKate Stone {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM, 389b9c1b51eSKate Stone gpr_cpsr}, 390b9c1b51eSKate Stone nullptr, 391b9c1b51eSKate Stone nullptr, 392b9c1b51eSKate Stone nullptr, 393b9c1b51eSKate Stone 0}, 394a63d08c9SGreg Clayton 395b9c1b51eSKate Stone {"s0", 396b9c1b51eSKate Stone NULL, 397b9c1b51eSKate Stone 4, 398b9c1b51eSKate Stone FPU_OFFSET(0), 399b9c1b51eSKate Stone eEncodingIEEE754, 400b9c1b51eSKate Stone eFormatFloat, 401b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 402b9c1b51eSKate Stone fpu_s0}, 403b9c1b51eSKate Stone nullptr, 404b9c1b51eSKate Stone nullptr, 405b9c1b51eSKate Stone nullptr, 406b9c1b51eSKate Stone 0}, 407b9c1b51eSKate Stone {"s1", 408b9c1b51eSKate Stone NULL, 409b9c1b51eSKate Stone 4, 410b9c1b51eSKate Stone FPU_OFFSET(1), 411b9c1b51eSKate Stone eEncodingIEEE754, 412b9c1b51eSKate Stone eFormatFloat, 413b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 414b9c1b51eSKate Stone fpu_s1}, 415b9c1b51eSKate Stone nullptr, 416b9c1b51eSKate Stone nullptr, 417b9c1b51eSKate Stone nullptr, 418b9c1b51eSKate Stone 0}, 419b9c1b51eSKate Stone {"s2", 420b9c1b51eSKate Stone NULL, 421b9c1b51eSKate Stone 4, 422b9c1b51eSKate Stone FPU_OFFSET(2), 423b9c1b51eSKate Stone eEncodingIEEE754, 424b9c1b51eSKate Stone eFormatFloat, 425b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 426b9c1b51eSKate Stone fpu_s2}, 427b9c1b51eSKate Stone nullptr, 428b9c1b51eSKate Stone nullptr, 429b9c1b51eSKate Stone nullptr, 430b9c1b51eSKate Stone 0}, 431b9c1b51eSKate Stone {"s3", 432b9c1b51eSKate Stone NULL, 433b9c1b51eSKate Stone 4, 434b9c1b51eSKate Stone FPU_OFFSET(3), 435b9c1b51eSKate Stone eEncodingIEEE754, 436b9c1b51eSKate Stone eFormatFloat, 437b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 438b9c1b51eSKate Stone fpu_s3}, 439b9c1b51eSKate Stone nullptr, 440b9c1b51eSKate Stone nullptr, 441b9c1b51eSKate Stone nullptr, 442b9c1b51eSKate Stone 0}, 443b9c1b51eSKate Stone {"s4", 444b9c1b51eSKate Stone NULL, 445b9c1b51eSKate Stone 4, 446b9c1b51eSKate Stone FPU_OFFSET(4), 447b9c1b51eSKate Stone eEncodingIEEE754, 448b9c1b51eSKate Stone eFormatFloat, 449b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 450b9c1b51eSKate Stone fpu_s4}, 451b9c1b51eSKate Stone nullptr, 452b9c1b51eSKate Stone nullptr, 453b9c1b51eSKate Stone nullptr, 454b9c1b51eSKate Stone 0}, 455b9c1b51eSKate Stone {"s5", 456b9c1b51eSKate Stone NULL, 457b9c1b51eSKate Stone 4, 458b9c1b51eSKate Stone FPU_OFFSET(5), 459b9c1b51eSKate Stone eEncodingIEEE754, 460b9c1b51eSKate Stone eFormatFloat, 461b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 462b9c1b51eSKate Stone fpu_s5}, 463b9c1b51eSKate Stone nullptr, 464b9c1b51eSKate Stone nullptr, 465b9c1b51eSKate Stone nullptr, 466b9c1b51eSKate Stone 0}, 467b9c1b51eSKate Stone {"s6", 468b9c1b51eSKate Stone NULL, 469b9c1b51eSKate Stone 4, 470b9c1b51eSKate Stone FPU_OFFSET(6), 471b9c1b51eSKate Stone eEncodingIEEE754, 472b9c1b51eSKate Stone eFormatFloat, 473b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 474b9c1b51eSKate Stone fpu_s6}, 475b9c1b51eSKate Stone nullptr, 476b9c1b51eSKate Stone nullptr, 477b9c1b51eSKate Stone nullptr, 478b9c1b51eSKate Stone 0}, 479b9c1b51eSKate Stone {"s7", 480b9c1b51eSKate Stone NULL, 481b9c1b51eSKate Stone 4, 482b9c1b51eSKate Stone FPU_OFFSET(7), 483b9c1b51eSKate Stone eEncodingIEEE754, 484b9c1b51eSKate Stone eFormatFloat, 485b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 486b9c1b51eSKate Stone fpu_s7}, 487b9c1b51eSKate Stone nullptr, 488b9c1b51eSKate Stone nullptr, 489b9c1b51eSKate Stone nullptr, 490b9c1b51eSKate Stone 0}, 491b9c1b51eSKate Stone {"s8", 492b9c1b51eSKate Stone NULL, 493b9c1b51eSKate Stone 4, 494b9c1b51eSKate Stone FPU_OFFSET(8), 495b9c1b51eSKate Stone eEncodingIEEE754, 496b9c1b51eSKate Stone eFormatFloat, 497b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 498b9c1b51eSKate Stone fpu_s8}, 499b9c1b51eSKate Stone nullptr, 500b9c1b51eSKate Stone nullptr, 501b9c1b51eSKate Stone nullptr, 502b9c1b51eSKate Stone 0}, 503b9c1b51eSKate Stone {"s9", 504b9c1b51eSKate Stone NULL, 505b9c1b51eSKate Stone 4, 506b9c1b51eSKate Stone FPU_OFFSET(9), 507b9c1b51eSKate Stone eEncodingIEEE754, 508b9c1b51eSKate Stone eFormatFloat, 509b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 510b9c1b51eSKate Stone fpu_s9}, 511b9c1b51eSKate Stone nullptr, 512b9c1b51eSKate Stone nullptr, 513b9c1b51eSKate Stone nullptr, 514b9c1b51eSKate Stone 0}, 515b9c1b51eSKate Stone {"s10", 516b9c1b51eSKate Stone NULL, 517b9c1b51eSKate Stone 4, 518b9c1b51eSKate Stone FPU_OFFSET(10), 519b9c1b51eSKate Stone eEncodingIEEE754, 520b9c1b51eSKate Stone eFormatFloat, 521b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 522b9c1b51eSKate Stone fpu_s10}, 523b9c1b51eSKate Stone nullptr, 524b9c1b51eSKate Stone nullptr, 525b9c1b51eSKate Stone nullptr, 526b9c1b51eSKate Stone 0}, 527b9c1b51eSKate Stone {"s11", 528b9c1b51eSKate Stone NULL, 529b9c1b51eSKate Stone 4, 530b9c1b51eSKate Stone FPU_OFFSET(11), 531b9c1b51eSKate Stone eEncodingIEEE754, 532b9c1b51eSKate Stone eFormatFloat, 533b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 534b9c1b51eSKate Stone fpu_s11}, 535b9c1b51eSKate Stone nullptr, 536b9c1b51eSKate Stone nullptr, 537b9c1b51eSKate Stone nullptr, 538b9c1b51eSKate Stone 0}, 539b9c1b51eSKate Stone {"s12", 540b9c1b51eSKate Stone NULL, 541b9c1b51eSKate Stone 4, 542b9c1b51eSKate Stone FPU_OFFSET(12), 543b9c1b51eSKate Stone eEncodingIEEE754, 544b9c1b51eSKate Stone eFormatFloat, 545b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 546b9c1b51eSKate Stone fpu_s12}, 547b9c1b51eSKate Stone nullptr, 548b9c1b51eSKate Stone nullptr, 549b9c1b51eSKate Stone nullptr, 550b9c1b51eSKate Stone 0}, 551b9c1b51eSKate Stone {"s13", 552b9c1b51eSKate Stone NULL, 553b9c1b51eSKate Stone 4, 554b9c1b51eSKate Stone FPU_OFFSET(13), 555b9c1b51eSKate Stone eEncodingIEEE754, 556b9c1b51eSKate Stone eFormatFloat, 557b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 558b9c1b51eSKate Stone fpu_s13}, 559b9c1b51eSKate Stone nullptr, 560b9c1b51eSKate Stone nullptr, 561b9c1b51eSKate Stone nullptr, 562b9c1b51eSKate Stone 0}, 563b9c1b51eSKate Stone {"s14", 564b9c1b51eSKate Stone NULL, 565b9c1b51eSKate Stone 4, 566b9c1b51eSKate Stone FPU_OFFSET(14), 567b9c1b51eSKate Stone eEncodingIEEE754, 568b9c1b51eSKate Stone eFormatFloat, 569b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 570b9c1b51eSKate Stone fpu_s14}, 571b9c1b51eSKate Stone nullptr, 572b9c1b51eSKate Stone nullptr, 573b9c1b51eSKate Stone nullptr, 574b9c1b51eSKate Stone 0}, 575b9c1b51eSKate Stone {"s15", 576b9c1b51eSKate Stone NULL, 577b9c1b51eSKate Stone 4, 578b9c1b51eSKate Stone FPU_OFFSET(15), 579b9c1b51eSKate Stone eEncodingIEEE754, 580b9c1b51eSKate Stone eFormatFloat, 581b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 582b9c1b51eSKate Stone fpu_s15}, 583b9c1b51eSKate Stone nullptr, 584b9c1b51eSKate Stone nullptr, 585b9c1b51eSKate Stone nullptr, 586b9c1b51eSKate Stone 0}, 587b9c1b51eSKate Stone {"s16", 588b9c1b51eSKate Stone NULL, 589b9c1b51eSKate Stone 4, 590b9c1b51eSKate Stone FPU_OFFSET(16), 591b9c1b51eSKate Stone eEncodingIEEE754, 592b9c1b51eSKate Stone eFormatFloat, 593b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 594b9c1b51eSKate Stone fpu_s16}, 595b9c1b51eSKate Stone nullptr, 596b9c1b51eSKate Stone nullptr, 597b9c1b51eSKate Stone nullptr, 598b9c1b51eSKate Stone 0}, 599b9c1b51eSKate Stone {"s17", 600b9c1b51eSKate Stone NULL, 601b9c1b51eSKate Stone 4, 602b9c1b51eSKate Stone FPU_OFFSET(17), 603b9c1b51eSKate Stone eEncodingIEEE754, 604b9c1b51eSKate Stone eFormatFloat, 605b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 606b9c1b51eSKate Stone fpu_s17}, 607b9c1b51eSKate Stone nullptr, 608b9c1b51eSKate Stone nullptr, 609b9c1b51eSKate Stone nullptr, 610b9c1b51eSKate Stone 0}, 611b9c1b51eSKate Stone {"s18", 612b9c1b51eSKate Stone NULL, 613b9c1b51eSKate Stone 4, 614b9c1b51eSKate Stone FPU_OFFSET(18), 615b9c1b51eSKate Stone eEncodingIEEE754, 616b9c1b51eSKate Stone eFormatFloat, 617b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 618b9c1b51eSKate Stone fpu_s18}, 619b9c1b51eSKate Stone nullptr, 620b9c1b51eSKate Stone nullptr, 621b9c1b51eSKate Stone nullptr, 622b9c1b51eSKate Stone 0}, 623b9c1b51eSKate Stone {"s19", 624b9c1b51eSKate Stone NULL, 625b9c1b51eSKate Stone 4, 626b9c1b51eSKate Stone FPU_OFFSET(19), 627b9c1b51eSKate Stone eEncodingIEEE754, 628b9c1b51eSKate Stone eFormatFloat, 629b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 630b9c1b51eSKate Stone fpu_s19}, 631b9c1b51eSKate Stone nullptr, 632b9c1b51eSKate Stone nullptr, 633b9c1b51eSKate Stone nullptr, 634b9c1b51eSKate Stone 0}, 635b9c1b51eSKate Stone {"s20", 636b9c1b51eSKate Stone NULL, 637b9c1b51eSKate Stone 4, 638b9c1b51eSKate Stone FPU_OFFSET(20), 639b9c1b51eSKate Stone eEncodingIEEE754, 640b9c1b51eSKate Stone eFormatFloat, 641b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 642b9c1b51eSKate Stone fpu_s20}, 643b9c1b51eSKate Stone nullptr, 644b9c1b51eSKate Stone nullptr, 645b9c1b51eSKate Stone nullptr, 646b9c1b51eSKate Stone 0}, 647b9c1b51eSKate Stone {"s21", 648b9c1b51eSKate Stone NULL, 649b9c1b51eSKate Stone 4, 650b9c1b51eSKate Stone FPU_OFFSET(21), 651b9c1b51eSKate Stone eEncodingIEEE754, 652b9c1b51eSKate Stone eFormatFloat, 653b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 654b9c1b51eSKate Stone fpu_s21}, 655b9c1b51eSKate Stone nullptr, 656b9c1b51eSKate Stone nullptr, 657b9c1b51eSKate Stone nullptr, 658b9c1b51eSKate Stone 0}, 659b9c1b51eSKate Stone {"s22", 660b9c1b51eSKate Stone NULL, 661b9c1b51eSKate Stone 4, 662b9c1b51eSKate Stone FPU_OFFSET(22), 663b9c1b51eSKate Stone eEncodingIEEE754, 664b9c1b51eSKate Stone eFormatFloat, 665b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 666b9c1b51eSKate Stone fpu_s22}, 667b9c1b51eSKate Stone nullptr, 668b9c1b51eSKate Stone nullptr, 669b9c1b51eSKate Stone nullptr, 670b9c1b51eSKate Stone 0}, 671b9c1b51eSKate Stone {"s23", 672b9c1b51eSKate Stone NULL, 673b9c1b51eSKate Stone 4, 674b9c1b51eSKate Stone FPU_OFFSET(23), 675b9c1b51eSKate Stone eEncodingIEEE754, 676b9c1b51eSKate Stone eFormatFloat, 677b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 678b9c1b51eSKate Stone fpu_s23}, 679b9c1b51eSKate Stone nullptr, 680b9c1b51eSKate Stone nullptr, 681b9c1b51eSKate Stone nullptr, 682b9c1b51eSKate Stone 0}, 683b9c1b51eSKate Stone {"s24", 684b9c1b51eSKate Stone NULL, 685b9c1b51eSKate Stone 4, 686b9c1b51eSKate Stone FPU_OFFSET(24), 687b9c1b51eSKate Stone eEncodingIEEE754, 688b9c1b51eSKate Stone eFormatFloat, 689b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 690b9c1b51eSKate Stone fpu_s24}, 691b9c1b51eSKate Stone nullptr, 692b9c1b51eSKate Stone nullptr, 693b9c1b51eSKate Stone nullptr, 694b9c1b51eSKate Stone 0}, 695b9c1b51eSKate Stone {"s25", 696b9c1b51eSKate Stone NULL, 697b9c1b51eSKate Stone 4, 698b9c1b51eSKate Stone FPU_OFFSET(25), 699b9c1b51eSKate Stone eEncodingIEEE754, 700b9c1b51eSKate Stone eFormatFloat, 701b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 702b9c1b51eSKate Stone fpu_s25}, 703b9c1b51eSKate Stone nullptr, 704b9c1b51eSKate Stone nullptr, 705b9c1b51eSKate Stone nullptr, 706b9c1b51eSKate Stone 0}, 707b9c1b51eSKate Stone {"s26", 708b9c1b51eSKate Stone NULL, 709b9c1b51eSKate Stone 4, 710b9c1b51eSKate Stone FPU_OFFSET(26), 711b9c1b51eSKate Stone eEncodingIEEE754, 712b9c1b51eSKate Stone eFormatFloat, 713b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 714b9c1b51eSKate Stone fpu_s26}, 715b9c1b51eSKate Stone nullptr, 716b9c1b51eSKate Stone nullptr, 717b9c1b51eSKate Stone nullptr, 718b9c1b51eSKate Stone 0}, 719b9c1b51eSKate Stone {"s27", 720b9c1b51eSKate Stone NULL, 721b9c1b51eSKate Stone 4, 722b9c1b51eSKate Stone FPU_OFFSET(27), 723b9c1b51eSKate Stone eEncodingIEEE754, 724b9c1b51eSKate Stone eFormatFloat, 725b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 726b9c1b51eSKate Stone fpu_s27}, 727b9c1b51eSKate Stone nullptr, 728b9c1b51eSKate Stone nullptr, 729b9c1b51eSKate Stone nullptr, 730b9c1b51eSKate Stone 0}, 731b9c1b51eSKate Stone {"s28", 732b9c1b51eSKate Stone NULL, 733b9c1b51eSKate Stone 4, 734b9c1b51eSKate Stone FPU_OFFSET(28), 735b9c1b51eSKate Stone eEncodingIEEE754, 736b9c1b51eSKate Stone eFormatFloat, 737b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 738b9c1b51eSKate Stone fpu_s28}, 739b9c1b51eSKate Stone nullptr, 740b9c1b51eSKate Stone nullptr, 741b9c1b51eSKate Stone nullptr, 742b9c1b51eSKate Stone 0}, 743b9c1b51eSKate Stone {"s29", 744b9c1b51eSKate Stone NULL, 745b9c1b51eSKate Stone 4, 746b9c1b51eSKate Stone FPU_OFFSET(29), 747b9c1b51eSKate Stone eEncodingIEEE754, 748b9c1b51eSKate Stone eFormatFloat, 749b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 750b9c1b51eSKate Stone fpu_s29}, 751b9c1b51eSKate Stone nullptr, 752b9c1b51eSKate Stone nullptr, 753b9c1b51eSKate Stone nullptr, 754b9c1b51eSKate Stone 0}, 755b9c1b51eSKate Stone {"s30", 756b9c1b51eSKate Stone NULL, 757b9c1b51eSKate Stone 4, 758b9c1b51eSKate Stone FPU_OFFSET(30), 759b9c1b51eSKate Stone eEncodingIEEE754, 760b9c1b51eSKate Stone eFormatFloat, 761b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 762b9c1b51eSKate Stone fpu_s30}, 763b9c1b51eSKate Stone nullptr, 764b9c1b51eSKate Stone nullptr, 765b9c1b51eSKate Stone nullptr, 766b9c1b51eSKate Stone 0}, 767b9c1b51eSKate Stone {"s31", 768b9c1b51eSKate Stone NULL, 769b9c1b51eSKate Stone 4, 770b9c1b51eSKate Stone FPU_OFFSET(31), 771b9c1b51eSKate Stone eEncodingIEEE754, 772b9c1b51eSKate Stone eFormatFloat, 773b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 774b9c1b51eSKate Stone fpu_s31}, 775b9c1b51eSKate Stone nullptr, 776b9c1b51eSKate Stone nullptr, 777b9c1b51eSKate Stone nullptr, 778b9c1b51eSKate Stone 0}, 779b9c1b51eSKate Stone {"fpscr", 780b9c1b51eSKate Stone NULL, 781b9c1b51eSKate Stone 4, 782b9c1b51eSKate Stone FPU_OFFSET(32), 783b9c1b51eSKate Stone eEncodingUint, 784b9c1b51eSKate Stone eFormatHex, 785b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 786b9c1b51eSKate Stone LLDB_INVALID_REGNUM, fpu_fpscr}, 787b9c1b51eSKate Stone nullptr, 788b9c1b51eSKate Stone nullptr, 789b9c1b51eSKate Stone nullptr, 790b9c1b51eSKate Stone 0}, 791a63d08c9SGreg Clayton 792b9c1b51eSKate Stone {"exception", 793b9c1b51eSKate Stone NULL, 794b9c1b51eSKate Stone 4, 795b9c1b51eSKate Stone EXC_OFFSET(0), 796b9c1b51eSKate Stone eEncodingUint, 797b9c1b51eSKate Stone eFormatHex, 798b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 799b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_exception}, 800b9c1b51eSKate Stone nullptr, 801b9c1b51eSKate Stone nullptr, 802b9c1b51eSKate Stone nullptr, 803b9c1b51eSKate Stone 0}, 804b9c1b51eSKate Stone {"fsr", 805b9c1b51eSKate Stone NULL, 806b9c1b51eSKate Stone 4, 807b9c1b51eSKate Stone EXC_OFFSET(1), 808b9c1b51eSKate Stone eEncodingUint, 809b9c1b51eSKate Stone eFormatHex, 810b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 811b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_fsr}, 812b9c1b51eSKate Stone nullptr, 813b9c1b51eSKate Stone nullptr, 814b9c1b51eSKate Stone nullptr, 815b9c1b51eSKate Stone 0}, 816b9c1b51eSKate Stone {"far", 817b9c1b51eSKate Stone NULL, 818b9c1b51eSKate Stone 4, 819b9c1b51eSKate Stone EXC_OFFSET(2), 820b9c1b51eSKate Stone eEncodingUint, 821b9c1b51eSKate Stone eFormatHex, 822b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 823b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_far}, 824b9c1b51eSKate Stone nullptr, 825b9c1b51eSKate Stone nullptr, 826b9c1b51eSKate Stone nullptr, 827b9c1b51eSKate Stone 0}, 828a63d08c9SGreg Clayton 829a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 0)}, 830a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 1)}, 831a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 2)}, 832a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 3)}, 833a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 4)}, 834a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 5)}, 835a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 6)}, 836a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 7)}, 837a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 8)}, 838a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 9)}, 839a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 10)}, 840a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 11)}, 841a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 12)}, 842a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 13)}, 843a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 14)}, 844a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 15)}, 845a63d08c9SGreg Clayton 846a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 0)}, 847a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 1)}, 848a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 2)}, 849a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 3)}, 850a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 4)}, 851a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 5)}, 852a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 6)}, 853a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 7)}, 854a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 8)}, 855a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 9)}, 856a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 10)}, 857a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 11)}, 858a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 12)}, 859a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 13)}, 860a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 14)}, 861a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 15)}, 862a63d08c9SGreg Clayton 863a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 0)}, 864a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 1)}, 865a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 2)}, 866a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 3)}, 867a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 4)}, 868a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 5)}, 869a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 6)}, 870a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 7)}, 871a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 8)}, 872a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 9)}, 873a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 10)}, 874a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 11)}, 875a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 12)}, 876a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 13)}, 877a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 14)}, 878a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 15)}, 879a63d08c9SGreg Clayton 880a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 0)}, 881a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 1)}, 882a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 2)}, 883a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 3)}, 884a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 4)}, 885a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 5)}, 886a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 6)}, 887a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 7)}, 888a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 8)}, 889a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 9)}, 890a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 10)}, 891a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 11)}, 892a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 12)}, 893a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 13)}, 894a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 14)}, 895b9c1b51eSKate Stone {DEFINE_DBG(wcr, 15)}}; 896a63d08c9SGreg Clayton 897a63d08c9SGreg Clayton // General purpose registers 898b9c1b51eSKate Stone static uint32_t g_gpr_regnums[] = { 899b9c1b51eSKate Stone gpr_r0, gpr_r1, gpr_r2, gpr_r3, gpr_r4, gpr_r5, gpr_r6, gpr_r7, gpr_r8, 900b9c1b51eSKate Stone gpr_r9, gpr_r10, gpr_r11, gpr_r12, gpr_sp, gpr_lr, gpr_pc, gpr_cpsr}; 901a63d08c9SGreg Clayton 902a63d08c9SGreg Clayton // Floating point registers 903b9c1b51eSKate Stone static uint32_t g_fpu_regnums[] = { 904b9c1b51eSKate Stone fpu_s0, fpu_s1, fpu_s2, fpu_s3, fpu_s4, fpu_s5, fpu_s6, 905b9c1b51eSKate Stone fpu_s7, fpu_s8, fpu_s9, fpu_s10, fpu_s11, fpu_s12, fpu_s13, 906b9c1b51eSKate Stone fpu_s14, fpu_s15, fpu_s16, fpu_s17, fpu_s18, fpu_s19, fpu_s20, 907b9c1b51eSKate Stone fpu_s21, fpu_s22, fpu_s23, fpu_s24, fpu_s25, fpu_s26, fpu_s27, 908b9c1b51eSKate Stone fpu_s28, fpu_s29, fpu_s30, fpu_s31, fpu_fpscr, 909a63d08c9SGreg Clayton }; 910a63d08c9SGreg Clayton 911a63d08c9SGreg Clayton // Exception registers 912a63d08c9SGreg Clayton 913b9c1b51eSKate Stone static uint32_t g_exc_regnums[] = { 914b9c1b51eSKate Stone exc_exception, exc_fsr, exc_far, 915a63d08c9SGreg Clayton }; 916a63d08c9SGreg Clayton 91728606954SSaleem Abdulrasool static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos); 918a63d08c9SGreg Clayton 919b9c1b51eSKate Stone RegisterContextDarwin_arm::RegisterContextDarwin_arm( 920b9c1b51eSKate Stone Thread &thread, uint32_t concrete_frame_idx) 921b9c1b51eSKate Stone : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() { 92263bd0db0SJason Molenda uint32_t i; 923b9c1b51eSKate Stone for (i = 0; i < kNumErrors; i++) { 92463bd0db0SJason Molenda gpr_errs[i] = -1; 92563bd0db0SJason Molenda fpu_errs[i] = -1; 92663bd0db0SJason Molenda exc_errs[i] = -1; 92763bd0db0SJason Molenda } 92863bd0db0SJason Molenda } 92963bd0db0SJason Molenda 930b9c1b51eSKate Stone RegisterContextDarwin_arm::~RegisterContextDarwin_arm() {} 93163bd0db0SJason Molenda 932b9c1b51eSKate Stone void RegisterContextDarwin_arm::InvalidateAllRegisters() { 933a63d08c9SGreg Clayton InvalidateAllRegisterStates(); 934a63d08c9SGreg Clayton } 935a63d08c9SGreg Clayton 936b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterCount() { 937a63d08c9SGreg Clayton assert(k_num_register_infos == k_num_registers); 938a63d08c9SGreg Clayton return k_num_registers; 939a63d08c9SGreg Clayton } 940a63d08c9SGreg Clayton 941a63d08c9SGreg Clayton const RegisterInfo * 942b9c1b51eSKate Stone RegisterContextDarwin_arm::GetRegisterInfoAtIndex(size_t reg) { 943a63d08c9SGreg Clayton assert(k_num_register_infos == k_num_registers); 944a63d08c9SGreg Clayton if (reg < k_num_registers) 945a63d08c9SGreg Clayton return &g_register_infos[reg]; 946a63d08c9SGreg Clayton return NULL; 947a63d08c9SGreg Clayton } 948a63d08c9SGreg Clayton 949b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterInfosCount() { 950a63d08c9SGreg Clayton return k_num_register_infos; 951a63d08c9SGreg Clayton } 952a63d08c9SGreg Clayton 953b9c1b51eSKate Stone const RegisterInfo *RegisterContextDarwin_arm::GetRegisterInfos() { 954a63d08c9SGreg Clayton return g_register_infos; 955a63d08c9SGreg Clayton } 956a63d08c9SGreg Clayton 957a63d08c9SGreg Clayton // Number of registers in each register set 95828606954SSaleem Abdulrasool const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums); 95928606954SSaleem Abdulrasool const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums); 96028606954SSaleem Abdulrasool const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums); 961a63d08c9SGreg Clayton 962a63d08c9SGreg Clayton //---------------------------------------------------------------------- 96305097246SAdrian Prantl // Register set definitions. The first definitions at register set index of 96405097246SAdrian Prantl // zero is for all registers, followed by other registers sets. The register 96505097246SAdrian Prantl // information for the all register set need not be filled in. 966a63d08c9SGreg Clayton //---------------------------------------------------------------------- 967b9c1b51eSKate Stone static const RegisterSet g_reg_sets[] = { 968a63d08c9SGreg Clayton { 969b9c1b51eSKate Stone "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, 970b9c1b51eSKate Stone }, 971a63d08c9SGreg Clayton {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums}, 972b9c1b51eSKate Stone {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}}; 973a63d08c9SGreg Clayton 97428606954SSaleem Abdulrasool const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets); 975a63d08c9SGreg Clayton 976b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterSetCount() { 977a63d08c9SGreg Clayton return k_num_regsets; 978a63d08c9SGreg Clayton } 979a63d08c9SGreg Clayton 980b9c1b51eSKate Stone const RegisterSet *RegisterContextDarwin_arm::GetRegisterSet(size_t reg_set) { 981a63d08c9SGreg Clayton if (reg_set < k_num_regsets) 982a63d08c9SGreg Clayton return &g_reg_sets[reg_set]; 983a63d08c9SGreg Clayton return NULL; 984a63d08c9SGreg Clayton } 985a63d08c9SGreg Clayton 986a63d08c9SGreg Clayton //---------------------------------------------------------------------- 987aaa0ba31SBruce Mitchener // Register information definitions for 32 bit i386. 988a63d08c9SGreg Clayton //---------------------------------------------------------------------- 989b9c1b51eSKate Stone int RegisterContextDarwin_arm::GetSetForNativeRegNum(int reg) { 990a63d08c9SGreg Clayton if (reg < fpu_s0) 991a63d08c9SGreg Clayton return GPRRegSet; 992a63d08c9SGreg Clayton else if (reg < exc_exception) 993a63d08c9SGreg Clayton return FPURegSet; 994a63d08c9SGreg Clayton else if (reg < k_num_registers) 995a63d08c9SGreg Clayton return EXCRegSet; 996a63d08c9SGreg Clayton return -1; 997a63d08c9SGreg Clayton } 998a63d08c9SGreg Clayton 999b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadGPR(bool force) { 1000a63d08c9SGreg Clayton int set = GPRRegSet; 1001b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1002a63d08c9SGreg Clayton SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr)); 1003a63d08c9SGreg Clayton } 1004a63d08c9SGreg Clayton return GetError(GPRRegSet, Read); 1005a63d08c9SGreg Clayton } 1006a63d08c9SGreg Clayton 1007b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadFPU(bool force) { 1008a63d08c9SGreg Clayton int set = FPURegSet; 1009b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1010a63d08c9SGreg Clayton SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu)); 1011a63d08c9SGreg Clayton } 1012a63d08c9SGreg Clayton return GetError(FPURegSet, Read); 1013a63d08c9SGreg Clayton } 1014a63d08c9SGreg Clayton 1015b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadEXC(bool force) { 1016a63d08c9SGreg Clayton int set = EXCRegSet; 1017b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1018a63d08c9SGreg Clayton SetError(set, Read, DoReadEXC(GetThreadID(), set, exc)); 1019a63d08c9SGreg Clayton } 1020a63d08c9SGreg Clayton return GetError(EXCRegSet, Read); 1021a63d08c9SGreg Clayton } 1022a63d08c9SGreg Clayton 1023b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadDBG(bool force) { 1024a63d08c9SGreg Clayton int set = DBGRegSet; 1025b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1026a63d08c9SGreg Clayton SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg)); 1027a63d08c9SGreg Clayton } 1028a63d08c9SGreg Clayton return GetError(DBGRegSet, Read); 1029a63d08c9SGreg Clayton } 1030a63d08c9SGreg Clayton 1031b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteGPR() { 1032a63d08c9SGreg Clayton int set = GPRRegSet; 1033b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1034a63d08c9SGreg Clayton SetError(set, Write, -1); 1035a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1036a63d08c9SGreg Clayton } 1037a63d08c9SGreg Clayton SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr)); 1038a63d08c9SGreg Clayton SetError(set, Read, -1); 1039a63d08c9SGreg Clayton return GetError(GPRRegSet, Write); 1040a63d08c9SGreg Clayton } 1041a63d08c9SGreg Clayton 1042b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteFPU() { 1043a63d08c9SGreg Clayton int set = FPURegSet; 1044b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1045a63d08c9SGreg Clayton SetError(set, Write, -1); 1046a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1047a63d08c9SGreg Clayton } 1048a63d08c9SGreg Clayton SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu)); 1049a63d08c9SGreg Clayton SetError(set, Read, -1); 1050a63d08c9SGreg Clayton return GetError(FPURegSet, Write); 1051a63d08c9SGreg Clayton } 1052a63d08c9SGreg Clayton 1053b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteEXC() { 1054a63d08c9SGreg Clayton int set = EXCRegSet; 1055b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1056a63d08c9SGreg Clayton SetError(set, Write, -1); 1057a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1058a63d08c9SGreg Clayton } 1059a63d08c9SGreg Clayton SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc)); 1060a63d08c9SGreg Clayton SetError(set, Read, -1); 1061a63d08c9SGreg Clayton return GetError(EXCRegSet, Write); 1062a63d08c9SGreg Clayton } 1063a63d08c9SGreg Clayton 1064b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteDBG() { 1065a63d08c9SGreg Clayton int set = DBGRegSet; 1066b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1067a63d08c9SGreg Clayton SetError(set, Write, -1); 1068a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1069a63d08c9SGreg Clayton } 1070a63d08c9SGreg Clayton SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg)); 1071a63d08c9SGreg Clayton SetError(set, Read, -1); 1072a63d08c9SGreg Clayton return GetError(DBGRegSet, Write); 1073a63d08c9SGreg Clayton } 1074a63d08c9SGreg Clayton 1075b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadRegisterSet(uint32_t set, bool force) { 1076b9c1b51eSKate Stone switch (set) { 1077b9c1b51eSKate Stone case GPRRegSet: 1078b9c1b51eSKate Stone return ReadGPR(force); 1079b9c1b51eSKate Stone case GPRAltRegSet: 1080b9c1b51eSKate Stone return ReadGPR(force); 1081b9c1b51eSKate Stone case FPURegSet: 1082b9c1b51eSKate Stone return ReadFPU(force); 1083b9c1b51eSKate Stone case EXCRegSet: 1084b9c1b51eSKate Stone return ReadEXC(force); 1085b9c1b51eSKate Stone case DBGRegSet: 1086b9c1b51eSKate Stone return ReadDBG(force); 1087b9c1b51eSKate Stone default: 1088b9c1b51eSKate Stone break; 1089a63d08c9SGreg Clayton } 1090a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1091a63d08c9SGreg Clayton } 1092a63d08c9SGreg Clayton 1093b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteRegisterSet(uint32_t set) { 1094a63d08c9SGreg Clayton // Make sure we have a valid context to set. 1095b9c1b51eSKate Stone if (RegisterSetIsCached(set)) { 1096b9c1b51eSKate Stone switch (set) { 1097b9c1b51eSKate Stone case GPRRegSet: 1098b9c1b51eSKate Stone return WriteGPR(); 1099b9c1b51eSKate Stone case GPRAltRegSet: 1100b9c1b51eSKate Stone return WriteGPR(); 1101b9c1b51eSKate Stone case FPURegSet: 1102b9c1b51eSKate Stone return WriteFPU(); 1103b9c1b51eSKate Stone case EXCRegSet: 1104b9c1b51eSKate Stone return WriteEXC(); 1105b9c1b51eSKate Stone case DBGRegSet: 1106b9c1b51eSKate Stone return WriteDBG(); 1107b9c1b51eSKate Stone default: 1108b9c1b51eSKate Stone break; 1109a63d08c9SGreg Clayton } 1110a63d08c9SGreg Clayton } 1111a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1112a63d08c9SGreg Clayton } 1113a63d08c9SGreg Clayton 1114b9c1b51eSKate Stone void RegisterContextDarwin_arm::LogDBGRegisters(Log *log, const DBG &dbg) { 1115b9c1b51eSKate Stone if (log) { 1116a63d08c9SGreg Clayton for (uint32_t i = 0; i < 16; i++) 1117b9c1b51eSKate Stone log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { " 1118b9c1b51eSKate Stone "0x%8.8x, 0x%8.8x }", 1119b9c1b51eSKate Stone i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]); 1120a63d08c9SGreg Clayton } 1121a63d08c9SGreg Clayton } 1122a63d08c9SGreg Clayton 1123b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ReadRegister(const RegisterInfo *reg_info, 1124b9c1b51eSKate Stone RegisterValue &value) { 1125a63d08c9SGreg Clayton const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 1126a63d08c9SGreg Clayton int set = RegisterContextDarwin_arm::GetSetForNativeRegNum(reg); 1127a63d08c9SGreg Clayton 1128a63d08c9SGreg Clayton if (set == -1) 1129a63d08c9SGreg Clayton return false; 1130a63d08c9SGreg Clayton 1131a63d08c9SGreg Clayton if (ReadRegisterSet(set, false) != KERN_SUCCESS) 1132a63d08c9SGreg Clayton return false; 1133a63d08c9SGreg Clayton 1134b9c1b51eSKate Stone switch (reg) { 1135a63d08c9SGreg Clayton case gpr_r0: 1136a63d08c9SGreg Clayton case gpr_r1: 1137a63d08c9SGreg Clayton case gpr_r2: 1138a63d08c9SGreg Clayton case gpr_r3: 1139a63d08c9SGreg Clayton case gpr_r4: 1140a63d08c9SGreg Clayton case gpr_r5: 1141a63d08c9SGreg Clayton case gpr_r6: 1142a63d08c9SGreg Clayton case gpr_r7: 1143a63d08c9SGreg Clayton case gpr_r8: 1144a63d08c9SGreg Clayton case gpr_r9: 1145a63d08c9SGreg Clayton case gpr_r10: 1146a63d08c9SGreg Clayton case gpr_r11: 1147a63d08c9SGreg Clayton case gpr_r12: 1148a63d08c9SGreg Clayton case gpr_sp: 1149a63d08c9SGreg Clayton case gpr_lr: 1150a63d08c9SGreg Clayton case gpr_pc: 1151a63d08c9SGreg Clayton case gpr_cpsr: 1152a63d08c9SGreg Clayton value.SetUInt32(gpr.r[reg - gpr_r0]); 1153a63d08c9SGreg Clayton break; 1154a63d08c9SGreg Clayton 1155a63d08c9SGreg Clayton case fpu_s0: 1156a63d08c9SGreg Clayton case fpu_s1: 1157a63d08c9SGreg Clayton case fpu_s2: 1158a63d08c9SGreg Clayton case fpu_s3: 1159a63d08c9SGreg Clayton case fpu_s4: 1160a63d08c9SGreg Clayton case fpu_s5: 1161a63d08c9SGreg Clayton case fpu_s6: 1162a63d08c9SGreg Clayton case fpu_s7: 1163a63d08c9SGreg Clayton case fpu_s8: 1164a63d08c9SGreg Clayton case fpu_s9: 1165a63d08c9SGreg Clayton case fpu_s10: 1166a63d08c9SGreg Clayton case fpu_s11: 1167a63d08c9SGreg Clayton case fpu_s12: 1168a63d08c9SGreg Clayton case fpu_s13: 1169a63d08c9SGreg Clayton case fpu_s14: 1170a63d08c9SGreg Clayton case fpu_s15: 1171a63d08c9SGreg Clayton case fpu_s16: 1172a63d08c9SGreg Clayton case fpu_s17: 1173a63d08c9SGreg Clayton case fpu_s18: 1174a63d08c9SGreg Clayton case fpu_s19: 1175a63d08c9SGreg Clayton case fpu_s20: 1176a63d08c9SGreg Clayton case fpu_s21: 1177a63d08c9SGreg Clayton case fpu_s22: 1178a63d08c9SGreg Clayton case fpu_s23: 1179a63d08c9SGreg Clayton case fpu_s24: 1180a63d08c9SGreg Clayton case fpu_s25: 1181a63d08c9SGreg Clayton case fpu_s26: 1182a63d08c9SGreg Clayton case fpu_s27: 1183a63d08c9SGreg Clayton case fpu_s28: 1184a63d08c9SGreg Clayton case fpu_s29: 1185a63d08c9SGreg Clayton case fpu_s30: 1186a63d08c9SGreg Clayton case fpu_s31: 1187a63d08c9SGreg Clayton value.SetUInt32(fpu.floats.s[reg], RegisterValue::eTypeFloat); 1188a63d08c9SGreg Clayton break; 1189a63d08c9SGreg Clayton 1190a63d08c9SGreg Clayton case fpu_fpscr: 1191a63d08c9SGreg Clayton value.SetUInt32(fpu.fpscr); 1192a63d08c9SGreg Clayton break; 1193a63d08c9SGreg Clayton 1194a63d08c9SGreg Clayton case exc_exception: 1195a63d08c9SGreg Clayton value.SetUInt32(exc.exception); 1196a63d08c9SGreg Clayton break; 1197a63d08c9SGreg Clayton case exc_fsr: 1198a63d08c9SGreg Clayton value.SetUInt32(exc.fsr); 1199a63d08c9SGreg Clayton break; 1200a63d08c9SGreg Clayton case exc_far: 1201a63d08c9SGreg Clayton value.SetUInt32(exc.far); 1202a63d08c9SGreg Clayton break; 1203a63d08c9SGreg Clayton 1204a63d08c9SGreg Clayton default: 1205a63d08c9SGreg Clayton value.SetValueToInvalid(); 1206a63d08c9SGreg Clayton return false; 1207a63d08c9SGreg Clayton } 1208a63d08c9SGreg Clayton return true; 1209a63d08c9SGreg Clayton } 1210a63d08c9SGreg Clayton 1211b9c1b51eSKate Stone bool RegisterContextDarwin_arm::WriteRegister(const RegisterInfo *reg_info, 1212b9c1b51eSKate Stone const RegisterValue &value) { 1213a63d08c9SGreg Clayton const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 1214a63d08c9SGreg Clayton int set = GetSetForNativeRegNum(reg); 1215a63d08c9SGreg Clayton 1216a63d08c9SGreg Clayton if (set == -1) 1217a63d08c9SGreg Clayton return false; 1218a63d08c9SGreg Clayton 1219a63d08c9SGreg Clayton if (ReadRegisterSet(set, false) != KERN_SUCCESS) 1220a63d08c9SGreg Clayton return false; 1221a63d08c9SGreg Clayton 1222b9c1b51eSKate Stone switch (reg) { 1223a63d08c9SGreg Clayton case gpr_r0: 1224a63d08c9SGreg Clayton case gpr_r1: 1225a63d08c9SGreg Clayton case gpr_r2: 1226a63d08c9SGreg Clayton case gpr_r3: 1227a63d08c9SGreg Clayton case gpr_r4: 1228a63d08c9SGreg Clayton case gpr_r5: 1229a63d08c9SGreg Clayton case gpr_r6: 1230a63d08c9SGreg Clayton case gpr_r7: 1231a63d08c9SGreg Clayton case gpr_r8: 1232a63d08c9SGreg Clayton case gpr_r9: 1233a63d08c9SGreg Clayton case gpr_r10: 1234a63d08c9SGreg Clayton case gpr_r11: 1235a63d08c9SGreg Clayton case gpr_r12: 1236a63d08c9SGreg Clayton case gpr_sp: 1237a63d08c9SGreg Clayton case gpr_lr: 1238a63d08c9SGreg Clayton case gpr_pc: 1239a63d08c9SGreg Clayton case gpr_cpsr: 1240a63d08c9SGreg Clayton gpr.r[reg - gpr_r0] = value.GetAsUInt32(); 1241a63d08c9SGreg Clayton break; 1242a63d08c9SGreg Clayton 1243a63d08c9SGreg Clayton case fpu_s0: 1244a63d08c9SGreg Clayton case fpu_s1: 1245a63d08c9SGreg Clayton case fpu_s2: 1246a63d08c9SGreg Clayton case fpu_s3: 1247a63d08c9SGreg Clayton case fpu_s4: 1248a63d08c9SGreg Clayton case fpu_s5: 1249a63d08c9SGreg Clayton case fpu_s6: 1250a63d08c9SGreg Clayton case fpu_s7: 1251a63d08c9SGreg Clayton case fpu_s8: 1252a63d08c9SGreg Clayton case fpu_s9: 1253a63d08c9SGreg Clayton case fpu_s10: 1254a63d08c9SGreg Clayton case fpu_s11: 1255a63d08c9SGreg Clayton case fpu_s12: 1256a63d08c9SGreg Clayton case fpu_s13: 1257a63d08c9SGreg Clayton case fpu_s14: 1258a63d08c9SGreg Clayton case fpu_s15: 1259a63d08c9SGreg Clayton case fpu_s16: 1260a63d08c9SGreg Clayton case fpu_s17: 1261a63d08c9SGreg Clayton case fpu_s18: 1262a63d08c9SGreg Clayton case fpu_s19: 1263a63d08c9SGreg Clayton case fpu_s20: 1264a63d08c9SGreg Clayton case fpu_s21: 1265a63d08c9SGreg Clayton case fpu_s22: 1266a63d08c9SGreg Clayton case fpu_s23: 1267a63d08c9SGreg Clayton case fpu_s24: 1268a63d08c9SGreg Clayton case fpu_s25: 1269a63d08c9SGreg Clayton case fpu_s26: 1270a63d08c9SGreg Clayton case fpu_s27: 1271a63d08c9SGreg Clayton case fpu_s28: 1272a63d08c9SGreg Clayton case fpu_s29: 1273a63d08c9SGreg Clayton case fpu_s30: 1274a63d08c9SGreg Clayton case fpu_s31: 1275a63d08c9SGreg Clayton fpu.floats.s[reg] = value.GetAsUInt32(); 1276a63d08c9SGreg Clayton break; 1277a63d08c9SGreg Clayton 1278a63d08c9SGreg Clayton case fpu_fpscr: 1279a63d08c9SGreg Clayton fpu.fpscr = value.GetAsUInt32(); 1280a63d08c9SGreg Clayton break; 1281a63d08c9SGreg Clayton 1282a63d08c9SGreg Clayton case exc_exception: 1283a63d08c9SGreg Clayton exc.exception = value.GetAsUInt32(); 1284a63d08c9SGreg Clayton break; 1285a63d08c9SGreg Clayton case exc_fsr: 1286a63d08c9SGreg Clayton exc.fsr = value.GetAsUInt32(); 1287a63d08c9SGreg Clayton break; 1288a63d08c9SGreg Clayton case exc_far: 1289a63d08c9SGreg Clayton exc.far = value.GetAsUInt32(); 1290a63d08c9SGreg Clayton break; 1291a63d08c9SGreg Clayton 1292a63d08c9SGreg Clayton default: 1293a63d08c9SGreg Clayton return false; 1294a63d08c9SGreg Clayton } 1295a63d08c9SGreg Clayton return WriteRegisterSet(set) == KERN_SUCCESS; 1296a63d08c9SGreg Clayton } 1297a63d08c9SGreg Clayton 1298b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ReadAllRegisterValues( 1299b9c1b51eSKate Stone lldb::DataBufferSP &data_sp) { 1300a63d08c9SGreg Clayton data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0)); 1301b9c1b51eSKate Stone if (data_sp && ReadGPR(false) == KERN_SUCCESS && 1302b9c1b51eSKate Stone ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) { 1303a63d08c9SGreg Clayton uint8_t *dst = data_sp->GetBytes(); 1304a63d08c9SGreg Clayton ::memcpy(dst, &gpr, sizeof(gpr)); 1305a63d08c9SGreg Clayton dst += sizeof(gpr); 1306a63d08c9SGreg Clayton 1307a63d08c9SGreg Clayton ::memcpy(dst, &fpu, sizeof(fpu)); 1308a63d08c9SGreg Clayton dst += sizeof(gpr); 1309a63d08c9SGreg Clayton 1310a63d08c9SGreg Clayton ::memcpy(dst, &exc, sizeof(exc)); 1311a63d08c9SGreg Clayton return true; 1312a63d08c9SGreg Clayton } 1313a63d08c9SGreg Clayton return false; 1314a63d08c9SGreg Clayton } 1315a63d08c9SGreg Clayton 1316b9c1b51eSKate Stone bool RegisterContextDarwin_arm::WriteAllRegisterValues( 1317b9c1b51eSKate Stone const lldb::DataBufferSP &data_sp) { 1318b9c1b51eSKate Stone if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) { 1319a63d08c9SGreg Clayton const uint8_t *src = data_sp->GetBytes(); 1320a63d08c9SGreg Clayton ::memcpy(&gpr, src, sizeof(gpr)); 1321a63d08c9SGreg Clayton src += sizeof(gpr); 1322a63d08c9SGreg Clayton 1323a63d08c9SGreg Clayton ::memcpy(&fpu, src, sizeof(fpu)); 1324a63d08c9SGreg Clayton src += sizeof(gpr); 1325a63d08c9SGreg Clayton 1326a63d08c9SGreg Clayton ::memcpy(&exc, src, sizeof(exc)); 1327a63d08c9SGreg Clayton uint32_t success_count = 0; 1328a63d08c9SGreg Clayton if (WriteGPR() == KERN_SUCCESS) 1329a63d08c9SGreg Clayton ++success_count; 1330a63d08c9SGreg Clayton if (WriteFPU() == KERN_SUCCESS) 1331a63d08c9SGreg Clayton ++success_count; 1332a63d08c9SGreg Clayton if (WriteEXC() == KERN_SUCCESS) 1333a63d08c9SGreg Clayton ++success_count; 1334a63d08c9SGreg Clayton return success_count == 3; 1335a63d08c9SGreg Clayton } 1336a63d08c9SGreg Clayton return false; 1337a63d08c9SGreg Clayton } 1338a63d08c9SGreg Clayton 1339b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::ConvertRegisterKindToRegisterNumber( 1340b9c1b51eSKate Stone lldb::RegisterKind kind, uint32_t reg) { 1341b9c1b51eSKate Stone if (kind == eRegisterKindGeneric) { 1342b9c1b51eSKate Stone switch (reg) { 1343b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_PC: 1344b9c1b51eSKate Stone return gpr_pc; 1345b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_SP: 1346b9c1b51eSKate Stone return gpr_sp; 1347b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_FP: 1348b9c1b51eSKate Stone return gpr_r7; 1349b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_RA: 1350b9c1b51eSKate Stone return gpr_lr; 1351b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_FLAGS: 1352b9c1b51eSKate Stone return gpr_cpsr; 1353a63d08c9SGreg Clayton default: 1354a63d08c9SGreg Clayton break; 1355a63d08c9SGreg Clayton } 1356b9c1b51eSKate Stone } else if (kind == eRegisterKindDWARF) { 1357b9c1b51eSKate Stone switch (reg) { 1358b9c1b51eSKate Stone case dwarf_r0: 1359b9c1b51eSKate Stone return gpr_r0; 1360b9c1b51eSKate Stone case dwarf_r1: 1361b9c1b51eSKate Stone return gpr_r1; 1362b9c1b51eSKate Stone case dwarf_r2: 1363b9c1b51eSKate Stone return gpr_r2; 1364b9c1b51eSKate Stone case dwarf_r3: 1365b9c1b51eSKate Stone return gpr_r3; 1366b9c1b51eSKate Stone case dwarf_r4: 1367b9c1b51eSKate Stone return gpr_r4; 1368b9c1b51eSKate Stone case dwarf_r5: 1369b9c1b51eSKate Stone return gpr_r5; 1370b9c1b51eSKate Stone case dwarf_r6: 1371b9c1b51eSKate Stone return gpr_r6; 1372b9c1b51eSKate Stone case dwarf_r7: 1373b9c1b51eSKate Stone return gpr_r7; 1374b9c1b51eSKate Stone case dwarf_r8: 1375b9c1b51eSKate Stone return gpr_r8; 1376b9c1b51eSKate Stone case dwarf_r9: 1377b9c1b51eSKate Stone return gpr_r9; 1378b9c1b51eSKate Stone case dwarf_r10: 1379b9c1b51eSKate Stone return gpr_r10; 1380b9c1b51eSKate Stone case dwarf_r11: 1381b9c1b51eSKate Stone return gpr_r11; 1382b9c1b51eSKate Stone case dwarf_r12: 1383b9c1b51eSKate Stone return gpr_r12; 1384b9c1b51eSKate Stone case dwarf_sp: 1385b9c1b51eSKate Stone return gpr_sp; 1386b9c1b51eSKate Stone case dwarf_lr: 1387b9c1b51eSKate Stone return gpr_lr; 1388b9c1b51eSKate Stone case dwarf_pc: 1389b9c1b51eSKate Stone return gpr_pc; 1390b9c1b51eSKate Stone case dwarf_spsr: 1391b9c1b51eSKate Stone return gpr_cpsr; 1392a63d08c9SGreg Clayton 1393b9c1b51eSKate Stone case dwarf_s0: 1394b9c1b51eSKate Stone return fpu_s0; 1395b9c1b51eSKate Stone case dwarf_s1: 1396b9c1b51eSKate Stone return fpu_s1; 1397b9c1b51eSKate Stone case dwarf_s2: 1398b9c1b51eSKate Stone return fpu_s2; 1399b9c1b51eSKate Stone case dwarf_s3: 1400b9c1b51eSKate Stone return fpu_s3; 1401b9c1b51eSKate Stone case dwarf_s4: 1402b9c1b51eSKate Stone return fpu_s4; 1403b9c1b51eSKate Stone case dwarf_s5: 1404b9c1b51eSKate Stone return fpu_s5; 1405b9c1b51eSKate Stone case dwarf_s6: 1406b9c1b51eSKate Stone return fpu_s6; 1407b9c1b51eSKate Stone case dwarf_s7: 1408b9c1b51eSKate Stone return fpu_s7; 1409b9c1b51eSKate Stone case dwarf_s8: 1410b9c1b51eSKate Stone return fpu_s8; 1411b9c1b51eSKate Stone case dwarf_s9: 1412b9c1b51eSKate Stone return fpu_s9; 1413b9c1b51eSKate Stone case dwarf_s10: 1414b9c1b51eSKate Stone return fpu_s10; 1415b9c1b51eSKate Stone case dwarf_s11: 1416b9c1b51eSKate Stone return fpu_s11; 1417b9c1b51eSKate Stone case dwarf_s12: 1418b9c1b51eSKate Stone return fpu_s12; 1419b9c1b51eSKate Stone case dwarf_s13: 1420b9c1b51eSKate Stone return fpu_s13; 1421b9c1b51eSKate Stone case dwarf_s14: 1422b9c1b51eSKate Stone return fpu_s14; 1423b9c1b51eSKate Stone case dwarf_s15: 1424b9c1b51eSKate Stone return fpu_s15; 1425b9c1b51eSKate Stone case dwarf_s16: 1426b9c1b51eSKate Stone return fpu_s16; 1427b9c1b51eSKate Stone case dwarf_s17: 1428b9c1b51eSKate Stone return fpu_s17; 1429b9c1b51eSKate Stone case dwarf_s18: 1430b9c1b51eSKate Stone return fpu_s18; 1431b9c1b51eSKate Stone case dwarf_s19: 1432b9c1b51eSKate Stone return fpu_s19; 1433b9c1b51eSKate Stone case dwarf_s20: 1434b9c1b51eSKate Stone return fpu_s20; 1435b9c1b51eSKate Stone case dwarf_s21: 1436b9c1b51eSKate Stone return fpu_s21; 1437b9c1b51eSKate Stone case dwarf_s22: 1438b9c1b51eSKate Stone return fpu_s22; 1439b9c1b51eSKate Stone case dwarf_s23: 1440b9c1b51eSKate Stone return fpu_s23; 1441b9c1b51eSKate Stone case dwarf_s24: 1442b9c1b51eSKate Stone return fpu_s24; 1443b9c1b51eSKate Stone case dwarf_s25: 1444b9c1b51eSKate Stone return fpu_s25; 1445b9c1b51eSKate Stone case dwarf_s26: 1446b9c1b51eSKate Stone return fpu_s26; 1447b9c1b51eSKate Stone case dwarf_s27: 1448b9c1b51eSKate Stone return fpu_s27; 1449b9c1b51eSKate Stone case dwarf_s28: 1450b9c1b51eSKate Stone return fpu_s28; 1451b9c1b51eSKate Stone case dwarf_s29: 1452b9c1b51eSKate Stone return fpu_s29; 1453b9c1b51eSKate Stone case dwarf_s30: 1454b9c1b51eSKate Stone return fpu_s30; 1455b9c1b51eSKate Stone case dwarf_s31: 1456b9c1b51eSKate Stone return fpu_s31; 1457a63d08c9SGreg Clayton 1458a63d08c9SGreg Clayton default: 1459a63d08c9SGreg Clayton break; 1460a63d08c9SGreg Clayton } 1461b9c1b51eSKate Stone } else if (kind == eRegisterKindEHFrame) { 1462b9c1b51eSKate Stone switch (reg) { 1463b9c1b51eSKate Stone case ehframe_r0: 1464b9c1b51eSKate Stone return gpr_r0; 1465b9c1b51eSKate Stone case ehframe_r1: 1466b9c1b51eSKate Stone return gpr_r1; 1467b9c1b51eSKate Stone case ehframe_r2: 1468b9c1b51eSKate Stone return gpr_r2; 1469b9c1b51eSKate Stone case ehframe_r3: 1470b9c1b51eSKate Stone return gpr_r3; 1471b9c1b51eSKate Stone case ehframe_r4: 1472b9c1b51eSKate Stone return gpr_r4; 1473b9c1b51eSKate Stone case ehframe_r5: 1474b9c1b51eSKate Stone return gpr_r5; 1475b9c1b51eSKate Stone case ehframe_r6: 1476b9c1b51eSKate Stone return gpr_r6; 1477b9c1b51eSKate Stone case ehframe_r7: 1478b9c1b51eSKate Stone return gpr_r7; 1479b9c1b51eSKate Stone case ehframe_r8: 1480b9c1b51eSKate Stone return gpr_r8; 1481b9c1b51eSKate Stone case ehframe_r9: 1482b9c1b51eSKate Stone return gpr_r9; 1483b9c1b51eSKate Stone case ehframe_r10: 1484b9c1b51eSKate Stone return gpr_r10; 1485b9c1b51eSKate Stone case ehframe_r11: 1486b9c1b51eSKate Stone return gpr_r11; 1487b9c1b51eSKate Stone case ehframe_r12: 1488b9c1b51eSKate Stone return gpr_r12; 1489b9c1b51eSKate Stone case ehframe_sp: 1490b9c1b51eSKate Stone return gpr_sp; 1491b9c1b51eSKate Stone case ehframe_lr: 1492b9c1b51eSKate Stone return gpr_lr; 1493b9c1b51eSKate Stone case ehframe_pc: 1494b9c1b51eSKate Stone return gpr_pc; 1495b9c1b51eSKate Stone case ehframe_cpsr: 1496b9c1b51eSKate Stone return gpr_cpsr; 1497a63d08c9SGreg Clayton } 1498b9c1b51eSKate Stone } else if (kind == eRegisterKindLLDB) { 1499a63d08c9SGreg Clayton return reg; 1500a63d08c9SGreg Clayton } 1501a63d08c9SGreg Clayton return LLDB_INVALID_REGNUM; 1502a63d08c9SGreg Clayton } 1503a63d08c9SGreg Clayton 1504b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::NumSupportedHardwareBreakpoints() { 150590da3ce3SPavel Labath #if defined(__APPLE__) && defined(__arm__) 1506a63d08c9SGreg Clayton // Set the init value to something that will let us know that we need to 1507a63d08c9SGreg Clayton // autodetect how many breakpoints are supported dynamically... 1508a63d08c9SGreg Clayton static uint32_t g_num_supported_hw_breakpoints = UINT32_MAX; 1509b9c1b51eSKate Stone if (g_num_supported_hw_breakpoints == UINT32_MAX) { 1510a63d08c9SGreg Clayton // Set this to zero in case we can't tell if there are any HW breakpoints 1511a63d08c9SGreg Clayton g_num_supported_hw_breakpoints = 0; 1512a63d08c9SGreg Clayton 1513a63d08c9SGreg Clayton uint32_t register_DBGDIDR; 1514a63d08c9SGreg Clayton 1515a63d08c9SGreg Clayton asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 1516dce502edSGreg Clayton g_num_supported_hw_breakpoints = Bits32(register_DBGDIDR, 27, 24); 1517a63d08c9SGreg Clayton // Zero is reserved for the BRP count, so don't increment it if it is zero 1518a63d08c9SGreg Clayton if (g_num_supported_hw_breakpoints > 0) 1519a63d08c9SGreg Clayton g_num_supported_hw_breakpoints++; 1520b9c1b51eSKate Stone // if (log) log->Printf ("DBGDIDR=0x%8.8x (number BRP pairs = %u)", 1521b9c1b51eSKate Stone // register_DBGDIDR, g_num_supported_hw_breakpoints); 1522a63d08c9SGreg Clayton } 1523a63d08c9SGreg Clayton return g_num_supported_hw_breakpoints; 1524a63d08c9SGreg Clayton #else 1525a63d08c9SGreg Clayton // TODO: figure out remote case here! 1526a63d08c9SGreg Clayton return 6; 1527a63d08c9SGreg Clayton #endif 1528a63d08c9SGreg Clayton } 1529a63d08c9SGreg Clayton 1530b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::SetHardwareBreakpoint(lldb::addr_t addr, 1531b9c1b51eSKate Stone size_t size) { 1532a63d08c9SGreg Clayton // Make sure our address isn't bogus 1533a63d08c9SGreg Clayton if (addr & 1) 1534a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1535a63d08c9SGreg Clayton 1536a63d08c9SGreg Clayton int kret = ReadDBG(false); 1537a63d08c9SGreg Clayton 1538b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1539a63d08c9SGreg Clayton const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints(); 1540a63d08c9SGreg Clayton uint32_t i; 1541b9c1b51eSKate Stone for (i = 0; i < num_hw_breakpoints; ++i) { 1542a63d08c9SGreg Clayton if ((dbg.bcr[i] & BCR_ENABLE) == 0) 1543a63d08c9SGreg Clayton break; // We found an available hw breakpoint slot (in i) 1544a63d08c9SGreg Clayton } 1545a63d08c9SGreg Clayton 1546a63d08c9SGreg Clayton // See if we found an available hw breakpoint slot above 1547b9c1b51eSKate Stone if (i < num_hw_breakpoints) { 1548a63d08c9SGreg Clayton // Make sure bits 1:0 are clear in our address 1549a63d08c9SGreg Clayton dbg.bvr[i] = addr & ~((lldb::addr_t)3); 1550a63d08c9SGreg Clayton 1551b9c1b51eSKate Stone if (size == 2 || addr & 2) { 1552a63d08c9SGreg Clayton uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1; 1553a63d08c9SGreg Clayton 1554a63d08c9SGreg Clayton // We have a thumb breakpoint 1555a63d08c9SGreg Clayton // We have an ARM breakpoint 1556a63d08c9SGreg Clayton dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch 1557b9c1b51eSKate Stone byte_addr_select | // Set the correct byte address select 1558b9c1b51eSKate Stone // so we only trigger on the correct 1559b9c1b51eSKate Stone // opcode 1560a63d08c9SGreg Clayton S_USER | // Which modes should this breakpoint stop in? 1561a63d08c9SGreg Clayton BCR_ENABLE; // Enable this hardware breakpoint 1562b9c1b51eSKate Stone // if (log) log->Printf 1563b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 1564b9c1b51eSKate Stone // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 1565b9c1b51eSKate Stone // 0x%8.8x (Thumb)", 156689f138aeSGreg Clayton // addr, 156789f138aeSGreg Clayton // size, 156889f138aeSGreg Clayton // i, 156989f138aeSGreg Clayton // i, 157089f138aeSGreg Clayton // dbg.bvr[i], 157189f138aeSGreg Clayton // dbg.bcr[i]); 1572b9c1b51eSKate Stone } else if (size == 4) { 1573a63d08c9SGreg Clayton // We have an ARM breakpoint 1574b9c1b51eSKate Stone dbg.bcr[i] = 1575b9c1b51eSKate Stone BCR_M_IMVA_MATCH | // Stop on address mismatch 1576a63d08c9SGreg Clayton BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA 1577a63d08c9SGreg Clayton S_USER | // Which modes should this breakpoint stop in? 1578a63d08c9SGreg Clayton BCR_ENABLE; // Enable this hardware breakpoint 1579b9c1b51eSKate Stone // if (log) log->Printf 1580b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 1581b9c1b51eSKate Stone // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 1582b9c1b51eSKate Stone // 0x%8.8x (ARM)", 158389f138aeSGreg Clayton // addr, 158489f138aeSGreg Clayton // size, 158589f138aeSGreg Clayton // i, 158689f138aeSGreg Clayton // i, 158789f138aeSGreg Clayton // dbg.bvr[i], 158889f138aeSGreg Clayton // dbg.bcr[i]); 1589a63d08c9SGreg Clayton } 1590a63d08c9SGreg Clayton 1591a63d08c9SGreg Clayton kret = WriteDBG(); 1592b9c1b51eSKate Stone // if (log) log->Printf 1593b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint() 1594b9c1b51eSKate Stone // WriteDBG() => 0x%8.8x.", kret); 1595a63d08c9SGreg Clayton 1596a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1597a63d08c9SGreg Clayton return i; 1598a63d08c9SGreg Clayton } 159989f138aeSGreg Clayton // else 160089f138aeSGreg Clayton // { 1601b9c1b51eSKate Stone // if (log) log->Printf 1602b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(addr = 1603b9c1b51eSKate Stone // %8.8p, size = %u) => all hardware breakpoint resources are 1604b9c1b51eSKate Stone // being used.", addr, size); 160589f138aeSGreg Clayton // } 1606a63d08c9SGreg Clayton } 1607a63d08c9SGreg Clayton 1608a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1609a63d08c9SGreg Clayton } 1610a63d08c9SGreg Clayton 1611b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ClearHardwareBreakpoint(uint32_t hw_index) { 1612a63d08c9SGreg Clayton int kret = ReadDBG(false); 1613a63d08c9SGreg Clayton 1614a63d08c9SGreg Clayton const uint32_t num_hw_points = NumSupportedHardwareBreakpoints(); 1615b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1616b9c1b51eSKate Stone if (hw_index < num_hw_points) { 1617a63d08c9SGreg Clayton dbg.bcr[hw_index] = 0; 1618b9c1b51eSKate Stone // if (log) log->Printf 1619b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::SetHardwareBreakpoint( %u ) - 1620b9c1b51eSKate Stone // BVR%u = 0x%8.8x BCR%u = 0x%8.8x", 162189f138aeSGreg Clayton // hw_index, 162289f138aeSGreg Clayton // hw_index, 162389f138aeSGreg Clayton // dbg.bvr[hw_index], 162489f138aeSGreg Clayton // hw_index, 162589f138aeSGreg Clayton // dbg.bcr[hw_index]); 1626a63d08c9SGreg Clayton 1627a63d08c9SGreg Clayton kret = WriteDBG(); 1628a63d08c9SGreg Clayton 1629a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1630a63d08c9SGreg Clayton return true; 1631a63d08c9SGreg Clayton } 1632a63d08c9SGreg Clayton } 1633a63d08c9SGreg Clayton return false; 1634a63d08c9SGreg Clayton } 1635a63d08c9SGreg Clayton 1636b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::NumSupportedHardwareWatchpoints() { 163790da3ce3SPavel Labath #if defined(__APPLE__) && defined(__arm__) 1638a63d08c9SGreg Clayton // Set the init value to something that will let us know that we need to 1639a63d08c9SGreg Clayton // autodetect how many watchpoints are supported dynamically... 1640a63d08c9SGreg Clayton static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX; 1641b9c1b51eSKate Stone if (g_num_supported_hw_watchpoints == UINT32_MAX) { 1642a63d08c9SGreg Clayton // Set this to zero in case we can't tell if there are any HW breakpoints 1643a63d08c9SGreg Clayton g_num_supported_hw_watchpoints = 0; 1644a63d08c9SGreg Clayton 1645a63d08c9SGreg Clayton uint32_t register_DBGDIDR; 1646a63d08c9SGreg Clayton asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 1647dce502edSGreg Clayton g_num_supported_hw_watchpoints = Bits32(register_DBGDIDR, 31, 28) + 1; 1648b9c1b51eSKate Stone // if (log) log->Printf ("DBGDIDR=0x%8.8x (number WRP pairs = %u)", 1649b9c1b51eSKate Stone // register_DBGDIDR, g_num_supported_hw_watchpoints); 1650a63d08c9SGreg Clayton } 1651a63d08c9SGreg Clayton return g_num_supported_hw_watchpoints; 1652a63d08c9SGreg Clayton #else 1653a63d08c9SGreg Clayton // TODO: figure out remote case here! 1654a63d08c9SGreg Clayton return 2; 1655a63d08c9SGreg Clayton #endif 1656a63d08c9SGreg Clayton } 1657a63d08c9SGreg Clayton 1658b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::SetHardwareWatchpoint(lldb::addr_t addr, 1659b9c1b51eSKate Stone size_t size, 1660b9c1b51eSKate Stone bool read, 1661b9c1b51eSKate Stone bool write) { 1662b9c1b51eSKate Stone // if (log) log->Printf 1663b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(addr = %8.8p, size 1664b9c1b51eSKate Stone // = %u, read = %u, write = %u)", addr, size, read, write); 1665a63d08c9SGreg Clayton 1666a63d08c9SGreg Clayton const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 1667a63d08c9SGreg Clayton 1668a63d08c9SGreg Clayton // Can't watch zero bytes 1669a63d08c9SGreg Clayton if (size == 0) 1670a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1671a63d08c9SGreg Clayton 1672a63d08c9SGreg Clayton // We must watch for either read or write 1673*a6682a41SJonas Devlieghere if (!read && !write) 1674a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1675a63d08c9SGreg Clayton 1676a63d08c9SGreg Clayton // Can't watch more than 4 bytes per WVR/WCR pair 1677a63d08c9SGreg Clayton if (size > 4) 1678a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1679a63d08c9SGreg Clayton 1680a63d08c9SGreg Clayton // We can only watch up to four bytes that follow a 4 byte aligned address 1681a63d08c9SGreg Clayton // per watchpoint register pair. Since we have at most so we can only watch 1682a63d08c9SGreg Clayton // until the next 4 byte boundary and we need to make sure we can properly 1683a63d08c9SGreg Clayton // encode this. 1684a63d08c9SGreg Clayton uint32_t addr_word_offset = addr % 4; 1685b9c1b51eSKate Stone // if (log) log->Printf 1686b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - 1687b9c1b51eSKate Stone // addr_word_offset = 0x%8.8x", addr_word_offset); 1688a63d08c9SGreg Clayton 1689a63d08c9SGreg Clayton uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset; 1690b9c1b51eSKate Stone // if (log) log->Printf 1691b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - byte_mask = 1692b9c1b51eSKate Stone // 0x%8.8x", byte_mask); 1693a63d08c9SGreg Clayton if (byte_mask > 0xfu) 1694a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1695a63d08c9SGreg Clayton 1696a63d08c9SGreg Clayton // Read the debug state 1697a63d08c9SGreg Clayton int kret = ReadDBG(false); 1698a63d08c9SGreg Clayton 1699b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1700a63d08c9SGreg Clayton // Check to make sure we have the needed hardware support 1701a63d08c9SGreg Clayton uint32_t i = 0; 1702a63d08c9SGreg Clayton 1703b9c1b51eSKate Stone for (i = 0; i < num_hw_watchpoints; ++i) { 1704a63d08c9SGreg Clayton if ((dbg.wcr[i] & WCR_ENABLE) == 0) 1705a63d08c9SGreg Clayton break; // We found an available hw breakpoint slot (in i) 1706a63d08c9SGreg Clayton } 1707a63d08c9SGreg Clayton 1708a63d08c9SGreg Clayton // See if we found an available hw breakpoint slot above 1709b9c1b51eSKate Stone if (i < num_hw_watchpoints) { 1710a63d08c9SGreg Clayton // Make the byte_mask into a valid Byte Address Select mask 1711a63d08c9SGreg Clayton uint32_t byte_address_select = byte_mask << 5; 1712a63d08c9SGreg Clayton // Make sure bits 1:0 are clear in our address 1713a63d08c9SGreg Clayton dbg.wvr[i] = addr & ~((lldb::addr_t)3); 1714b9c1b51eSKate Stone dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA 1715b9c1b51eSKate Stone // that we will watch 1716a63d08c9SGreg Clayton S_USER | // Stop only in user mode 1717a63d08c9SGreg Clayton (read ? WCR_LOAD : 0) | // Stop on read access? 1718a63d08c9SGreg Clayton (write ? WCR_STORE : 0) | // Stop on write access? 1719a63d08c9SGreg Clayton WCR_ENABLE; // Enable this watchpoint; 1720a63d08c9SGreg Clayton 1721a63d08c9SGreg Clayton kret = WriteDBG(); 1722b9c1b51eSKate Stone // if (log) log->Printf 1723b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() 1724b9c1b51eSKate Stone // WriteDBG() => 0x%8.8x.", kret); 1725a63d08c9SGreg Clayton 1726a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1727a63d08c9SGreg Clayton return i; 1728b9c1b51eSKate Stone } else { 1729b9c1b51eSKate Stone // if (log) log->Printf 1730b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(): All 1731b9c1b51eSKate Stone // hardware resources (%u) are in use.", num_hw_watchpoints); 1732a63d08c9SGreg Clayton } 1733a63d08c9SGreg Clayton } 1734a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1735a63d08c9SGreg Clayton } 1736a63d08c9SGreg Clayton 1737b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ClearHardwareWatchpoint(uint32_t hw_index) { 1738a63d08c9SGreg Clayton int kret = ReadDBG(false); 1739a63d08c9SGreg Clayton 1740a63d08c9SGreg Clayton const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 1741b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1742b9c1b51eSKate Stone if (hw_index < num_hw_points) { 1743a63d08c9SGreg Clayton dbg.wcr[hw_index] = 0; 1744b9c1b51eSKate Stone // if (log) log->Printf 1745b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::ClearHardwareWatchpoint( %u ) - 1746b9c1b51eSKate Stone // WVR%u = 0x%8.8x WCR%u = 0x%8.8x", 174789f138aeSGreg Clayton // hw_index, 174889f138aeSGreg Clayton // hw_index, 174989f138aeSGreg Clayton // dbg.wvr[hw_index], 175089f138aeSGreg Clayton // hw_index, 175189f138aeSGreg Clayton // dbg.wcr[hw_index]); 1752a63d08c9SGreg Clayton 1753a63d08c9SGreg Clayton kret = WriteDBG(); 1754a63d08c9SGreg Clayton 1755a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1756a63d08c9SGreg Clayton return true; 1757a63d08c9SGreg Clayton } 1758a63d08c9SGreg Clayton } 1759a63d08c9SGreg Clayton return false; 1760a63d08c9SGreg Clayton } 1761