1a63d08c9SGreg Clayton //===-- RegisterContextDarwin_arm.cpp ---------------------------*- C++ -*-===// 2a63d08c9SGreg Clayton // 3a63d08c9SGreg Clayton // The LLVM Compiler Infrastructure 4a63d08c9SGreg Clayton // 5a63d08c9SGreg Clayton // This file is distributed under the University of Illinois Open Source 6a63d08c9SGreg Clayton // License. See LICENSE.TXT for details. 7a63d08c9SGreg Clayton // 8a63d08c9SGreg Clayton //===----------------------------------------------------------------------===// 9a63d08c9SGreg Clayton 10a67dd8fcSPeter Collingbourne #if defined(__APPLE__) 11a67dd8fcSPeter Collingbourne 12a63d08c9SGreg Clayton #include "RegisterContextDarwin_arm.h" 13a63d08c9SGreg Clayton 14a63d08c9SGreg Clayton // C Includes 15a63d08c9SGreg Clayton #include <mach/mach_types.h> 16a63d08c9SGreg Clayton #include <mach/thread_act.h> 17a63d08c9SGreg Clayton 18a63d08c9SGreg Clayton // C++ Includes 19a63d08c9SGreg Clayton // Other libraries and framework includes 20a63d08c9SGreg Clayton #include "lldb/Core/RegisterValue.h" 21a63d08c9SGreg Clayton #include "lldb/Core/Scalar.h" 22*666cc0b2SZachary Turner #include "lldb/Utility/DataBufferHeap.h" 23*666cc0b2SZachary Turner #include "lldb/Utility/DataExtractor.h" 2401c3243fSZachary Turner #include "lldb/Utility/Endian.h" 256f9e6901SZachary Turner #include "lldb/Utility/Log.h" 2612a19904SDaniel Dunbar #include "llvm/Support/Compiler.h" 2712a19904SDaniel Dunbar 28dce502edSGreg Clayton #include "Plugins/Process/Utility/InstructionUtils.h" 29dce502edSGreg Clayton 3012a19904SDaniel Dunbar // Support building against older versions of LLVM, this macro was added 3112a19904SDaniel Dunbar // recently. 3212a19904SDaniel Dunbar #ifndef LLVM_EXTENSION 3312a19904SDaniel Dunbar #define LLVM_EXTENSION 3412a19904SDaniel Dunbar #endif 35a63d08c9SGreg Clayton 36a63d08c9SGreg Clayton // Project includes 37a63d08c9SGreg Clayton #include "ARM_DWARF_Registers.h" 3863bd0db0SJason Molenda #include "Utility/ARM_ehframe_Registers.h" 39a63d08c9SGreg Clayton 4028606954SSaleem Abdulrasool #include "llvm/ADT/STLExtras.h" 4128606954SSaleem Abdulrasool 42a63d08c9SGreg Clayton using namespace lldb; 43a63d08c9SGreg Clayton using namespace lldb_private; 44a63d08c9SGreg Clayton 45b9c1b51eSKate Stone enum { 46a63d08c9SGreg Clayton gpr_r0 = 0, 47a63d08c9SGreg Clayton gpr_r1, 48a63d08c9SGreg Clayton gpr_r2, 49a63d08c9SGreg Clayton gpr_r3, 50a63d08c9SGreg Clayton gpr_r4, 51a63d08c9SGreg Clayton gpr_r5, 52a63d08c9SGreg Clayton gpr_r6, 53a63d08c9SGreg Clayton gpr_r7, 54a63d08c9SGreg Clayton gpr_r8, 55a63d08c9SGreg Clayton gpr_r9, 56a63d08c9SGreg Clayton gpr_r10, 57a63d08c9SGreg Clayton gpr_r11, 58a63d08c9SGreg Clayton gpr_r12, 59b9c1b51eSKate Stone gpr_r13, 60b9c1b51eSKate Stone gpr_sp = gpr_r13, 61b9c1b51eSKate Stone gpr_r14, 62b9c1b51eSKate Stone gpr_lr = gpr_r14, 63b9c1b51eSKate Stone gpr_r15, 64b9c1b51eSKate Stone gpr_pc = gpr_r15, 65a63d08c9SGreg Clayton gpr_cpsr, 66a63d08c9SGreg Clayton 67a63d08c9SGreg Clayton fpu_s0, 68a63d08c9SGreg Clayton fpu_s1, 69a63d08c9SGreg Clayton fpu_s2, 70a63d08c9SGreg Clayton fpu_s3, 71a63d08c9SGreg Clayton fpu_s4, 72a63d08c9SGreg Clayton fpu_s5, 73a63d08c9SGreg Clayton fpu_s6, 74a63d08c9SGreg Clayton fpu_s7, 75a63d08c9SGreg Clayton fpu_s8, 76a63d08c9SGreg Clayton fpu_s9, 77a63d08c9SGreg Clayton fpu_s10, 78a63d08c9SGreg Clayton fpu_s11, 79a63d08c9SGreg Clayton fpu_s12, 80a63d08c9SGreg Clayton fpu_s13, 81a63d08c9SGreg Clayton fpu_s14, 82a63d08c9SGreg Clayton fpu_s15, 83a63d08c9SGreg Clayton fpu_s16, 84a63d08c9SGreg Clayton fpu_s17, 85a63d08c9SGreg Clayton fpu_s18, 86a63d08c9SGreg Clayton fpu_s19, 87a63d08c9SGreg Clayton fpu_s20, 88a63d08c9SGreg Clayton fpu_s21, 89a63d08c9SGreg Clayton fpu_s22, 90a63d08c9SGreg Clayton fpu_s23, 91a63d08c9SGreg Clayton fpu_s24, 92a63d08c9SGreg Clayton fpu_s25, 93a63d08c9SGreg Clayton fpu_s26, 94a63d08c9SGreg Clayton fpu_s27, 95a63d08c9SGreg Clayton fpu_s28, 96a63d08c9SGreg Clayton fpu_s29, 97a63d08c9SGreg Clayton fpu_s30, 98a63d08c9SGreg Clayton fpu_s31, 99a63d08c9SGreg Clayton fpu_fpscr, 100a63d08c9SGreg Clayton 101a63d08c9SGreg Clayton exc_exception, 102a63d08c9SGreg Clayton exc_fsr, 103a63d08c9SGreg Clayton exc_far, 104a63d08c9SGreg Clayton 105a63d08c9SGreg Clayton dbg_bvr0, 106a63d08c9SGreg Clayton dbg_bvr1, 107a63d08c9SGreg Clayton dbg_bvr2, 108a63d08c9SGreg Clayton dbg_bvr3, 109a63d08c9SGreg Clayton dbg_bvr4, 110a63d08c9SGreg Clayton dbg_bvr5, 111a63d08c9SGreg Clayton dbg_bvr6, 112a63d08c9SGreg Clayton dbg_bvr7, 113a63d08c9SGreg Clayton dbg_bvr8, 114a63d08c9SGreg Clayton dbg_bvr9, 115a63d08c9SGreg Clayton dbg_bvr10, 116a63d08c9SGreg Clayton dbg_bvr11, 117a63d08c9SGreg Clayton dbg_bvr12, 118a63d08c9SGreg Clayton dbg_bvr13, 119a63d08c9SGreg Clayton dbg_bvr14, 120a63d08c9SGreg Clayton dbg_bvr15, 121a63d08c9SGreg Clayton 122a63d08c9SGreg Clayton dbg_bcr0, 123a63d08c9SGreg Clayton dbg_bcr1, 124a63d08c9SGreg Clayton dbg_bcr2, 125a63d08c9SGreg Clayton dbg_bcr3, 126a63d08c9SGreg Clayton dbg_bcr4, 127a63d08c9SGreg Clayton dbg_bcr5, 128a63d08c9SGreg Clayton dbg_bcr6, 129a63d08c9SGreg Clayton dbg_bcr7, 130a63d08c9SGreg Clayton dbg_bcr8, 131a63d08c9SGreg Clayton dbg_bcr9, 132a63d08c9SGreg Clayton dbg_bcr10, 133a63d08c9SGreg Clayton dbg_bcr11, 134a63d08c9SGreg Clayton dbg_bcr12, 135a63d08c9SGreg Clayton dbg_bcr13, 136a63d08c9SGreg Clayton dbg_bcr14, 137a63d08c9SGreg Clayton dbg_bcr15, 138a63d08c9SGreg Clayton 139a63d08c9SGreg Clayton dbg_wvr0, 140a63d08c9SGreg Clayton dbg_wvr1, 141a63d08c9SGreg Clayton dbg_wvr2, 142a63d08c9SGreg Clayton dbg_wvr3, 143a63d08c9SGreg Clayton dbg_wvr4, 144a63d08c9SGreg Clayton dbg_wvr5, 145a63d08c9SGreg Clayton dbg_wvr6, 146a63d08c9SGreg Clayton dbg_wvr7, 147a63d08c9SGreg Clayton dbg_wvr8, 148a63d08c9SGreg Clayton dbg_wvr9, 149a63d08c9SGreg Clayton dbg_wvr10, 150a63d08c9SGreg Clayton dbg_wvr11, 151a63d08c9SGreg Clayton dbg_wvr12, 152a63d08c9SGreg Clayton dbg_wvr13, 153a63d08c9SGreg Clayton dbg_wvr14, 154a63d08c9SGreg Clayton dbg_wvr15, 155a63d08c9SGreg Clayton 156a63d08c9SGreg Clayton dbg_wcr0, 157a63d08c9SGreg Clayton dbg_wcr1, 158a63d08c9SGreg Clayton dbg_wcr2, 159a63d08c9SGreg Clayton dbg_wcr3, 160a63d08c9SGreg Clayton dbg_wcr4, 161a63d08c9SGreg Clayton dbg_wcr5, 162a63d08c9SGreg Clayton dbg_wcr6, 163a63d08c9SGreg Clayton dbg_wcr7, 164a63d08c9SGreg Clayton dbg_wcr8, 165a63d08c9SGreg Clayton dbg_wcr9, 166a63d08c9SGreg Clayton dbg_wcr10, 167a63d08c9SGreg Clayton dbg_wcr11, 168a63d08c9SGreg Clayton dbg_wcr12, 169a63d08c9SGreg Clayton dbg_wcr13, 170a63d08c9SGreg Clayton dbg_wcr14, 171a63d08c9SGreg Clayton dbg_wcr15, 172a63d08c9SGreg Clayton 173a63d08c9SGreg Clayton k_num_registers 174a63d08c9SGreg Clayton }; 175a63d08c9SGreg Clayton 176a63d08c9SGreg Clayton #define GPR_OFFSET(idx) ((idx)*4) 177a63d08c9SGreg Clayton #define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR)) 178b9c1b51eSKate Stone #define EXC_OFFSET(idx) \ 179b9c1b51eSKate Stone ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR) + \ 180b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU)) 181b9c1b51eSKate Stone #define DBG_OFFSET(reg) \ 182b9c1b51eSKate Stone ((LLVM_EXTENSION offsetof(RegisterContextDarwin_arm::DBG, reg) + \ 183b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::GPR) + \ 184b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU) + \ 185b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::EXC))) 186a63d08c9SGreg Clayton 187b9c1b51eSKate Stone #define DEFINE_DBG(reg, i) \ 188b9c1b51eSKate Stone #reg, NULL, sizeof(((RegisterContextDarwin_arm::DBG *) NULL)->reg[i]), \ 189b9c1b51eSKate Stone DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, \ 190b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 191b9c1b51eSKate Stone LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 192b9c1b51eSKate Stone LLDB_INVALID_REGNUM }, \ 193b9c1b51eSKate Stone nullptr, nullptr, nullptr, 0 194b9c1b51eSKate Stone #define REG_CONTEXT_SIZE \ 195b9c1b51eSKate Stone (sizeof(RegisterContextDarwin_arm::GPR) + \ 196b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU) + \ 197b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::EXC)) 198a63d08c9SGreg Clayton 199a63d08c9SGreg Clayton static RegisterInfo g_register_infos[] = { 200a63d08c9SGreg Clayton // General purpose registers 201b9c1b51eSKate Stone // NAME ALT SZ OFFSET ENCODING FORMAT 202b9c1b51eSKate Stone // EH_FRAME DWARF GENERIC 203b9c1b51eSKate Stone // PROCESS PLUGIN LLDB NATIVE 204b9c1b51eSKate Stone // ====== ======= == ============= ============= ============ 205b9c1b51eSKate Stone // =============== =============== ========================= 206b9c1b51eSKate Stone // ===================== ============= 207b9c1b51eSKate Stone {"r0", 208b9c1b51eSKate Stone NULL, 209b9c1b51eSKate Stone 4, 210b9c1b51eSKate Stone GPR_OFFSET(0), 211b9c1b51eSKate Stone eEncodingUint, 212b9c1b51eSKate Stone eFormatHex, 213b9c1b51eSKate Stone {ehframe_r0, dwarf_r0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r0}, 214b9c1b51eSKate Stone nullptr, 215b9c1b51eSKate Stone nullptr, 216b9c1b51eSKate Stone nullptr, 217b9c1b51eSKate Stone 0}, 218b9c1b51eSKate Stone {"r1", 219b9c1b51eSKate Stone NULL, 220b9c1b51eSKate Stone 4, 221b9c1b51eSKate Stone GPR_OFFSET(1), 222b9c1b51eSKate Stone eEncodingUint, 223b9c1b51eSKate Stone eFormatHex, 224b9c1b51eSKate Stone {ehframe_r1, dwarf_r1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r1}, 225b9c1b51eSKate Stone nullptr, 226b9c1b51eSKate Stone nullptr, 227b9c1b51eSKate Stone nullptr, 228b9c1b51eSKate Stone 0}, 229b9c1b51eSKate Stone {"r2", 230b9c1b51eSKate Stone NULL, 231b9c1b51eSKate Stone 4, 232b9c1b51eSKate Stone GPR_OFFSET(2), 233b9c1b51eSKate Stone eEncodingUint, 234b9c1b51eSKate Stone eFormatHex, 235b9c1b51eSKate Stone {ehframe_r2, dwarf_r2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r2}, 236b9c1b51eSKate Stone nullptr, 237b9c1b51eSKate Stone nullptr, 238b9c1b51eSKate Stone nullptr, 239b9c1b51eSKate Stone 0}, 240b9c1b51eSKate Stone {"r3", 241b9c1b51eSKate Stone NULL, 242b9c1b51eSKate Stone 4, 243b9c1b51eSKate Stone GPR_OFFSET(3), 244b9c1b51eSKate Stone eEncodingUint, 245b9c1b51eSKate Stone eFormatHex, 246b9c1b51eSKate Stone {ehframe_r3, dwarf_r3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r3}, 247b9c1b51eSKate Stone nullptr, 248b9c1b51eSKate Stone nullptr, 249b9c1b51eSKate Stone nullptr, 250b9c1b51eSKate Stone 0}, 251b9c1b51eSKate Stone {"r4", 252b9c1b51eSKate Stone NULL, 253b9c1b51eSKate Stone 4, 254b9c1b51eSKate Stone GPR_OFFSET(4), 255b9c1b51eSKate Stone eEncodingUint, 256b9c1b51eSKate Stone eFormatHex, 257b9c1b51eSKate Stone {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4}, 258b9c1b51eSKate Stone nullptr, 259b9c1b51eSKate Stone nullptr, 260b9c1b51eSKate Stone nullptr, 261b9c1b51eSKate Stone 0}, 262b9c1b51eSKate Stone {"r5", 263b9c1b51eSKate Stone NULL, 264b9c1b51eSKate Stone 4, 265b9c1b51eSKate Stone GPR_OFFSET(5), 266b9c1b51eSKate Stone eEncodingUint, 267b9c1b51eSKate Stone eFormatHex, 268b9c1b51eSKate Stone {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5}, 269b9c1b51eSKate Stone nullptr, 270b9c1b51eSKate Stone nullptr, 271b9c1b51eSKate Stone nullptr, 272b9c1b51eSKate Stone 0}, 273b9c1b51eSKate Stone {"r6", 274b9c1b51eSKate Stone NULL, 275b9c1b51eSKate Stone 4, 276b9c1b51eSKate Stone GPR_OFFSET(6), 277b9c1b51eSKate Stone eEncodingUint, 278b9c1b51eSKate Stone eFormatHex, 279b9c1b51eSKate Stone {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6}, 280b9c1b51eSKate Stone nullptr, 281b9c1b51eSKate Stone nullptr, 282b9c1b51eSKate Stone nullptr, 283b9c1b51eSKate Stone 0}, 284b9c1b51eSKate Stone {"r7", 285b9c1b51eSKate Stone NULL, 286b9c1b51eSKate Stone 4, 287b9c1b51eSKate Stone GPR_OFFSET(7), 288b9c1b51eSKate Stone eEncodingUint, 289b9c1b51eSKate Stone eFormatHex, 290b9c1b51eSKate Stone {ehframe_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, 291b9c1b51eSKate Stone gpr_r7}, 292b9c1b51eSKate Stone nullptr, 293b9c1b51eSKate Stone nullptr, 294b9c1b51eSKate Stone nullptr, 295b9c1b51eSKate Stone 0}, 296b9c1b51eSKate Stone {"r8", 297b9c1b51eSKate Stone NULL, 298b9c1b51eSKate Stone 4, 299b9c1b51eSKate Stone GPR_OFFSET(8), 300b9c1b51eSKate Stone eEncodingUint, 301b9c1b51eSKate Stone eFormatHex, 302b9c1b51eSKate Stone {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8}, 303b9c1b51eSKate Stone nullptr, 304b9c1b51eSKate Stone nullptr, 305b9c1b51eSKate Stone nullptr, 306b9c1b51eSKate Stone 0}, 307b9c1b51eSKate Stone {"r9", 308b9c1b51eSKate Stone NULL, 309b9c1b51eSKate Stone 4, 310b9c1b51eSKate Stone GPR_OFFSET(9), 311b9c1b51eSKate Stone eEncodingUint, 312b9c1b51eSKate Stone eFormatHex, 313b9c1b51eSKate Stone {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9}, 314b9c1b51eSKate Stone nullptr, 315b9c1b51eSKate Stone nullptr, 316b9c1b51eSKate Stone nullptr, 317b9c1b51eSKate Stone 0}, 318b9c1b51eSKate Stone {"r10", 319b9c1b51eSKate Stone NULL, 320b9c1b51eSKate Stone 4, 321b9c1b51eSKate Stone GPR_OFFSET(10), 322b9c1b51eSKate Stone eEncodingUint, 323b9c1b51eSKate Stone eFormatHex, 324b9c1b51eSKate Stone {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 325b9c1b51eSKate Stone gpr_r10}, 326b9c1b51eSKate Stone nullptr, 327b9c1b51eSKate Stone nullptr, 328b9c1b51eSKate Stone nullptr, 329b9c1b51eSKate Stone 0}, 330b9c1b51eSKate Stone {"r11", 331b9c1b51eSKate Stone NULL, 332b9c1b51eSKate Stone 4, 333b9c1b51eSKate Stone GPR_OFFSET(11), 334b9c1b51eSKate Stone eEncodingUint, 335b9c1b51eSKate Stone eFormatHex, 336b9c1b51eSKate Stone {ehframe_r11, dwarf_r11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 337b9c1b51eSKate Stone gpr_r11}, 338b9c1b51eSKate Stone nullptr, 339b9c1b51eSKate Stone nullptr, 340b9c1b51eSKate Stone nullptr, 341b9c1b51eSKate Stone 0}, 342b9c1b51eSKate Stone {"r12", 343b9c1b51eSKate Stone NULL, 344b9c1b51eSKate Stone 4, 345b9c1b51eSKate Stone GPR_OFFSET(12), 346b9c1b51eSKate Stone eEncodingUint, 347b9c1b51eSKate Stone eFormatHex, 348b9c1b51eSKate Stone {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 349b9c1b51eSKate Stone gpr_r12}, 350b9c1b51eSKate Stone nullptr, 351b9c1b51eSKate Stone nullptr, 352b9c1b51eSKate Stone nullptr, 353b9c1b51eSKate Stone 0}, 354b9c1b51eSKate Stone {"sp", 355b9c1b51eSKate Stone "r13", 356b9c1b51eSKate Stone 4, 357b9c1b51eSKate Stone GPR_OFFSET(13), 358b9c1b51eSKate Stone eEncodingUint, 359b9c1b51eSKate Stone eFormatHex, 360b9c1b51eSKate Stone {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, 361b9c1b51eSKate Stone gpr_sp}, 362b9c1b51eSKate Stone nullptr, 363b9c1b51eSKate Stone nullptr, 364b9c1b51eSKate Stone nullptr, 365b9c1b51eSKate Stone 0}, 366b9c1b51eSKate Stone {"lr", 367b9c1b51eSKate Stone "r14", 368b9c1b51eSKate Stone 4, 369b9c1b51eSKate Stone GPR_OFFSET(14), 370b9c1b51eSKate Stone eEncodingUint, 371b9c1b51eSKate Stone eFormatHex, 372b9c1b51eSKate Stone {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, 373b9c1b51eSKate Stone gpr_lr}, 374b9c1b51eSKate Stone nullptr, 375b9c1b51eSKate Stone nullptr, 376b9c1b51eSKate Stone nullptr, 377b9c1b51eSKate Stone 0}, 378b9c1b51eSKate Stone {"pc", 379b9c1b51eSKate Stone "r15", 380b9c1b51eSKate Stone 4, 381b9c1b51eSKate Stone GPR_OFFSET(15), 382b9c1b51eSKate Stone eEncodingUint, 383b9c1b51eSKate Stone eFormatHex, 384b9c1b51eSKate Stone {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, 385b9c1b51eSKate Stone gpr_pc}, 386b9c1b51eSKate Stone nullptr, 387b9c1b51eSKate Stone nullptr, 388b9c1b51eSKate Stone nullptr, 389b9c1b51eSKate Stone 0}, 390b9c1b51eSKate Stone {"cpsr", 391b9c1b51eSKate Stone "psr", 392b9c1b51eSKate Stone 4, 393b9c1b51eSKate Stone GPR_OFFSET(16), 394b9c1b51eSKate Stone eEncodingUint, 395b9c1b51eSKate Stone eFormatHex, 396b9c1b51eSKate Stone {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM, 397b9c1b51eSKate Stone gpr_cpsr}, 398b9c1b51eSKate Stone nullptr, 399b9c1b51eSKate Stone nullptr, 400b9c1b51eSKate Stone nullptr, 401b9c1b51eSKate Stone 0}, 402a63d08c9SGreg Clayton 403b9c1b51eSKate Stone {"s0", 404b9c1b51eSKate Stone NULL, 405b9c1b51eSKate Stone 4, 406b9c1b51eSKate Stone FPU_OFFSET(0), 407b9c1b51eSKate Stone eEncodingIEEE754, 408b9c1b51eSKate Stone eFormatFloat, 409b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 410b9c1b51eSKate Stone fpu_s0}, 411b9c1b51eSKate Stone nullptr, 412b9c1b51eSKate Stone nullptr, 413b9c1b51eSKate Stone nullptr, 414b9c1b51eSKate Stone 0}, 415b9c1b51eSKate Stone {"s1", 416b9c1b51eSKate Stone NULL, 417b9c1b51eSKate Stone 4, 418b9c1b51eSKate Stone FPU_OFFSET(1), 419b9c1b51eSKate Stone eEncodingIEEE754, 420b9c1b51eSKate Stone eFormatFloat, 421b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 422b9c1b51eSKate Stone fpu_s1}, 423b9c1b51eSKate Stone nullptr, 424b9c1b51eSKate Stone nullptr, 425b9c1b51eSKate Stone nullptr, 426b9c1b51eSKate Stone 0}, 427b9c1b51eSKate Stone {"s2", 428b9c1b51eSKate Stone NULL, 429b9c1b51eSKate Stone 4, 430b9c1b51eSKate Stone FPU_OFFSET(2), 431b9c1b51eSKate Stone eEncodingIEEE754, 432b9c1b51eSKate Stone eFormatFloat, 433b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 434b9c1b51eSKate Stone fpu_s2}, 435b9c1b51eSKate Stone nullptr, 436b9c1b51eSKate Stone nullptr, 437b9c1b51eSKate Stone nullptr, 438b9c1b51eSKate Stone 0}, 439b9c1b51eSKate Stone {"s3", 440b9c1b51eSKate Stone NULL, 441b9c1b51eSKate Stone 4, 442b9c1b51eSKate Stone FPU_OFFSET(3), 443b9c1b51eSKate Stone eEncodingIEEE754, 444b9c1b51eSKate Stone eFormatFloat, 445b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 446b9c1b51eSKate Stone fpu_s3}, 447b9c1b51eSKate Stone nullptr, 448b9c1b51eSKate Stone nullptr, 449b9c1b51eSKate Stone nullptr, 450b9c1b51eSKate Stone 0}, 451b9c1b51eSKate Stone {"s4", 452b9c1b51eSKate Stone NULL, 453b9c1b51eSKate Stone 4, 454b9c1b51eSKate Stone FPU_OFFSET(4), 455b9c1b51eSKate Stone eEncodingIEEE754, 456b9c1b51eSKate Stone eFormatFloat, 457b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 458b9c1b51eSKate Stone fpu_s4}, 459b9c1b51eSKate Stone nullptr, 460b9c1b51eSKate Stone nullptr, 461b9c1b51eSKate Stone nullptr, 462b9c1b51eSKate Stone 0}, 463b9c1b51eSKate Stone {"s5", 464b9c1b51eSKate Stone NULL, 465b9c1b51eSKate Stone 4, 466b9c1b51eSKate Stone FPU_OFFSET(5), 467b9c1b51eSKate Stone eEncodingIEEE754, 468b9c1b51eSKate Stone eFormatFloat, 469b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 470b9c1b51eSKate Stone fpu_s5}, 471b9c1b51eSKate Stone nullptr, 472b9c1b51eSKate Stone nullptr, 473b9c1b51eSKate Stone nullptr, 474b9c1b51eSKate Stone 0}, 475b9c1b51eSKate Stone {"s6", 476b9c1b51eSKate Stone NULL, 477b9c1b51eSKate Stone 4, 478b9c1b51eSKate Stone FPU_OFFSET(6), 479b9c1b51eSKate Stone eEncodingIEEE754, 480b9c1b51eSKate Stone eFormatFloat, 481b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 482b9c1b51eSKate Stone fpu_s6}, 483b9c1b51eSKate Stone nullptr, 484b9c1b51eSKate Stone nullptr, 485b9c1b51eSKate Stone nullptr, 486b9c1b51eSKate Stone 0}, 487b9c1b51eSKate Stone {"s7", 488b9c1b51eSKate Stone NULL, 489b9c1b51eSKate Stone 4, 490b9c1b51eSKate Stone FPU_OFFSET(7), 491b9c1b51eSKate Stone eEncodingIEEE754, 492b9c1b51eSKate Stone eFormatFloat, 493b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 494b9c1b51eSKate Stone fpu_s7}, 495b9c1b51eSKate Stone nullptr, 496b9c1b51eSKate Stone nullptr, 497b9c1b51eSKate Stone nullptr, 498b9c1b51eSKate Stone 0}, 499b9c1b51eSKate Stone {"s8", 500b9c1b51eSKate Stone NULL, 501b9c1b51eSKate Stone 4, 502b9c1b51eSKate Stone FPU_OFFSET(8), 503b9c1b51eSKate Stone eEncodingIEEE754, 504b9c1b51eSKate Stone eFormatFloat, 505b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 506b9c1b51eSKate Stone fpu_s8}, 507b9c1b51eSKate Stone nullptr, 508b9c1b51eSKate Stone nullptr, 509b9c1b51eSKate Stone nullptr, 510b9c1b51eSKate Stone 0}, 511b9c1b51eSKate Stone {"s9", 512b9c1b51eSKate Stone NULL, 513b9c1b51eSKate Stone 4, 514b9c1b51eSKate Stone FPU_OFFSET(9), 515b9c1b51eSKate Stone eEncodingIEEE754, 516b9c1b51eSKate Stone eFormatFloat, 517b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 518b9c1b51eSKate Stone fpu_s9}, 519b9c1b51eSKate Stone nullptr, 520b9c1b51eSKate Stone nullptr, 521b9c1b51eSKate Stone nullptr, 522b9c1b51eSKate Stone 0}, 523b9c1b51eSKate Stone {"s10", 524b9c1b51eSKate Stone NULL, 525b9c1b51eSKate Stone 4, 526b9c1b51eSKate Stone FPU_OFFSET(10), 527b9c1b51eSKate Stone eEncodingIEEE754, 528b9c1b51eSKate Stone eFormatFloat, 529b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 530b9c1b51eSKate Stone fpu_s10}, 531b9c1b51eSKate Stone nullptr, 532b9c1b51eSKate Stone nullptr, 533b9c1b51eSKate Stone nullptr, 534b9c1b51eSKate Stone 0}, 535b9c1b51eSKate Stone {"s11", 536b9c1b51eSKate Stone NULL, 537b9c1b51eSKate Stone 4, 538b9c1b51eSKate Stone FPU_OFFSET(11), 539b9c1b51eSKate Stone eEncodingIEEE754, 540b9c1b51eSKate Stone eFormatFloat, 541b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 542b9c1b51eSKate Stone fpu_s11}, 543b9c1b51eSKate Stone nullptr, 544b9c1b51eSKate Stone nullptr, 545b9c1b51eSKate Stone nullptr, 546b9c1b51eSKate Stone 0}, 547b9c1b51eSKate Stone {"s12", 548b9c1b51eSKate Stone NULL, 549b9c1b51eSKate Stone 4, 550b9c1b51eSKate Stone FPU_OFFSET(12), 551b9c1b51eSKate Stone eEncodingIEEE754, 552b9c1b51eSKate Stone eFormatFloat, 553b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 554b9c1b51eSKate Stone fpu_s12}, 555b9c1b51eSKate Stone nullptr, 556b9c1b51eSKate Stone nullptr, 557b9c1b51eSKate Stone nullptr, 558b9c1b51eSKate Stone 0}, 559b9c1b51eSKate Stone {"s13", 560b9c1b51eSKate Stone NULL, 561b9c1b51eSKate Stone 4, 562b9c1b51eSKate Stone FPU_OFFSET(13), 563b9c1b51eSKate Stone eEncodingIEEE754, 564b9c1b51eSKate Stone eFormatFloat, 565b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 566b9c1b51eSKate Stone fpu_s13}, 567b9c1b51eSKate Stone nullptr, 568b9c1b51eSKate Stone nullptr, 569b9c1b51eSKate Stone nullptr, 570b9c1b51eSKate Stone 0}, 571b9c1b51eSKate Stone {"s14", 572b9c1b51eSKate Stone NULL, 573b9c1b51eSKate Stone 4, 574b9c1b51eSKate Stone FPU_OFFSET(14), 575b9c1b51eSKate Stone eEncodingIEEE754, 576b9c1b51eSKate Stone eFormatFloat, 577b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 578b9c1b51eSKate Stone fpu_s14}, 579b9c1b51eSKate Stone nullptr, 580b9c1b51eSKate Stone nullptr, 581b9c1b51eSKate Stone nullptr, 582b9c1b51eSKate Stone 0}, 583b9c1b51eSKate Stone {"s15", 584b9c1b51eSKate Stone NULL, 585b9c1b51eSKate Stone 4, 586b9c1b51eSKate Stone FPU_OFFSET(15), 587b9c1b51eSKate Stone eEncodingIEEE754, 588b9c1b51eSKate Stone eFormatFloat, 589b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 590b9c1b51eSKate Stone fpu_s15}, 591b9c1b51eSKate Stone nullptr, 592b9c1b51eSKate Stone nullptr, 593b9c1b51eSKate Stone nullptr, 594b9c1b51eSKate Stone 0}, 595b9c1b51eSKate Stone {"s16", 596b9c1b51eSKate Stone NULL, 597b9c1b51eSKate Stone 4, 598b9c1b51eSKate Stone FPU_OFFSET(16), 599b9c1b51eSKate Stone eEncodingIEEE754, 600b9c1b51eSKate Stone eFormatFloat, 601b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 602b9c1b51eSKate Stone fpu_s16}, 603b9c1b51eSKate Stone nullptr, 604b9c1b51eSKate Stone nullptr, 605b9c1b51eSKate Stone nullptr, 606b9c1b51eSKate Stone 0}, 607b9c1b51eSKate Stone {"s17", 608b9c1b51eSKate Stone NULL, 609b9c1b51eSKate Stone 4, 610b9c1b51eSKate Stone FPU_OFFSET(17), 611b9c1b51eSKate Stone eEncodingIEEE754, 612b9c1b51eSKate Stone eFormatFloat, 613b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 614b9c1b51eSKate Stone fpu_s17}, 615b9c1b51eSKate Stone nullptr, 616b9c1b51eSKate Stone nullptr, 617b9c1b51eSKate Stone nullptr, 618b9c1b51eSKate Stone 0}, 619b9c1b51eSKate Stone {"s18", 620b9c1b51eSKate Stone NULL, 621b9c1b51eSKate Stone 4, 622b9c1b51eSKate Stone FPU_OFFSET(18), 623b9c1b51eSKate Stone eEncodingIEEE754, 624b9c1b51eSKate Stone eFormatFloat, 625b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 626b9c1b51eSKate Stone fpu_s18}, 627b9c1b51eSKate Stone nullptr, 628b9c1b51eSKate Stone nullptr, 629b9c1b51eSKate Stone nullptr, 630b9c1b51eSKate Stone 0}, 631b9c1b51eSKate Stone {"s19", 632b9c1b51eSKate Stone NULL, 633b9c1b51eSKate Stone 4, 634b9c1b51eSKate Stone FPU_OFFSET(19), 635b9c1b51eSKate Stone eEncodingIEEE754, 636b9c1b51eSKate Stone eFormatFloat, 637b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 638b9c1b51eSKate Stone fpu_s19}, 639b9c1b51eSKate Stone nullptr, 640b9c1b51eSKate Stone nullptr, 641b9c1b51eSKate Stone nullptr, 642b9c1b51eSKate Stone 0}, 643b9c1b51eSKate Stone {"s20", 644b9c1b51eSKate Stone NULL, 645b9c1b51eSKate Stone 4, 646b9c1b51eSKate Stone FPU_OFFSET(20), 647b9c1b51eSKate Stone eEncodingIEEE754, 648b9c1b51eSKate Stone eFormatFloat, 649b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 650b9c1b51eSKate Stone fpu_s20}, 651b9c1b51eSKate Stone nullptr, 652b9c1b51eSKate Stone nullptr, 653b9c1b51eSKate Stone nullptr, 654b9c1b51eSKate Stone 0}, 655b9c1b51eSKate Stone {"s21", 656b9c1b51eSKate Stone NULL, 657b9c1b51eSKate Stone 4, 658b9c1b51eSKate Stone FPU_OFFSET(21), 659b9c1b51eSKate Stone eEncodingIEEE754, 660b9c1b51eSKate Stone eFormatFloat, 661b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 662b9c1b51eSKate Stone fpu_s21}, 663b9c1b51eSKate Stone nullptr, 664b9c1b51eSKate Stone nullptr, 665b9c1b51eSKate Stone nullptr, 666b9c1b51eSKate Stone 0}, 667b9c1b51eSKate Stone {"s22", 668b9c1b51eSKate Stone NULL, 669b9c1b51eSKate Stone 4, 670b9c1b51eSKate Stone FPU_OFFSET(22), 671b9c1b51eSKate Stone eEncodingIEEE754, 672b9c1b51eSKate Stone eFormatFloat, 673b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 674b9c1b51eSKate Stone fpu_s22}, 675b9c1b51eSKate Stone nullptr, 676b9c1b51eSKate Stone nullptr, 677b9c1b51eSKate Stone nullptr, 678b9c1b51eSKate Stone 0}, 679b9c1b51eSKate Stone {"s23", 680b9c1b51eSKate Stone NULL, 681b9c1b51eSKate Stone 4, 682b9c1b51eSKate Stone FPU_OFFSET(23), 683b9c1b51eSKate Stone eEncodingIEEE754, 684b9c1b51eSKate Stone eFormatFloat, 685b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 686b9c1b51eSKate Stone fpu_s23}, 687b9c1b51eSKate Stone nullptr, 688b9c1b51eSKate Stone nullptr, 689b9c1b51eSKate Stone nullptr, 690b9c1b51eSKate Stone 0}, 691b9c1b51eSKate Stone {"s24", 692b9c1b51eSKate Stone NULL, 693b9c1b51eSKate Stone 4, 694b9c1b51eSKate Stone FPU_OFFSET(24), 695b9c1b51eSKate Stone eEncodingIEEE754, 696b9c1b51eSKate Stone eFormatFloat, 697b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 698b9c1b51eSKate Stone fpu_s24}, 699b9c1b51eSKate Stone nullptr, 700b9c1b51eSKate Stone nullptr, 701b9c1b51eSKate Stone nullptr, 702b9c1b51eSKate Stone 0}, 703b9c1b51eSKate Stone {"s25", 704b9c1b51eSKate Stone NULL, 705b9c1b51eSKate Stone 4, 706b9c1b51eSKate Stone FPU_OFFSET(25), 707b9c1b51eSKate Stone eEncodingIEEE754, 708b9c1b51eSKate Stone eFormatFloat, 709b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 710b9c1b51eSKate Stone fpu_s25}, 711b9c1b51eSKate Stone nullptr, 712b9c1b51eSKate Stone nullptr, 713b9c1b51eSKate Stone nullptr, 714b9c1b51eSKate Stone 0}, 715b9c1b51eSKate Stone {"s26", 716b9c1b51eSKate Stone NULL, 717b9c1b51eSKate Stone 4, 718b9c1b51eSKate Stone FPU_OFFSET(26), 719b9c1b51eSKate Stone eEncodingIEEE754, 720b9c1b51eSKate Stone eFormatFloat, 721b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 722b9c1b51eSKate Stone fpu_s26}, 723b9c1b51eSKate Stone nullptr, 724b9c1b51eSKate Stone nullptr, 725b9c1b51eSKate Stone nullptr, 726b9c1b51eSKate Stone 0}, 727b9c1b51eSKate Stone {"s27", 728b9c1b51eSKate Stone NULL, 729b9c1b51eSKate Stone 4, 730b9c1b51eSKate Stone FPU_OFFSET(27), 731b9c1b51eSKate Stone eEncodingIEEE754, 732b9c1b51eSKate Stone eFormatFloat, 733b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 734b9c1b51eSKate Stone fpu_s27}, 735b9c1b51eSKate Stone nullptr, 736b9c1b51eSKate Stone nullptr, 737b9c1b51eSKate Stone nullptr, 738b9c1b51eSKate Stone 0}, 739b9c1b51eSKate Stone {"s28", 740b9c1b51eSKate Stone NULL, 741b9c1b51eSKate Stone 4, 742b9c1b51eSKate Stone FPU_OFFSET(28), 743b9c1b51eSKate Stone eEncodingIEEE754, 744b9c1b51eSKate Stone eFormatFloat, 745b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 746b9c1b51eSKate Stone fpu_s28}, 747b9c1b51eSKate Stone nullptr, 748b9c1b51eSKate Stone nullptr, 749b9c1b51eSKate Stone nullptr, 750b9c1b51eSKate Stone 0}, 751b9c1b51eSKate Stone {"s29", 752b9c1b51eSKate Stone NULL, 753b9c1b51eSKate Stone 4, 754b9c1b51eSKate Stone FPU_OFFSET(29), 755b9c1b51eSKate Stone eEncodingIEEE754, 756b9c1b51eSKate Stone eFormatFloat, 757b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 758b9c1b51eSKate Stone fpu_s29}, 759b9c1b51eSKate Stone nullptr, 760b9c1b51eSKate Stone nullptr, 761b9c1b51eSKate Stone nullptr, 762b9c1b51eSKate Stone 0}, 763b9c1b51eSKate Stone {"s30", 764b9c1b51eSKate Stone NULL, 765b9c1b51eSKate Stone 4, 766b9c1b51eSKate Stone FPU_OFFSET(30), 767b9c1b51eSKate Stone eEncodingIEEE754, 768b9c1b51eSKate Stone eFormatFloat, 769b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 770b9c1b51eSKate Stone fpu_s30}, 771b9c1b51eSKate Stone nullptr, 772b9c1b51eSKate Stone nullptr, 773b9c1b51eSKate Stone nullptr, 774b9c1b51eSKate Stone 0}, 775b9c1b51eSKate Stone {"s31", 776b9c1b51eSKate Stone NULL, 777b9c1b51eSKate Stone 4, 778b9c1b51eSKate Stone FPU_OFFSET(31), 779b9c1b51eSKate Stone eEncodingIEEE754, 780b9c1b51eSKate Stone eFormatFloat, 781b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 782b9c1b51eSKate Stone fpu_s31}, 783b9c1b51eSKate Stone nullptr, 784b9c1b51eSKate Stone nullptr, 785b9c1b51eSKate Stone nullptr, 786b9c1b51eSKate Stone 0}, 787b9c1b51eSKate Stone {"fpscr", 788b9c1b51eSKate Stone NULL, 789b9c1b51eSKate Stone 4, 790b9c1b51eSKate Stone FPU_OFFSET(32), 791b9c1b51eSKate Stone eEncodingUint, 792b9c1b51eSKate Stone eFormatHex, 793b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 794b9c1b51eSKate Stone LLDB_INVALID_REGNUM, fpu_fpscr}, 795b9c1b51eSKate Stone nullptr, 796b9c1b51eSKate Stone nullptr, 797b9c1b51eSKate Stone nullptr, 798b9c1b51eSKate Stone 0}, 799a63d08c9SGreg Clayton 800b9c1b51eSKate Stone {"exception", 801b9c1b51eSKate Stone NULL, 802b9c1b51eSKate Stone 4, 803b9c1b51eSKate Stone EXC_OFFSET(0), 804b9c1b51eSKate Stone eEncodingUint, 805b9c1b51eSKate Stone eFormatHex, 806b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 807b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_exception}, 808b9c1b51eSKate Stone nullptr, 809b9c1b51eSKate Stone nullptr, 810b9c1b51eSKate Stone nullptr, 811b9c1b51eSKate Stone 0}, 812b9c1b51eSKate Stone {"fsr", 813b9c1b51eSKate Stone NULL, 814b9c1b51eSKate Stone 4, 815b9c1b51eSKate Stone EXC_OFFSET(1), 816b9c1b51eSKate Stone eEncodingUint, 817b9c1b51eSKate Stone eFormatHex, 818b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 819b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_fsr}, 820b9c1b51eSKate Stone nullptr, 821b9c1b51eSKate Stone nullptr, 822b9c1b51eSKate Stone nullptr, 823b9c1b51eSKate Stone 0}, 824b9c1b51eSKate Stone {"far", 825b9c1b51eSKate Stone NULL, 826b9c1b51eSKate Stone 4, 827b9c1b51eSKate Stone EXC_OFFSET(2), 828b9c1b51eSKate Stone eEncodingUint, 829b9c1b51eSKate Stone eFormatHex, 830b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 831b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_far}, 832b9c1b51eSKate Stone nullptr, 833b9c1b51eSKate Stone nullptr, 834b9c1b51eSKate Stone nullptr, 835b9c1b51eSKate Stone 0}, 836a63d08c9SGreg Clayton 837a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 0)}, 838a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 1)}, 839a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 2)}, 840a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 3)}, 841a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 4)}, 842a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 5)}, 843a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 6)}, 844a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 7)}, 845a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 8)}, 846a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 9)}, 847a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 10)}, 848a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 11)}, 849a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 12)}, 850a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 13)}, 851a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 14)}, 852a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 15)}, 853a63d08c9SGreg Clayton 854a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 0)}, 855a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 1)}, 856a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 2)}, 857a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 3)}, 858a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 4)}, 859a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 5)}, 860a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 6)}, 861a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 7)}, 862a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 8)}, 863a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 9)}, 864a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 10)}, 865a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 11)}, 866a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 12)}, 867a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 13)}, 868a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 14)}, 869a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 15)}, 870a63d08c9SGreg Clayton 871a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 0)}, 872a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 1)}, 873a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 2)}, 874a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 3)}, 875a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 4)}, 876a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 5)}, 877a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 6)}, 878a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 7)}, 879a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 8)}, 880a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 9)}, 881a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 10)}, 882a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 11)}, 883a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 12)}, 884a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 13)}, 885a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 14)}, 886a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 15)}, 887a63d08c9SGreg Clayton 888a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 0)}, 889a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 1)}, 890a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 2)}, 891a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 3)}, 892a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 4)}, 893a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 5)}, 894a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 6)}, 895a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 7)}, 896a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 8)}, 897a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 9)}, 898a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 10)}, 899a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 11)}, 900a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 12)}, 901a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 13)}, 902a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 14)}, 903b9c1b51eSKate Stone {DEFINE_DBG(wcr, 15)}}; 904a63d08c9SGreg Clayton 905a63d08c9SGreg Clayton // General purpose registers 906b9c1b51eSKate Stone static uint32_t g_gpr_regnums[] = { 907b9c1b51eSKate Stone gpr_r0, gpr_r1, gpr_r2, gpr_r3, gpr_r4, gpr_r5, gpr_r6, gpr_r7, gpr_r8, 908b9c1b51eSKate Stone gpr_r9, gpr_r10, gpr_r11, gpr_r12, gpr_sp, gpr_lr, gpr_pc, gpr_cpsr}; 909a63d08c9SGreg Clayton 910a63d08c9SGreg Clayton // Floating point registers 911b9c1b51eSKate Stone static uint32_t g_fpu_regnums[] = { 912b9c1b51eSKate Stone fpu_s0, fpu_s1, fpu_s2, fpu_s3, fpu_s4, fpu_s5, fpu_s6, 913b9c1b51eSKate Stone fpu_s7, fpu_s8, fpu_s9, fpu_s10, fpu_s11, fpu_s12, fpu_s13, 914b9c1b51eSKate Stone fpu_s14, fpu_s15, fpu_s16, fpu_s17, fpu_s18, fpu_s19, fpu_s20, 915b9c1b51eSKate Stone fpu_s21, fpu_s22, fpu_s23, fpu_s24, fpu_s25, fpu_s26, fpu_s27, 916b9c1b51eSKate Stone fpu_s28, fpu_s29, fpu_s30, fpu_s31, fpu_fpscr, 917a63d08c9SGreg Clayton }; 918a63d08c9SGreg Clayton 919a63d08c9SGreg Clayton // Exception registers 920a63d08c9SGreg Clayton 921b9c1b51eSKate Stone static uint32_t g_exc_regnums[] = { 922b9c1b51eSKate Stone exc_exception, exc_fsr, exc_far, 923a63d08c9SGreg Clayton }; 924a63d08c9SGreg Clayton 92528606954SSaleem Abdulrasool static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos); 926a63d08c9SGreg Clayton 927b9c1b51eSKate Stone RegisterContextDarwin_arm::RegisterContextDarwin_arm( 928b9c1b51eSKate Stone Thread &thread, uint32_t concrete_frame_idx) 929b9c1b51eSKate Stone : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() { 93063bd0db0SJason Molenda uint32_t i; 931b9c1b51eSKate Stone for (i = 0; i < kNumErrors; i++) { 93263bd0db0SJason Molenda gpr_errs[i] = -1; 93363bd0db0SJason Molenda fpu_errs[i] = -1; 93463bd0db0SJason Molenda exc_errs[i] = -1; 93563bd0db0SJason Molenda } 93663bd0db0SJason Molenda } 93763bd0db0SJason Molenda 938b9c1b51eSKate Stone RegisterContextDarwin_arm::~RegisterContextDarwin_arm() {} 93963bd0db0SJason Molenda 940b9c1b51eSKate Stone void RegisterContextDarwin_arm::InvalidateAllRegisters() { 941a63d08c9SGreg Clayton InvalidateAllRegisterStates(); 942a63d08c9SGreg Clayton } 943a63d08c9SGreg Clayton 944b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterCount() { 945a63d08c9SGreg Clayton assert(k_num_register_infos == k_num_registers); 946a63d08c9SGreg Clayton return k_num_registers; 947a63d08c9SGreg Clayton } 948a63d08c9SGreg Clayton 949a63d08c9SGreg Clayton const RegisterInfo * 950b9c1b51eSKate Stone RegisterContextDarwin_arm::GetRegisterInfoAtIndex(size_t reg) { 951a63d08c9SGreg Clayton assert(k_num_register_infos == k_num_registers); 952a63d08c9SGreg Clayton if (reg < k_num_registers) 953a63d08c9SGreg Clayton return &g_register_infos[reg]; 954a63d08c9SGreg Clayton return NULL; 955a63d08c9SGreg Clayton } 956a63d08c9SGreg Clayton 957b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterInfosCount() { 958a63d08c9SGreg Clayton return k_num_register_infos; 959a63d08c9SGreg Clayton } 960a63d08c9SGreg Clayton 961b9c1b51eSKate Stone const RegisterInfo *RegisterContextDarwin_arm::GetRegisterInfos() { 962a63d08c9SGreg Clayton return g_register_infos; 963a63d08c9SGreg Clayton } 964a63d08c9SGreg Clayton 965a63d08c9SGreg Clayton // Number of registers in each register set 96628606954SSaleem Abdulrasool const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums); 96728606954SSaleem Abdulrasool const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums); 96828606954SSaleem Abdulrasool const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums); 969a63d08c9SGreg Clayton 970a63d08c9SGreg Clayton //---------------------------------------------------------------------- 971a63d08c9SGreg Clayton // Register set definitions. The first definitions at register set index 972a63d08c9SGreg Clayton // of zero is for all registers, followed by other registers sets. The 973a63d08c9SGreg Clayton // register information for the all register set need not be filled in. 974a63d08c9SGreg Clayton //---------------------------------------------------------------------- 975b9c1b51eSKate Stone static const RegisterSet g_reg_sets[] = { 976a63d08c9SGreg Clayton { 977b9c1b51eSKate Stone "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, 978b9c1b51eSKate Stone }, 979a63d08c9SGreg Clayton {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums}, 980b9c1b51eSKate Stone {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}}; 981a63d08c9SGreg Clayton 98228606954SSaleem Abdulrasool const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets); 983a63d08c9SGreg Clayton 984b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterSetCount() { 985a63d08c9SGreg Clayton return k_num_regsets; 986a63d08c9SGreg Clayton } 987a63d08c9SGreg Clayton 988b9c1b51eSKate Stone const RegisterSet *RegisterContextDarwin_arm::GetRegisterSet(size_t reg_set) { 989a63d08c9SGreg Clayton if (reg_set < k_num_regsets) 990a63d08c9SGreg Clayton return &g_reg_sets[reg_set]; 991a63d08c9SGreg Clayton return NULL; 992a63d08c9SGreg Clayton } 993a63d08c9SGreg Clayton 994a63d08c9SGreg Clayton //---------------------------------------------------------------------- 995aaa0ba31SBruce Mitchener // Register information definitions for 32 bit i386. 996a63d08c9SGreg Clayton //---------------------------------------------------------------------- 997b9c1b51eSKate Stone int RegisterContextDarwin_arm::GetSetForNativeRegNum(int reg) { 998a63d08c9SGreg Clayton if (reg < fpu_s0) 999a63d08c9SGreg Clayton return GPRRegSet; 1000a63d08c9SGreg Clayton else if (reg < exc_exception) 1001a63d08c9SGreg Clayton return FPURegSet; 1002a63d08c9SGreg Clayton else if (reg < k_num_registers) 1003a63d08c9SGreg Clayton return EXCRegSet; 1004a63d08c9SGreg Clayton return -1; 1005a63d08c9SGreg Clayton } 1006a63d08c9SGreg Clayton 1007b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadGPR(bool force) { 1008a63d08c9SGreg Clayton int set = GPRRegSet; 1009b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1010a63d08c9SGreg Clayton SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr)); 1011a63d08c9SGreg Clayton } 1012a63d08c9SGreg Clayton return GetError(GPRRegSet, Read); 1013a63d08c9SGreg Clayton } 1014a63d08c9SGreg Clayton 1015b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadFPU(bool force) { 1016a63d08c9SGreg Clayton int set = FPURegSet; 1017b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1018a63d08c9SGreg Clayton SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu)); 1019a63d08c9SGreg Clayton } 1020a63d08c9SGreg Clayton return GetError(FPURegSet, Read); 1021a63d08c9SGreg Clayton } 1022a63d08c9SGreg Clayton 1023b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadEXC(bool force) { 1024a63d08c9SGreg Clayton int set = EXCRegSet; 1025b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1026a63d08c9SGreg Clayton SetError(set, Read, DoReadEXC(GetThreadID(), set, exc)); 1027a63d08c9SGreg Clayton } 1028a63d08c9SGreg Clayton return GetError(EXCRegSet, Read); 1029a63d08c9SGreg Clayton } 1030a63d08c9SGreg Clayton 1031b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadDBG(bool force) { 1032a63d08c9SGreg Clayton int set = DBGRegSet; 1033b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1034a63d08c9SGreg Clayton SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg)); 1035a63d08c9SGreg Clayton } 1036a63d08c9SGreg Clayton return GetError(DBGRegSet, Read); 1037a63d08c9SGreg Clayton } 1038a63d08c9SGreg Clayton 1039b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteGPR() { 1040a63d08c9SGreg Clayton int set = GPRRegSet; 1041b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1042a63d08c9SGreg Clayton SetError(set, Write, -1); 1043a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1044a63d08c9SGreg Clayton } 1045a63d08c9SGreg Clayton SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr)); 1046a63d08c9SGreg Clayton SetError(set, Read, -1); 1047a63d08c9SGreg Clayton return GetError(GPRRegSet, Write); 1048a63d08c9SGreg Clayton } 1049a63d08c9SGreg Clayton 1050b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteFPU() { 1051a63d08c9SGreg Clayton int set = FPURegSet; 1052b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1053a63d08c9SGreg Clayton SetError(set, Write, -1); 1054a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1055a63d08c9SGreg Clayton } 1056a63d08c9SGreg Clayton SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu)); 1057a63d08c9SGreg Clayton SetError(set, Read, -1); 1058a63d08c9SGreg Clayton return GetError(FPURegSet, Write); 1059a63d08c9SGreg Clayton } 1060a63d08c9SGreg Clayton 1061b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteEXC() { 1062a63d08c9SGreg Clayton int set = EXCRegSet; 1063b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1064a63d08c9SGreg Clayton SetError(set, Write, -1); 1065a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1066a63d08c9SGreg Clayton } 1067a63d08c9SGreg Clayton SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc)); 1068a63d08c9SGreg Clayton SetError(set, Read, -1); 1069a63d08c9SGreg Clayton return GetError(EXCRegSet, Write); 1070a63d08c9SGreg Clayton } 1071a63d08c9SGreg Clayton 1072b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteDBG() { 1073a63d08c9SGreg Clayton int set = DBGRegSet; 1074b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1075a63d08c9SGreg Clayton SetError(set, Write, -1); 1076a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1077a63d08c9SGreg Clayton } 1078a63d08c9SGreg Clayton SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg)); 1079a63d08c9SGreg Clayton SetError(set, Read, -1); 1080a63d08c9SGreg Clayton return GetError(DBGRegSet, Write); 1081a63d08c9SGreg Clayton } 1082a63d08c9SGreg Clayton 1083b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadRegisterSet(uint32_t set, bool force) { 1084b9c1b51eSKate Stone switch (set) { 1085b9c1b51eSKate Stone case GPRRegSet: 1086b9c1b51eSKate Stone return ReadGPR(force); 1087b9c1b51eSKate Stone case GPRAltRegSet: 1088b9c1b51eSKate Stone return ReadGPR(force); 1089b9c1b51eSKate Stone case FPURegSet: 1090b9c1b51eSKate Stone return ReadFPU(force); 1091b9c1b51eSKate Stone case EXCRegSet: 1092b9c1b51eSKate Stone return ReadEXC(force); 1093b9c1b51eSKate Stone case DBGRegSet: 1094b9c1b51eSKate Stone return ReadDBG(force); 1095b9c1b51eSKate Stone default: 1096b9c1b51eSKate Stone break; 1097a63d08c9SGreg Clayton } 1098a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1099a63d08c9SGreg Clayton } 1100a63d08c9SGreg Clayton 1101b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteRegisterSet(uint32_t set) { 1102a63d08c9SGreg Clayton // Make sure we have a valid context to set. 1103b9c1b51eSKate Stone if (RegisterSetIsCached(set)) { 1104b9c1b51eSKate Stone switch (set) { 1105b9c1b51eSKate Stone case GPRRegSet: 1106b9c1b51eSKate Stone return WriteGPR(); 1107b9c1b51eSKate Stone case GPRAltRegSet: 1108b9c1b51eSKate Stone return WriteGPR(); 1109b9c1b51eSKate Stone case FPURegSet: 1110b9c1b51eSKate Stone return WriteFPU(); 1111b9c1b51eSKate Stone case EXCRegSet: 1112b9c1b51eSKate Stone return WriteEXC(); 1113b9c1b51eSKate Stone case DBGRegSet: 1114b9c1b51eSKate Stone return WriteDBG(); 1115b9c1b51eSKate Stone default: 1116b9c1b51eSKate Stone break; 1117a63d08c9SGreg Clayton } 1118a63d08c9SGreg Clayton } 1119a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1120a63d08c9SGreg Clayton } 1121a63d08c9SGreg Clayton 1122b9c1b51eSKate Stone void RegisterContextDarwin_arm::LogDBGRegisters(Log *log, const DBG &dbg) { 1123b9c1b51eSKate Stone if (log) { 1124a63d08c9SGreg Clayton for (uint32_t i = 0; i < 16; i++) 1125b9c1b51eSKate Stone log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { " 1126b9c1b51eSKate Stone "0x%8.8x, 0x%8.8x }", 1127b9c1b51eSKate Stone i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]); 1128a63d08c9SGreg Clayton } 1129a63d08c9SGreg Clayton } 1130a63d08c9SGreg Clayton 1131b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ReadRegister(const RegisterInfo *reg_info, 1132b9c1b51eSKate Stone RegisterValue &value) { 1133a63d08c9SGreg Clayton const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 1134a63d08c9SGreg Clayton int set = RegisterContextDarwin_arm::GetSetForNativeRegNum(reg); 1135a63d08c9SGreg Clayton 1136a63d08c9SGreg Clayton if (set == -1) 1137a63d08c9SGreg Clayton return false; 1138a63d08c9SGreg Clayton 1139a63d08c9SGreg Clayton if (ReadRegisterSet(set, false) != KERN_SUCCESS) 1140a63d08c9SGreg Clayton return false; 1141a63d08c9SGreg Clayton 1142b9c1b51eSKate Stone switch (reg) { 1143a63d08c9SGreg Clayton case gpr_r0: 1144a63d08c9SGreg Clayton case gpr_r1: 1145a63d08c9SGreg Clayton case gpr_r2: 1146a63d08c9SGreg Clayton case gpr_r3: 1147a63d08c9SGreg Clayton case gpr_r4: 1148a63d08c9SGreg Clayton case gpr_r5: 1149a63d08c9SGreg Clayton case gpr_r6: 1150a63d08c9SGreg Clayton case gpr_r7: 1151a63d08c9SGreg Clayton case gpr_r8: 1152a63d08c9SGreg Clayton case gpr_r9: 1153a63d08c9SGreg Clayton case gpr_r10: 1154a63d08c9SGreg Clayton case gpr_r11: 1155a63d08c9SGreg Clayton case gpr_r12: 1156a63d08c9SGreg Clayton case gpr_sp: 1157a63d08c9SGreg Clayton case gpr_lr: 1158a63d08c9SGreg Clayton case gpr_pc: 1159a63d08c9SGreg Clayton case gpr_cpsr: 1160a63d08c9SGreg Clayton value.SetUInt32(gpr.r[reg - gpr_r0]); 1161a63d08c9SGreg Clayton break; 1162a63d08c9SGreg Clayton 1163a63d08c9SGreg Clayton case fpu_s0: 1164a63d08c9SGreg Clayton case fpu_s1: 1165a63d08c9SGreg Clayton case fpu_s2: 1166a63d08c9SGreg Clayton case fpu_s3: 1167a63d08c9SGreg Clayton case fpu_s4: 1168a63d08c9SGreg Clayton case fpu_s5: 1169a63d08c9SGreg Clayton case fpu_s6: 1170a63d08c9SGreg Clayton case fpu_s7: 1171a63d08c9SGreg Clayton case fpu_s8: 1172a63d08c9SGreg Clayton case fpu_s9: 1173a63d08c9SGreg Clayton case fpu_s10: 1174a63d08c9SGreg Clayton case fpu_s11: 1175a63d08c9SGreg Clayton case fpu_s12: 1176a63d08c9SGreg Clayton case fpu_s13: 1177a63d08c9SGreg Clayton case fpu_s14: 1178a63d08c9SGreg Clayton case fpu_s15: 1179a63d08c9SGreg Clayton case fpu_s16: 1180a63d08c9SGreg Clayton case fpu_s17: 1181a63d08c9SGreg Clayton case fpu_s18: 1182a63d08c9SGreg Clayton case fpu_s19: 1183a63d08c9SGreg Clayton case fpu_s20: 1184a63d08c9SGreg Clayton case fpu_s21: 1185a63d08c9SGreg Clayton case fpu_s22: 1186a63d08c9SGreg Clayton case fpu_s23: 1187a63d08c9SGreg Clayton case fpu_s24: 1188a63d08c9SGreg Clayton case fpu_s25: 1189a63d08c9SGreg Clayton case fpu_s26: 1190a63d08c9SGreg Clayton case fpu_s27: 1191a63d08c9SGreg Clayton case fpu_s28: 1192a63d08c9SGreg Clayton case fpu_s29: 1193a63d08c9SGreg Clayton case fpu_s30: 1194a63d08c9SGreg Clayton case fpu_s31: 1195a63d08c9SGreg Clayton value.SetUInt32(fpu.floats.s[reg], RegisterValue::eTypeFloat); 1196a63d08c9SGreg Clayton break; 1197a63d08c9SGreg Clayton 1198a63d08c9SGreg Clayton case fpu_fpscr: 1199a63d08c9SGreg Clayton value.SetUInt32(fpu.fpscr); 1200a63d08c9SGreg Clayton break; 1201a63d08c9SGreg Clayton 1202a63d08c9SGreg Clayton case exc_exception: 1203a63d08c9SGreg Clayton value.SetUInt32(exc.exception); 1204a63d08c9SGreg Clayton break; 1205a63d08c9SGreg Clayton case exc_fsr: 1206a63d08c9SGreg Clayton value.SetUInt32(exc.fsr); 1207a63d08c9SGreg Clayton break; 1208a63d08c9SGreg Clayton case exc_far: 1209a63d08c9SGreg Clayton value.SetUInt32(exc.far); 1210a63d08c9SGreg Clayton break; 1211a63d08c9SGreg Clayton 1212a63d08c9SGreg Clayton default: 1213a63d08c9SGreg Clayton value.SetValueToInvalid(); 1214a63d08c9SGreg Clayton return false; 1215a63d08c9SGreg Clayton } 1216a63d08c9SGreg Clayton return true; 1217a63d08c9SGreg Clayton } 1218a63d08c9SGreg Clayton 1219b9c1b51eSKate Stone bool RegisterContextDarwin_arm::WriteRegister(const RegisterInfo *reg_info, 1220b9c1b51eSKate Stone const RegisterValue &value) { 1221a63d08c9SGreg Clayton const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 1222a63d08c9SGreg Clayton int set = GetSetForNativeRegNum(reg); 1223a63d08c9SGreg Clayton 1224a63d08c9SGreg Clayton if (set == -1) 1225a63d08c9SGreg Clayton return false; 1226a63d08c9SGreg Clayton 1227a63d08c9SGreg Clayton if (ReadRegisterSet(set, false) != KERN_SUCCESS) 1228a63d08c9SGreg Clayton return false; 1229a63d08c9SGreg Clayton 1230b9c1b51eSKate Stone switch (reg) { 1231a63d08c9SGreg Clayton case gpr_r0: 1232a63d08c9SGreg Clayton case gpr_r1: 1233a63d08c9SGreg Clayton case gpr_r2: 1234a63d08c9SGreg Clayton case gpr_r3: 1235a63d08c9SGreg Clayton case gpr_r4: 1236a63d08c9SGreg Clayton case gpr_r5: 1237a63d08c9SGreg Clayton case gpr_r6: 1238a63d08c9SGreg Clayton case gpr_r7: 1239a63d08c9SGreg Clayton case gpr_r8: 1240a63d08c9SGreg Clayton case gpr_r9: 1241a63d08c9SGreg Clayton case gpr_r10: 1242a63d08c9SGreg Clayton case gpr_r11: 1243a63d08c9SGreg Clayton case gpr_r12: 1244a63d08c9SGreg Clayton case gpr_sp: 1245a63d08c9SGreg Clayton case gpr_lr: 1246a63d08c9SGreg Clayton case gpr_pc: 1247a63d08c9SGreg Clayton case gpr_cpsr: 1248a63d08c9SGreg Clayton gpr.r[reg - gpr_r0] = value.GetAsUInt32(); 1249a63d08c9SGreg Clayton break; 1250a63d08c9SGreg Clayton 1251a63d08c9SGreg Clayton case fpu_s0: 1252a63d08c9SGreg Clayton case fpu_s1: 1253a63d08c9SGreg Clayton case fpu_s2: 1254a63d08c9SGreg Clayton case fpu_s3: 1255a63d08c9SGreg Clayton case fpu_s4: 1256a63d08c9SGreg Clayton case fpu_s5: 1257a63d08c9SGreg Clayton case fpu_s6: 1258a63d08c9SGreg Clayton case fpu_s7: 1259a63d08c9SGreg Clayton case fpu_s8: 1260a63d08c9SGreg Clayton case fpu_s9: 1261a63d08c9SGreg Clayton case fpu_s10: 1262a63d08c9SGreg Clayton case fpu_s11: 1263a63d08c9SGreg Clayton case fpu_s12: 1264a63d08c9SGreg Clayton case fpu_s13: 1265a63d08c9SGreg Clayton case fpu_s14: 1266a63d08c9SGreg Clayton case fpu_s15: 1267a63d08c9SGreg Clayton case fpu_s16: 1268a63d08c9SGreg Clayton case fpu_s17: 1269a63d08c9SGreg Clayton case fpu_s18: 1270a63d08c9SGreg Clayton case fpu_s19: 1271a63d08c9SGreg Clayton case fpu_s20: 1272a63d08c9SGreg Clayton case fpu_s21: 1273a63d08c9SGreg Clayton case fpu_s22: 1274a63d08c9SGreg Clayton case fpu_s23: 1275a63d08c9SGreg Clayton case fpu_s24: 1276a63d08c9SGreg Clayton case fpu_s25: 1277a63d08c9SGreg Clayton case fpu_s26: 1278a63d08c9SGreg Clayton case fpu_s27: 1279a63d08c9SGreg Clayton case fpu_s28: 1280a63d08c9SGreg Clayton case fpu_s29: 1281a63d08c9SGreg Clayton case fpu_s30: 1282a63d08c9SGreg Clayton case fpu_s31: 1283a63d08c9SGreg Clayton fpu.floats.s[reg] = value.GetAsUInt32(); 1284a63d08c9SGreg Clayton break; 1285a63d08c9SGreg Clayton 1286a63d08c9SGreg Clayton case fpu_fpscr: 1287a63d08c9SGreg Clayton fpu.fpscr = value.GetAsUInt32(); 1288a63d08c9SGreg Clayton break; 1289a63d08c9SGreg Clayton 1290a63d08c9SGreg Clayton case exc_exception: 1291a63d08c9SGreg Clayton exc.exception = value.GetAsUInt32(); 1292a63d08c9SGreg Clayton break; 1293a63d08c9SGreg Clayton case exc_fsr: 1294a63d08c9SGreg Clayton exc.fsr = value.GetAsUInt32(); 1295a63d08c9SGreg Clayton break; 1296a63d08c9SGreg Clayton case exc_far: 1297a63d08c9SGreg Clayton exc.far = value.GetAsUInt32(); 1298a63d08c9SGreg Clayton break; 1299a63d08c9SGreg Clayton 1300a63d08c9SGreg Clayton default: 1301a63d08c9SGreg Clayton return false; 1302a63d08c9SGreg Clayton } 1303a63d08c9SGreg Clayton return WriteRegisterSet(set) == KERN_SUCCESS; 1304a63d08c9SGreg Clayton } 1305a63d08c9SGreg Clayton 1306b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ReadAllRegisterValues( 1307b9c1b51eSKate Stone lldb::DataBufferSP &data_sp) { 1308a63d08c9SGreg Clayton data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0)); 1309b9c1b51eSKate Stone if (data_sp && ReadGPR(false) == KERN_SUCCESS && 1310b9c1b51eSKate Stone ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) { 1311a63d08c9SGreg Clayton uint8_t *dst = data_sp->GetBytes(); 1312a63d08c9SGreg Clayton ::memcpy(dst, &gpr, sizeof(gpr)); 1313a63d08c9SGreg Clayton dst += sizeof(gpr); 1314a63d08c9SGreg Clayton 1315a63d08c9SGreg Clayton ::memcpy(dst, &fpu, sizeof(fpu)); 1316a63d08c9SGreg Clayton dst += sizeof(gpr); 1317a63d08c9SGreg Clayton 1318a63d08c9SGreg Clayton ::memcpy(dst, &exc, sizeof(exc)); 1319a63d08c9SGreg Clayton return true; 1320a63d08c9SGreg Clayton } 1321a63d08c9SGreg Clayton return false; 1322a63d08c9SGreg Clayton } 1323a63d08c9SGreg Clayton 1324b9c1b51eSKate Stone bool RegisterContextDarwin_arm::WriteAllRegisterValues( 1325b9c1b51eSKate Stone const lldb::DataBufferSP &data_sp) { 1326b9c1b51eSKate Stone if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) { 1327a63d08c9SGreg Clayton const uint8_t *src = data_sp->GetBytes(); 1328a63d08c9SGreg Clayton ::memcpy(&gpr, src, sizeof(gpr)); 1329a63d08c9SGreg Clayton src += sizeof(gpr); 1330a63d08c9SGreg Clayton 1331a63d08c9SGreg Clayton ::memcpy(&fpu, src, sizeof(fpu)); 1332a63d08c9SGreg Clayton src += sizeof(gpr); 1333a63d08c9SGreg Clayton 1334a63d08c9SGreg Clayton ::memcpy(&exc, src, sizeof(exc)); 1335a63d08c9SGreg Clayton uint32_t success_count = 0; 1336a63d08c9SGreg Clayton if (WriteGPR() == KERN_SUCCESS) 1337a63d08c9SGreg Clayton ++success_count; 1338a63d08c9SGreg Clayton if (WriteFPU() == KERN_SUCCESS) 1339a63d08c9SGreg Clayton ++success_count; 1340a63d08c9SGreg Clayton if (WriteEXC() == KERN_SUCCESS) 1341a63d08c9SGreg Clayton ++success_count; 1342a63d08c9SGreg Clayton return success_count == 3; 1343a63d08c9SGreg Clayton } 1344a63d08c9SGreg Clayton return false; 1345a63d08c9SGreg Clayton } 1346a63d08c9SGreg Clayton 1347b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::ConvertRegisterKindToRegisterNumber( 1348b9c1b51eSKate Stone lldb::RegisterKind kind, uint32_t reg) { 1349b9c1b51eSKate Stone if (kind == eRegisterKindGeneric) { 1350b9c1b51eSKate Stone switch (reg) { 1351b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_PC: 1352b9c1b51eSKate Stone return gpr_pc; 1353b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_SP: 1354b9c1b51eSKate Stone return gpr_sp; 1355b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_FP: 1356b9c1b51eSKate Stone return gpr_r7; 1357b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_RA: 1358b9c1b51eSKate Stone return gpr_lr; 1359b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_FLAGS: 1360b9c1b51eSKate Stone return gpr_cpsr; 1361a63d08c9SGreg Clayton default: 1362a63d08c9SGreg Clayton break; 1363a63d08c9SGreg Clayton } 1364b9c1b51eSKate Stone } else if (kind == eRegisterKindDWARF) { 1365b9c1b51eSKate Stone switch (reg) { 1366b9c1b51eSKate Stone case dwarf_r0: 1367b9c1b51eSKate Stone return gpr_r0; 1368b9c1b51eSKate Stone case dwarf_r1: 1369b9c1b51eSKate Stone return gpr_r1; 1370b9c1b51eSKate Stone case dwarf_r2: 1371b9c1b51eSKate Stone return gpr_r2; 1372b9c1b51eSKate Stone case dwarf_r3: 1373b9c1b51eSKate Stone return gpr_r3; 1374b9c1b51eSKate Stone case dwarf_r4: 1375b9c1b51eSKate Stone return gpr_r4; 1376b9c1b51eSKate Stone case dwarf_r5: 1377b9c1b51eSKate Stone return gpr_r5; 1378b9c1b51eSKate Stone case dwarf_r6: 1379b9c1b51eSKate Stone return gpr_r6; 1380b9c1b51eSKate Stone case dwarf_r7: 1381b9c1b51eSKate Stone return gpr_r7; 1382b9c1b51eSKate Stone case dwarf_r8: 1383b9c1b51eSKate Stone return gpr_r8; 1384b9c1b51eSKate Stone case dwarf_r9: 1385b9c1b51eSKate Stone return gpr_r9; 1386b9c1b51eSKate Stone case dwarf_r10: 1387b9c1b51eSKate Stone return gpr_r10; 1388b9c1b51eSKate Stone case dwarf_r11: 1389b9c1b51eSKate Stone return gpr_r11; 1390b9c1b51eSKate Stone case dwarf_r12: 1391b9c1b51eSKate Stone return gpr_r12; 1392b9c1b51eSKate Stone case dwarf_sp: 1393b9c1b51eSKate Stone return gpr_sp; 1394b9c1b51eSKate Stone case dwarf_lr: 1395b9c1b51eSKate Stone return gpr_lr; 1396b9c1b51eSKate Stone case dwarf_pc: 1397b9c1b51eSKate Stone return gpr_pc; 1398b9c1b51eSKate Stone case dwarf_spsr: 1399b9c1b51eSKate Stone return gpr_cpsr; 1400a63d08c9SGreg Clayton 1401b9c1b51eSKate Stone case dwarf_s0: 1402b9c1b51eSKate Stone return fpu_s0; 1403b9c1b51eSKate Stone case dwarf_s1: 1404b9c1b51eSKate Stone return fpu_s1; 1405b9c1b51eSKate Stone case dwarf_s2: 1406b9c1b51eSKate Stone return fpu_s2; 1407b9c1b51eSKate Stone case dwarf_s3: 1408b9c1b51eSKate Stone return fpu_s3; 1409b9c1b51eSKate Stone case dwarf_s4: 1410b9c1b51eSKate Stone return fpu_s4; 1411b9c1b51eSKate Stone case dwarf_s5: 1412b9c1b51eSKate Stone return fpu_s5; 1413b9c1b51eSKate Stone case dwarf_s6: 1414b9c1b51eSKate Stone return fpu_s6; 1415b9c1b51eSKate Stone case dwarf_s7: 1416b9c1b51eSKate Stone return fpu_s7; 1417b9c1b51eSKate Stone case dwarf_s8: 1418b9c1b51eSKate Stone return fpu_s8; 1419b9c1b51eSKate Stone case dwarf_s9: 1420b9c1b51eSKate Stone return fpu_s9; 1421b9c1b51eSKate Stone case dwarf_s10: 1422b9c1b51eSKate Stone return fpu_s10; 1423b9c1b51eSKate Stone case dwarf_s11: 1424b9c1b51eSKate Stone return fpu_s11; 1425b9c1b51eSKate Stone case dwarf_s12: 1426b9c1b51eSKate Stone return fpu_s12; 1427b9c1b51eSKate Stone case dwarf_s13: 1428b9c1b51eSKate Stone return fpu_s13; 1429b9c1b51eSKate Stone case dwarf_s14: 1430b9c1b51eSKate Stone return fpu_s14; 1431b9c1b51eSKate Stone case dwarf_s15: 1432b9c1b51eSKate Stone return fpu_s15; 1433b9c1b51eSKate Stone case dwarf_s16: 1434b9c1b51eSKate Stone return fpu_s16; 1435b9c1b51eSKate Stone case dwarf_s17: 1436b9c1b51eSKate Stone return fpu_s17; 1437b9c1b51eSKate Stone case dwarf_s18: 1438b9c1b51eSKate Stone return fpu_s18; 1439b9c1b51eSKate Stone case dwarf_s19: 1440b9c1b51eSKate Stone return fpu_s19; 1441b9c1b51eSKate Stone case dwarf_s20: 1442b9c1b51eSKate Stone return fpu_s20; 1443b9c1b51eSKate Stone case dwarf_s21: 1444b9c1b51eSKate Stone return fpu_s21; 1445b9c1b51eSKate Stone case dwarf_s22: 1446b9c1b51eSKate Stone return fpu_s22; 1447b9c1b51eSKate Stone case dwarf_s23: 1448b9c1b51eSKate Stone return fpu_s23; 1449b9c1b51eSKate Stone case dwarf_s24: 1450b9c1b51eSKate Stone return fpu_s24; 1451b9c1b51eSKate Stone case dwarf_s25: 1452b9c1b51eSKate Stone return fpu_s25; 1453b9c1b51eSKate Stone case dwarf_s26: 1454b9c1b51eSKate Stone return fpu_s26; 1455b9c1b51eSKate Stone case dwarf_s27: 1456b9c1b51eSKate Stone return fpu_s27; 1457b9c1b51eSKate Stone case dwarf_s28: 1458b9c1b51eSKate Stone return fpu_s28; 1459b9c1b51eSKate Stone case dwarf_s29: 1460b9c1b51eSKate Stone return fpu_s29; 1461b9c1b51eSKate Stone case dwarf_s30: 1462b9c1b51eSKate Stone return fpu_s30; 1463b9c1b51eSKate Stone case dwarf_s31: 1464b9c1b51eSKate Stone return fpu_s31; 1465a63d08c9SGreg Clayton 1466a63d08c9SGreg Clayton default: 1467a63d08c9SGreg Clayton break; 1468a63d08c9SGreg Clayton } 1469b9c1b51eSKate Stone } else if (kind == eRegisterKindEHFrame) { 1470b9c1b51eSKate Stone switch (reg) { 1471b9c1b51eSKate Stone case ehframe_r0: 1472b9c1b51eSKate Stone return gpr_r0; 1473b9c1b51eSKate Stone case ehframe_r1: 1474b9c1b51eSKate Stone return gpr_r1; 1475b9c1b51eSKate Stone case ehframe_r2: 1476b9c1b51eSKate Stone return gpr_r2; 1477b9c1b51eSKate Stone case ehframe_r3: 1478b9c1b51eSKate Stone return gpr_r3; 1479b9c1b51eSKate Stone case ehframe_r4: 1480b9c1b51eSKate Stone return gpr_r4; 1481b9c1b51eSKate Stone case ehframe_r5: 1482b9c1b51eSKate Stone return gpr_r5; 1483b9c1b51eSKate Stone case ehframe_r6: 1484b9c1b51eSKate Stone return gpr_r6; 1485b9c1b51eSKate Stone case ehframe_r7: 1486b9c1b51eSKate Stone return gpr_r7; 1487b9c1b51eSKate Stone case ehframe_r8: 1488b9c1b51eSKate Stone return gpr_r8; 1489b9c1b51eSKate Stone case ehframe_r9: 1490b9c1b51eSKate Stone return gpr_r9; 1491b9c1b51eSKate Stone case ehframe_r10: 1492b9c1b51eSKate Stone return gpr_r10; 1493b9c1b51eSKate Stone case ehframe_r11: 1494b9c1b51eSKate Stone return gpr_r11; 1495b9c1b51eSKate Stone case ehframe_r12: 1496b9c1b51eSKate Stone return gpr_r12; 1497b9c1b51eSKate Stone case ehframe_sp: 1498b9c1b51eSKate Stone return gpr_sp; 1499b9c1b51eSKate Stone case ehframe_lr: 1500b9c1b51eSKate Stone return gpr_lr; 1501b9c1b51eSKate Stone case ehframe_pc: 1502b9c1b51eSKate Stone return gpr_pc; 1503b9c1b51eSKate Stone case ehframe_cpsr: 1504b9c1b51eSKate Stone return gpr_cpsr; 1505a63d08c9SGreg Clayton } 1506b9c1b51eSKate Stone } else if (kind == eRegisterKindLLDB) { 1507a63d08c9SGreg Clayton return reg; 1508a63d08c9SGreg Clayton } 1509a63d08c9SGreg Clayton return LLDB_INVALID_REGNUM; 1510a63d08c9SGreg Clayton } 1511a63d08c9SGreg Clayton 1512b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::NumSupportedHardwareBreakpoints() { 1513a63d08c9SGreg Clayton #if defined(__arm__) 1514a63d08c9SGreg Clayton // Set the init value to something that will let us know that we need to 1515a63d08c9SGreg Clayton // autodetect how many breakpoints are supported dynamically... 1516a63d08c9SGreg Clayton static uint32_t g_num_supported_hw_breakpoints = UINT32_MAX; 1517b9c1b51eSKate Stone if (g_num_supported_hw_breakpoints == UINT32_MAX) { 1518a63d08c9SGreg Clayton // Set this to zero in case we can't tell if there are any HW breakpoints 1519a63d08c9SGreg Clayton g_num_supported_hw_breakpoints = 0; 1520a63d08c9SGreg Clayton 1521a63d08c9SGreg Clayton uint32_t register_DBGDIDR; 1522a63d08c9SGreg Clayton 1523a63d08c9SGreg Clayton asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 1524dce502edSGreg Clayton g_num_supported_hw_breakpoints = Bits32(register_DBGDIDR, 27, 24); 1525a63d08c9SGreg Clayton // Zero is reserved for the BRP count, so don't increment it if it is zero 1526a63d08c9SGreg Clayton if (g_num_supported_hw_breakpoints > 0) 1527a63d08c9SGreg Clayton g_num_supported_hw_breakpoints++; 1528b9c1b51eSKate Stone // if (log) log->Printf ("DBGDIDR=0x%8.8x (number BRP pairs = %u)", 1529b9c1b51eSKate Stone // register_DBGDIDR, g_num_supported_hw_breakpoints); 1530a63d08c9SGreg Clayton } 1531a63d08c9SGreg Clayton return g_num_supported_hw_breakpoints; 1532a63d08c9SGreg Clayton #else 1533a63d08c9SGreg Clayton // TODO: figure out remote case here! 1534a63d08c9SGreg Clayton return 6; 1535a63d08c9SGreg Clayton #endif 1536a63d08c9SGreg Clayton } 1537a63d08c9SGreg Clayton 1538b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::SetHardwareBreakpoint(lldb::addr_t addr, 1539b9c1b51eSKate Stone size_t size) { 1540a63d08c9SGreg Clayton // Make sure our address isn't bogus 1541a63d08c9SGreg Clayton if (addr & 1) 1542a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1543a63d08c9SGreg Clayton 1544a63d08c9SGreg Clayton int kret = ReadDBG(false); 1545a63d08c9SGreg Clayton 1546b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1547a63d08c9SGreg Clayton const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints(); 1548a63d08c9SGreg Clayton uint32_t i; 1549b9c1b51eSKate Stone for (i = 0; i < num_hw_breakpoints; ++i) { 1550a63d08c9SGreg Clayton if ((dbg.bcr[i] & BCR_ENABLE) == 0) 1551a63d08c9SGreg Clayton break; // We found an available hw breakpoint slot (in i) 1552a63d08c9SGreg Clayton } 1553a63d08c9SGreg Clayton 1554a63d08c9SGreg Clayton // See if we found an available hw breakpoint slot above 1555b9c1b51eSKate Stone if (i < num_hw_breakpoints) { 1556a63d08c9SGreg Clayton // Make sure bits 1:0 are clear in our address 1557a63d08c9SGreg Clayton dbg.bvr[i] = addr & ~((lldb::addr_t)3); 1558a63d08c9SGreg Clayton 1559b9c1b51eSKate Stone if (size == 2 || addr & 2) { 1560a63d08c9SGreg Clayton uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1; 1561a63d08c9SGreg Clayton 1562a63d08c9SGreg Clayton // We have a thumb breakpoint 1563a63d08c9SGreg Clayton // We have an ARM breakpoint 1564a63d08c9SGreg Clayton dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch 1565b9c1b51eSKate Stone byte_addr_select | // Set the correct byte address select 1566b9c1b51eSKate Stone // so we only trigger on the correct 1567b9c1b51eSKate Stone // opcode 1568a63d08c9SGreg Clayton S_USER | // Which modes should this breakpoint stop in? 1569a63d08c9SGreg Clayton BCR_ENABLE; // Enable this hardware breakpoint 1570b9c1b51eSKate Stone // if (log) log->Printf 1571b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 1572b9c1b51eSKate Stone // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 1573b9c1b51eSKate Stone // 0x%8.8x (Thumb)", 157489f138aeSGreg Clayton // addr, 157589f138aeSGreg Clayton // size, 157689f138aeSGreg Clayton // i, 157789f138aeSGreg Clayton // i, 157889f138aeSGreg Clayton // dbg.bvr[i], 157989f138aeSGreg Clayton // dbg.bcr[i]); 1580b9c1b51eSKate Stone } else if (size == 4) { 1581a63d08c9SGreg Clayton // We have an ARM breakpoint 1582b9c1b51eSKate Stone dbg.bcr[i] = 1583b9c1b51eSKate Stone BCR_M_IMVA_MATCH | // Stop on address mismatch 1584a63d08c9SGreg Clayton BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA 1585a63d08c9SGreg Clayton S_USER | // Which modes should this breakpoint stop in? 1586a63d08c9SGreg Clayton BCR_ENABLE; // Enable this hardware breakpoint 1587b9c1b51eSKate Stone // if (log) log->Printf 1588b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 1589b9c1b51eSKate Stone // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 1590b9c1b51eSKate Stone // 0x%8.8x (ARM)", 159189f138aeSGreg Clayton // addr, 159289f138aeSGreg Clayton // size, 159389f138aeSGreg Clayton // i, 159489f138aeSGreg Clayton // i, 159589f138aeSGreg Clayton // dbg.bvr[i], 159689f138aeSGreg Clayton // dbg.bcr[i]); 1597a63d08c9SGreg Clayton } 1598a63d08c9SGreg Clayton 1599a63d08c9SGreg Clayton kret = WriteDBG(); 1600b9c1b51eSKate Stone // if (log) log->Printf 1601b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint() 1602b9c1b51eSKate Stone // WriteDBG() => 0x%8.8x.", kret); 1603a63d08c9SGreg Clayton 1604a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1605a63d08c9SGreg Clayton return i; 1606a63d08c9SGreg Clayton } 160789f138aeSGreg Clayton // else 160889f138aeSGreg Clayton // { 1609b9c1b51eSKate Stone // if (log) log->Printf 1610b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(addr = 1611b9c1b51eSKate Stone // %8.8p, size = %u) => all hardware breakpoint resources are 1612b9c1b51eSKate Stone // being used.", addr, size); 161389f138aeSGreg Clayton // } 1614a63d08c9SGreg Clayton } 1615a63d08c9SGreg Clayton 1616a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1617a63d08c9SGreg Clayton } 1618a63d08c9SGreg Clayton 1619b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ClearHardwareBreakpoint(uint32_t hw_index) { 1620a63d08c9SGreg Clayton int kret = ReadDBG(false); 1621a63d08c9SGreg Clayton 1622a63d08c9SGreg Clayton const uint32_t num_hw_points = NumSupportedHardwareBreakpoints(); 1623b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1624b9c1b51eSKate Stone if (hw_index < num_hw_points) { 1625a63d08c9SGreg Clayton dbg.bcr[hw_index] = 0; 1626b9c1b51eSKate Stone // if (log) log->Printf 1627b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::SetHardwareBreakpoint( %u ) - 1628b9c1b51eSKate Stone // BVR%u = 0x%8.8x BCR%u = 0x%8.8x", 162989f138aeSGreg Clayton // hw_index, 163089f138aeSGreg Clayton // hw_index, 163189f138aeSGreg Clayton // dbg.bvr[hw_index], 163289f138aeSGreg Clayton // hw_index, 163389f138aeSGreg Clayton // dbg.bcr[hw_index]); 1634a63d08c9SGreg Clayton 1635a63d08c9SGreg Clayton kret = WriteDBG(); 1636a63d08c9SGreg Clayton 1637a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1638a63d08c9SGreg Clayton return true; 1639a63d08c9SGreg Clayton } 1640a63d08c9SGreg Clayton } 1641a63d08c9SGreg Clayton return false; 1642a63d08c9SGreg Clayton } 1643a63d08c9SGreg Clayton 1644b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::NumSupportedHardwareWatchpoints() { 1645a63d08c9SGreg Clayton #if defined(__arm__) 1646a63d08c9SGreg Clayton // Set the init value to something that will let us know that we need to 1647a63d08c9SGreg Clayton // autodetect how many watchpoints are supported dynamically... 1648a63d08c9SGreg Clayton static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX; 1649b9c1b51eSKate Stone if (g_num_supported_hw_watchpoints == UINT32_MAX) { 1650a63d08c9SGreg Clayton // Set this to zero in case we can't tell if there are any HW breakpoints 1651a63d08c9SGreg Clayton g_num_supported_hw_watchpoints = 0; 1652a63d08c9SGreg Clayton 1653a63d08c9SGreg Clayton uint32_t register_DBGDIDR; 1654a63d08c9SGreg Clayton asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 1655dce502edSGreg Clayton g_num_supported_hw_watchpoints = Bits32(register_DBGDIDR, 31, 28) + 1; 1656b9c1b51eSKate Stone // if (log) log->Printf ("DBGDIDR=0x%8.8x (number WRP pairs = %u)", 1657b9c1b51eSKate Stone // register_DBGDIDR, g_num_supported_hw_watchpoints); 1658a63d08c9SGreg Clayton } 1659a63d08c9SGreg Clayton return g_num_supported_hw_watchpoints; 1660a63d08c9SGreg Clayton #else 1661a63d08c9SGreg Clayton // TODO: figure out remote case here! 1662a63d08c9SGreg Clayton return 2; 1663a63d08c9SGreg Clayton #endif 1664a63d08c9SGreg Clayton } 1665a63d08c9SGreg Clayton 1666b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::SetHardwareWatchpoint(lldb::addr_t addr, 1667b9c1b51eSKate Stone size_t size, 1668b9c1b51eSKate Stone bool read, 1669b9c1b51eSKate Stone bool write) { 1670b9c1b51eSKate Stone // if (log) log->Printf 1671b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(addr = %8.8p, size 1672b9c1b51eSKate Stone // = %u, read = %u, write = %u)", addr, size, read, write); 1673a63d08c9SGreg Clayton 1674a63d08c9SGreg Clayton const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 1675a63d08c9SGreg Clayton 1676a63d08c9SGreg Clayton // Can't watch zero bytes 1677a63d08c9SGreg Clayton if (size == 0) 1678a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1679a63d08c9SGreg Clayton 1680a63d08c9SGreg Clayton // We must watch for either read or write 1681a63d08c9SGreg Clayton if (read == false && write == false) 1682a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1683a63d08c9SGreg Clayton 1684a63d08c9SGreg Clayton // Can't watch more than 4 bytes per WVR/WCR pair 1685a63d08c9SGreg Clayton if (size > 4) 1686a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1687a63d08c9SGreg Clayton 1688a63d08c9SGreg Clayton // We can only watch up to four bytes that follow a 4 byte aligned address 1689a63d08c9SGreg Clayton // per watchpoint register pair. Since we have at most so we can only watch 1690a63d08c9SGreg Clayton // until the next 4 byte boundary and we need to make sure we can properly 1691a63d08c9SGreg Clayton // encode this. 1692a63d08c9SGreg Clayton uint32_t addr_word_offset = addr % 4; 1693b9c1b51eSKate Stone // if (log) log->Printf 1694b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - 1695b9c1b51eSKate Stone // addr_word_offset = 0x%8.8x", addr_word_offset); 1696a63d08c9SGreg Clayton 1697a63d08c9SGreg Clayton uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset; 1698b9c1b51eSKate Stone // if (log) log->Printf 1699b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - byte_mask = 1700b9c1b51eSKate Stone // 0x%8.8x", byte_mask); 1701a63d08c9SGreg Clayton if (byte_mask > 0xfu) 1702a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1703a63d08c9SGreg Clayton 1704a63d08c9SGreg Clayton // Read the debug state 1705a63d08c9SGreg Clayton int kret = ReadDBG(false); 1706a63d08c9SGreg Clayton 1707b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1708a63d08c9SGreg Clayton // Check to make sure we have the needed hardware support 1709a63d08c9SGreg Clayton uint32_t i = 0; 1710a63d08c9SGreg Clayton 1711b9c1b51eSKate Stone for (i = 0; i < num_hw_watchpoints; ++i) { 1712a63d08c9SGreg Clayton if ((dbg.wcr[i] & WCR_ENABLE) == 0) 1713a63d08c9SGreg Clayton break; // We found an available hw breakpoint slot (in i) 1714a63d08c9SGreg Clayton } 1715a63d08c9SGreg Clayton 1716a63d08c9SGreg Clayton // See if we found an available hw breakpoint slot above 1717b9c1b51eSKate Stone if (i < num_hw_watchpoints) { 1718a63d08c9SGreg Clayton // Make the byte_mask into a valid Byte Address Select mask 1719a63d08c9SGreg Clayton uint32_t byte_address_select = byte_mask << 5; 1720a63d08c9SGreg Clayton // Make sure bits 1:0 are clear in our address 1721a63d08c9SGreg Clayton dbg.wvr[i] = addr & ~((lldb::addr_t)3); 1722b9c1b51eSKate Stone dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA 1723b9c1b51eSKate Stone // that we will watch 1724a63d08c9SGreg Clayton S_USER | // Stop only in user mode 1725a63d08c9SGreg Clayton (read ? WCR_LOAD : 0) | // Stop on read access? 1726a63d08c9SGreg Clayton (write ? WCR_STORE : 0) | // Stop on write access? 1727a63d08c9SGreg Clayton WCR_ENABLE; // Enable this watchpoint; 1728a63d08c9SGreg Clayton 1729a63d08c9SGreg Clayton kret = WriteDBG(); 1730b9c1b51eSKate Stone // if (log) log->Printf 1731b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() 1732b9c1b51eSKate Stone // WriteDBG() => 0x%8.8x.", kret); 1733a63d08c9SGreg Clayton 1734a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1735a63d08c9SGreg Clayton return i; 1736b9c1b51eSKate Stone } else { 1737b9c1b51eSKate Stone // if (log) log->Printf 1738b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(): All 1739b9c1b51eSKate Stone // hardware resources (%u) are in use.", num_hw_watchpoints); 1740a63d08c9SGreg Clayton } 1741a63d08c9SGreg Clayton } 1742a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1743a63d08c9SGreg Clayton } 1744a63d08c9SGreg Clayton 1745b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ClearHardwareWatchpoint(uint32_t hw_index) { 1746a63d08c9SGreg Clayton int kret = ReadDBG(false); 1747a63d08c9SGreg Clayton 1748a63d08c9SGreg Clayton const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 1749b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1750b9c1b51eSKate Stone if (hw_index < num_hw_points) { 1751a63d08c9SGreg Clayton dbg.wcr[hw_index] = 0; 1752b9c1b51eSKate Stone // if (log) log->Printf 1753b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::ClearHardwareWatchpoint( %u ) - 1754b9c1b51eSKate Stone // WVR%u = 0x%8.8x WCR%u = 0x%8.8x", 175589f138aeSGreg Clayton // hw_index, 175689f138aeSGreg Clayton // hw_index, 175789f138aeSGreg Clayton // dbg.wvr[hw_index], 175889f138aeSGreg Clayton // hw_index, 175989f138aeSGreg Clayton // dbg.wcr[hw_index]); 1760a63d08c9SGreg Clayton 1761a63d08c9SGreg Clayton kret = WriteDBG(); 1762a63d08c9SGreg Clayton 1763a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1764a63d08c9SGreg Clayton return true; 1765a63d08c9SGreg Clayton } 1766a63d08c9SGreg Clayton } 1767a63d08c9SGreg Clayton return false; 1768a63d08c9SGreg Clayton } 1769a63d08c9SGreg Clayton 1770a67dd8fcSPeter Collingbourne #endif 1771