1a63d08c9SGreg Clayton //===-- RegisterContextDarwin_arm.cpp ---------------------------*- C++ -*-===// 2a63d08c9SGreg Clayton // 3*2946cd70SChandler Carruth // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*2946cd70SChandler Carruth // See https://llvm.org/LICENSE.txt for license information. 5*2946cd70SChandler Carruth // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6a63d08c9SGreg Clayton // 7a63d08c9SGreg Clayton //===----------------------------------------------------------------------===// 8a63d08c9SGreg Clayton 9a63d08c9SGreg Clayton #include "RegisterContextDarwin_arm.h" 10981a34c4SPavel Labath #include "RegisterContextDarwinConstants.h" 11a63d08c9SGreg Clayton 12666cc0b2SZachary Turner #include "lldb/Utility/DataBufferHeap.h" 13666cc0b2SZachary Turner #include "lldb/Utility/DataExtractor.h" 1401c3243fSZachary Turner #include "lldb/Utility/Endian.h" 156f9e6901SZachary Turner #include "lldb/Utility/Log.h" 16d821c997SPavel Labath #include "lldb/Utility/RegisterValue.h" 17d821c997SPavel Labath #include "lldb/Utility/Scalar.h" 1812a19904SDaniel Dunbar #include "llvm/Support/Compiler.h" 1912a19904SDaniel Dunbar 20dce502edSGreg Clayton #include "Plugins/Process/Utility/InstructionUtils.h" 21dce502edSGreg Clayton 2212a19904SDaniel Dunbar // Support building against older versions of LLVM, this macro was added 2312a19904SDaniel Dunbar // recently. 2412a19904SDaniel Dunbar #ifndef LLVM_EXTENSION 2512a19904SDaniel Dunbar #define LLVM_EXTENSION 2612a19904SDaniel Dunbar #endif 27a63d08c9SGreg Clayton 28ff9c4ff1SEric Liu #include "Utility/ARM_DWARF_Registers.h" 2963bd0db0SJason Molenda #include "Utility/ARM_ehframe_Registers.h" 30a63d08c9SGreg Clayton 3128606954SSaleem Abdulrasool #include "llvm/ADT/STLExtras.h" 3228606954SSaleem Abdulrasool 33a63d08c9SGreg Clayton using namespace lldb; 34a63d08c9SGreg Clayton using namespace lldb_private; 35a63d08c9SGreg Clayton 36b9c1b51eSKate Stone enum { 37a63d08c9SGreg Clayton gpr_r0 = 0, 38a63d08c9SGreg Clayton gpr_r1, 39a63d08c9SGreg Clayton gpr_r2, 40a63d08c9SGreg Clayton gpr_r3, 41a63d08c9SGreg Clayton gpr_r4, 42a63d08c9SGreg Clayton gpr_r5, 43a63d08c9SGreg Clayton gpr_r6, 44a63d08c9SGreg Clayton gpr_r7, 45a63d08c9SGreg Clayton gpr_r8, 46a63d08c9SGreg Clayton gpr_r9, 47a63d08c9SGreg Clayton gpr_r10, 48a63d08c9SGreg Clayton gpr_r11, 49a63d08c9SGreg Clayton gpr_r12, 50b9c1b51eSKate Stone gpr_r13, 51b9c1b51eSKate Stone gpr_sp = gpr_r13, 52b9c1b51eSKate Stone gpr_r14, 53b9c1b51eSKate Stone gpr_lr = gpr_r14, 54b9c1b51eSKate Stone gpr_r15, 55b9c1b51eSKate Stone gpr_pc = gpr_r15, 56a63d08c9SGreg Clayton gpr_cpsr, 57a63d08c9SGreg Clayton 58a63d08c9SGreg Clayton fpu_s0, 59a63d08c9SGreg Clayton fpu_s1, 60a63d08c9SGreg Clayton fpu_s2, 61a63d08c9SGreg Clayton fpu_s3, 62a63d08c9SGreg Clayton fpu_s4, 63a63d08c9SGreg Clayton fpu_s5, 64a63d08c9SGreg Clayton fpu_s6, 65a63d08c9SGreg Clayton fpu_s7, 66a63d08c9SGreg Clayton fpu_s8, 67a63d08c9SGreg Clayton fpu_s9, 68a63d08c9SGreg Clayton fpu_s10, 69a63d08c9SGreg Clayton fpu_s11, 70a63d08c9SGreg Clayton fpu_s12, 71a63d08c9SGreg Clayton fpu_s13, 72a63d08c9SGreg Clayton fpu_s14, 73a63d08c9SGreg Clayton fpu_s15, 74a63d08c9SGreg Clayton fpu_s16, 75a63d08c9SGreg Clayton fpu_s17, 76a63d08c9SGreg Clayton fpu_s18, 77a63d08c9SGreg Clayton fpu_s19, 78a63d08c9SGreg Clayton fpu_s20, 79a63d08c9SGreg Clayton fpu_s21, 80a63d08c9SGreg Clayton fpu_s22, 81a63d08c9SGreg Clayton fpu_s23, 82a63d08c9SGreg Clayton fpu_s24, 83a63d08c9SGreg Clayton fpu_s25, 84a63d08c9SGreg Clayton fpu_s26, 85a63d08c9SGreg Clayton fpu_s27, 86a63d08c9SGreg Clayton fpu_s28, 87a63d08c9SGreg Clayton fpu_s29, 88a63d08c9SGreg Clayton fpu_s30, 89a63d08c9SGreg Clayton fpu_s31, 90a63d08c9SGreg Clayton fpu_fpscr, 91a63d08c9SGreg Clayton 92a63d08c9SGreg Clayton exc_exception, 93a63d08c9SGreg Clayton exc_fsr, 94a63d08c9SGreg Clayton exc_far, 95a63d08c9SGreg Clayton 96a63d08c9SGreg Clayton dbg_bvr0, 97a63d08c9SGreg Clayton dbg_bvr1, 98a63d08c9SGreg Clayton dbg_bvr2, 99a63d08c9SGreg Clayton dbg_bvr3, 100a63d08c9SGreg Clayton dbg_bvr4, 101a63d08c9SGreg Clayton dbg_bvr5, 102a63d08c9SGreg Clayton dbg_bvr6, 103a63d08c9SGreg Clayton dbg_bvr7, 104a63d08c9SGreg Clayton dbg_bvr8, 105a63d08c9SGreg Clayton dbg_bvr9, 106a63d08c9SGreg Clayton dbg_bvr10, 107a63d08c9SGreg Clayton dbg_bvr11, 108a63d08c9SGreg Clayton dbg_bvr12, 109a63d08c9SGreg Clayton dbg_bvr13, 110a63d08c9SGreg Clayton dbg_bvr14, 111a63d08c9SGreg Clayton dbg_bvr15, 112a63d08c9SGreg Clayton 113a63d08c9SGreg Clayton dbg_bcr0, 114a63d08c9SGreg Clayton dbg_bcr1, 115a63d08c9SGreg Clayton dbg_bcr2, 116a63d08c9SGreg Clayton dbg_bcr3, 117a63d08c9SGreg Clayton dbg_bcr4, 118a63d08c9SGreg Clayton dbg_bcr5, 119a63d08c9SGreg Clayton dbg_bcr6, 120a63d08c9SGreg Clayton dbg_bcr7, 121a63d08c9SGreg Clayton dbg_bcr8, 122a63d08c9SGreg Clayton dbg_bcr9, 123a63d08c9SGreg Clayton dbg_bcr10, 124a63d08c9SGreg Clayton dbg_bcr11, 125a63d08c9SGreg Clayton dbg_bcr12, 126a63d08c9SGreg Clayton dbg_bcr13, 127a63d08c9SGreg Clayton dbg_bcr14, 128a63d08c9SGreg Clayton dbg_bcr15, 129a63d08c9SGreg Clayton 130a63d08c9SGreg Clayton dbg_wvr0, 131a63d08c9SGreg Clayton dbg_wvr1, 132a63d08c9SGreg Clayton dbg_wvr2, 133a63d08c9SGreg Clayton dbg_wvr3, 134a63d08c9SGreg Clayton dbg_wvr4, 135a63d08c9SGreg Clayton dbg_wvr5, 136a63d08c9SGreg Clayton dbg_wvr6, 137a63d08c9SGreg Clayton dbg_wvr7, 138a63d08c9SGreg Clayton dbg_wvr8, 139a63d08c9SGreg Clayton dbg_wvr9, 140a63d08c9SGreg Clayton dbg_wvr10, 141a63d08c9SGreg Clayton dbg_wvr11, 142a63d08c9SGreg Clayton dbg_wvr12, 143a63d08c9SGreg Clayton dbg_wvr13, 144a63d08c9SGreg Clayton dbg_wvr14, 145a63d08c9SGreg Clayton dbg_wvr15, 146a63d08c9SGreg Clayton 147a63d08c9SGreg Clayton dbg_wcr0, 148a63d08c9SGreg Clayton dbg_wcr1, 149a63d08c9SGreg Clayton dbg_wcr2, 150a63d08c9SGreg Clayton dbg_wcr3, 151a63d08c9SGreg Clayton dbg_wcr4, 152a63d08c9SGreg Clayton dbg_wcr5, 153a63d08c9SGreg Clayton dbg_wcr6, 154a63d08c9SGreg Clayton dbg_wcr7, 155a63d08c9SGreg Clayton dbg_wcr8, 156a63d08c9SGreg Clayton dbg_wcr9, 157a63d08c9SGreg Clayton dbg_wcr10, 158a63d08c9SGreg Clayton dbg_wcr11, 159a63d08c9SGreg Clayton dbg_wcr12, 160a63d08c9SGreg Clayton dbg_wcr13, 161a63d08c9SGreg Clayton dbg_wcr14, 162a63d08c9SGreg Clayton dbg_wcr15, 163a63d08c9SGreg Clayton 164a63d08c9SGreg Clayton k_num_registers 165a63d08c9SGreg Clayton }; 166a63d08c9SGreg Clayton 167a63d08c9SGreg Clayton #define GPR_OFFSET(idx) ((idx)*4) 168a63d08c9SGreg Clayton #define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR)) 169b9c1b51eSKate Stone #define EXC_OFFSET(idx) \ 170b9c1b51eSKate Stone ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR) + \ 171b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU)) 172b9c1b51eSKate Stone #define DBG_OFFSET(reg) \ 173b9c1b51eSKate Stone ((LLVM_EXTENSION offsetof(RegisterContextDarwin_arm::DBG, reg) + \ 174b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::GPR) + \ 175b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU) + \ 176b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::EXC))) 177a63d08c9SGreg Clayton 178b9c1b51eSKate Stone #define DEFINE_DBG(reg, i) \ 179b9c1b51eSKate Stone #reg, NULL, sizeof(((RegisterContextDarwin_arm::DBG *) NULL)->reg[i]), \ 180b9c1b51eSKate Stone DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, \ 181b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 182b9c1b51eSKate Stone LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 183b9c1b51eSKate Stone LLDB_INVALID_REGNUM }, \ 184b9c1b51eSKate Stone nullptr, nullptr, nullptr, 0 185b9c1b51eSKate Stone #define REG_CONTEXT_SIZE \ 186b9c1b51eSKate Stone (sizeof(RegisterContextDarwin_arm::GPR) + \ 187b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::FPU) + \ 188b9c1b51eSKate Stone sizeof(RegisterContextDarwin_arm::EXC)) 189a63d08c9SGreg Clayton 190a63d08c9SGreg Clayton static RegisterInfo g_register_infos[] = { 191a63d08c9SGreg Clayton // General purpose registers 192b9c1b51eSKate Stone // NAME ALT SZ OFFSET ENCODING FORMAT 193b9c1b51eSKate Stone // EH_FRAME DWARF GENERIC 194b9c1b51eSKate Stone // PROCESS PLUGIN LLDB NATIVE 195b9c1b51eSKate Stone // ====== ======= == ============= ============= ============ 196b9c1b51eSKate Stone // =============== =============== ========================= 197b9c1b51eSKate Stone // ===================== ============= 198b9c1b51eSKate Stone {"r0", 199b9c1b51eSKate Stone NULL, 200b9c1b51eSKate Stone 4, 201b9c1b51eSKate Stone GPR_OFFSET(0), 202b9c1b51eSKate Stone eEncodingUint, 203b9c1b51eSKate Stone eFormatHex, 204b9c1b51eSKate Stone {ehframe_r0, dwarf_r0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r0}, 205b9c1b51eSKate Stone nullptr, 206b9c1b51eSKate Stone nullptr, 207b9c1b51eSKate Stone nullptr, 208b9c1b51eSKate Stone 0}, 209b9c1b51eSKate Stone {"r1", 210b9c1b51eSKate Stone NULL, 211b9c1b51eSKate Stone 4, 212b9c1b51eSKate Stone GPR_OFFSET(1), 213b9c1b51eSKate Stone eEncodingUint, 214b9c1b51eSKate Stone eFormatHex, 215b9c1b51eSKate Stone {ehframe_r1, dwarf_r1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r1}, 216b9c1b51eSKate Stone nullptr, 217b9c1b51eSKate Stone nullptr, 218b9c1b51eSKate Stone nullptr, 219b9c1b51eSKate Stone 0}, 220b9c1b51eSKate Stone {"r2", 221b9c1b51eSKate Stone NULL, 222b9c1b51eSKate Stone 4, 223b9c1b51eSKate Stone GPR_OFFSET(2), 224b9c1b51eSKate Stone eEncodingUint, 225b9c1b51eSKate Stone eFormatHex, 226b9c1b51eSKate Stone {ehframe_r2, dwarf_r2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r2}, 227b9c1b51eSKate Stone nullptr, 228b9c1b51eSKate Stone nullptr, 229b9c1b51eSKate Stone nullptr, 230b9c1b51eSKate Stone 0}, 231b9c1b51eSKate Stone {"r3", 232b9c1b51eSKate Stone NULL, 233b9c1b51eSKate Stone 4, 234b9c1b51eSKate Stone GPR_OFFSET(3), 235b9c1b51eSKate Stone eEncodingUint, 236b9c1b51eSKate Stone eFormatHex, 237b9c1b51eSKate Stone {ehframe_r3, dwarf_r3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r3}, 238b9c1b51eSKate Stone nullptr, 239b9c1b51eSKate Stone nullptr, 240b9c1b51eSKate Stone nullptr, 241b9c1b51eSKate Stone 0}, 242b9c1b51eSKate Stone {"r4", 243b9c1b51eSKate Stone NULL, 244b9c1b51eSKate Stone 4, 245b9c1b51eSKate Stone GPR_OFFSET(4), 246b9c1b51eSKate Stone eEncodingUint, 247b9c1b51eSKate Stone eFormatHex, 248b9c1b51eSKate Stone {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4}, 249b9c1b51eSKate Stone nullptr, 250b9c1b51eSKate Stone nullptr, 251b9c1b51eSKate Stone nullptr, 252b9c1b51eSKate Stone 0}, 253b9c1b51eSKate Stone {"r5", 254b9c1b51eSKate Stone NULL, 255b9c1b51eSKate Stone 4, 256b9c1b51eSKate Stone GPR_OFFSET(5), 257b9c1b51eSKate Stone eEncodingUint, 258b9c1b51eSKate Stone eFormatHex, 259b9c1b51eSKate Stone {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5}, 260b9c1b51eSKate Stone nullptr, 261b9c1b51eSKate Stone nullptr, 262b9c1b51eSKate Stone nullptr, 263b9c1b51eSKate Stone 0}, 264b9c1b51eSKate Stone {"r6", 265b9c1b51eSKate Stone NULL, 266b9c1b51eSKate Stone 4, 267b9c1b51eSKate Stone GPR_OFFSET(6), 268b9c1b51eSKate Stone eEncodingUint, 269b9c1b51eSKate Stone eFormatHex, 270b9c1b51eSKate Stone {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6}, 271b9c1b51eSKate Stone nullptr, 272b9c1b51eSKate Stone nullptr, 273b9c1b51eSKate Stone nullptr, 274b9c1b51eSKate Stone 0}, 275b9c1b51eSKate Stone {"r7", 276b9c1b51eSKate Stone NULL, 277b9c1b51eSKate Stone 4, 278b9c1b51eSKate Stone GPR_OFFSET(7), 279b9c1b51eSKate Stone eEncodingUint, 280b9c1b51eSKate Stone eFormatHex, 281b9c1b51eSKate Stone {ehframe_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, 282b9c1b51eSKate Stone gpr_r7}, 283b9c1b51eSKate Stone nullptr, 284b9c1b51eSKate Stone nullptr, 285b9c1b51eSKate Stone nullptr, 286b9c1b51eSKate Stone 0}, 287b9c1b51eSKate Stone {"r8", 288b9c1b51eSKate Stone NULL, 289b9c1b51eSKate Stone 4, 290b9c1b51eSKate Stone GPR_OFFSET(8), 291b9c1b51eSKate Stone eEncodingUint, 292b9c1b51eSKate Stone eFormatHex, 293b9c1b51eSKate Stone {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8}, 294b9c1b51eSKate Stone nullptr, 295b9c1b51eSKate Stone nullptr, 296b9c1b51eSKate Stone nullptr, 297b9c1b51eSKate Stone 0}, 298b9c1b51eSKate Stone {"r9", 299b9c1b51eSKate Stone NULL, 300b9c1b51eSKate Stone 4, 301b9c1b51eSKate Stone GPR_OFFSET(9), 302b9c1b51eSKate Stone eEncodingUint, 303b9c1b51eSKate Stone eFormatHex, 304b9c1b51eSKate Stone {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9}, 305b9c1b51eSKate Stone nullptr, 306b9c1b51eSKate Stone nullptr, 307b9c1b51eSKate Stone nullptr, 308b9c1b51eSKate Stone 0}, 309b9c1b51eSKate Stone {"r10", 310b9c1b51eSKate Stone NULL, 311b9c1b51eSKate Stone 4, 312b9c1b51eSKate Stone GPR_OFFSET(10), 313b9c1b51eSKate Stone eEncodingUint, 314b9c1b51eSKate Stone eFormatHex, 315b9c1b51eSKate Stone {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 316b9c1b51eSKate Stone gpr_r10}, 317b9c1b51eSKate Stone nullptr, 318b9c1b51eSKate Stone nullptr, 319b9c1b51eSKate Stone nullptr, 320b9c1b51eSKate Stone 0}, 321b9c1b51eSKate Stone {"r11", 322b9c1b51eSKate Stone NULL, 323b9c1b51eSKate Stone 4, 324b9c1b51eSKate Stone GPR_OFFSET(11), 325b9c1b51eSKate Stone eEncodingUint, 326b9c1b51eSKate Stone eFormatHex, 327b9c1b51eSKate Stone {ehframe_r11, dwarf_r11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 328b9c1b51eSKate Stone gpr_r11}, 329b9c1b51eSKate Stone nullptr, 330b9c1b51eSKate Stone nullptr, 331b9c1b51eSKate Stone nullptr, 332b9c1b51eSKate Stone 0}, 333b9c1b51eSKate Stone {"r12", 334b9c1b51eSKate Stone NULL, 335b9c1b51eSKate Stone 4, 336b9c1b51eSKate Stone GPR_OFFSET(12), 337b9c1b51eSKate Stone eEncodingUint, 338b9c1b51eSKate Stone eFormatHex, 339b9c1b51eSKate Stone {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 340b9c1b51eSKate Stone gpr_r12}, 341b9c1b51eSKate Stone nullptr, 342b9c1b51eSKate Stone nullptr, 343b9c1b51eSKate Stone nullptr, 344b9c1b51eSKate Stone 0}, 345b9c1b51eSKate Stone {"sp", 346b9c1b51eSKate Stone "r13", 347b9c1b51eSKate Stone 4, 348b9c1b51eSKate Stone GPR_OFFSET(13), 349b9c1b51eSKate Stone eEncodingUint, 350b9c1b51eSKate Stone eFormatHex, 351b9c1b51eSKate Stone {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, 352b9c1b51eSKate Stone gpr_sp}, 353b9c1b51eSKate Stone nullptr, 354b9c1b51eSKate Stone nullptr, 355b9c1b51eSKate Stone nullptr, 356b9c1b51eSKate Stone 0}, 357b9c1b51eSKate Stone {"lr", 358b9c1b51eSKate Stone "r14", 359b9c1b51eSKate Stone 4, 360b9c1b51eSKate Stone GPR_OFFSET(14), 361b9c1b51eSKate Stone eEncodingUint, 362b9c1b51eSKate Stone eFormatHex, 363b9c1b51eSKate Stone {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, 364b9c1b51eSKate Stone gpr_lr}, 365b9c1b51eSKate Stone nullptr, 366b9c1b51eSKate Stone nullptr, 367b9c1b51eSKate Stone nullptr, 368b9c1b51eSKate Stone 0}, 369b9c1b51eSKate Stone {"pc", 370b9c1b51eSKate Stone "r15", 371b9c1b51eSKate Stone 4, 372b9c1b51eSKate Stone GPR_OFFSET(15), 373b9c1b51eSKate Stone eEncodingUint, 374b9c1b51eSKate Stone eFormatHex, 375b9c1b51eSKate Stone {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, 376b9c1b51eSKate Stone gpr_pc}, 377b9c1b51eSKate Stone nullptr, 378b9c1b51eSKate Stone nullptr, 379b9c1b51eSKate Stone nullptr, 380b9c1b51eSKate Stone 0}, 381b9c1b51eSKate Stone {"cpsr", 382b9c1b51eSKate Stone "psr", 383b9c1b51eSKate Stone 4, 384b9c1b51eSKate Stone GPR_OFFSET(16), 385b9c1b51eSKate Stone eEncodingUint, 386b9c1b51eSKate Stone eFormatHex, 387b9c1b51eSKate Stone {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM, 388b9c1b51eSKate Stone gpr_cpsr}, 389b9c1b51eSKate Stone nullptr, 390b9c1b51eSKate Stone nullptr, 391b9c1b51eSKate Stone nullptr, 392b9c1b51eSKate Stone 0}, 393a63d08c9SGreg Clayton 394b9c1b51eSKate Stone {"s0", 395b9c1b51eSKate Stone NULL, 396b9c1b51eSKate Stone 4, 397b9c1b51eSKate Stone FPU_OFFSET(0), 398b9c1b51eSKate Stone eEncodingIEEE754, 399b9c1b51eSKate Stone eFormatFloat, 400b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 401b9c1b51eSKate Stone fpu_s0}, 402b9c1b51eSKate Stone nullptr, 403b9c1b51eSKate Stone nullptr, 404b9c1b51eSKate Stone nullptr, 405b9c1b51eSKate Stone 0}, 406b9c1b51eSKate Stone {"s1", 407b9c1b51eSKate Stone NULL, 408b9c1b51eSKate Stone 4, 409b9c1b51eSKate Stone FPU_OFFSET(1), 410b9c1b51eSKate Stone eEncodingIEEE754, 411b9c1b51eSKate Stone eFormatFloat, 412b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 413b9c1b51eSKate Stone fpu_s1}, 414b9c1b51eSKate Stone nullptr, 415b9c1b51eSKate Stone nullptr, 416b9c1b51eSKate Stone nullptr, 417b9c1b51eSKate Stone 0}, 418b9c1b51eSKate Stone {"s2", 419b9c1b51eSKate Stone NULL, 420b9c1b51eSKate Stone 4, 421b9c1b51eSKate Stone FPU_OFFSET(2), 422b9c1b51eSKate Stone eEncodingIEEE754, 423b9c1b51eSKate Stone eFormatFloat, 424b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 425b9c1b51eSKate Stone fpu_s2}, 426b9c1b51eSKate Stone nullptr, 427b9c1b51eSKate Stone nullptr, 428b9c1b51eSKate Stone nullptr, 429b9c1b51eSKate Stone 0}, 430b9c1b51eSKate Stone {"s3", 431b9c1b51eSKate Stone NULL, 432b9c1b51eSKate Stone 4, 433b9c1b51eSKate Stone FPU_OFFSET(3), 434b9c1b51eSKate Stone eEncodingIEEE754, 435b9c1b51eSKate Stone eFormatFloat, 436b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 437b9c1b51eSKate Stone fpu_s3}, 438b9c1b51eSKate Stone nullptr, 439b9c1b51eSKate Stone nullptr, 440b9c1b51eSKate Stone nullptr, 441b9c1b51eSKate Stone 0}, 442b9c1b51eSKate Stone {"s4", 443b9c1b51eSKate Stone NULL, 444b9c1b51eSKate Stone 4, 445b9c1b51eSKate Stone FPU_OFFSET(4), 446b9c1b51eSKate Stone eEncodingIEEE754, 447b9c1b51eSKate Stone eFormatFloat, 448b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 449b9c1b51eSKate Stone fpu_s4}, 450b9c1b51eSKate Stone nullptr, 451b9c1b51eSKate Stone nullptr, 452b9c1b51eSKate Stone nullptr, 453b9c1b51eSKate Stone 0}, 454b9c1b51eSKate Stone {"s5", 455b9c1b51eSKate Stone NULL, 456b9c1b51eSKate Stone 4, 457b9c1b51eSKate Stone FPU_OFFSET(5), 458b9c1b51eSKate Stone eEncodingIEEE754, 459b9c1b51eSKate Stone eFormatFloat, 460b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 461b9c1b51eSKate Stone fpu_s5}, 462b9c1b51eSKate Stone nullptr, 463b9c1b51eSKate Stone nullptr, 464b9c1b51eSKate Stone nullptr, 465b9c1b51eSKate Stone 0}, 466b9c1b51eSKate Stone {"s6", 467b9c1b51eSKate Stone NULL, 468b9c1b51eSKate Stone 4, 469b9c1b51eSKate Stone FPU_OFFSET(6), 470b9c1b51eSKate Stone eEncodingIEEE754, 471b9c1b51eSKate Stone eFormatFloat, 472b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 473b9c1b51eSKate Stone fpu_s6}, 474b9c1b51eSKate Stone nullptr, 475b9c1b51eSKate Stone nullptr, 476b9c1b51eSKate Stone nullptr, 477b9c1b51eSKate Stone 0}, 478b9c1b51eSKate Stone {"s7", 479b9c1b51eSKate Stone NULL, 480b9c1b51eSKate Stone 4, 481b9c1b51eSKate Stone FPU_OFFSET(7), 482b9c1b51eSKate Stone eEncodingIEEE754, 483b9c1b51eSKate Stone eFormatFloat, 484b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 485b9c1b51eSKate Stone fpu_s7}, 486b9c1b51eSKate Stone nullptr, 487b9c1b51eSKate Stone nullptr, 488b9c1b51eSKate Stone nullptr, 489b9c1b51eSKate Stone 0}, 490b9c1b51eSKate Stone {"s8", 491b9c1b51eSKate Stone NULL, 492b9c1b51eSKate Stone 4, 493b9c1b51eSKate Stone FPU_OFFSET(8), 494b9c1b51eSKate Stone eEncodingIEEE754, 495b9c1b51eSKate Stone eFormatFloat, 496b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 497b9c1b51eSKate Stone fpu_s8}, 498b9c1b51eSKate Stone nullptr, 499b9c1b51eSKate Stone nullptr, 500b9c1b51eSKate Stone nullptr, 501b9c1b51eSKate Stone 0}, 502b9c1b51eSKate Stone {"s9", 503b9c1b51eSKate Stone NULL, 504b9c1b51eSKate Stone 4, 505b9c1b51eSKate Stone FPU_OFFSET(9), 506b9c1b51eSKate Stone eEncodingIEEE754, 507b9c1b51eSKate Stone eFormatFloat, 508b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 509b9c1b51eSKate Stone fpu_s9}, 510b9c1b51eSKate Stone nullptr, 511b9c1b51eSKate Stone nullptr, 512b9c1b51eSKate Stone nullptr, 513b9c1b51eSKate Stone 0}, 514b9c1b51eSKate Stone {"s10", 515b9c1b51eSKate Stone NULL, 516b9c1b51eSKate Stone 4, 517b9c1b51eSKate Stone FPU_OFFSET(10), 518b9c1b51eSKate Stone eEncodingIEEE754, 519b9c1b51eSKate Stone eFormatFloat, 520b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 521b9c1b51eSKate Stone fpu_s10}, 522b9c1b51eSKate Stone nullptr, 523b9c1b51eSKate Stone nullptr, 524b9c1b51eSKate Stone nullptr, 525b9c1b51eSKate Stone 0}, 526b9c1b51eSKate Stone {"s11", 527b9c1b51eSKate Stone NULL, 528b9c1b51eSKate Stone 4, 529b9c1b51eSKate Stone FPU_OFFSET(11), 530b9c1b51eSKate Stone eEncodingIEEE754, 531b9c1b51eSKate Stone eFormatFloat, 532b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 533b9c1b51eSKate Stone fpu_s11}, 534b9c1b51eSKate Stone nullptr, 535b9c1b51eSKate Stone nullptr, 536b9c1b51eSKate Stone nullptr, 537b9c1b51eSKate Stone 0}, 538b9c1b51eSKate Stone {"s12", 539b9c1b51eSKate Stone NULL, 540b9c1b51eSKate Stone 4, 541b9c1b51eSKate Stone FPU_OFFSET(12), 542b9c1b51eSKate Stone eEncodingIEEE754, 543b9c1b51eSKate Stone eFormatFloat, 544b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 545b9c1b51eSKate Stone fpu_s12}, 546b9c1b51eSKate Stone nullptr, 547b9c1b51eSKate Stone nullptr, 548b9c1b51eSKate Stone nullptr, 549b9c1b51eSKate Stone 0}, 550b9c1b51eSKate Stone {"s13", 551b9c1b51eSKate Stone NULL, 552b9c1b51eSKate Stone 4, 553b9c1b51eSKate Stone FPU_OFFSET(13), 554b9c1b51eSKate Stone eEncodingIEEE754, 555b9c1b51eSKate Stone eFormatFloat, 556b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 557b9c1b51eSKate Stone fpu_s13}, 558b9c1b51eSKate Stone nullptr, 559b9c1b51eSKate Stone nullptr, 560b9c1b51eSKate Stone nullptr, 561b9c1b51eSKate Stone 0}, 562b9c1b51eSKate Stone {"s14", 563b9c1b51eSKate Stone NULL, 564b9c1b51eSKate Stone 4, 565b9c1b51eSKate Stone FPU_OFFSET(14), 566b9c1b51eSKate Stone eEncodingIEEE754, 567b9c1b51eSKate Stone eFormatFloat, 568b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 569b9c1b51eSKate Stone fpu_s14}, 570b9c1b51eSKate Stone nullptr, 571b9c1b51eSKate Stone nullptr, 572b9c1b51eSKate Stone nullptr, 573b9c1b51eSKate Stone 0}, 574b9c1b51eSKate Stone {"s15", 575b9c1b51eSKate Stone NULL, 576b9c1b51eSKate Stone 4, 577b9c1b51eSKate Stone FPU_OFFSET(15), 578b9c1b51eSKate Stone eEncodingIEEE754, 579b9c1b51eSKate Stone eFormatFloat, 580b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 581b9c1b51eSKate Stone fpu_s15}, 582b9c1b51eSKate Stone nullptr, 583b9c1b51eSKate Stone nullptr, 584b9c1b51eSKate Stone nullptr, 585b9c1b51eSKate Stone 0}, 586b9c1b51eSKate Stone {"s16", 587b9c1b51eSKate Stone NULL, 588b9c1b51eSKate Stone 4, 589b9c1b51eSKate Stone FPU_OFFSET(16), 590b9c1b51eSKate Stone eEncodingIEEE754, 591b9c1b51eSKate Stone eFormatFloat, 592b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 593b9c1b51eSKate Stone fpu_s16}, 594b9c1b51eSKate Stone nullptr, 595b9c1b51eSKate Stone nullptr, 596b9c1b51eSKate Stone nullptr, 597b9c1b51eSKate Stone 0}, 598b9c1b51eSKate Stone {"s17", 599b9c1b51eSKate Stone NULL, 600b9c1b51eSKate Stone 4, 601b9c1b51eSKate Stone FPU_OFFSET(17), 602b9c1b51eSKate Stone eEncodingIEEE754, 603b9c1b51eSKate Stone eFormatFloat, 604b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 605b9c1b51eSKate Stone fpu_s17}, 606b9c1b51eSKate Stone nullptr, 607b9c1b51eSKate Stone nullptr, 608b9c1b51eSKate Stone nullptr, 609b9c1b51eSKate Stone 0}, 610b9c1b51eSKate Stone {"s18", 611b9c1b51eSKate Stone NULL, 612b9c1b51eSKate Stone 4, 613b9c1b51eSKate Stone FPU_OFFSET(18), 614b9c1b51eSKate Stone eEncodingIEEE754, 615b9c1b51eSKate Stone eFormatFloat, 616b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 617b9c1b51eSKate Stone fpu_s18}, 618b9c1b51eSKate Stone nullptr, 619b9c1b51eSKate Stone nullptr, 620b9c1b51eSKate Stone nullptr, 621b9c1b51eSKate Stone 0}, 622b9c1b51eSKate Stone {"s19", 623b9c1b51eSKate Stone NULL, 624b9c1b51eSKate Stone 4, 625b9c1b51eSKate Stone FPU_OFFSET(19), 626b9c1b51eSKate Stone eEncodingIEEE754, 627b9c1b51eSKate Stone eFormatFloat, 628b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 629b9c1b51eSKate Stone fpu_s19}, 630b9c1b51eSKate Stone nullptr, 631b9c1b51eSKate Stone nullptr, 632b9c1b51eSKate Stone nullptr, 633b9c1b51eSKate Stone 0}, 634b9c1b51eSKate Stone {"s20", 635b9c1b51eSKate Stone NULL, 636b9c1b51eSKate Stone 4, 637b9c1b51eSKate Stone FPU_OFFSET(20), 638b9c1b51eSKate Stone eEncodingIEEE754, 639b9c1b51eSKate Stone eFormatFloat, 640b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 641b9c1b51eSKate Stone fpu_s20}, 642b9c1b51eSKate Stone nullptr, 643b9c1b51eSKate Stone nullptr, 644b9c1b51eSKate Stone nullptr, 645b9c1b51eSKate Stone 0}, 646b9c1b51eSKate Stone {"s21", 647b9c1b51eSKate Stone NULL, 648b9c1b51eSKate Stone 4, 649b9c1b51eSKate Stone FPU_OFFSET(21), 650b9c1b51eSKate Stone eEncodingIEEE754, 651b9c1b51eSKate Stone eFormatFloat, 652b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 653b9c1b51eSKate Stone fpu_s21}, 654b9c1b51eSKate Stone nullptr, 655b9c1b51eSKate Stone nullptr, 656b9c1b51eSKate Stone nullptr, 657b9c1b51eSKate Stone 0}, 658b9c1b51eSKate Stone {"s22", 659b9c1b51eSKate Stone NULL, 660b9c1b51eSKate Stone 4, 661b9c1b51eSKate Stone FPU_OFFSET(22), 662b9c1b51eSKate Stone eEncodingIEEE754, 663b9c1b51eSKate Stone eFormatFloat, 664b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 665b9c1b51eSKate Stone fpu_s22}, 666b9c1b51eSKate Stone nullptr, 667b9c1b51eSKate Stone nullptr, 668b9c1b51eSKate Stone nullptr, 669b9c1b51eSKate Stone 0}, 670b9c1b51eSKate Stone {"s23", 671b9c1b51eSKate Stone NULL, 672b9c1b51eSKate Stone 4, 673b9c1b51eSKate Stone FPU_OFFSET(23), 674b9c1b51eSKate Stone eEncodingIEEE754, 675b9c1b51eSKate Stone eFormatFloat, 676b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 677b9c1b51eSKate Stone fpu_s23}, 678b9c1b51eSKate Stone nullptr, 679b9c1b51eSKate Stone nullptr, 680b9c1b51eSKate Stone nullptr, 681b9c1b51eSKate Stone 0}, 682b9c1b51eSKate Stone {"s24", 683b9c1b51eSKate Stone NULL, 684b9c1b51eSKate Stone 4, 685b9c1b51eSKate Stone FPU_OFFSET(24), 686b9c1b51eSKate Stone eEncodingIEEE754, 687b9c1b51eSKate Stone eFormatFloat, 688b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 689b9c1b51eSKate Stone fpu_s24}, 690b9c1b51eSKate Stone nullptr, 691b9c1b51eSKate Stone nullptr, 692b9c1b51eSKate Stone nullptr, 693b9c1b51eSKate Stone 0}, 694b9c1b51eSKate Stone {"s25", 695b9c1b51eSKate Stone NULL, 696b9c1b51eSKate Stone 4, 697b9c1b51eSKate Stone FPU_OFFSET(25), 698b9c1b51eSKate Stone eEncodingIEEE754, 699b9c1b51eSKate Stone eFormatFloat, 700b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 701b9c1b51eSKate Stone fpu_s25}, 702b9c1b51eSKate Stone nullptr, 703b9c1b51eSKate Stone nullptr, 704b9c1b51eSKate Stone nullptr, 705b9c1b51eSKate Stone 0}, 706b9c1b51eSKate Stone {"s26", 707b9c1b51eSKate Stone NULL, 708b9c1b51eSKate Stone 4, 709b9c1b51eSKate Stone FPU_OFFSET(26), 710b9c1b51eSKate Stone eEncodingIEEE754, 711b9c1b51eSKate Stone eFormatFloat, 712b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 713b9c1b51eSKate Stone fpu_s26}, 714b9c1b51eSKate Stone nullptr, 715b9c1b51eSKate Stone nullptr, 716b9c1b51eSKate Stone nullptr, 717b9c1b51eSKate Stone 0}, 718b9c1b51eSKate Stone {"s27", 719b9c1b51eSKate Stone NULL, 720b9c1b51eSKate Stone 4, 721b9c1b51eSKate Stone FPU_OFFSET(27), 722b9c1b51eSKate Stone eEncodingIEEE754, 723b9c1b51eSKate Stone eFormatFloat, 724b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 725b9c1b51eSKate Stone fpu_s27}, 726b9c1b51eSKate Stone nullptr, 727b9c1b51eSKate Stone nullptr, 728b9c1b51eSKate Stone nullptr, 729b9c1b51eSKate Stone 0}, 730b9c1b51eSKate Stone {"s28", 731b9c1b51eSKate Stone NULL, 732b9c1b51eSKate Stone 4, 733b9c1b51eSKate Stone FPU_OFFSET(28), 734b9c1b51eSKate Stone eEncodingIEEE754, 735b9c1b51eSKate Stone eFormatFloat, 736b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 737b9c1b51eSKate Stone fpu_s28}, 738b9c1b51eSKate Stone nullptr, 739b9c1b51eSKate Stone nullptr, 740b9c1b51eSKate Stone nullptr, 741b9c1b51eSKate Stone 0}, 742b9c1b51eSKate Stone {"s29", 743b9c1b51eSKate Stone NULL, 744b9c1b51eSKate Stone 4, 745b9c1b51eSKate Stone FPU_OFFSET(29), 746b9c1b51eSKate Stone eEncodingIEEE754, 747b9c1b51eSKate Stone eFormatFloat, 748b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 749b9c1b51eSKate Stone fpu_s29}, 750b9c1b51eSKate Stone nullptr, 751b9c1b51eSKate Stone nullptr, 752b9c1b51eSKate Stone nullptr, 753b9c1b51eSKate Stone 0}, 754b9c1b51eSKate Stone {"s30", 755b9c1b51eSKate Stone NULL, 756b9c1b51eSKate Stone 4, 757b9c1b51eSKate Stone FPU_OFFSET(30), 758b9c1b51eSKate Stone eEncodingIEEE754, 759b9c1b51eSKate Stone eFormatFloat, 760b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 761b9c1b51eSKate Stone fpu_s30}, 762b9c1b51eSKate Stone nullptr, 763b9c1b51eSKate Stone nullptr, 764b9c1b51eSKate Stone nullptr, 765b9c1b51eSKate Stone 0}, 766b9c1b51eSKate Stone {"s31", 767b9c1b51eSKate Stone NULL, 768b9c1b51eSKate Stone 4, 769b9c1b51eSKate Stone FPU_OFFSET(31), 770b9c1b51eSKate Stone eEncodingIEEE754, 771b9c1b51eSKate Stone eFormatFloat, 772b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 773b9c1b51eSKate Stone fpu_s31}, 774b9c1b51eSKate Stone nullptr, 775b9c1b51eSKate Stone nullptr, 776b9c1b51eSKate Stone nullptr, 777b9c1b51eSKate Stone 0}, 778b9c1b51eSKate Stone {"fpscr", 779b9c1b51eSKate Stone NULL, 780b9c1b51eSKate Stone 4, 781b9c1b51eSKate Stone FPU_OFFSET(32), 782b9c1b51eSKate Stone eEncodingUint, 783b9c1b51eSKate Stone eFormatHex, 784b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 785b9c1b51eSKate Stone LLDB_INVALID_REGNUM, fpu_fpscr}, 786b9c1b51eSKate Stone nullptr, 787b9c1b51eSKate Stone nullptr, 788b9c1b51eSKate Stone nullptr, 789b9c1b51eSKate Stone 0}, 790a63d08c9SGreg Clayton 791b9c1b51eSKate Stone {"exception", 792b9c1b51eSKate Stone NULL, 793b9c1b51eSKate Stone 4, 794b9c1b51eSKate Stone EXC_OFFSET(0), 795b9c1b51eSKate Stone eEncodingUint, 796b9c1b51eSKate Stone eFormatHex, 797b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 798b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_exception}, 799b9c1b51eSKate Stone nullptr, 800b9c1b51eSKate Stone nullptr, 801b9c1b51eSKate Stone nullptr, 802b9c1b51eSKate Stone 0}, 803b9c1b51eSKate Stone {"fsr", 804b9c1b51eSKate Stone NULL, 805b9c1b51eSKate Stone 4, 806b9c1b51eSKate Stone EXC_OFFSET(1), 807b9c1b51eSKate Stone eEncodingUint, 808b9c1b51eSKate Stone eFormatHex, 809b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 810b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_fsr}, 811b9c1b51eSKate Stone nullptr, 812b9c1b51eSKate Stone nullptr, 813b9c1b51eSKate Stone nullptr, 814b9c1b51eSKate Stone 0}, 815b9c1b51eSKate Stone {"far", 816b9c1b51eSKate Stone NULL, 817b9c1b51eSKate Stone 4, 818b9c1b51eSKate Stone EXC_OFFSET(2), 819b9c1b51eSKate Stone eEncodingUint, 820b9c1b51eSKate Stone eFormatHex, 821b9c1b51eSKate Stone {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 822b9c1b51eSKate Stone LLDB_INVALID_REGNUM, exc_far}, 823b9c1b51eSKate Stone nullptr, 824b9c1b51eSKate Stone nullptr, 825b9c1b51eSKate Stone nullptr, 826b9c1b51eSKate Stone 0}, 827a63d08c9SGreg Clayton 828a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 0)}, 829a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 1)}, 830a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 2)}, 831a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 3)}, 832a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 4)}, 833a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 5)}, 834a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 6)}, 835a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 7)}, 836a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 8)}, 837a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 9)}, 838a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 10)}, 839a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 11)}, 840a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 12)}, 841a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 13)}, 842a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 14)}, 843a63d08c9SGreg Clayton {DEFINE_DBG(bvr, 15)}, 844a63d08c9SGreg Clayton 845a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 0)}, 846a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 1)}, 847a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 2)}, 848a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 3)}, 849a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 4)}, 850a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 5)}, 851a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 6)}, 852a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 7)}, 853a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 8)}, 854a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 9)}, 855a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 10)}, 856a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 11)}, 857a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 12)}, 858a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 13)}, 859a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 14)}, 860a63d08c9SGreg Clayton {DEFINE_DBG(bcr, 15)}, 861a63d08c9SGreg Clayton 862a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 0)}, 863a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 1)}, 864a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 2)}, 865a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 3)}, 866a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 4)}, 867a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 5)}, 868a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 6)}, 869a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 7)}, 870a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 8)}, 871a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 9)}, 872a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 10)}, 873a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 11)}, 874a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 12)}, 875a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 13)}, 876a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 14)}, 877a63d08c9SGreg Clayton {DEFINE_DBG(wvr, 15)}, 878a63d08c9SGreg Clayton 879a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 0)}, 880a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 1)}, 881a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 2)}, 882a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 3)}, 883a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 4)}, 884a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 5)}, 885a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 6)}, 886a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 7)}, 887a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 8)}, 888a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 9)}, 889a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 10)}, 890a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 11)}, 891a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 12)}, 892a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 13)}, 893a63d08c9SGreg Clayton {DEFINE_DBG(wcr, 14)}, 894b9c1b51eSKate Stone {DEFINE_DBG(wcr, 15)}}; 895a63d08c9SGreg Clayton 896a63d08c9SGreg Clayton // General purpose registers 897b9c1b51eSKate Stone static uint32_t g_gpr_regnums[] = { 898b9c1b51eSKate Stone gpr_r0, gpr_r1, gpr_r2, gpr_r3, gpr_r4, gpr_r5, gpr_r6, gpr_r7, gpr_r8, 899b9c1b51eSKate Stone gpr_r9, gpr_r10, gpr_r11, gpr_r12, gpr_sp, gpr_lr, gpr_pc, gpr_cpsr}; 900a63d08c9SGreg Clayton 901a63d08c9SGreg Clayton // Floating point registers 902b9c1b51eSKate Stone static uint32_t g_fpu_regnums[] = { 903b9c1b51eSKate Stone fpu_s0, fpu_s1, fpu_s2, fpu_s3, fpu_s4, fpu_s5, fpu_s6, 904b9c1b51eSKate Stone fpu_s7, fpu_s8, fpu_s9, fpu_s10, fpu_s11, fpu_s12, fpu_s13, 905b9c1b51eSKate Stone fpu_s14, fpu_s15, fpu_s16, fpu_s17, fpu_s18, fpu_s19, fpu_s20, 906b9c1b51eSKate Stone fpu_s21, fpu_s22, fpu_s23, fpu_s24, fpu_s25, fpu_s26, fpu_s27, 907b9c1b51eSKate Stone fpu_s28, fpu_s29, fpu_s30, fpu_s31, fpu_fpscr, 908a63d08c9SGreg Clayton }; 909a63d08c9SGreg Clayton 910a63d08c9SGreg Clayton // Exception registers 911a63d08c9SGreg Clayton 912b9c1b51eSKate Stone static uint32_t g_exc_regnums[] = { 913b9c1b51eSKate Stone exc_exception, exc_fsr, exc_far, 914a63d08c9SGreg Clayton }; 915a63d08c9SGreg Clayton 91628606954SSaleem Abdulrasool static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos); 917a63d08c9SGreg Clayton 918b9c1b51eSKate Stone RegisterContextDarwin_arm::RegisterContextDarwin_arm( 919b9c1b51eSKate Stone Thread &thread, uint32_t concrete_frame_idx) 920b9c1b51eSKate Stone : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() { 92163bd0db0SJason Molenda uint32_t i; 922b9c1b51eSKate Stone for (i = 0; i < kNumErrors; i++) { 92363bd0db0SJason Molenda gpr_errs[i] = -1; 92463bd0db0SJason Molenda fpu_errs[i] = -1; 92563bd0db0SJason Molenda exc_errs[i] = -1; 92663bd0db0SJason Molenda } 92763bd0db0SJason Molenda } 92863bd0db0SJason Molenda 929b9c1b51eSKate Stone RegisterContextDarwin_arm::~RegisterContextDarwin_arm() {} 93063bd0db0SJason Molenda 931b9c1b51eSKate Stone void RegisterContextDarwin_arm::InvalidateAllRegisters() { 932a63d08c9SGreg Clayton InvalidateAllRegisterStates(); 933a63d08c9SGreg Clayton } 934a63d08c9SGreg Clayton 935b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterCount() { 936a63d08c9SGreg Clayton assert(k_num_register_infos == k_num_registers); 937a63d08c9SGreg Clayton return k_num_registers; 938a63d08c9SGreg Clayton } 939a63d08c9SGreg Clayton 940a63d08c9SGreg Clayton const RegisterInfo * 941b9c1b51eSKate Stone RegisterContextDarwin_arm::GetRegisterInfoAtIndex(size_t reg) { 942a63d08c9SGreg Clayton assert(k_num_register_infos == k_num_registers); 943a63d08c9SGreg Clayton if (reg < k_num_registers) 944a63d08c9SGreg Clayton return &g_register_infos[reg]; 945a63d08c9SGreg Clayton return NULL; 946a63d08c9SGreg Clayton } 947a63d08c9SGreg Clayton 948b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterInfosCount() { 949a63d08c9SGreg Clayton return k_num_register_infos; 950a63d08c9SGreg Clayton } 951a63d08c9SGreg Clayton 952b9c1b51eSKate Stone const RegisterInfo *RegisterContextDarwin_arm::GetRegisterInfos() { 953a63d08c9SGreg Clayton return g_register_infos; 954a63d08c9SGreg Clayton } 955a63d08c9SGreg Clayton 956a63d08c9SGreg Clayton // Number of registers in each register set 95728606954SSaleem Abdulrasool const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums); 95828606954SSaleem Abdulrasool const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums); 95928606954SSaleem Abdulrasool const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums); 960a63d08c9SGreg Clayton 961a63d08c9SGreg Clayton //---------------------------------------------------------------------- 96205097246SAdrian Prantl // Register set definitions. The first definitions at register set index of 96305097246SAdrian Prantl // zero is for all registers, followed by other registers sets. The register 96405097246SAdrian Prantl // information for the all register set need not be filled in. 965a63d08c9SGreg Clayton //---------------------------------------------------------------------- 966b9c1b51eSKate Stone static const RegisterSet g_reg_sets[] = { 967a63d08c9SGreg Clayton { 968b9c1b51eSKate Stone "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, 969b9c1b51eSKate Stone }, 970a63d08c9SGreg Clayton {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums}, 971b9c1b51eSKate Stone {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}}; 972a63d08c9SGreg Clayton 97328606954SSaleem Abdulrasool const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets); 974a63d08c9SGreg Clayton 975b9c1b51eSKate Stone size_t RegisterContextDarwin_arm::GetRegisterSetCount() { 976a63d08c9SGreg Clayton return k_num_regsets; 977a63d08c9SGreg Clayton } 978a63d08c9SGreg Clayton 979b9c1b51eSKate Stone const RegisterSet *RegisterContextDarwin_arm::GetRegisterSet(size_t reg_set) { 980a63d08c9SGreg Clayton if (reg_set < k_num_regsets) 981a63d08c9SGreg Clayton return &g_reg_sets[reg_set]; 982a63d08c9SGreg Clayton return NULL; 983a63d08c9SGreg Clayton } 984a63d08c9SGreg Clayton 985a63d08c9SGreg Clayton //---------------------------------------------------------------------- 986aaa0ba31SBruce Mitchener // Register information definitions for 32 bit i386. 987a63d08c9SGreg Clayton //---------------------------------------------------------------------- 988b9c1b51eSKate Stone int RegisterContextDarwin_arm::GetSetForNativeRegNum(int reg) { 989a63d08c9SGreg Clayton if (reg < fpu_s0) 990a63d08c9SGreg Clayton return GPRRegSet; 991a63d08c9SGreg Clayton else if (reg < exc_exception) 992a63d08c9SGreg Clayton return FPURegSet; 993a63d08c9SGreg Clayton else if (reg < k_num_registers) 994a63d08c9SGreg Clayton return EXCRegSet; 995a63d08c9SGreg Clayton return -1; 996a63d08c9SGreg Clayton } 997a63d08c9SGreg Clayton 998b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadGPR(bool force) { 999a63d08c9SGreg Clayton int set = GPRRegSet; 1000b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1001a63d08c9SGreg Clayton SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr)); 1002a63d08c9SGreg Clayton } 1003a63d08c9SGreg Clayton return GetError(GPRRegSet, Read); 1004a63d08c9SGreg Clayton } 1005a63d08c9SGreg Clayton 1006b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadFPU(bool force) { 1007a63d08c9SGreg Clayton int set = FPURegSet; 1008b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1009a63d08c9SGreg Clayton SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu)); 1010a63d08c9SGreg Clayton } 1011a63d08c9SGreg Clayton return GetError(FPURegSet, Read); 1012a63d08c9SGreg Clayton } 1013a63d08c9SGreg Clayton 1014b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadEXC(bool force) { 1015a63d08c9SGreg Clayton int set = EXCRegSet; 1016b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1017a63d08c9SGreg Clayton SetError(set, Read, DoReadEXC(GetThreadID(), set, exc)); 1018a63d08c9SGreg Clayton } 1019a63d08c9SGreg Clayton return GetError(EXCRegSet, Read); 1020a63d08c9SGreg Clayton } 1021a63d08c9SGreg Clayton 1022b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadDBG(bool force) { 1023a63d08c9SGreg Clayton int set = DBGRegSet; 1024b9c1b51eSKate Stone if (force || !RegisterSetIsCached(set)) { 1025a63d08c9SGreg Clayton SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg)); 1026a63d08c9SGreg Clayton } 1027a63d08c9SGreg Clayton return GetError(DBGRegSet, Read); 1028a63d08c9SGreg Clayton } 1029a63d08c9SGreg Clayton 1030b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteGPR() { 1031a63d08c9SGreg Clayton int set = GPRRegSet; 1032b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1033a63d08c9SGreg Clayton SetError(set, Write, -1); 1034a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1035a63d08c9SGreg Clayton } 1036a63d08c9SGreg Clayton SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr)); 1037a63d08c9SGreg Clayton SetError(set, Read, -1); 1038a63d08c9SGreg Clayton return GetError(GPRRegSet, Write); 1039a63d08c9SGreg Clayton } 1040a63d08c9SGreg Clayton 1041b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteFPU() { 1042a63d08c9SGreg Clayton int set = FPURegSet; 1043b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1044a63d08c9SGreg Clayton SetError(set, Write, -1); 1045a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1046a63d08c9SGreg Clayton } 1047a63d08c9SGreg Clayton SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu)); 1048a63d08c9SGreg Clayton SetError(set, Read, -1); 1049a63d08c9SGreg Clayton return GetError(FPURegSet, Write); 1050a63d08c9SGreg Clayton } 1051a63d08c9SGreg Clayton 1052b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteEXC() { 1053a63d08c9SGreg Clayton int set = EXCRegSet; 1054b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1055a63d08c9SGreg Clayton SetError(set, Write, -1); 1056a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1057a63d08c9SGreg Clayton } 1058a63d08c9SGreg Clayton SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc)); 1059a63d08c9SGreg Clayton SetError(set, Read, -1); 1060a63d08c9SGreg Clayton return GetError(EXCRegSet, Write); 1061a63d08c9SGreg Clayton } 1062a63d08c9SGreg Clayton 1063b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteDBG() { 1064a63d08c9SGreg Clayton int set = DBGRegSet; 1065b9c1b51eSKate Stone if (!RegisterSetIsCached(set)) { 1066a63d08c9SGreg Clayton SetError(set, Write, -1); 1067a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1068a63d08c9SGreg Clayton } 1069a63d08c9SGreg Clayton SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg)); 1070a63d08c9SGreg Clayton SetError(set, Read, -1); 1071a63d08c9SGreg Clayton return GetError(DBGRegSet, Write); 1072a63d08c9SGreg Clayton } 1073a63d08c9SGreg Clayton 1074b9c1b51eSKate Stone int RegisterContextDarwin_arm::ReadRegisterSet(uint32_t set, bool force) { 1075b9c1b51eSKate Stone switch (set) { 1076b9c1b51eSKate Stone case GPRRegSet: 1077b9c1b51eSKate Stone return ReadGPR(force); 1078b9c1b51eSKate Stone case GPRAltRegSet: 1079b9c1b51eSKate Stone return ReadGPR(force); 1080b9c1b51eSKate Stone case FPURegSet: 1081b9c1b51eSKate Stone return ReadFPU(force); 1082b9c1b51eSKate Stone case EXCRegSet: 1083b9c1b51eSKate Stone return ReadEXC(force); 1084b9c1b51eSKate Stone case DBGRegSet: 1085b9c1b51eSKate Stone return ReadDBG(force); 1086b9c1b51eSKate Stone default: 1087b9c1b51eSKate Stone break; 1088a63d08c9SGreg Clayton } 1089a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1090a63d08c9SGreg Clayton } 1091a63d08c9SGreg Clayton 1092b9c1b51eSKate Stone int RegisterContextDarwin_arm::WriteRegisterSet(uint32_t set) { 1093a63d08c9SGreg Clayton // Make sure we have a valid context to set. 1094b9c1b51eSKate Stone if (RegisterSetIsCached(set)) { 1095b9c1b51eSKate Stone switch (set) { 1096b9c1b51eSKate Stone case GPRRegSet: 1097b9c1b51eSKate Stone return WriteGPR(); 1098b9c1b51eSKate Stone case GPRAltRegSet: 1099b9c1b51eSKate Stone return WriteGPR(); 1100b9c1b51eSKate Stone case FPURegSet: 1101b9c1b51eSKate Stone return WriteFPU(); 1102b9c1b51eSKate Stone case EXCRegSet: 1103b9c1b51eSKate Stone return WriteEXC(); 1104b9c1b51eSKate Stone case DBGRegSet: 1105b9c1b51eSKate Stone return WriteDBG(); 1106b9c1b51eSKate Stone default: 1107b9c1b51eSKate Stone break; 1108a63d08c9SGreg Clayton } 1109a63d08c9SGreg Clayton } 1110a63d08c9SGreg Clayton return KERN_INVALID_ARGUMENT; 1111a63d08c9SGreg Clayton } 1112a63d08c9SGreg Clayton 1113b9c1b51eSKate Stone void RegisterContextDarwin_arm::LogDBGRegisters(Log *log, const DBG &dbg) { 1114b9c1b51eSKate Stone if (log) { 1115a63d08c9SGreg Clayton for (uint32_t i = 0; i < 16; i++) 1116b9c1b51eSKate Stone log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { " 1117b9c1b51eSKate Stone "0x%8.8x, 0x%8.8x }", 1118b9c1b51eSKate Stone i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]); 1119a63d08c9SGreg Clayton } 1120a63d08c9SGreg Clayton } 1121a63d08c9SGreg Clayton 1122b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ReadRegister(const RegisterInfo *reg_info, 1123b9c1b51eSKate Stone RegisterValue &value) { 1124a63d08c9SGreg Clayton const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 1125a63d08c9SGreg Clayton int set = RegisterContextDarwin_arm::GetSetForNativeRegNum(reg); 1126a63d08c9SGreg Clayton 1127a63d08c9SGreg Clayton if (set == -1) 1128a63d08c9SGreg Clayton return false; 1129a63d08c9SGreg Clayton 1130a63d08c9SGreg Clayton if (ReadRegisterSet(set, false) != KERN_SUCCESS) 1131a63d08c9SGreg Clayton return false; 1132a63d08c9SGreg Clayton 1133b9c1b51eSKate Stone switch (reg) { 1134a63d08c9SGreg Clayton case gpr_r0: 1135a63d08c9SGreg Clayton case gpr_r1: 1136a63d08c9SGreg Clayton case gpr_r2: 1137a63d08c9SGreg Clayton case gpr_r3: 1138a63d08c9SGreg Clayton case gpr_r4: 1139a63d08c9SGreg Clayton case gpr_r5: 1140a63d08c9SGreg Clayton case gpr_r6: 1141a63d08c9SGreg Clayton case gpr_r7: 1142a63d08c9SGreg Clayton case gpr_r8: 1143a63d08c9SGreg Clayton case gpr_r9: 1144a63d08c9SGreg Clayton case gpr_r10: 1145a63d08c9SGreg Clayton case gpr_r11: 1146a63d08c9SGreg Clayton case gpr_r12: 1147a63d08c9SGreg Clayton case gpr_sp: 1148a63d08c9SGreg Clayton case gpr_lr: 1149a63d08c9SGreg Clayton case gpr_pc: 1150a63d08c9SGreg Clayton case gpr_cpsr: 1151a63d08c9SGreg Clayton value.SetUInt32(gpr.r[reg - gpr_r0]); 1152a63d08c9SGreg Clayton break; 1153a63d08c9SGreg Clayton 1154a63d08c9SGreg Clayton case fpu_s0: 1155a63d08c9SGreg Clayton case fpu_s1: 1156a63d08c9SGreg Clayton case fpu_s2: 1157a63d08c9SGreg Clayton case fpu_s3: 1158a63d08c9SGreg Clayton case fpu_s4: 1159a63d08c9SGreg Clayton case fpu_s5: 1160a63d08c9SGreg Clayton case fpu_s6: 1161a63d08c9SGreg Clayton case fpu_s7: 1162a63d08c9SGreg Clayton case fpu_s8: 1163a63d08c9SGreg Clayton case fpu_s9: 1164a63d08c9SGreg Clayton case fpu_s10: 1165a63d08c9SGreg Clayton case fpu_s11: 1166a63d08c9SGreg Clayton case fpu_s12: 1167a63d08c9SGreg Clayton case fpu_s13: 1168a63d08c9SGreg Clayton case fpu_s14: 1169a63d08c9SGreg Clayton case fpu_s15: 1170a63d08c9SGreg Clayton case fpu_s16: 1171a63d08c9SGreg Clayton case fpu_s17: 1172a63d08c9SGreg Clayton case fpu_s18: 1173a63d08c9SGreg Clayton case fpu_s19: 1174a63d08c9SGreg Clayton case fpu_s20: 1175a63d08c9SGreg Clayton case fpu_s21: 1176a63d08c9SGreg Clayton case fpu_s22: 1177a63d08c9SGreg Clayton case fpu_s23: 1178a63d08c9SGreg Clayton case fpu_s24: 1179a63d08c9SGreg Clayton case fpu_s25: 1180a63d08c9SGreg Clayton case fpu_s26: 1181a63d08c9SGreg Clayton case fpu_s27: 1182a63d08c9SGreg Clayton case fpu_s28: 1183a63d08c9SGreg Clayton case fpu_s29: 1184a63d08c9SGreg Clayton case fpu_s30: 1185a63d08c9SGreg Clayton case fpu_s31: 1186a63d08c9SGreg Clayton value.SetUInt32(fpu.floats.s[reg], RegisterValue::eTypeFloat); 1187a63d08c9SGreg Clayton break; 1188a63d08c9SGreg Clayton 1189a63d08c9SGreg Clayton case fpu_fpscr: 1190a63d08c9SGreg Clayton value.SetUInt32(fpu.fpscr); 1191a63d08c9SGreg Clayton break; 1192a63d08c9SGreg Clayton 1193a63d08c9SGreg Clayton case exc_exception: 1194a63d08c9SGreg Clayton value.SetUInt32(exc.exception); 1195a63d08c9SGreg Clayton break; 1196a63d08c9SGreg Clayton case exc_fsr: 1197a63d08c9SGreg Clayton value.SetUInt32(exc.fsr); 1198a63d08c9SGreg Clayton break; 1199a63d08c9SGreg Clayton case exc_far: 1200a63d08c9SGreg Clayton value.SetUInt32(exc.far); 1201a63d08c9SGreg Clayton break; 1202a63d08c9SGreg Clayton 1203a63d08c9SGreg Clayton default: 1204a63d08c9SGreg Clayton value.SetValueToInvalid(); 1205a63d08c9SGreg Clayton return false; 1206a63d08c9SGreg Clayton } 1207a63d08c9SGreg Clayton return true; 1208a63d08c9SGreg Clayton } 1209a63d08c9SGreg Clayton 1210b9c1b51eSKate Stone bool RegisterContextDarwin_arm::WriteRegister(const RegisterInfo *reg_info, 1211b9c1b51eSKate Stone const RegisterValue &value) { 1212a63d08c9SGreg Clayton const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 1213a63d08c9SGreg Clayton int set = GetSetForNativeRegNum(reg); 1214a63d08c9SGreg Clayton 1215a63d08c9SGreg Clayton if (set == -1) 1216a63d08c9SGreg Clayton return false; 1217a63d08c9SGreg Clayton 1218a63d08c9SGreg Clayton if (ReadRegisterSet(set, false) != KERN_SUCCESS) 1219a63d08c9SGreg Clayton return false; 1220a63d08c9SGreg Clayton 1221b9c1b51eSKate Stone switch (reg) { 1222a63d08c9SGreg Clayton case gpr_r0: 1223a63d08c9SGreg Clayton case gpr_r1: 1224a63d08c9SGreg Clayton case gpr_r2: 1225a63d08c9SGreg Clayton case gpr_r3: 1226a63d08c9SGreg Clayton case gpr_r4: 1227a63d08c9SGreg Clayton case gpr_r5: 1228a63d08c9SGreg Clayton case gpr_r6: 1229a63d08c9SGreg Clayton case gpr_r7: 1230a63d08c9SGreg Clayton case gpr_r8: 1231a63d08c9SGreg Clayton case gpr_r9: 1232a63d08c9SGreg Clayton case gpr_r10: 1233a63d08c9SGreg Clayton case gpr_r11: 1234a63d08c9SGreg Clayton case gpr_r12: 1235a63d08c9SGreg Clayton case gpr_sp: 1236a63d08c9SGreg Clayton case gpr_lr: 1237a63d08c9SGreg Clayton case gpr_pc: 1238a63d08c9SGreg Clayton case gpr_cpsr: 1239a63d08c9SGreg Clayton gpr.r[reg - gpr_r0] = value.GetAsUInt32(); 1240a63d08c9SGreg Clayton break; 1241a63d08c9SGreg Clayton 1242a63d08c9SGreg Clayton case fpu_s0: 1243a63d08c9SGreg Clayton case fpu_s1: 1244a63d08c9SGreg Clayton case fpu_s2: 1245a63d08c9SGreg Clayton case fpu_s3: 1246a63d08c9SGreg Clayton case fpu_s4: 1247a63d08c9SGreg Clayton case fpu_s5: 1248a63d08c9SGreg Clayton case fpu_s6: 1249a63d08c9SGreg Clayton case fpu_s7: 1250a63d08c9SGreg Clayton case fpu_s8: 1251a63d08c9SGreg Clayton case fpu_s9: 1252a63d08c9SGreg Clayton case fpu_s10: 1253a63d08c9SGreg Clayton case fpu_s11: 1254a63d08c9SGreg Clayton case fpu_s12: 1255a63d08c9SGreg Clayton case fpu_s13: 1256a63d08c9SGreg Clayton case fpu_s14: 1257a63d08c9SGreg Clayton case fpu_s15: 1258a63d08c9SGreg Clayton case fpu_s16: 1259a63d08c9SGreg Clayton case fpu_s17: 1260a63d08c9SGreg Clayton case fpu_s18: 1261a63d08c9SGreg Clayton case fpu_s19: 1262a63d08c9SGreg Clayton case fpu_s20: 1263a63d08c9SGreg Clayton case fpu_s21: 1264a63d08c9SGreg Clayton case fpu_s22: 1265a63d08c9SGreg Clayton case fpu_s23: 1266a63d08c9SGreg Clayton case fpu_s24: 1267a63d08c9SGreg Clayton case fpu_s25: 1268a63d08c9SGreg Clayton case fpu_s26: 1269a63d08c9SGreg Clayton case fpu_s27: 1270a63d08c9SGreg Clayton case fpu_s28: 1271a63d08c9SGreg Clayton case fpu_s29: 1272a63d08c9SGreg Clayton case fpu_s30: 1273a63d08c9SGreg Clayton case fpu_s31: 1274a63d08c9SGreg Clayton fpu.floats.s[reg] = value.GetAsUInt32(); 1275a63d08c9SGreg Clayton break; 1276a63d08c9SGreg Clayton 1277a63d08c9SGreg Clayton case fpu_fpscr: 1278a63d08c9SGreg Clayton fpu.fpscr = value.GetAsUInt32(); 1279a63d08c9SGreg Clayton break; 1280a63d08c9SGreg Clayton 1281a63d08c9SGreg Clayton case exc_exception: 1282a63d08c9SGreg Clayton exc.exception = value.GetAsUInt32(); 1283a63d08c9SGreg Clayton break; 1284a63d08c9SGreg Clayton case exc_fsr: 1285a63d08c9SGreg Clayton exc.fsr = value.GetAsUInt32(); 1286a63d08c9SGreg Clayton break; 1287a63d08c9SGreg Clayton case exc_far: 1288a63d08c9SGreg Clayton exc.far = value.GetAsUInt32(); 1289a63d08c9SGreg Clayton break; 1290a63d08c9SGreg Clayton 1291a63d08c9SGreg Clayton default: 1292a63d08c9SGreg Clayton return false; 1293a63d08c9SGreg Clayton } 1294a63d08c9SGreg Clayton return WriteRegisterSet(set) == KERN_SUCCESS; 1295a63d08c9SGreg Clayton } 1296a63d08c9SGreg Clayton 1297b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ReadAllRegisterValues( 1298b9c1b51eSKate Stone lldb::DataBufferSP &data_sp) { 1299a63d08c9SGreg Clayton data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0)); 1300b9c1b51eSKate Stone if (data_sp && ReadGPR(false) == KERN_SUCCESS && 1301b9c1b51eSKate Stone ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) { 1302a63d08c9SGreg Clayton uint8_t *dst = data_sp->GetBytes(); 1303a63d08c9SGreg Clayton ::memcpy(dst, &gpr, sizeof(gpr)); 1304a63d08c9SGreg Clayton dst += sizeof(gpr); 1305a63d08c9SGreg Clayton 1306a63d08c9SGreg Clayton ::memcpy(dst, &fpu, sizeof(fpu)); 1307a63d08c9SGreg Clayton dst += sizeof(gpr); 1308a63d08c9SGreg Clayton 1309a63d08c9SGreg Clayton ::memcpy(dst, &exc, sizeof(exc)); 1310a63d08c9SGreg Clayton return true; 1311a63d08c9SGreg Clayton } 1312a63d08c9SGreg Clayton return false; 1313a63d08c9SGreg Clayton } 1314a63d08c9SGreg Clayton 1315b9c1b51eSKate Stone bool RegisterContextDarwin_arm::WriteAllRegisterValues( 1316b9c1b51eSKate Stone const lldb::DataBufferSP &data_sp) { 1317b9c1b51eSKate Stone if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) { 1318a63d08c9SGreg Clayton const uint8_t *src = data_sp->GetBytes(); 1319a63d08c9SGreg Clayton ::memcpy(&gpr, src, sizeof(gpr)); 1320a63d08c9SGreg Clayton src += sizeof(gpr); 1321a63d08c9SGreg Clayton 1322a63d08c9SGreg Clayton ::memcpy(&fpu, src, sizeof(fpu)); 1323a63d08c9SGreg Clayton src += sizeof(gpr); 1324a63d08c9SGreg Clayton 1325a63d08c9SGreg Clayton ::memcpy(&exc, src, sizeof(exc)); 1326a63d08c9SGreg Clayton uint32_t success_count = 0; 1327a63d08c9SGreg Clayton if (WriteGPR() == KERN_SUCCESS) 1328a63d08c9SGreg Clayton ++success_count; 1329a63d08c9SGreg Clayton if (WriteFPU() == KERN_SUCCESS) 1330a63d08c9SGreg Clayton ++success_count; 1331a63d08c9SGreg Clayton if (WriteEXC() == KERN_SUCCESS) 1332a63d08c9SGreg Clayton ++success_count; 1333a63d08c9SGreg Clayton return success_count == 3; 1334a63d08c9SGreg Clayton } 1335a63d08c9SGreg Clayton return false; 1336a63d08c9SGreg Clayton } 1337a63d08c9SGreg Clayton 1338b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::ConvertRegisterKindToRegisterNumber( 1339b9c1b51eSKate Stone lldb::RegisterKind kind, uint32_t reg) { 1340b9c1b51eSKate Stone if (kind == eRegisterKindGeneric) { 1341b9c1b51eSKate Stone switch (reg) { 1342b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_PC: 1343b9c1b51eSKate Stone return gpr_pc; 1344b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_SP: 1345b9c1b51eSKate Stone return gpr_sp; 1346b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_FP: 1347b9c1b51eSKate Stone return gpr_r7; 1348b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_RA: 1349b9c1b51eSKate Stone return gpr_lr; 1350b9c1b51eSKate Stone case LLDB_REGNUM_GENERIC_FLAGS: 1351b9c1b51eSKate Stone return gpr_cpsr; 1352a63d08c9SGreg Clayton default: 1353a63d08c9SGreg Clayton break; 1354a63d08c9SGreg Clayton } 1355b9c1b51eSKate Stone } else if (kind == eRegisterKindDWARF) { 1356b9c1b51eSKate Stone switch (reg) { 1357b9c1b51eSKate Stone case dwarf_r0: 1358b9c1b51eSKate Stone return gpr_r0; 1359b9c1b51eSKate Stone case dwarf_r1: 1360b9c1b51eSKate Stone return gpr_r1; 1361b9c1b51eSKate Stone case dwarf_r2: 1362b9c1b51eSKate Stone return gpr_r2; 1363b9c1b51eSKate Stone case dwarf_r3: 1364b9c1b51eSKate Stone return gpr_r3; 1365b9c1b51eSKate Stone case dwarf_r4: 1366b9c1b51eSKate Stone return gpr_r4; 1367b9c1b51eSKate Stone case dwarf_r5: 1368b9c1b51eSKate Stone return gpr_r5; 1369b9c1b51eSKate Stone case dwarf_r6: 1370b9c1b51eSKate Stone return gpr_r6; 1371b9c1b51eSKate Stone case dwarf_r7: 1372b9c1b51eSKate Stone return gpr_r7; 1373b9c1b51eSKate Stone case dwarf_r8: 1374b9c1b51eSKate Stone return gpr_r8; 1375b9c1b51eSKate Stone case dwarf_r9: 1376b9c1b51eSKate Stone return gpr_r9; 1377b9c1b51eSKate Stone case dwarf_r10: 1378b9c1b51eSKate Stone return gpr_r10; 1379b9c1b51eSKate Stone case dwarf_r11: 1380b9c1b51eSKate Stone return gpr_r11; 1381b9c1b51eSKate Stone case dwarf_r12: 1382b9c1b51eSKate Stone return gpr_r12; 1383b9c1b51eSKate Stone case dwarf_sp: 1384b9c1b51eSKate Stone return gpr_sp; 1385b9c1b51eSKate Stone case dwarf_lr: 1386b9c1b51eSKate Stone return gpr_lr; 1387b9c1b51eSKate Stone case dwarf_pc: 1388b9c1b51eSKate Stone return gpr_pc; 1389b9c1b51eSKate Stone case dwarf_spsr: 1390b9c1b51eSKate Stone return gpr_cpsr; 1391a63d08c9SGreg Clayton 1392b9c1b51eSKate Stone case dwarf_s0: 1393b9c1b51eSKate Stone return fpu_s0; 1394b9c1b51eSKate Stone case dwarf_s1: 1395b9c1b51eSKate Stone return fpu_s1; 1396b9c1b51eSKate Stone case dwarf_s2: 1397b9c1b51eSKate Stone return fpu_s2; 1398b9c1b51eSKate Stone case dwarf_s3: 1399b9c1b51eSKate Stone return fpu_s3; 1400b9c1b51eSKate Stone case dwarf_s4: 1401b9c1b51eSKate Stone return fpu_s4; 1402b9c1b51eSKate Stone case dwarf_s5: 1403b9c1b51eSKate Stone return fpu_s5; 1404b9c1b51eSKate Stone case dwarf_s6: 1405b9c1b51eSKate Stone return fpu_s6; 1406b9c1b51eSKate Stone case dwarf_s7: 1407b9c1b51eSKate Stone return fpu_s7; 1408b9c1b51eSKate Stone case dwarf_s8: 1409b9c1b51eSKate Stone return fpu_s8; 1410b9c1b51eSKate Stone case dwarf_s9: 1411b9c1b51eSKate Stone return fpu_s9; 1412b9c1b51eSKate Stone case dwarf_s10: 1413b9c1b51eSKate Stone return fpu_s10; 1414b9c1b51eSKate Stone case dwarf_s11: 1415b9c1b51eSKate Stone return fpu_s11; 1416b9c1b51eSKate Stone case dwarf_s12: 1417b9c1b51eSKate Stone return fpu_s12; 1418b9c1b51eSKate Stone case dwarf_s13: 1419b9c1b51eSKate Stone return fpu_s13; 1420b9c1b51eSKate Stone case dwarf_s14: 1421b9c1b51eSKate Stone return fpu_s14; 1422b9c1b51eSKate Stone case dwarf_s15: 1423b9c1b51eSKate Stone return fpu_s15; 1424b9c1b51eSKate Stone case dwarf_s16: 1425b9c1b51eSKate Stone return fpu_s16; 1426b9c1b51eSKate Stone case dwarf_s17: 1427b9c1b51eSKate Stone return fpu_s17; 1428b9c1b51eSKate Stone case dwarf_s18: 1429b9c1b51eSKate Stone return fpu_s18; 1430b9c1b51eSKate Stone case dwarf_s19: 1431b9c1b51eSKate Stone return fpu_s19; 1432b9c1b51eSKate Stone case dwarf_s20: 1433b9c1b51eSKate Stone return fpu_s20; 1434b9c1b51eSKate Stone case dwarf_s21: 1435b9c1b51eSKate Stone return fpu_s21; 1436b9c1b51eSKate Stone case dwarf_s22: 1437b9c1b51eSKate Stone return fpu_s22; 1438b9c1b51eSKate Stone case dwarf_s23: 1439b9c1b51eSKate Stone return fpu_s23; 1440b9c1b51eSKate Stone case dwarf_s24: 1441b9c1b51eSKate Stone return fpu_s24; 1442b9c1b51eSKate Stone case dwarf_s25: 1443b9c1b51eSKate Stone return fpu_s25; 1444b9c1b51eSKate Stone case dwarf_s26: 1445b9c1b51eSKate Stone return fpu_s26; 1446b9c1b51eSKate Stone case dwarf_s27: 1447b9c1b51eSKate Stone return fpu_s27; 1448b9c1b51eSKate Stone case dwarf_s28: 1449b9c1b51eSKate Stone return fpu_s28; 1450b9c1b51eSKate Stone case dwarf_s29: 1451b9c1b51eSKate Stone return fpu_s29; 1452b9c1b51eSKate Stone case dwarf_s30: 1453b9c1b51eSKate Stone return fpu_s30; 1454b9c1b51eSKate Stone case dwarf_s31: 1455b9c1b51eSKate Stone return fpu_s31; 1456a63d08c9SGreg Clayton 1457a63d08c9SGreg Clayton default: 1458a63d08c9SGreg Clayton break; 1459a63d08c9SGreg Clayton } 1460b9c1b51eSKate Stone } else if (kind == eRegisterKindEHFrame) { 1461b9c1b51eSKate Stone switch (reg) { 1462b9c1b51eSKate Stone case ehframe_r0: 1463b9c1b51eSKate Stone return gpr_r0; 1464b9c1b51eSKate Stone case ehframe_r1: 1465b9c1b51eSKate Stone return gpr_r1; 1466b9c1b51eSKate Stone case ehframe_r2: 1467b9c1b51eSKate Stone return gpr_r2; 1468b9c1b51eSKate Stone case ehframe_r3: 1469b9c1b51eSKate Stone return gpr_r3; 1470b9c1b51eSKate Stone case ehframe_r4: 1471b9c1b51eSKate Stone return gpr_r4; 1472b9c1b51eSKate Stone case ehframe_r5: 1473b9c1b51eSKate Stone return gpr_r5; 1474b9c1b51eSKate Stone case ehframe_r6: 1475b9c1b51eSKate Stone return gpr_r6; 1476b9c1b51eSKate Stone case ehframe_r7: 1477b9c1b51eSKate Stone return gpr_r7; 1478b9c1b51eSKate Stone case ehframe_r8: 1479b9c1b51eSKate Stone return gpr_r8; 1480b9c1b51eSKate Stone case ehframe_r9: 1481b9c1b51eSKate Stone return gpr_r9; 1482b9c1b51eSKate Stone case ehframe_r10: 1483b9c1b51eSKate Stone return gpr_r10; 1484b9c1b51eSKate Stone case ehframe_r11: 1485b9c1b51eSKate Stone return gpr_r11; 1486b9c1b51eSKate Stone case ehframe_r12: 1487b9c1b51eSKate Stone return gpr_r12; 1488b9c1b51eSKate Stone case ehframe_sp: 1489b9c1b51eSKate Stone return gpr_sp; 1490b9c1b51eSKate Stone case ehframe_lr: 1491b9c1b51eSKate Stone return gpr_lr; 1492b9c1b51eSKate Stone case ehframe_pc: 1493b9c1b51eSKate Stone return gpr_pc; 1494b9c1b51eSKate Stone case ehframe_cpsr: 1495b9c1b51eSKate Stone return gpr_cpsr; 1496a63d08c9SGreg Clayton } 1497b9c1b51eSKate Stone } else if (kind == eRegisterKindLLDB) { 1498a63d08c9SGreg Clayton return reg; 1499a63d08c9SGreg Clayton } 1500a63d08c9SGreg Clayton return LLDB_INVALID_REGNUM; 1501a63d08c9SGreg Clayton } 1502a63d08c9SGreg Clayton 1503b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::NumSupportedHardwareBreakpoints() { 150490da3ce3SPavel Labath #if defined(__APPLE__) && defined(__arm__) 1505a63d08c9SGreg Clayton // Set the init value to something that will let us know that we need to 1506a63d08c9SGreg Clayton // autodetect how many breakpoints are supported dynamically... 1507a63d08c9SGreg Clayton static uint32_t g_num_supported_hw_breakpoints = UINT32_MAX; 1508b9c1b51eSKate Stone if (g_num_supported_hw_breakpoints == UINT32_MAX) { 1509a63d08c9SGreg Clayton // Set this to zero in case we can't tell if there are any HW breakpoints 1510a63d08c9SGreg Clayton g_num_supported_hw_breakpoints = 0; 1511a63d08c9SGreg Clayton 1512a63d08c9SGreg Clayton uint32_t register_DBGDIDR; 1513a63d08c9SGreg Clayton 1514a63d08c9SGreg Clayton asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 1515dce502edSGreg Clayton g_num_supported_hw_breakpoints = Bits32(register_DBGDIDR, 27, 24); 1516a63d08c9SGreg Clayton // Zero is reserved for the BRP count, so don't increment it if it is zero 1517a63d08c9SGreg Clayton if (g_num_supported_hw_breakpoints > 0) 1518a63d08c9SGreg Clayton g_num_supported_hw_breakpoints++; 1519b9c1b51eSKate Stone // if (log) log->Printf ("DBGDIDR=0x%8.8x (number BRP pairs = %u)", 1520b9c1b51eSKate Stone // register_DBGDIDR, g_num_supported_hw_breakpoints); 1521a63d08c9SGreg Clayton } 1522a63d08c9SGreg Clayton return g_num_supported_hw_breakpoints; 1523a63d08c9SGreg Clayton #else 1524a63d08c9SGreg Clayton // TODO: figure out remote case here! 1525a63d08c9SGreg Clayton return 6; 1526a63d08c9SGreg Clayton #endif 1527a63d08c9SGreg Clayton } 1528a63d08c9SGreg Clayton 1529b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::SetHardwareBreakpoint(lldb::addr_t addr, 1530b9c1b51eSKate Stone size_t size) { 1531a63d08c9SGreg Clayton // Make sure our address isn't bogus 1532a63d08c9SGreg Clayton if (addr & 1) 1533a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1534a63d08c9SGreg Clayton 1535a63d08c9SGreg Clayton int kret = ReadDBG(false); 1536a63d08c9SGreg Clayton 1537b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1538a63d08c9SGreg Clayton const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints(); 1539a63d08c9SGreg Clayton uint32_t i; 1540b9c1b51eSKate Stone for (i = 0; i < num_hw_breakpoints; ++i) { 1541a63d08c9SGreg Clayton if ((dbg.bcr[i] & BCR_ENABLE) == 0) 1542a63d08c9SGreg Clayton break; // We found an available hw breakpoint slot (in i) 1543a63d08c9SGreg Clayton } 1544a63d08c9SGreg Clayton 1545a63d08c9SGreg Clayton // See if we found an available hw breakpoint slot above 1546b9c1b51eSKate Stone if (i < num_hw_breakpoints) { 1547a63d08c9SGreg Clayton // Make sure bits 1:0 are clear in our address 1548a63d08c9SGreg Clayton dbg.bvr[i] = addr & ~((lldb::addr_t)3); 1549a63d08c9SGreg Clayton 1550b9c1b51eSKate Stone if (size == 2 || addr & 2) { 1551a63d08c9SGreg Clayton uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1; 1552a63d08c9SGreg Clayton 1553a63d08c9SGreg Clayton // We have a thumb breakpoint 1554a63d08c9SGreg Clayton // We have an ARM breakpoint 1555a63d08c9SGreg Clayton dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch 1556b9c1b51eSKate Stone byte_addr_select | // Set the correct byte address select 1557b9c1b51eSKate Stone // so we only trigger on the correct 1558b9c1b51eSKate Stone // opcode 1559a63d08c9SGreg Clayton S_USER | // Which modes should this breakpoint stop in? 1560a63d08c9SGreg Clayton BCR_ENABLE; // Enable this hardware breakpoint 1561b9c1b51eSKate Stone // if (log) log->Printf 1562b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 1563b9c1b51eSKate Stone // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 1564b9c1b51eSKate Stone // 0x%8.8x (Thumb)", 156589f138aeSGreg Clayton // addr, 156689f138aeSGreg Clayton // size, 156789f138aeSGreg Clayton // i, 156889f138aeSGreg Clayton // i, 156989f138aeSGreg Clayton // dbg.bvr[i], 157089f138aeSGreg Clayton // dbg.bcr[i]); 1571b9c1b51eSKate Stone } else if (size == 4) { 1572a63d08c9SGreg Clayton // We have an ARM breakpoint 1573b9c1b51eSKate Stone dbg.bcr[i] = 1574b9c1b51eSKate Stone BCR_M_IMVA_MATCH | // Stop on address mismatch 1575a63d08c9SGreg Clayton BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA 1576a63d08c9SGreg Clayton S_USER | // Which modes should this breakpoint stop in? 1577a63d08c9SGreg Clayton BCR_ENABLE; // Enable this hardware breakpoint 1578b9c1b51eSKate Stone // if (log) log->Printf 1579b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 1580b9c1b51eSKate Stone // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 1581b9c1b51eSKate Stone // 0x%8.8x (ARM)", 158289f138aeSGreg Clayton // addr, 158389f138aeSGreg Clayton // size, 158489f138aeSGreg Clayton // i, 158589f138aeSGreg Clayton // i, 158689f138aeSGreg Clayton // dbg.bvr[i], 158789f138aeSGreg Clayton // dbg.bcr[i]); 1588a63d08c9SGreg Clayton } 1589a63d08c9SGreg Clayton 1590a63d08c9SGreg Clayton kret = WriteDBG(); 1591b9c1b51eSKate Stone // if (log) log->Printf 1592b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint() 1593b9c1b51eSKate Stone // WriteDBG() => 0x%8.8x.", kret); 1594a63d08c9SGreg Clayton 1595a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1596a63d08c9SGreg Clayton return i; 1597a63d08c9SGreg Clayton } 159889f138aeSGreg Clayton // else 159989f138aeSGreg Clayton // { 1600b9c1b51eSKate Stone // if (log) log->Printf 1601b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(addr = 1602b9c1b51eSKate Stone // %8.8p, size = %u) => all hardware breakpoint resources are 1603b9c1b51eSKate Stone // being used.", addr, size); 160489f138aeSGreg Clayton // } 1605a63d08c9SGreg Clayton } 1606a63d08c9SGreg Clayton 1607a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1608a63d08c9SGreg Clayton } 1609a63d08c9SGreg Clayton 1610b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ClearHardwareBreakpoint(uint32_t hw_index) { 1611a63d08c9SGreg Clayton int kret = ReadDBG(false); 1612a63d08c9SGreg Clayton 1613a63d08c9SGreg Clayton const uint32_t num_hw_points = NumSupportedHardwareBreakpoints(); 1614b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1615b9c1b51eSKate Stone if (hw_index < num_hw_points) { 1616a63d08c9SGreg Clayton dbg.bcr[hw_index] = 0; 1617b9c1b51eSKate Stone // if (log) log->Printf 1618b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::SetHardwareBreakpoint( %u ) - 1619b9c1b51eSKate Stone // BVR%u = 0x%8.8x BCR%u = 0x%8.8x", 162089f138aeSGreg Clayton // hw_index, 162189f138aeSGreg Clayton // hw_index, 162289f138aeSGreg Clayton // dbg.bvr[hw_index], 162389f138aeSGreg Clayton // hw_index, 162489f138aeSGreg Clayton // dbg.bcr[hw_index]); 1625a63d08c9SGreg Clayton 1626a63d08c9SGreg Clayton kret = WriteDBG(); 1627a63d08c9SGreg Clayton 1628a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1629a63d08c9SGreg Clayton return true; 1630a63d08c9SGreg Clayton } 1631a63d08c9SGreg Clayton } 1632a63d08c9SGreg Clayton return false; 1633a63d08c9SGreg Clayton } 1634a63d08c9SGreg Clayton 1635b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::NumSupportedHardwareWatchpoints() { 163690da3ce3SPavel Labath #if defined(__APPLE__) && defined(__arm__) 1637a63d08c9SGreg Clayton // Set the init value to something that will let us know that we need to 1638a63d08c9SGreg Clayton // autodetect how many watchpoints are supported dynamically... 1639a63d08c9SGreg Clayton static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX; 1640b9c1b51eSKate Stone if (g_num_supported_hw_watchpoints == UINT32_MAX) { 1641a63d08c9SGreg Clayton // Set this to zero in case we can't tell if there are any HW breakpoints 1642a63d08c9SGreg Clayton g_num_supported_hw_watchpoints = 0; 1643a63d08c9SGreg Clayton 1644a63d08c9SGreg Clayton uint32_t register_DBGDIDR; 1645a63d08c9SGreg Clayton asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 1646dce502edSGreg Clayton g_num_supported_hw_watchpoints = Bits32(register_DBGDIDR, 31, 28) + 1; 1647b9c1b51eSKate Stone // if (log) log->Printf ("DBGDIDR=0x%8.8x (number WRP pairs = %u)", 1648b9c1b51eSKate Stone // register_DBGDIDR, g_num_supported_hw_watchpoints); 1649a63d08c9SGreg Clayton } 1650a63d08c9SGreg Clayton return g_num_supported_hw_watchpoints; 1651a63d08c9SGreg Clayton #else 1652a63d08c9SGreg Clayton // TODO: figure out remote case here! 1653a63d08c9SGreg Clayton return 2; 1654a63d08c9SGreg Clayton #endif 1655a63d08c9SGreg Clayton } 1656a63d08c9SGreg Clayton 1657b9c1b51eSKate Stone uint32_t RegisterContextDarwin_arm::SetHardwareWatchpoint(lldb::addr_t addr, 1658b9c1b51eSKate Stone size_t size, 1659b9c1b51eSKate Stone bool read, 1660b9c1b51eSKate Stone bool write) { 1661b9c1b51eSKate Stone // if (log) log->Printf 1662b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(addr = %8.8p, size 1663b9c1b51eSKate Stone // = %u, read = %u, write = %u)", addr, size, read, write); 1664a63d08c9SGreg Clayton 1665a63d08c9SGreg Clayton const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 1666a63d08c9SGreg Clayton 1667a63d08c9SGreg Clayton // Can't watch zero bytes 1668a63d08c9SGreg Clayton if (size == 0) 1669a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1670a63d08c9SGreg Clayton 1671a63d08c9SGreg Clayton // We must watch for either read or write 1672a6682a41SJonas Devlieghere if (!read && !write) 1673a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1674a63d08c9SGreg Clayton 1675a63d08c9SGreg Clayton // Can't watch more than 4 bytes per WVR/WCR pair 1676a63d08c9SGreg Clayton if (size > 4) 1677a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1678a63d08c9SGreg Clayton 1679a63d08c9SGreg Clayton // We can only watch up to four bytes that follow a 4 byte aligned address 1680a63d08c9SGreg Clayton // per watchpoint register pair. Since we have at most so we can only watch 1681a63d08c9SGreg Clayton // until the next 4 byte boundary and we need to make sure we can properly 1682a63d08c9SGreg Clayton // encode this. 1683a63d08c9SGreg Clayton uint32_t addr_word_offset = addr % 4; 1684b9c1b51eSKate Stone // if (log) log->Printf 1685b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - 1686b9c1b51eSKate Stone // addr_word_offset = 0x%8.8x", addr_word_offset); 1687a63d08c9SGreg Clayton 1688a63d08c9SGreg Clayton uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset; 1689b9c1b51eSKate Stone // if (log) log->Printf 1690b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - byte_mask = 1691b9c1b51eSKate Stone // 0x%8.8x", byte_mask); 1692a63d08c9SGreg Clayton if (byte_mask > 0xfu) 1693a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1694a63d08c9SGreg Clayton 1695a63d08c9SGreg Clayton // Read the debug state 1696a63d08c9SGreg Clayton int kret = ReadDBG(false); 1697a63d08c9SGreg Clayton 1698b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1699a63d08c9SGreg Clayton // Check to make sure we have the needed hardware support 1700a63d08c9SGreg Clayton uint32_t i = 0; 1701a63d08c9SGreg Clayton 1702b9c1b51eSKate Stone for (i = 0; i < num_hw_watchpoints; ++i) { 1703a63d08c9SGreg Clayton if ((dbg.wcr[i] & WCR_ENABLE) == 0) 1704a63d08c9SGreg Clayton break; // We found an available hw breakpoint slot (in i) 1705a63d08c9SGreg Clayton } 1706a63d08c9SGreg Clayton 1707a63d08c9SGreg Clayton // See if we found an available hw breakpoint slot above 1708b9c1b51eSKate Stone if (i < num_hw_watchpoints) { 1709a63d08c9SGreg Clayton // Make the byte_mask into a valid Byte Address Select mask 1710a63d08c9SGreg Clayton uint32_t byte_address_select = byte_mask << 5; 1711a63d08c9SGreg Clayton // Make sure bits 1:0 are clear in our address 1712a63d08c9SGreg Clayton dbg.wvr[i] = addr & ~((lldb::addr_t)3); 1713b9c1b51eSKate Stone dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA 1714b9c1b51eSKate Stone // that we will watch 1715a63d08c9SGreg Clayton S_USER | // Stop only in user mode 1716a63d08c9SGreg Clayton (read ? WCR_LOAD : 0) | // Stop on read access? 1717a63d08c9SGreg Clayton (write ? WCR_STORE : 0) | // Stop on write access? 1718a63d08c9SGreg Clayton WCR_ENABLE; // Enable this watchpoint; 1719a63d08c9SGreg Clayton 1720a63d08c9SGreg Clayton kret = WriteDBG(); 1721b9c1b51eSKate Stone // if (log) log->Printf 1722b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() 1723b9c1b51eSKate Stone // WriteDBG() => 0x%8.8x.", kret); 1724a63d08c9SGreg Clayton 1725a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1726a63d08c9SGreg Clayton return i; 1727b9c1b51eSKate Stone } else { 1728b9c1b51eSKate Stone // if (log) log->Printf 1729b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(): All 1730b9c1b51eSKate Stone // hardware resources (%u) are in use.", num_hw_watchpoints); 1731a63d08c9SGreg Clayton } 1732a63d08c9SGreg Clayton } 1733a63d08c9SGreg Clayton return LLDB_INVALID_INDEX32; 1734a63d08c9SGreg Clayton } 1735a63d08c9SGreg Clayton 1736b9c1b51eSKate Stone bool RegisterContextDarwin_arm::ClearHardwareWatchpoint(uint32_t hw_index) { 1737a63d08c9SGreg Clayton int kret = ReadDBG(false); 1738a63d08c9SGreg Clayton 1739a63d08c9SGreg Clayton const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 1740b9c1b51eSKate Stone if (kret == KERN_SUCCESS) { 1741b9c1b51eSKate Stone if (hw_index < num_hw_points) { 1742a63d08c9SGreg Clayton dbg.wcr[hw_index] = 0; 1743b9c1b51eSKate Stone // if (log) log->Printf 1744b9c1b51eSKate Stone // ("RegisterContextDarwin_arm::ClearHardwareWatchpoint( %u ) - 1745b9c1b51eSKate Stone // WVR%u = 0x%8.8x WCR%u = 0x%8.8x", 174689f138aeSGreg Clayton // hw_index, 174789f138aeSGreg Clayton // hw_index, 174889f138aeSGreg Clayton // dbg.wvr[hw_index], 174989f138aeSGreg Clayton // hw_index, 175089f138aeSGreg Clayton // dbg.wcr[hw_index]); 1751a63d08c9SGreg Clayton 1752a63d08c9SGreg Clayton kret = WriteDBG(); 1753a63d08c9SGreg Clayton 1754a63d08c9SGreg Clayton if (kret == KERN_SUCCESS) 1755a63d08c9SGreg Clayton return true; 1756a63d08c9SGreg Clayton } 1757a63d08c9SGreg Clayton } 1758a63d08c9SGreg Clayton return false; 1759a63d08c9SGreg Clayton } 1760