1 //===-- lldb_ARMDefines.h ---------------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifndef lldb_ARMDefines_h_ 11 #define lldb_ARMDefines_h_ 12 13 #include <cassert> 14 #include <cstdint> 15 16 // Common definitions for the ARM/Thumb Instruction Set Architecture. 17 18 namespace lldb_private { 19 20 // ARM shifter types 21 typedef enum { 22 SRType_LSL, 23 SRType_LSR, 24 SRType_ASR, 25 SRType_ROR, 26 SRType_RRX, 27 SRType_Invalid 28 } ARM_ShifterType; 29 30 // ARM conditions // Meaning (integer) Meaning (floating-point) 31 // Condition flags 32 #define COND_EQ \ 33 0x0 // Equal Equal Z == 1 34 #define COND_NE \ 35 0x1 // Not equal Not equal, or unordered Z == 0 36 #define COND_CS \ 37 0x2 // Carry set >, ==, or unordered C == 1 38 #define COND_HS 0x2 39 #define COND_CC \ 40 0x3 // Carry clear Less than C == 0 41 #define COND_LO 0x3 42 #define COND_MI \ 43 0x4 // Minus, negative Less than N == 1 44 #define COND_PL \ 45 0x5 // Plus, positive or zero >, ==, or unordered N == 0 46 #define COND_VS \ 47 0x6 // Overflow Unordered V == 1 48 #define COND_VC \ 49 0x7 // No overflow Not unordered V == 0 50 #define COND_HI \ 51 0x8 // Unsigned higher Greater than, or unordered C == 1 and Z == 52 // 0 53 #define COND_LS \ 54 0x9 // Unsigned lower or same Less than or equal C == 0 or Z == 55 // 1 56 #define COND_GE \ 57 0xA // Greater than or equal Greater than or equal N == V 58 #define COND_LT \ 59 0xB // Less than Less than, or unordered N != V 60 #define COND_GT \ 61 0xC // Greater than Greater than Z == 0 and N == 62 // V 63 #define COND_LE \ 64 0xD // Less than or equal <, ==, or unordered Z == 1 or N != 65 // V 66 #define COND_AL \ 67 0xE // Always (unconditional) Always (unconditional) Any 68 #define COND_UNCOND 0xF 69 70 static inline const char *ARMCondCodeToString(uint32_t CC) { 71 switch (CC) { 72 default: 73 assert(0 && "Unknown condition code"); 74 case COND_EQ: 75 return "eq"; 76 case COND_NE: 77 return "ne"; 78 case COND_HS: 79 return "hs"; 80 case COND_LO: 81 return "lo"; 82 case COND_MI: 83 return "mi"; 84 case COND_PL: 85 return "pl"; 86 case COND_VS: 87 return "vs"; 88 case COND_VC: 89 return "vc"; 90 case COND_HI: 91 return "hi"; 92 case COND_LS: 93 return "ls"; 94 case COND_GE: 95 return "ge"; 96 case COND_LT: 97 return "lt"; 98 case COND_GT: 99 return "gt"; 100 case COND_LE: 101 return "le"; 102 case COND_AL: 103 return "al"; 104 } 105 } 106 107 static inline bool ARMConditionPassed(const uint32_t condition, 108 const uint32_t cpsr) { 109 const uint32_t cpsr_n = (cpsr >> 31) & 1u; // Negative condition code flag 110 const uint32_t cpsr_z = (cpsr >> 30) & 1u; // Zero condition code flag 111 const uint32_t cpsr_c = (cpsr >> 29) & 1u; // Carry condition code flag 112 const uint32_t cpsr_v = (cpsr >> 28) & 1u; // Overflow condition code flag 113 114 switch (condition) { 115 case COND_EQ: 116 return (cpsr_z == 1); 117 case COND_NE: 118 return (cpsr_z == 0); 119 case COND_CS: 120 return (cpsr_c == 1); 121 case COND_CC: 122 return (cpsr_c == 0); 123 case COND_MI: 124 return (cpsr_n == 1); 125 case COND_PL: 126 return (cpsr_n == 0); 127 case COND_VS: 128 return (cpsr_v == 1); 129 case COND_VC: 130 return (cpsr_v == 0); 131 case COND_HI: 132 return ((cpsr_c == 1) && (cpsr_z == 0)); 133 case COND_LS: 134 return ((cpsr_c == 0) || (cpsr_z == 1)); 135 case COND_GE: 136 return (cpsr_n == cpsr_v); 137 case COND_LT: 138 return (cpsr_n != cpsr_v); 139 case COND_GT: 140 return ((cpsr_z == 0) && (cpsr_n == cpsr_v)); 141 case COND_LE: 142 return ((cpsr_z == 1) || (cpsr_n != cpsr_v)); 143 case COND_AL: 144 case COND_UNCOND: 145 default: 146 return true; 147 } 148 return false; 149 } 150 151 // Bit positions for CPSR 152 #define CPSR_T_POS 5 153 #define CPSR_F_POS 6 154 #define CPSR_I_POS 7 155 #define CPSR_A_POS 8 156 #define CPSR_E_POS 9 157 #define CPSR_J_POS 24 158 #define CPSR_Q_POS 27 159 #define CPSR_V_POS 28 160 #define CPSR_C_POS 29 161 #define CPSR_Z_POS 30 162 #define CPSR_N_POS 31 163 164 // CPSR mode definitions 165 #define CPSR_MODE_USR 0x10u 166 #define CPSR_MODE_FIQ 0x11u 167 #define CPSR_MODE_IRQ 0x12u 168 #define CPSR_MODE_SVC 0x13u 169 #define CPSR_MODE_ABT 0x17u 170 #define CPSR_MODE_UND 0x1bu 171 #define CPSR_MODE_SYS 0x1fu 172 173 // Masks for CPSR 174 #define MASK_CPSR_MODE_MASK (0x0000001fu) 175 #define MASK_CPSR_IT_MASK (0x0600fc00u) 176 #define MASK_CPSR_T (1u << CPSR_T_POS) 177 #define MASK_CPSR_F (1u << CPSR_F_POS) 178 #define MASK_CPSR_I (1u << CPSR_I_POS) 179 #define MASK_CPSR_A (1u << CPSR_A_POS) 180 #define MASK_CPSR_E (1u << CPSR_E_POS) 181 #define MASK_CPSR_GE_MASK (0x000f0000u) 182 #define MASK_CPSR_J (1u << CPSR_J_POS) 183 #define MASK_CPSR_Q (1u << CPSR_Q_POS) 184 #define MASK_CPSR_V (1u << CPSR_V_POS) 185 #define MASK_CPSR_C (1u << CPSR_C_POS) 186 #define MASK_CPSR_Z (1u << CPSR_Z_POS) 187 #define MASK_CPSR_N (1u << CPSR_N_POS) 188 189 } // namespace lldb_private 190 191 #endif // lldb_ARMDefines_h_ 192