1 //===-- NativeRegisterContextLinux_x86_64.cpp ---------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #if defined(__i386__) || defined(__x86_64__) 11 12 #include "NativeRegisterContextLinux_x86_64.h" 13 14 #include "lldb/Core/RegisterValue.h" 15 #include "lldb/Host/HostInfo.h" 16 #include "lldb/Utility/DataBufferHeap.h" 17 #include "lldb/Utility/Log.h" 18 #include "lldb/Utility/Status.h" 19 20 #include "Plugins/Process/Utility/RegisterContextLinux_i386.h" 21 #include "Plugins/Process/Utility/RegisterContextLinux_x86_64.h" 22 23 #include <linux/elf.h> 24 25 using namespace lldb_private; 26 using namespace lldb_private::process_linux; 27 28 // ---------------------------------------------------------------------------- 29 // Private namespace. 30 // ---------------------------------------------------------------------------- 31 32 namespace { 33 // x86 32-bit general purpose registers. 34 const uint32_t g_gpr_regnums_i386[] = { 35 lldb_eax_i386, lldb_ebx_i386, lldb_ecx_i386, lldb_edx_i386, 36 lldb_edi_i386, lldb_esi_i386, lldb_ebp_i386, lldb_esp_i386, 37 lldb_eip_i386, lldb_eflags_i386, lldb_cs_i386, lldb_fs_i386, 38 lldb_gs_i386, lldb_ss_i386, lldb_ds_i386, lldb_es_i386, 39 lldb_ax_i386, lldb_bx_i386, lldb_cx_i386, lldb_dx_i386, 40 lldb_di_i386, lldb_si_i386, lldb_bp_i386, lldb_sp_i386, 41 lldb_ah_i386, lldb_bh_i386, lldb_ch_i386, lldb_dh_i386, 42 lldb_al_i386, lldb_bl_i386, lldb_cl_i386, lldb_dl_i386, 43 LLDB_INVALID_REGNUM // register sets need to end with this flag 44 }; 45 static_assert((sizeof(g_gpr_regnums_i386) / sizeof(g_gpr_regnums_i386[0])) - 46 1 == 47 k_num_gpr_registers_i386, 48 "g_gpr_regnums_i386 has wrong number of register infos"); 49 50 // x86 32-bit floating point registers. 51 const uint32_t g_fpu_regnums_i386[] = { 52 lldb_fctrl_i386, lldb_fstat_i386, lldb_ftag_i386, lldb_fop_i386, 53 lldb_fiseg_i386, lldb_fioff_i386, lldb_foseg_i386, lldb_fooff_i386, 54 lldb_mxcsr_i386, lldb_mxcsrmask_i386, lldb_st0_i386, lldb_st1_i386, 55 lldb_st2_i386, lldb_st3_i386, lldb_st4_i386, lldb_st5_i386, 56 lldb_st6_i386, lldb_st7_i386, lldb_mm0_i386, lldb_mm1_i386, 57 lldb_mm2_i386, lldb_mm3_i386, lldb_mm4_i386, lldb_mm5_i386, 58 lldb_mm6_i386, lldb_mm7_i386, lldb_xmm0_i386, lldb_xmm1_i386, 59 lldb_xmm2_i386, lldb_xmm3_i386, lldb_xmm4_i386, lldb_xmm5_i386, 60 lldb_xmm6_i386, lldb_xmm7_i386, 61 LLDB_INVALID_REGNUM // register sets need to end with this flag 62 }; 63 static_assert((sizeof(g_fpu_regnums_i386) / sizeof(g_fpu_regnums_i386[0])) - 64 1 == 65 k_num_fpr_registers_i386, 66 "g_fpu_regnums_i386 has wrong number of register infos"); 67 68 // x86 32-bit AVX registers. 69 const uint32_t g_avx_regnums_i386[] = { 70 lldb_ymm0_i386, lldb_ymm1_i386, lldb_ymm2_i386, lldb_ymm3_i386, 71 lldb_ymm4_i386, lldb_ymm5_i386, lldb_ymm6_i386, lldb_ymm7_i386, 72 LLDB_INVALID_REGNUM // register sets need to end with this flag 73 }; 74 static_assert((sizeof(g_avx_regnums_i386) / sizeof(g_avx_regnums_i386[0])) - 75 1 == 76 k_num_avx_registers_i386, 77 " g_avx_regnums_i386 has wrong number of register infos"); 78 79 // x64 32-bit MPX registers. 80 static const uint32_t g_mpx_regnums_i386[] = { 81 lldb_bnd0_i386, lldb_bnd1_i386, lldb_bnd2_i386, lldb_bnd3_i386, 82 lldb_bndcfgu_i386, lldb_bndstatus_i386, 83 LLDB_INVALID_REGNUM // register sets need to end with this flag 84 }; 85 static_assert((sizeof(g_mpx_regnums_i386) / sizeof(g_mpx_regnums_i386[0])) - 86 1 == 87 k_num_mpx_registers_i386, 88 "g_mpx_regnums_x86_64 has wrong number of register infos"); 89 90 // x86 64-bit general purpose registers. 91 static const uint32_t g_gpr_regnums_x86_64[] = { 92 lldb_rax_x86_64, lldb_rbx_x86_64, lldb_rcx_x86_64, lldb_rdx_x86_64, 93 lldb_rdi_x86_64, lldb_rsi_x86_64, lldb_rbp_x86_64, lldb_rsp_x86_64, 94 lldb_r8_x86_64, lldb_r9_x86_64, lldb_r10_x86_64, lldb_r11_x86_64, 95 lldb_r12_x86_64, lldb_r13_x86_64, lldb_r14_x86_64, lldb_r15_x86_64, 96 lldb_rip_x86_64, lldb_rflags_x86_64, lldb_cs_x86_64, lldb_fs_x86_64, 97 lldb_gs_x86_64, lldb_ss_x86_64, lldb_ds_x86_64, lldb_es_x86_64, 98 lldb_eax_x86_64, lldb_ebx_x86_64, lldb_ecx_x86_64, lldb_edx_x86_64, 99 lldb_edi_x86_64, lldb_esi_x86_64, lldb_ebp_x86_64, lldb_esp_x86_64, 100 lldb_r8d_x86_64, // Low 32 bits or r8 101 lldb_r9d_x86_64, // Low 32 bits or r9 102 lldb_r10d_x86_64, // Low 32 bits or r10 103 lldb_r11d_x86_64, // Low 32 bits or r11 104 lldb_r12d_x86_64, // Low 32 bits or r12 105 lldb_r13d_x86_64, // Low 32 bits or r13 106 lldb_r14d_x86_64, // Low 32 bits or r14 107 lldb_r15d_x86_64, // Low 32 bits or r15 108 lldb_ax_x86_64, lldb_bx_x86_64, lldb_cx_x86_64, lldb_dx_x86_64, 109 lldb_di_x86_64, lldb_si_x86_64, lldb_bp_x86_64, lldb_sp_x86_64, 110 lldb_r8w_x86_64, // Low 16 bits or r8 111 lldb_r9w_x86_64, // Low 16 bits or r9 112 lldb_r10w_x86_64, // Low 16 bits or r10 113 lldb_r11w_x86_64, // Low 16 bits or r11 114 lldb_r12w_x86_64, // Low 16 bits or r12 115 lldb_r13w_x86_64, // Low 16 bits or r13 116 lldb_r14w_x86_64, // Low 16 bits or r14 117 lldb_r15w_x86_64, // Low 16 bits or r15 118 lldb_ah_x86_64, lldb_bh_x86_64, lldb_ch_x86_64, lldb_dh_x86_64, 119 lldb_al_x86_64, lldb_bl_x86_64, lldb_cl_x86_64, lldb_dl_x86_64, 120 lldb_dil_x86_64, lldb_sil_x86_64, lldb_bpl_x86_64, lldb_spl_x86_64, 121 lldb_r8l_x86_64, // Low 8 bits or r8 122 lldb_r9l_x86_64, // Low 8 bits or r9 123 lldb_r10l_x86_64, // Low 8 bits or r10 124 lldb_r11l_x86_64, // Low 8 bits or r11 125 lldb_r12l_x86_64, // Low 8 bits or r12 126 lldb_r13l_x86_64, // Low 8 bits or r13 127 lldb_r14l_x86_64, // Low 8 bits or r14 128 lldb_r15l_x86_64, // Low 8 bits or r15 129 LLDB_INVALID_REGNUM // register sets need to end with this flag 130 }; 131 static_assert((sizeof(g_gpr_regnums_x86_64) / sizeof(g_gpr_regnums_x86_64[0])) - 132 1 == 133 k_num_gpr_registers_x86_64, 134 "g_gpr_regnums_x86_64 has wrong number of register infos"); 135 136 // x86 64-bit floating point registers. 137 static const uint32_t g_fpu_regnums_x86_64[] = { 138 lldb_fctrl_x86_64, lldb_fstat_x86_64, lldb_ftag_x86_64, 139 lldb_fop_x86_64, lldb_fiseg_x86_64, lldb_fioff_x86_64, 140 lldb_foseg_x86_64, lldb_fooff_x86_64, lldb_mxcsr_x86_64, 141 lldb_mxcsrmask_x86_64, lldb_st0_x86_64, lldb_st1_x86_64, 142 lldb_st2_x86_64, lldb_st3_x86_64, lldb_st4_x86_64, 143 lldb_st5_x86_64, lldb_st6_x86_64, lldb_st7_x86_64, 144 lldb_mm0_x86_64, lldb_mm1_x86_64, lldb_mm2_x86_64, 145 lldb_mm3_x86_64, lldb_mm4_x86_64, lldb_mm5_x86_64, 146 lldb_mm6_x86_64, lldb_mm7_x86_64, lldb_xmm0_x86_64, 147 lldb_xmm1_x86_64, lldb_xmm2_x86_64, lldb_xmm3_x86_64, 148 lldb_xmm4_x86_64, lldb_xmm5_x86_64, lldb_xmm6_x86_64, 149 lldb_xmm7_x86_64, lldb_xmm8_x86_64, lldb_xmm9_x86_64, 150 lldb_xmm10_x86_64, lldb_xmm11_x86_64, lldb_xmm12_x86_64, 151 lldb_xmm13_x86_64, lldb_xmm14_x86_64, lldb_xmm15_x86_64, 152 LLDB_INVALID_REGNUM // register sets need to end with this flag 153 }; 154 static_assert((sizeof(g_fpu_regnums_x86_64) / sizeof(g_fpu_regnums_x86_64[0])) - 155 1 == 156 k_num_fpr_registers_x86_64, 157 "g_fpu_regnums_x86_64 has wrong number of register infos"); 158 159 // x86 64-bit AVX registers. 160 static const uint32_t g_avx_regnums_x86_64[] = { 161 lldb_ymm0_x86_64, lldb_ymm1_x86_64, lldb_ymm2_x86_64, lldb_ymm3_x86_64, 162 lldb_ymm4_x86_64, lldb_ymm5_x86_64, lldb_ymm6_x86_64, lldb_ymm7_x86_64, 163 lldb_ymm8_x86_64, lldb_ymm9_x86_64, lldb_ymm10_x86_64, lldb_ymm11_x86_64, 164 lldb_ymm12_x86_64, lldb_ymm13_x86_64, lldb_ymm14_x86_64, lldb_ymm15_x86_64, 165 LLDB_INVALID_REGNUM // register sets need to end with this flag 166 }; 167 static_assert((sizeof(g_avx_regnums_x86_64) / sizeof(g_avx_regnums_x86_64[0])) - 168 1 == 169 k_num_avx_registers_x86_64, 170 "g_avx_regnums_x86_64 has wrong number of register infos"); 171 172 // x86 64-bit MPX registers. 173 static const uint32_t g_mpx_regnums_x86_64[] = { 174 lldb_bnd0_x86_64, lldb_bnd1_x86_64, lldb_bnd2_x86_64, 175 lldb_bnd3_x86_64, lldb_bndcfgu_x86_64, lldb_bndstatus_x86_64, 176 LLDB_INVALID_REGNUM // register sets need to end with this flag 177 }; 178 static_assert((sizeof(g_mpx_regnums_x86_64) / sizeof(g_mpx_regnums_x86_64[0])) - 179 1 == 180 k_num_mpx_registers_x86_64, 181 "g_mpx_regnums_x86_64 has wrong number of register infos"); 182 183 // Number of register sets provided by this context. 184 enum { k_num_extended_register_sets = 2, k_num_register_sets = 4 }; 185 186 // Register sets for x86 32-bit. 187 static const RegisterSet g_reg_sets_i386[k_num_register_sets] = { 188 {"General Purpose Registers", "gpr", k_num_gpr_registers_i386, 189 g_gpr_regnums_i386}, 190 {"Floating Point Registers", "fpu", k_num_fpr_registers_i386, 191 g_fpu_regnums_i386}, 192 {"Advanced Vector Extensions", "avx", k_num_avx_registers_i386, 193 g_avx_regnums_i386}, 194 { "Memory Protection Extensions", "mpx", k_num_mpx_registers_i386, 195 g_mpx_regnums_i386}}; 196 197 // Register sets for x86 64-bit. 198 static const RegisterSet g_reg_sets_x86_64[k_num_register_sets] = { 199 {"General Purpose Registers", "gpr", k_num_gpr_registers_x86_64, 200 g_gpr_regnums_x86_64}, 201 {"Floating Point Registers", "fpu", k_num_fpr_registers_x86_64, 202 g_fpu_regnums_x86_64}, 203 {"Advanced Vector Extensions", "avx", k_num_avx_registers_x86_64, 204 g_avx_regnums_x86_64}, 205 { "Memory Protection Extensions", "mpx", k_num_mpx_registers_x86_64, 206 g_mpx_regnums_x86_64}}; 207 } 208 209 #define REG_CONTEXT_SIZE (GetRegisterInfoInterface().GetGPRSize() + sizeof(FPR)) 210 211 // ---------------------------------------------------------------------------- 212 // Required ptrace defines. 213 // ---------------------------------------------------------------------------- 214 215 // Support ptrace extensions even when compiled without required kernel support 216 #ifndef NT_X86_XSTATE 217 #define NT_X86_XSTATE 0x202 218 #endif 219 #ifndef NT_PRXFPREG 220 #define NT_PRXFPREG 0x46e62b7f 221 #endif 222 223 // On x86_64 NT_PRFPREG is used to access the FXSAVE area. On i386, we need to 224 // use NT_PRXFPREG. 225 static inline unsigned int fxsr_regset(const ArchSpec &arch) { 226 return arch.GetAddressByteSize() == 8 ? NT_PRFPREG : NT_PRXFPREG; 227 } 228 229 // ---------------------------------------------------------------------------- 230 // Required MPX define. 231 // ---------------------------------------------------------------------------- 232 233 // Support MPX extensions also if compiled with compiler without MPX support. 234 #ifndef bit_MPX 235 #define bit_MPX 0x4000 236 #endif 237 238 // ---------------------------------------------------------------------------- 239 // XCR0 extended register sets masks. 240 // ---------------------------------------------------------------------------- 241 #define mask_XSTATE_AVX (1ULL << 2) 242 #define mask_XSTATE_BNDREGS (1ULL << 3) 243 #define mask_XSTATE_BNDCFG (1ULL << 4) 244 #define mask_XSTATE_MPX (mask_XSTATE_BNDREGS | mask_XSTATE_BNDCFG) 245 246 NativeRegisterContextLinux * 247 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux( 248 const ArchSpec &target_arch, NativeThreadProtocol &native_thread, 249 uint32_t concrete_frame_idx) { 250 return new NativeRegisterContextLinux_x86_64(target_arch, native_thread, 251 concrete_frame_idx); 252 } 253 254 // ---------------------------------------------------------------------------- 255 // NativeRegisterContextLinux_x86_64 members. 256 // ---------------------------------------------------------------------------- 257 258 static RegisterInfoInterface * 259 CreateRegisterInfoInterface(const ArchSpec &target_arch) { 260 if (HostInfo::GetArchitecture().GetAddressByteSize() == 4) { 261 // 32-bit hosts run with a RegisterContextLinux_i386 context. 262 return new RegisterContextLinux_i386(target_arch); 263 } else { 264 assert((HostInfo::GetArchitecture().GetAddressByteSize() == 8) && 265 "Register setting path assumes this is a 64-bit host"); 266 // X86_64 hosts know how to work with 64-bit and 32-bit EXEs using the 267 // x86_64 register context. 268 return new RegisterContextLinux_x86_64(target_arch); 269 } 270 } 271 272 NativeRegisterContextLinux_x86_64::NativeRegisterContextLinux_x86_64( 273 const ArchSpec &target_arch, NativeThreadProtocol &native_thread, 274 uint32_t concrete_frame_idx) 275 : NativeRegisterContextLinux(native_thread, concrete_frame_idx, 276 CreateRegisterInfoInterface(target_arch)), 277 m_xstate_type(XStateType::Invalid), m_fpr(), m_iovec(), m_ymm_set(), 278 m_mpx_set(), m_reg_info(), m_gpr_x86_64() { 279 // Set up data about ranges of valid registers. 280 switch (target_arch.GetMachine()) { 281 case llvm::Triple::x86: 282 m_reg_info.num_registers = k_num_registers_i386; 283 m_reg_info.num_gpr_registers = k_num_gpr_registers_i386; 284 m_reg_info.num_fpr_registers = k_num_fpr_registers_i386; 285 m_reg_info.num_avx_registers = k_num_avx_registers_i386; 286 m_reg_info.num_mpx_registers = k_num_mpx_registers_i386; 287 m_reg_info.last_gpr = k_last_gpr_i386; 288 m_reg_info.first_fpr = k_first_fpr_i386; 289 m_reg_info.last_fpr = k_last_fpr_i386; 290 m_reg_info.first_st = lldb_st0_i386; 291 m_reg_info.last_st = lldb_st7_i386; 292 m_reg_info.first_mm = lldb_mm0_i386; 293 m_reg_info.last_mm = lldb_mm7_i386; 294 m_reg_info.first_xmm = lldb_xmm0_i386; 295 m_reg_info.last_xmm = lldb_xmm7_i386; 296 m_reg_info.first_ymm = lldb_ymm0_i386; 297 m_reg_info.last_ymm = lldb_ymm7_i386; 298 m_reg_info.first_mpxr = lldb_bnd0_i386; 299 m_reg_info.last_mpxr = lldb_bnd3_i386; 300 m_reg_info.first_mpxc = lldb_bndcfgu_i386; 301 m_reg_info.last_mpxc = lldb_bndstatus_i386; 302 m_reg_info.first_dr = lldb_dr0_i386; 303 m_reg_info.gpr_flags = lldb_eflags_i386; 304 break; 305 case llvm::Triple::x86_64: 306 m_reg_info.num_registers = k_num_registers_x86_64; 307 m_reg_info.num_gpr_registers = k_num_gpr_registers_x86_64; 308 m_reg_info.num_fpr_registers = k_num_fpr_registers_x86_64; 309 m_reg_info.num_avx_registers = k_num_avx_registers_x86_64; 310 m_reg_info.num_mpx_registers = k_num_mpx_registers_x86_64; 311 m_reg_info.last_gpr = k_last_gpr_x86_64; 312 m_reg_info.first_fpr = k_first_fpr_x86_64; 313 m_reg_info.last_fpr = k_last_fpr_x86_64; 314 m_reg_info.first_st = lldb_st0_x86_64; 315 m_reg_info.last_st = lldb_st7_x86_64; 316 m_reg_info.first_mm = lldb_mm0_x86_64; 317 m_reg_info.last_mm = lldb_mm7_x86_64; 318 m_reg_info.first_xmm = lldb_xmm0_x86_64; 319 m_reg_info.last_xmm = lldb_xmm15_x86_64; 320 m_reg_info.first_ymm = lldb_ymm0_x86_64; 321 m_reg_info.last_ymm = lldb_ymm15_x86_64; 322 m_reg_info.first_mpxr = lldb_bnd0_x86_64; 323 m_reg_info.last_mpxr = lldb_bnd3_x86_64; 324 m_reg_info.first_mpxc = lldb_bndcfgu_x86_64; 325 m_reg_info.last_mpxc = lldb_bndstatus_x86_64; 326 m_reg_info.first_dr = lldb_dr0_x86_64; 327 m_reg_info.gpr_flags = lldb_rflags_x86_64; 328 break; 329 default: 330 assert(false && "Unhandled target architecture."); 331 break; 332 } 333 334 // Initialize m_iovec to point to the buffer and buffer size 335 // using the conventions of Berkeley style UIO structures, as required 336 // by PTRACE extensions. 337 m_iovec.iov_base = &m_fpr.xstate.xsave; 338 m_iovec.iov_len = sizeof(m_fpr.xstate.xsave); 339 340 // Clear out the FPR state. 341 ::memset(&m_fpr, 0, sizeof(FPR)); 342 343 // Store byte offset of fctrl (i.e. first register of FPR) 344 const RegisterInfo *reg_info_fctrl = GetRegisterInfoByName("fctrl"); 345 m_fctrl_offset_in_userarea = reg_info_fctrl->byte_offset; 346 } 347 348 // CONSIDER after local and llgs debugging are merged, register set support can 349 // be moved into a base x86-64 class with IsRegisterSetAvailable made virtual. 350 uint32_t NativeRegisterContextLinux_x86_64::GetRegisterSetCount() const { 351 uint32_t sets = 0; 352 for (uint32_t set_index = 0; set_index < k_num_register_sets; ++set_index) { 353 if (IsRegisterSetAvailable(set_index)) 354 ++sets; 355 } 356 357 return sets; 358 } 359 360 uint32_t NativeRegisterContextLinux_x86_64::GetUserRegisterCount() const { 361 uint32_t count = 0; 362 for (uint32_t set_index = 0; set_index < k_num_register_sets; ++set_index) { 363 const RegisterSet *set = GetRegisterSet(set_index); 364 if (set) 365 count += set->num_registers; 366 } 367 return count; 368 } 369 370 const RegisterSet * 371 NativeRegisterContextLinux_x86_64::GetRegisterSet(uint32_t set_index) const { 372 if (!IsRegisterSetAvailable(set_index)) 373 return nullptr; 374 375 switch (GetRegisterInfoInterface().GetTargetArchitecture().GetMachine()) { 376 case llvm::Triple::x86: 377 return &g_reg_sets_i386[set_index]; 378 case llvm::Triple::x86_64: 379 return &g_reg_sets_x86_64[set_index]; 380 default: 381 assert(false && "Unhandled target architecture."); 382 return nullptr; 383 } 384 385 return nullptr; 386 } 387 388 Status 389 NativeRegisterContextLinux_x86_64::ReadRegister(const RegisterInfo *reg_info, 390 RegisterValue ®_value) { 391 Status error; 392 393 if (!reg_info) { 394 error.SetErrorString("reg_info NULL"); 395 return error; 396 } 397 398 const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB]; 399 if (reg == LLDB_INVALID_REGNUM) { 400 // This is likely an internal register for lldb use only and should not be 401 // directly queried. 402 error.SetErrorStringWithFormat("register \"%s\" is an internal-only lldb " 403 "register, cannot read directly", 404 reg_info->name); 405 return error; 406 } 407 408 if (IsFPR(reg) || IsAVX(reg) || IsMPX(reg)) { 409 error = ReadFPR(); 410 if (error.Fail()) 411 return error; 412 } else { 413 uint32_t full_reg = reg; 414 bool is_subreg = reg_info->invalidate_regs && 415 (reg_info->invalidate_regs[0] != LLDB_INVALID_REGNUM); 416 417 if (is_subreg) { 418 // Read the full aligned 64-bit register. 419 full_reg = reg_info->invalidate_regs[0]; 420 } 421 422 error = ReadRegisterRaw(full_reg, reg_value); 423 424 if (error.Success()) { 425 // If our read was not aligned (for ah,bh,ch,dh), shift our returned value 426 // one byte to the right. 427 if (is_subreg && (reg_info->byte_offset & 0x1)) 428 reg_value.SetUInt64(reg_value.GetAsUInt64() >> 8); 429 430 // If our return byte size was greater than the return value reg size, 431 // then 432 // use the type specified by reg_info rather than the uint64_t default 433 if (reg_value.GetByteSize() > reg_info->byte_size) 434 reg_value.SetType(reg_info); 435 } 436 return error; 437 } 438 439 if (reg_info->encoding == lldb::eEncodingVector) { 440 lldb::ByteOrder byte_order = GetByteOrder(); 441 442 if (byte_order != lldb::eByteOrderInvalid) { 443 if (reg >= m_reg_info.first_st && reg <= m_reg_info.last_st) 444 reg_value.SetBytes( 445 m_fpr.xstate.fxsave.stmm[reg - m_reg_info.first_st].bytes, 446 reg_info->byte_size, byte_order); 447 if (reg >= m_reg_info.first_mm && reg <= m_reg_info.last_mm) 448 reg_value.SetBytes( 449 m_fpr.xstate.fxsave.stmm[reg - m_reg_info.first_mm].bytes, 450 reg_info->byte_size, byte_order); 451 if (reg >= m_reg_info.first_xmm && reg <= m_reg_info.last_xmm) 452 reg_value.SetBytes( 453 m_fpr.xstate.fxsave.xmm[reg - m_reg_info.first_xmm].bytes, 454 reg_info->byte_size, byte_order); 455 if (reg >= m_reg_info.first_ymm && reg <= m_reg_info.last_ymm) { 456 // Concatenate ymm using the register halves in xmm.bytes and ymmh.bytes 457 if (CopyXSTATEtoYMM(reg, byte_order)) 458 reg_value.SetBytes(m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes, 459 reg_info->byte_size, byte_order); 460 else { 461 error.SetErrorString("failed to copy ymm register value"); 462 return error; 463 } 464 } 465 if (reg >= m_reg_info.first_mpxr && reg <= m_reg_info.last_mpxr) { 466 if (CopyXSTATEtoMPX(reg)) 467 reg_value.SetBytes(m_mpx_set.mpxr[reg - m_reg_info.first_mpxr].bytes, 468 reg_info->byte_size, byte_order); 469 else { 470 error.SetErrorString("failed to copy mpx register value"); 471 return error; 472 } 473 } 474 if (reg >= m_reg_info.first_mpxc && reg <= m_reg_info.last_mpxc) { 475 if (CopyXSTATEtoMPX(reg)) 476 reg_value.SetBytes(m_mpx_set.mpxc[reg - m_reg_info.first_mpxc].bytes, 477 reg_info->byte_size, byte_order); 478 else { 479 error.SetErrorString("failed to copy mpx register value"); 480 return error; 481 } 482 } 483 484 if (reg_value.GetType() != RegisterValue::eTypeBytes) 485 error.SetErrorString( 486 "write failed - type was expected to be RegisterValue::eTypeBytes"); 487 488 return error; 489 } 490 491 error.SetErrorString("byte order is invalid"); 492 return error; 493 } 494 495 // Get pointer to m_fpr.xstate.fxsave variable and set the data from it. 496 497 // Byte offsets of all registers are calculated wrt 'UserArea' structure. 498 // However, ReadFPR() reads fpu registers {using ptrace(PTRACE_GETFPREGS,..)} 499 // and stores them in 'm_fpr' (of type FPR structure). To extract values of 500 // fpu 501 // registers, m_fpr should be read at byte offsets calculated wrt to FPR 502 // structure. 503 504 // Since, FPR structure is also one of the member of UserArea structure. 505 // byte_offset(fpu wrt FPR) = byte_offset(fpu wrt UserArea) - 506 // byte_offset(fctrl wrt UserArea) 507 assert((reg_info->byte_offset - m_fctrl_offset_in_userarea) < sizeof(m_fpr)); 508 uint8_t *src = 509 (uint8_t *)&m_fpr + reg_info->byte_offset - m_fctrl_offset_in_userarea; 510 switch (reg_info->byte_size) { 511 case 1: 512 reg_value.SetUInt8(*(uint8_t *)src); 513 break; 514 case 2: 515 reg_value.SetUInt16(*(uint16_t *)src); 516 break; 517 case 4: 518 reg_value.SetUInt32(*(uint32_t *)src); 519 break; 520 case 8: 521 reg_value.SetUInt64(*(uint64_t *)src); 522 break; 523 default: 524 assert(false && "Unhandled data size."); 525 error.SetErrorStringWithFormat("unhandled byte size: %" PRIu32, 526 reg_info->byte_size); 527 break; 528 } 529 530 return error; 531 } 532 533 Status NativeRegisterContextLinux_x86_64::WriteRegister( 534 const RegisterInfo *reg_info, const RegisterValue ®_value) { 535 assert(reg_info && "reg_info is null"); 536 537 const uint32_t reg_index = reg_info->kinds[lldb::eRegisterKindLLDB]; 538 if (reg_index == LLDB_INVALID_REGNUM) 539 return Status("no lldb regnum for %s", reg_info && reg_info->name 540 ? reg_info->name 541 : "<unknown register>"); 542 543 if (IsGPR(reg_index)) 544 return WriteRegisterRaw(reg_index, reg_value); 545 546 if (IsFPR(reg_index) || IsAVX(reg_index) || IsMPX(reg_index)) { 547 if (reg_info->encoding == lldb::eEncodingVector) { 548 if (reg_index >= m_reg_info.first_st && reg_index <= m_reg_info.last_st) 549 ::memcpy( 550 m_fpr.xstate.fxsave.stmm[reg_index - m_reg_info.first_st].bytes, 551 reg_value.GetBytes(), reg_value.GetByteSize()); 552 553 if (reg_index >= m_reg_info.first_mm && reg_index <= m_reg_info.last_mm) 554 ::memcpy( 555 m_fpr.xstate.fxsave.stmm[reg_index - m_reg_info.first_mm].bytes, 556 reg_value.GetBytes(), reg_value.GetByteSize()); 557 558 if (reg_index >= m_reg_info.first_xmm && reg_index <= m_reg_info.last_xmm) 559 ::memcpy( 560 m_fpr.xstate.fxsave.xmm[reg_index - m_reg_info.first_xmm].bytes, 561 reg_value.GetBytes(), reg_value.GetByteSize()); 562 563 if (reg_index >= m_reg_info.first_ymm && 564 reg_index <= m_reg_info.last_ymm) { 565 // Store ymm register content, and split into the register halves in 566 // xmm.bytes and ymmh.bytes 567 ::memcpy(m_ymm_set.ymm[reg_index - m_reg_info.first_ymm].bytes, 568 reg_value.GetBytes(), reg_value.GetByteSize()); 569 if (!CopyYMMtoXSTATE(reg_index, GetByteOrder())) 570 return Status("CopyYMMtoXSTATE() failed"); 571 } 572 573 if (reg_index >= m_reg_info.first_mpxr && 574 reg_index <= m_reg_info.last_mpxr) { 575 ::memcpy(m_mpx_set.mpxr[reg_index - m_reg_info.first_mpxr].bytes, 576 reg_value.GetBytes(), reg_value.GetByteSize()); 577 if (!CopyMPXtoXSTATE(reg_index)) 578 return Status("CopyMPXtoXSTATE() failed"); 579 } 580 581 if (reg_index >= m_reg_info.first_mpxc && 582 reg_index <= m_reg_info.last_mpxc) { 583 ::memcpy(m_mpx_set.mpxc[reg_index - m_reg_info.first_mpxc].bytes, 584 reg_value.GetBytes(), reg_value.GetByteSize()); 585 if (!CopyMPXtoXSTATE(reg_index)) 586 return Status("CopyMPXtoXSTATE() failed"); 587 } 588 } else { 589 // Get pointer to m_fpr.xstate.fxsave variable and set the data to it. 590 591 // Byte offsets of all registers are calculated wrt 'UserArea' structure. 592 // However, WriteFPR() takes m_fpr (of type FPR structure) and writes only 593 // fpu 594 // registers using ptrace(PTRACE_SETFPREGS,..) API. Hence fpu registers 595 // should 596 // be written in m_fpr at byte offsets calculated wrt FPR structure. 597 598 // Since, FPR structure is also one of the member of UserArea structure. 599 // byte_offset(fpu wrt FPR) = byte_offset(fpu wrt UserArea) - 600 // byte_offset(fctrl wrt UserArea) 601 assert((reg_info->byte_offset - m_fctrl_offset_in_userarea) < 602 sizeof(m_fpr)); 603 uint8_t *dst = (uint8_t *)&m_fpr + reg_info->byte_offset - 604 m_fctrl_offset_in_userarea; 605 switch (reg_info->byte_size) { 606 case 1: 607 *(uint8_t *)dst = reg_value.GetAsUInt8(); 608 break; 609 case 2: 610 *(uint16_t *)dst = reg_value.GetAsUInt16(); 611 break; 612 case 4: 613 *(uint32_t *)dst = reg_value.GetAsUInt32(); 614 break; 615 case 8: 616 *(uint64_t *)dst = reg_value.GetAsUInt64(); 617 break; 618 default: 619 assert(false && "Unhandled data size."); 620 return Status("unhandled register data size %" PRIu32, 621 reg_info->byte_size); 622 } 623 } 624 625 Status error = WriteFPR(); 626 if (error.Fail()) 627 return error; 628 629 if (IsAVX(reg_index)) { 630 if (!CopyYMMtoXSTATE(reg_index, GetByteOrder())) 631 return Status("CopyYMMtoXSTATE() failed"); 632 } 633 634 if (IsMPX(reg_index)) { 635 if (!CopyMPXtoXSTATE(reg_index)) 636 return Status("CopyMPXtoXSTATE() failed"); 637 } 638 return Status(); 639 } 640 return Status("failed - register wasn't recognized to be a GPR or an FPR, " 641 "write strategy unknown"); 642 } 643 644 Status NativeRegisterContextLinux_x86_64::ReadAllRegisterValues( 645 lldb::DataBufferSP &data_sp) { 646 Status error; 647 648 data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0)); 649 error = ReadGPR(); 650 if (error.Fail()) 651 return error; 652 653 error = ReadFPR(); 654 if (error.Fail()) 655 return error; 656 657 uint8_t *dst = data_sp->GetBytes(); 658 ::memcpy(dst, &m_gpr_x86_64, GetRegisterInfoInterface().GetGPRSize()); 659 dst += GetRegisterInfoInterface().GetGPRSize(); 660 if (m_xstate_type == XStateType::FXSAVE) 661 ::memcpy(dst, &m_fpr.xstate.fxsave, sizeof(m_fpr.xstate.fxsave)); 662 else if (m_xstate_type == XStateType::XSAVE) { 663 lldb::ByteOrder byte_order = GetByteOrder(); 664 665 if (IsCPUFeatureAvailable(RegSet::avx)) { 666 // Assemble the YMM register content from the register halves. 667 for (uint32_t reg = m_reg_info.first_ymm; reg <= m_reg_info.last_ymm; 668 ++reg) { 669 if (!CopyXSTATEtoYMM(reg, byte_order)) { 670 error.SetErrorStringWithFormat( 671 "NativeRegisterContextLinux_x86_64::%s " 672 "CopyXSTATEtoYMM() failed for reg num " 673 "%" PRIu32, 674 __FUNCTION__, reg); 675 return error; 676 } 677 } 678 } 679 680 if (IsCPUFeatureAvailable(RegSet::mpx)) { 681 for (uint32_t reg = m_reg_info.first_mpxr; reg <= m_reg_info.last_mpxc; 682 ++reg) { 683 if (!CopyXSTATEtoMPX(reg)) { 684 error.SetErrorStringWithFormat( 685 "NativeRegisterContextLinux_x86_64::%s " 686 "CopyXSTATEtoMPX() failed for reg num " 687 "%" PRIu32, 688 __FUNCTION__, reg); 689 return error; 690 } 691 } 692 } 693 // Copy the extended register state including the assembled ymm registers. 694 ::memcpy(dst, &m_fpr, sizeof(m_fpr)); 695 } else { 696 assert(false && "how do we save the floating point registers?"); 697 error.SetErrorString("unsure how to save the floating point registers"); 698 } 699 /** The following code is specific to Linux x86 based architectures, 700 * where the register orig_eax (32 bit)/orig_rax (64 bit) is set to 701 * -1 to solve the bug 23659, such a setting prevents the automatic 702 * decrement of the instruction pointer which was causing the SIGILL 703 * exception. 704 * **/ 705 706 RegisterValue value((uint64_t)-1); 707 const RegisterInfo *reg_info = 708 GetRegisterInfoInterface().GetDynamicRegisterInfo("orig_eax"); 709 if (reg_info == nullptr) 710 reg_info = GetRegisterInfoInterface().GetDynamicRegisterInfo("orig_rax"); 711 712 if (reg_info != nullptr) 713 return DoWriteRegisterValue(reg_info->byte_offset, reg_info->name, value); 714 715 return error; 716 } 717 718 Status NativeRegisterContextLinux_x86_64::WriteAllRegisterValues( 719 const lldb::DataBufferSP &data_sp) { 720 Status error; 721 722 if (!data_sp) { 723 error.SetErrorStringWithFormat( 724 "NativeRegisterContextLinux_x86_64::%s invalid data_sp provided", 725 __FUNCTION__); 726 return error; 727 } 728 729 if (data_sp->GetByteSize() != REG_CONTEXT_SIZE) { 730 error.SetErrorStringWithFormatv( 731 "data_sp contained mismatched data size, expected {0}, actual {1}", 732 REG_CONTEXT_SIZE, data_sp->GetByteSize()); 733 return error; 734 } 735 736 uint8_t *src = data_sp->GetBytes(); 737 if (src == nullptr) { 738 error.SetErrorStringWithFormat("NativeRegisterContextLinux_x86_64::%s " 739 "DataBuffer::GetBytes() returned a null " 740 "pointer", 741 __FUNCTION__); 742 return error; 743 } 744 ::memcpy(&m_gpr_x86_64, src, GetRegisterInfoInterface().GetGPRSize()); 745 746 error = WriteGPR(); 747 if (error.Fail()) 748 return error; 749 750 src += GetRegisterInfoInterface().GetGPRSize(); 751 if (m_xstate_type == XStateType::FXSAVE) 752 ::memcpy(&m_fpr.xstate.fxsave, src, sizeof(m_fpr.xstate.fxsave)); 753 else if (m_xstate_type == XStateType::XSAVE) 754 ::memcpy(&m_fpr.xstate.xsave, src, sizeof(m_fpr.xstate.xsave)); 755 756 error = WriteFPR(); 757 if (error.Fail()) 758 return error; 759 760 if (m_xstate_type == XStateType::XSAVE) { 761 lldb::ByteOrder byte_order = GetByteOrder(); 762 763 if (IsCPUFeatureAvailable(RegSet::avx)) { 764 // Parse the YMM register content from the register halves. 765 for (uint32_t reg = m_reg_info.first_ymm; reg <= m_reg_info.last_ymm; 766 ++reg) { 767 if (!CopyYMMtoXSTATE(reg, byte_order)) { 768 error.SetErrorStringWithFormat( 769 "NativeRegisterContextLinux_x86_64::%s " 770 "CopyYMMtoXSTATE() failed for reg num " 771 "%" PRIu32, 772 __FUNCTION__, reg); 773 return error; 774 } 775 } 776 } 777 778 if (IsCPUFeatureAvailable(RegSet::mpx)) { 779 for (uint32_t reg = m_reg_info.first_mpxr; reg <= m_reg_info.last_mpxc; 780 ++reg) { 781 if (!CopyMPXtoXSTATE(reg)) { 782 error.SetErrorStringWithFormat( 783 "NativeRegisterContextLinux_x86_64::%s " 784 "CopyMPXtoXSTATE() failed for reg num " 785 "%" PRIu32, 786 __FUNCTION__, reg); 787 return error; 788 } 789 } 790 } 791 } 792 793 return error; 794 } 795 796 bool NativeRegisterContextLinux_x86_64::IsCPUFeatureAvailable( 797 RegSet feature_code) const { 798 if (m_xstate_type == XStateType::Invalid) { 799 if (const_cast<NativeRegisterContextLinux_x86_64 *>(this)->ReadFPR().Fail()) 800 return false; 801 } 802 switch (feature_code) { 803 case RegSet::gpr: 804 case RegSet::fpu: 805 return true; 806 case RegSet::avx: // Check if CPU has AVX and if there is kernel support, by 807 // reading in the XCR0 area of XSAVE. 808 if ((m_fpr.xstate.xsave.i387.xcr0 & mask_XSTATE_AVX) == mask_XSTATE_AVX) 809 return true; 810 break; 811 case RegSet::mpx: // Check if CPU has MPX and if there is kernel support, by 812 // reading in the XCR0 area of XSAVE. 813 if ((m_fpr.xstate.xsave.i387.xcr0 & mask_XSTATE_MPX) == mask_XSTATE_MPX) 814 return true; 815 break; 816 } 817 return false; 818 } 819 820 bool NativeRegisterContextLinux_x86_64::IsRegisterSetAvailable( 821 uint32_t set_index) const { 822 uint32_t num_sets = k_num_register_sets - k_num_extended_register_sets; 823 824 switch (static_cast<RegSet>(set_index)) { 825 case RegSet::gpr: 826 case RegSet::fpu: 827 return (set_index < num_sets); 828 case RegSet::avx: 829 return IsCPUFeatureAvailable(RegSet::avx); 830 case RegSet::mpx: 831 return IsCPUFeatureAvailable(RegSet::mpx); 832 } 833 return false; 834 } 835 836 bool NativeRegisterContextLinux_x86_64::IsGPR(uint32_t reg_index) const { 837 // GPRs come first. 838 return reg_index <= m_reg_info.last_gpr; 839 } 840 841 bool NativeRegisterContextLinux_x86_64::IsFPR(uint32_t reg_index) const { 842 return (m_reg_info.first_fpr <= reg_index && 843 reg_index <= m_reg_info.last_fpr); 844 } 845 846 Status NativeRegisterContextLinux_x86_64::WriteFPR() { 847 switch (m_xstate_type) { 848 case XStateType::FXSAVE: 849 return WriteRegisterSet( 850 &m_iovec, sizeof(m_fpr.xstate.xsave), 851 fxsr_regset(GetRegisterInfoInterface().GetTargetArchitecture())); 852 case XStateType::XSAVE: 853 return WriteRegisterSet(&m_iovec, sizeof(m_fpr.xstate.xsave), 854 NT_X86_XSTATE); 855 default: 856 return Status("Unrecognized FPR type."); 857 } 858 } 859 860 bool NativeRegisterContextLinux_x86_64::IsAVX(uint32_t reg_index) const { 861 if (!IsCPUFeatureAvailable(RegSet::avx)) 862 return false; 863 return (m_reg_info.first_ymm <= reg_index && 864 reg_index <= m_reg_info.last_ymm); 865 } 866 867 bool NativeRegisterContextLinux_x86_64::CopyXSTATEtoYMM( 868 uint32_t reg_index, lldb::ByteOrder byte_order) { 869 if (!IsAVX(reg_index)) 870 return false; 871 872 if (byte_order == lldb::eByteOrderLittle) { 873 ::memcpy(m_ymm_set.ymm[reg_index - m_reg_info.first_ymm].bytes, 874 m_fpr.xstate.fxsave.xmm[reg_index - m_reg_info.first_ymm].bytes, 875 sizeof(XMMReg)); 876 ::memcpy(m_ymm_set.ymm[reg_index - m_reg_info.first_ymm].bytes + 877 sizeof(XMMReg), 878 m_fpr.xstate.xsave.ymmh[reg_index - m_reg_info.first_ymm].bytes, 879 sizeof(YMMHReg)); 880 return true; 881 } 882 883 if (byte_order == lldb::eByteOrderBig) { 884 ::memcpy(m_ymm_set.ymm[reg_index - m_reg_info.first_ymm].bytes + 885 sizeof(XMMReg), 886 m_fpr.xstate.fxsave.xmm[reg_index - m_reg_info.first_ymm].bytes, 887 sizeof(XMMReg)); 888 ::memcpy(m_ymm_set.ymm[reg_index - m_reg_info.first_ymm].bytes, 889 m_fpr.xstate.xsave.ymmh[reg_index - m_reg_info.first_ymm].bytes, 890 sizeof(YMMHReg)); 891 return true; 892 } 893 return false; // unsupported or invalid byte order 894 } 895 896 bool NativeRegisterContextLinux_x86_64::CopyYMMtoXSTATE( 897 uint32_t reg, lldb::ByteOrder byte_order) { 898 if (!IsAVX(reg)) 899 return false; 900 901 if (byte_order == lldb::eByteOrderLittle) { 902 ::memcpy(m_fpr.xstate.fxsave.xmm[reg - m_reg_info.first_ymm].bytes, 903 m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes, sizeof(XMMReg)); 904 ::memcpy(m_fpr.xstate.xsave.ymmh[reg - m_reg_info.first_ymm].bytes, 905 m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes + sizeof(XMMReg), 906 sizeof(YMMHReg)); 907 return true; 908 } 909 910 if (byte_order == lldb::eByteOrderBig) { 911 ::memcpy(m_fpr.xstate.fxsave.xmm[reg - m_reg_info.first_ymm].bytes, 912 m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes + sizeof(XMMReg), 913 sizeof(XMMReg)); 914 ::memcpy(m_fpr.xstate.xsave.ymmh[reg - m_reg_info.first_ymm].bytes, 915 m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes, sizeof(YMMHReg)); 916 return true; 917 } 918 return false; // unsupported or invalid byte order 919 } 920 921 void *NativeRegisterContextLinux_x86_64::GetFPRBuffer() { 922 switch (m_xstate_type) { 923 case XStateType::FXSAVE: 924 return &m_fpr.xstate.fxsave; 925 case XStateType::XSAVE: 926 return &m_iovec; 927 default: 928 return nullptr; 929 } 930 } 931 932 size_t NativeRegisterContextLinux_x86_64::GetFPRSize() { 933 switch (m_xstate_type) { 934 case XStateType::FXSAVE: 935 return sizeof(m_fpr.xstate.fxsave); 936 case XStateType::XSAVE: 937 return sizeof(m_iovec); 938 default: 939 return 0; 940 } 941 } 942 943 Status NativeRegisterContextLinux_x86_64::ReadFPR() { 944 Status error; 945 946 // Probe XSAVE and if it is not supported fall back to FXSAVE. 947 if (m_xstate_type != XStateType::FXSAVE) { 948 error = 949 ReadRegisterSet(&m_iovec, sizeof(m_fpr.xstate.xsave), NT_X86_XSTATE); 950 if (!error.Fail()) { 951 m_xstate_type = XStateType::XSAVE; 952 return error; 953 } 954 } 955 error = ReadRegisterSet( 956 &m_iovec, sizeof(m_fpr.xstate.xsave), 957 fxsr_regset(GetRegisterInfoInterface().GetTargetArchitecture())); 958 if (!error.Fail()) { 959 m_xstate_type = XStateType::FXSAVE; 960 return error; 961 } 962 return Status("Unrecognized FPR type."); 963 } 964 965 bool NativeRegisterContextLinux_x86_64::IsMPX(uint32_t reg_index) const { 966 if (!IsCPUFeatureAvailable(RegSet::mpx)) 967 return false; 968 return (m_reg_info.first_mpxr <= reg_index && 969 reg_index <= m_reg_info.last_mpxc); 970 } 971 972 bool NativeRegisterContextLinux_x86_64::CopyXSTATEtoMPX(uint32_t reg) { 973 if (!IsMPX(reg)) 974 return false; 975 976 if (reg >= m_reg_info.first_mpxr && reg <= m_reg_info.last_mpxr) { 977 ::memcpy(m_mpx_set.mpxr[reg - m_reg_info.first_mpxr].bytes, 978 m_fpr.xstate.xsave.mpxr[reg - m_reg_info.first_mpxr].bytes, 979 sizeof(MPXReg)); 980 } else { 981 ::memcpy(m_mpx_set.mpxc[reg - m_reg_info.first_mpxc].bytes, 982 m_fpr.xstate.xsave.mpxc[reg - m_reg_info.first_mpxc].bytes, 983 sizeof(MPXCsr)); 984 } 985 return true; 986 } 987 988 bool NativeRegisterContextLinux_x86_64::CopyMPXtoXSTATE(uint32_t reg) { 989 if (!IsMPX(reg)) 990 return false; 991 992 if (reg >= m_reg_info.first_mpxr && reg <= m_reg_info.last_mpxr) { 993 ::memcpy(m_fpr.xstate.xsave.mpxr[reg - m_reg_info.first_mpxr].bytes, 994 m_mpx_set.mpxr[reg - m_reg_info.first_mpxr].bytes, sizeof(MPXReg)); 995 } else { 996 ::memcpy(m_fpr.xstate.xsave.mpxc[reg - m_reg_info.first_mpxc].bytes, 997 m_mpx_set.mpxc[reg - m_reg_info.first_mpxc].bytes, sizeof(MPXCsr)); 998 } 999 return true; 1000 } 1001 1002 Status NativeRegisterContextLinux_x86_64::IsWatchpointHit(uint32_t wp_index, 1003 bool &is_hit) { 1004 if (wp_index >= NumSupportedHardwareWatchpoints()) 1005 return Status("Watchpoint index out of range"); 1006 1007 RegisterValue reg_value; 1008 Status error = ReadRegisterRaw(m_reg_info.first_dr + 6, reg_value); 1009 if (error.Fail()) { 1010 is_hit = false; 1011 return error; 1012 } 1013 1014 uint64_t status_bits = reg_value.GetAsUInt64(); 1015 1016 is_hit = status_bits & (1 << wp_index); 1017 1018 return error; 1019 } 1020 1021 Status NativeRegisterContextLinux_x86_64::GetWatchpointHitIndex( 1022 uint32_t &wp_index, lldb::addr_t trap_addr) { 1023 uint32_t num_hw_wps = NumSupportedHardwareWatchpoints(); 1024 for (wp_index = 0; wp_index < num_hw_wps; ++wp_index) { 1025 bool is_hit; 1026 Status error = IsWatchpointHit(wp_index, is_hit); 1027 if (error.Fail()) { 1028 wp_index = LLDB_INVALID_INDEX32; 1029 return error; 1030 } else if (is_hit) { 1031 return error; 1032 } 1033 } 1034 wp_index = LLDB_INVALID_INDEX32; 1035 return Status(); 1036 } 1037 1038 Status NativeRegisterContextLinux_x86_64::IsWatchpointVacant(uint32_t wp_index, 1039 bool &is_vacant) { 1040 if (wp_index >= NumSupportedHardwareWatchpoints()) 1041 return Status("Watchpoint index out of range"); 1042 1043 RegisterValue reg_value; 1044 Status error = ReadRegisterRaw(m_reg_info.first_dr + 7, reg_value); 1045 if (error.Fail()) { 1046 is_vacant = false; 1047 return error; 1048 } 1049 1050 uint64_t control_bits = reg_value.GetAsUInt64(); 1051 1052 is_vacant = !(control_bits & (1 << (2 * wp_index))); 1053 1054 return error; 1055 } 1056 1057 Status NativeRegisterContextLinux_x86_64::SetHardwareWatchpointWithIndex( 1058 lldb::addr_t addr, size_t size, uint32_t watch_flags, uint32_t wp_index) { 1059 1060 if (wp_index >= NumSupportedHardwareWatchpoints()) 1061 return Status("Watchpoint index out of range"); 1062 1063 // Read only watchpoints aren't supported on x86_64. Fall back to read/write 1064 // waitchpoints instead. 1065 // TODO: Add logic to detect when a write happens and ignore that watchpoint 1066 // hit. 1067 if (watch_flags == 0x2) 1068 watch_flags = 0x3; 1069 1070 if (watch_flags != 0x1 && watch_flags != 0x3) 1071 return Status("Invalid read/write bits for watchpoint"); 1072 1073 if (size != 1 && size != 2 && size != 4 && size != 8) 1074 return Status("Invalid size for watchpoint"); 1075 1076 bool is_vacant; 1077 Status error = IsWatchpointVacant(wp_index, is_vacant); 1078 if (error.Fail()) 1079 return error; 1080 if (!is_vacant) 1081 return Status("Watchpoint index not vacant"); 1082 1083 RegisterValue reg_value; 1084 error = ReadRegisterRaw(m_reg_info.first_dr + 7, reg_value); 1085 if (error.Fail()) 1086 return error; 1087 1088 // for watchpoints 0, 1, 2, or 3, respectively, 1089 // set bits 1, 3, 5, or 7 1090 uint64_t enable_bit = 1 << (2 * wp_index); 1091 1092 // set bits 16-17, 20-21, 24-25, or 28-29 1093 // with 0b01 for write, and 0b11 for read/write 1094 uint64_t rw_bits = watch_flags << (16 + 4 * wp_index); 1095 1096 // set bits 18-19, 22-23, 26-27, or 30-31 1097 // with 0b00, 0b01, 0b10, or 0b11 1098 // for 1, 2, 8 (if supported), or 4 bytes, respectively 1099 uint64_t size_bits = (size == 8 ? 0x2 : size - 1) << (18 + 4 * wp_index); 1100 1101 uint64_t bit_mask = (0x3 << (2 * wp_index)) | (0xF << (16 + 4 * wp_index)); 1102 1103 uint64_t control_bits = reg_value.GetAsUInt64() & ~bit_mask; 1104 1105 control_bits |= enable_bit | rw_bits | size_bits; 1106 1107 error = WriteRegisterRaw(m_reg_info.first_dr + wp_index, RegisterValue(addr)); 1108 if (error.Fail()) 1109 return error; 1110 1111 error = 1112 WriteRegisterRaw(m_reg_info.first_dr + 7, RegisterValue(control_bits)); 1113 if (error.Fail()) 1114 return error; 1115 1116 error.Clear(); 1117 return error; 1118 } 1119 1120 bool NativeRegisterContextLinux_x86_64::ClearHardwareWatchpoint( 1121 uint32_t wp_index) { 1122 if (wp_index >= NumSupportedHardwareWatchpoints()) 1123 return false; 1124 1125 RegisterValue reg_value; 1126 1127 // for watchpoints 0, 1, 2, or 3, respectively, 1128 // clear bits 0, 1, 2, or 3 of the debug status register (DR6) 1129 Status error = ReadRegisterRaw(m_reg_info.first_dr + 6, reg_value); 1130 if (error.Fail()) 1131 return false; 1132 uint64_t bit_mask = 1 << wp_index; 1133 uint64_t status_bits = reg_value.GetAsUInt64() & ~bit_mask; 1134 error = WriteRegisterRaw(m_reg_info.first_dr + 6, RegisterValue(status_bits)); 1135 if (error.Fail()) 1136 return false; 1137 1138 // for watchpoints 0, 1, 2, or 3, respectively, 1139 // clear bits {0-1,16-19}, {2-3,20-23}, {4-5,24-27}, or {6-7,28-31} 1140 // of the debug control register (DR7) 1141 error = ReadRegisterRaw(m_reg_info.first_dr + 7, reg_value); 1142 if (error.Fail()) 1143 return false; 1144 bit_mask = (0x3 << (2 * wp_index)) | (0xF << (16 + 4 * wp_index)); 1145 uint64_t control_bits = reg_value.GetAsUInt64() & ~bit_mask; 1146 return WriteRegisterRaw(m_reg_info.first_dr + 7, RegisterValue(control_bits)) 1147 .Success(); 1148 } 1149 1150 Status NativeRegisterContextLinux_x86_64::ClearAllHardwareWatchpoints() { 1151 RegisterValue reg_value; 1152 1153 // clear bits {0-4} of the debug status register (DR6) 1154 Status error = ReadRegisterRaw(m_reg_info.first_dr + 6, reg_value); 1155 if (error.Fail()) 1156 return error; 1157 uint64_t bit_mask = 0xF; 1158 uint64_t status_bits = reg_value.GetAsUInt64() & ~bit_mask; 1159 error = WriteRegisterRaw(m_reg_info.first_dr + 6, RegisterValue(status_bits)); 1160 if (error.Fail()) 1161 return error; 1162 1163 // clear bits {0-7,16-31} of the debug control register (DR7) 1164 error = ReadRegisterRaw(m_reg_info.first_dr + 7, reg_value); 1165 if (error.Fail()) 1166 return error; 1167 bit_mask = 0xFF | (0xFFFF << 16); 1168 uint64_t control_bits = reg_value.GetAsUInt64() & ~bit_mask; 1169 return WriteRegisterRaw(m_reg_info.first_dr + 7, RegisterValue(control_bits)); 1170 } 1171 1172 uint32_t NativeRegisterContextLinux_x86_64::SetHardwareWatchpoint( 1173 lldb::addr_t addr, size_t size, uint32_t watch_flags) { 1174 Log *log(GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS)); 1175 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 1176 for (uint32_t wp_index = 0; wp_index < num_hw_watchpoints; ++wp_index) { 1177 bool is_vacant; 1178 Status error = IsWatchpointVacant(wp_index, is_vacant); 1179 if (is_vacant) { 1180 error = SetHardwareWatchpointWithIndex(addr, size, watch_flags, wp_index); 1181 if (error.Success()) 1182 return wp_index; 1183 } 1184 if (error.Fail() && log) { 1185 log->Printf("NativeRegisterContextLinux_x86_64::%s Error: %s", 1186 __FUNCTION__, error.AsCString()); 1187 } 1188 } 1189 return LLDB_INVALID_INDEX32; 1190 } 1191 1192 lldb::addr_t 1193 NativeRegisterContextLinux_x86_64::GetWatchpointAddress(uint32_t wp_index) { 1194 if (wp_index >= NumSupportedHardwareWatchpoints()) 1195 return LLDB_INVALID_ADDRESS; 1196 RegisterValue reg_value; 1197 if (ReadRegisterRaw(m_reg_info.first_dr + wp_index, reg_value).Fail()) 1198 return LLDB_INVALID_ADDRESS; 1199 return reg_value.GetAsUInt64(); 1200 } 1201 1202 uint32_t NativeRegisterContextLinux_x86_64::NumSupportedHardwareWatchpoints() { 1203 // Available debug address registers: dr0, dr1, dr2, dr3 1204 return 4; 1205 } 1206 1207 #endif // defined(__i386__) || defined(__x86_64__) 1208