1 //===-- NativeRegisterContextLinux_arm64.cpp --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #if defined(__arm64__) || defined(__aarch64__) 10 11 #include "NativeRegisterContextLinux_arm.h" 12 #include "NativeRegisterContextLinux_arm64.h" 13 14 15 #include "lldb/Host/common/NativeProcessProtocol.h" 16 #include "lldb/Utility/DataBufferHeap.h" 17 #include "lldb/Utility/Log.h" 18 #include "lldb/Utility/RegisterValue.h" 19 #include "lldb/Utility/Status.h" 20 21 #include "Plugins/Process/Linux/NativeProcessLinux.h" 22 #include "Plugins/Process/Linux/Procfs.h" 23 #include "Plugins/Process/POSIX/ProcessPOSIXLog.h" 24 #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h" 25 26 // System includes - They have to be included after framework includes because 27 // they define some macros which collide with variable names in other modules 28 #include <sys/socket.h> 29 // NT_PRSTATUS and NT_FPREGSET definition 30 #include <elf.h> 31 // user_hwdebug_state definition 32 #include <asm/ptrace.h> 33 34 #define REG_CONTEXT_SIZE (GetGPRSize() + GetFPRSize()) 35 36 using namespace lldb; 37 using namespace lldb_private; 38 using namespace lldb_private::process_linux; 39 40 // ARM64 general purpose registers. 41 static const uint32_t g_gpr_regnums_arm64[] = { 42 gpr_x0_arm64, gpr_x1_arm64, gpr_x2_arm64, gpr_x3_arm64, 43 gpr_x4_arm64, gpr_x5_arm64, gpr_x6_arm64, gpr_x7_arm64, 44 gpr_x8_arm64, gpr_x9_arm64, gpr_x10_arm64, gpr_x11_arm64, 45 gpr_x12_arm64, gpr_x13_arm64, gpr_x14_arm64, gpr_x15_arm64, 46 gpr_x16_arm64, gpr_x17_arm64, gpr_x18_arm64, gpr_x19_arm64, 47 gpr_x20_arm64, gpr_x21_arm64, gpr_x22_arm64, gpr_x23_arm64, 48 gpr_x24_arm64, gpr_x25_arm64, gpr_x26_arm64, gpr_x27_arm64, 49 gpr_x28_arm64, gpr_fp_arm64, gpr_lr_arm64, gpr_sp_arm64, 50 gpr_pc_arm64, gpr_cpsr_arm64, gpr_w0_arm64, gpr_w1_arm64, 51 gpr_w2_arm64, gpr_w3_arm64, gpr_w4_arm64, gpr_w5_arm64, 52 gpr_w6_arm64, gpr_w7_arm64, gpr_w8_arm64, gpr_w9_arm64, 53 gpr_w10_arm64, gpr_w11_arm64, gpr_w12_arm64, gpr_w13_arm64, 54 gpr_w14_arm64, gpr_w15_arm64, gpr_w16_arm64, gpr_w17_arm64, 55 gpr_w18_arm64, gpr_w19_arm64, gpr_w20_arm64, gpr_w21_arm64, 56 gpr_w22_arm64, gpr_w23_arm64, gpr_w24_arm64, gpr_w25_arm64, 57 gpr_w26_arm64, gpr_w27_arm64, gpr_w28_arm64, 58 LLDB_INVALID_REGNUM // register sets need to end with this flag 59 }; 60 static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) - 61 1) == k_num_gpr_registers_arm64, 62 "g_gpr_regnums_arm64 has wrong number of register infos"); 63 64 // ARM64 floating point registers. 65 static const uint32_t g_fpu_regnums_arm64[] = { 66 fpu_v0_arm64, fpu_v1_arm64, fpu_v2_arm64, fpu_v3_arm64, 67 fpu_v4_arm64, fpu_v5_arm64, fpu_v6_arm64, fpu_v7_arm64, 68 fpu_v8_arm64, fpu_v9_arm64, fpu_v10_arm64, fpu_v11_arm64, 69 fpu_v12_arm64, fpu_v13_arm64, fpu_v14_arm64, fpu_v15_arm64, 70 fpu_v16_arm64, fpu_v17_arm64, fpu_v18_arm64, fpu_v19_arm64, 71 fpu_v20_arm64, fpu_v21_arm64, fpu_v22_arm64, fpu_v23_arm64, 72 fpu_v24_arm64, fpu_v25_arm64, fpu_v26_arm64, fpu_v27_arm64, 73 fpu_v28_arm64, fpu_v29_arm64, fpu_v30_arm64, fpu_v31_arm64, 74 fpu_s0_arm64, fpu_s1_arm64, fpu_s2_arm64, fpu_s3_arm64, 75 fpu_s4_arm64, fpu_s5_arm64, fpu_s6_arm64, fpu_s7_arm64, 76 fpu_s8_arm64, fpu_s9_arm64, fpu_s10_arm64, fpu_s11_arm64, 77 fpu_s12_arm64, fpu_s13_arm64, fpu_s14_arm64, fpu_s15_arm64, 78 fpu_s16_arm64, fpu_s17_arm64, fpu_s18_arm64, fpu_s19_arm64, 79 fpu_s20_arm64, fpu_s21_arm64, fpu_s22_arm64, fpu_s23_arm64, 80 fpu_s24_arm64, fpu_s25_arm64, fpu_s26_arm64, fpu_s27_arm64, 81 fpu_s28_arm64, fpu_s29_arm64, fpu_s30_arm64, fpu_s31_arm64, 82 83 fpu_d0_arm64, fpu_d1_arm64, fpu_d2_arm64, fpu_d3_arm64, 84 fpu_d4_arm64, fpu_d5_arm64, fpu_d6_arm64, fpu_d7_arm64, 85 fpu_d8_arm64, fpu_d9_arm64, fpu_d10_arm64, fpu_d11_arm64, 86 fpu_d12_arm64, fpu_d13_arm64, fpu_d14_arm64, fpu_d15_arm64, 87 fpu_d16_arm64, fpu_d17_arm64, fpu_d18_arm64, fpu_d19_arm64, 88 fpu_d20_arm64, fpu_d21_arm64, fpu_d22_arm64, fpu_d23_arm64, 89 fpu_d24_arm64, fpu_d25_arm64, fpu_d26_arm64, fpu_d27_arm64, 90 fpu_d28_arm64, fpu_d29_arm64, fpu_d30_arm64, fpu_d31_arm64, 91 fpu_fpsr_arm64, fpu_fpcr_arm64, 92 LLDB_INVALID_REGNUM // register sets need to end with this flag 93 }; 94 static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) - 95 1) == k_num_fpr_registers_arm64, 96 "g_fpu_regnums_arm64 has wrong number of register infos"); 97 98 namespace { 99 // Number of register sets provided by this context. 100 enum { k_num_register_sets = 2 }; 101 } 102 103 // Register sets for ARM64. 104 static const RegisterSet g_reg_sets_arm64[k_num_register_sets] = { 105 {"General Purpose Registers", "gpr", k_num_gpr_registers_arm64, 106 g_gpr_regnums_arm64}, 107 {"Floating Point Registers", "fpu", k_num_fpr_registers_arm64, 108 g_fpu_regnums_arm64}}; 109 110 std::unique_ptr<NativeRegisterContextLinux> 111 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux( 112 const ArchSpec &target_arch, NativeThreadProtocol &native_thread) { 113 switch (target_arch.GetMachine()) { 114 case llvm::Triple::arm: 115 return llvm::make_unique<NativeRegisterContextLinux_arm>(target_arch, 116 native_thread); 117 case llvm::Triple::aarch64: 118 return llvm::make_unique<NativeRegisterContextLinux_arm64>(target_arch, 119 native_thread); 120 default: 121 llvm_unreachable("have no register context for architecture"); 122 } 123 } 124 125 NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64( 126 const ArchSpec &target_arch, NativeThreadProtocol &native_thread) 127 : NativeRegisterContextLinux(native_thread, 128 new RegisterInfoPOSIX_arm64(target_arch)) { 129 switch (target_arch.GetMachine()) { 130 case llvm::Triple::aarch64: 131 m_reg_info.num_registers = k_num_registers_arm64; 132 m_reg_info.num_gpr_registers = k_num_gpr_registers_arm64; 133 m_reg_info.num_fpr_registers = k_num_fpr_registers_arm64; 134 m_reg_info.last_gpr = k_last_gpr_arm64; 135 m_reg_info.first_fpr = k_first_fpr_arm64; 136 m_reg_info.last_fpr = k_last_fpr_arm64; 137 m_reg_info.first_fpr_v = fpu_v0_arm64; 138 m_reg_info.last_fpr_v = fpu_v31_arm64; 139 m_reg_info.gpr_flags = gpr_cpsr_arm64; 140 break; 141 default: 142 llvm_unreachable("Unhandled target architecture."); 143 break; 144 } 145 146 ::memset(&m_fpr, 0, sizeof(m_fpr)); 147 ::memset(&m_gpr_arm64, 0, sizeof(m_gpr_arm64)); 148 ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs)); 149 ::memset(&m_hbr_regs, 0, sizeof(m_hbr_regs)); 150 151 // 16 is just a maximum value, query hardware for actual watchpoint count 152 m_max_hwp_supported = 16; 153 m_max_hbp_supported = 16; 154 m_refresh_hwdebug_info = true; 155 } 156 157 uint32_t NativeRegisterContextLinux_arm64::GetRegisterSetCount() const { 158 return k_num_register_sets; 159 } 160 161 const RegisterSet * 162 NativeRegisterContextLinux_arm64::GetRegisterSet(uint32_t set_index) const { 163 if (set_index < k_num_register_sets) 164 return &g_reg_sets_arm64[set_index]; 165 166 return nullptr; 167 } 168 169 uint32_t NativeRegisterContextLinux_arm64::GetUserRegisterCount() const { 170 uint32_t count = 0; 171 for (uint32_t set_index = 0; set_index < k_num_register_sets; ++set_index) 172 count += g_reg_sets_arm64[set_index].num_registers; 173 return count; 174 } 175 176 Status 177 NativeRegisterContextLinux_arm64::ReadRegister(const RegisterInfo *reg_info, 178 RegisterValue ®_value) { 179 Status error; 180 181 if (!reg_info) { 182 error.SetErrorString("reg_info NULL"); 183 return error; 184 } 185 186 const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB]; 187 188 if (IsFPR(reg)) { 189 error = ReadFPR(); 190 if (error.Fail()) 191 return error; 192 } else { 193 uint32_t full_reg = reg; 194 bool is_subreg = reg_info->invalidate_regs && 195 (reg_info->invalidate_regs[0] != LLDB_INVALID_REGNUM); 196 197 if (is_subreg) { 198 // Read the full aligned 64-bit register. 199 full_reg = reg_info->invalidate_regs[0]; 200 } 201 202 error = ReadRegisterRaw(full_reg, reg_value); 203 204 if (error.Success()) { 205 // If our read was not aligned (for ah,bh,ch,dh), shift our returned 206 // value one byte to the right. 207 if (is_subreg && (reg_info->byte_offset & 0x1)) 208 reg_value.SetUInt64(reg_value.GetAsUInt64() >> 8); 209 210 // If our return byte size was greater than the return value reg size, 211 // then use the type specified by reg_info rather than the uint64_t 212 // default 213 if (reg_value.GetByteSize() > reg_info->byte_size) 214 reg_value.SetType(reg_info); 215 } 216 return error; 217 } 218 219 // Get pointer to m_fpr variable and set the data from it. 220 uint32_t fpr_offset = CalculateFprOffset(reg_info); 221 assert(fpr_offset < sizeof m_fpr); 222 uint8_t *src = (uint8_t *)&m_fpr + fpr_offset; 223 reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size, 224 eByteOrderLittle, error); 225 226 return error; 227 } 228 229 Status NativeRegisterContextLinux_arm64::WriteRegister( 230 const RegisterInfo *reg_info, const RegisterValue ®_value) { 231 if (!reg_info) 232 return Status("reg_info NULL"); 233 234 const uint32_t reg_index = reg_info->kinds[lldb::eRegisterKindLLDB]; 235 if (reg_index == LLDB_INVALID_REGNUM) 236 return Status("no lldb regnum for %s", reg_info && reg_info->name 237 ? reg_info->name 238 : "<unknown register>"); 239 240 if (IsGPR(reg_index)) 241 return WriteRegisterRaw(reg_index, reg_value); 242 243 if (IsFPR(reg_index)) { 244 // Get pointer to m_fpr variable and set the data to it. 245 uint32_t fpr_offset = CalculateFprOffset(reg_info); 246 assert(fpr_offset < sizeof m_fpr); 247 uint8_t *dst = (uint8_t *)&m_fpr + fpr_offset; 248 switch (reg_info->byte_size) { 249 case 2: 250 *(uint16_t *)dst = reg_value.GetAsUInt16(); 251 break; 252 case 4: 253 *(uint32_t *)dst = reg_value.GetAsUInt32(); 254 break; 255 case 8: 256 *(uint64_t *)dst = reg_value.GetAsUInt64(); 257 break; 258 default: 259 assert(false && "Unhandled data size."); 260 return Status("unhandled register data size %" PRIu32, 261 reg_info->byte_size); 262 } 263 264 Status error = WriteFPR(); 265 if (error.Fail()) 266 return error; 267 268 return Status(); 269 } 270 271 return Status("failed - register wasn't recognized to be a GPR or an FPR, " 272 "write strategy unknown"); 273 } 274 275 Status NativeRegisterContextLinux_arm64::ReadAllRegisterValues( 276 lldb::DataBufferSP &data_sp) { 277 Status error; 278 279 data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0)); 280 error = ReadGPR(); 281 if (error.Fail()) 282 return error; 283 284 error = ReadFPR(); 285 if (error.Fail()) 286 return error; 287 288 uint8_t *dst = data_sp->GetBytes(); 289 ::memcpy(dst, &m_gpr_arm64, GetGPRSize()); 290 dst += GetGPRSize(); 291 ::memcpy(dst, &m_fpr, sizeof(m_fpr)); 292 293 return error; 294 } 295 296 Status NativeRegisterContextLinux_arm64::WriteAllRegisterValues( 297 const lldb::DataBufferSP &data_sp) { 298 Status error; 299 300 if (!data_sp) { 301 error.SetErrorStringWithFormat( 302 "NativeRegisterContextLinux_x86_64::%s invalid data_sp provided", 303 __FUNCTION__); 304 return error; 305 } 306 307 if (data_sp->GetByteSize() != REG_CONTEXT_SIZE) { 308 error.SetErrorStringWithFormat( 309 "NativeRegisterContextLinux_x86_64::%s data_sp contained mismatched " 310 "data size, expected %" PRIu64 ", actual %" PRIu64, 311 __FUNCTION__, REG_CONTEXT_SIZE, data_sp->GetByteSize()); 312 return error; 313 } 314 315 uint8_t *src = data_sp->GetBytes(); 316 if (src == nullptr) { 317 error.SetErrorStringWithFormat("NativeRegisterContextLinux_x86_64::%s " 318 "DataBuffer::GetBytes() returned a null " 319 "pointer", 320 __FUNCTION__); 321 return error; 322 } 323 ::memcpy(&m_gpr_arm64, src, GetRegisterInfoInterface().GetGPRSize()); 324 325 error = WriteGPR(); 326 if (error.Fail()) 327 return error; 328 329 src += GetRegisterInfoInterface().GetGPRSize(); 330 ::memcpy(&m_fpr, src, sizeof(m_fpr)); 331 332 error = WriteFPR(); 333 if (error.Fail()) 334 return error; 335 336 return error; 337 } 338 339 bool NativeRegisterContextLinux_arm64::IsGPR(unsigned reg) const { 340 return reg <= m_reg_info.last_gpr; // GPR's come first. 341 } 342 343 bool NativeRegisterContextLinux_arm64::IsFPR(unsigned reg) const { 344 return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr); 345 } 346 347 uint32_t NativeRegisterContextLinux_arm64::NumSupportedHardwareBreakpoints() { 348 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 349 350 if (log) 351 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 352 353 Status error; 354 355 // Read hardware breakpoint and watchpoint information. 356 error = ReadHardwareDebugInfo(); 357 358 if (error.Fail()) 359 return 0; 360 361 return m_max_hbp_supported; 362 } 363 364 uint32_t 365 NativeRegisterContextLinux_arm64::SetHardwareBreakpoint(lldb::addr_t addr, 366 size_t size) { 367 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 368 LLDB_LOG(log, "addr: {0:x}, size: {1:x}", addr, size); 369 370 // Read hardware breakpoint and watchpoint information. 371 Status error = ReadHardwareDebugInfo(); 372 373 if (error.Fail()) 374 return LLDB_INVALID_INDEX32; 375 376 uint32_t control_value = 0, bp_index = 0; 377 378 // Check if size has a valid hardware breakpoint length. 379 if (size != 4) 380 return LLDB_INVALID_INDEX32; // Invalid size for a AArch64 hardware 381 // breakpoint 382 383 // Check 4-byte alignment for hardware breakpoint target address. 384 if (addr & 0x03) 385 return LLDB_INVALID_INDEX32; // Invalid address, should be 4-byte aligned. 386 387 // Setup control value 388 control_value = 0; 389 control_value |= ((1 << size) - 1) << 5; 390 control_value |= (2 << 1) | 1; 391 392 // Iterate over stored breakpoints and find a free bp_index 393 bp_index = LLDB_INVALID_INDEX32; 394 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 395 if ((m_hbr_regs[i].control & 1) == 0) { 396 bp_index = i; // Mark last free slot 397 } else if (m_hbr_regs[i].address == addr) { 398 return LLDB_INVALID_INDEX32; // We do not support duplicate breakpoints. 399 } 400 } 401 402 if (bp_index == LLDB_INVALID_INDEX32) 403 return LLDB_INVALID_INDEX32; 404 405 // Update breakpoint in local cache 406 m_hbr_regs[bp_index].real_addr = addr; 407 m_hbr_regs[bp_index].address = addr; 408 m_hbr_regs[bp_index].control = control_value; 409 410 // PTRACE call to set corresponding hardware breakpoint register. 411 error = WriteHardwareDebugRegs(eDREGTypeBREAK); 412 413 if (error.Fail()) { 414 m_hbr_regs[bp_index].address = 0; 415 m_hbr_regs[bp_index].control &= ~1; 416 417 return LLDB_INVALID_INDEX32; 418 } 419 420 return bp_index; 421 } 422 423 bool NativeRegisterContextLinux_arm64::ClearHardwareBreakpoint( 424 uint32_t hw_idx) { 425 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 426 LLDB_LOG(log, "hw_idx: {0}", hw_idx); 427 428 // Read hardware breakpoint and watchpoint information. 429 Status error = ReadHardwareDebugInfo(); 430 431 if (error.Fail()) 432 return false; 433 434 if (hw_idx >= m_max_hbp_supported) 435 return false; 436 437 // Create a backup we can revert to in case of failure. 438 lldb::addr_t tempAddr = m_hbr_regs[hw_idx].address; 439 uint32_t tempControl = m_hbr_regs[hw_idx].control; 440 441 m_hbr_regs[hw_idx].control &= ~1; 442 m_hbr_regs[hw_idx].address = 0; 443 444 // PTRACE call to clear corresponding hardware breakpoint register. 445 error = WriteHardwareDebugRegs(eDREGTypeBREAK); 446 447 if (error.Fail()) { 448 m_hbr_regs[hw_idx].control = tempControl; 449 m_hbr_regs[hw_idx].address = tempAddr; 450 451 return false; 452 } 453 454 return true; 455 } 456 457 Status NativeRegisterContextLinux_arm64::GetHardwareBreakHitIndex( 458 uint32_t &bp_index, lldb::addr_t trap_addr) { 459 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 460 461 if (log) 462 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 463 464 lldb::addr_t break_addr; 465 466 for (bp_index = 0; bp_index < m_max_hbp_supported; ++bp_index) { 467 break_addr = m_hbr_regs[bp_index].address; 468 469 if ((m_hbr_regs[bp_index].control & 0x1) && (trap_addr == break_addr)) { 470 m_hbr_regs[bp_index].hit_addr = trap_addr; 471 return Status(); 472 } 473 } 474 475 bp_index = LLDB_INVALID_INDEX32; 476 return Status(); 477 } 478 479 Status NativeRegisterContextLinux_arm64::ClearAllHardwareBreakpoints() { 480 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 481 482 if (log) 483 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 484 485 Status error; 486 487 // Read hardware breakpoint and watchpoint information. 488 error = ReadHardwareDebugInfo(); 489 490 if (error.Fail()) 491 return error; 492 493 lldb::addr_t tempAddr = 0; 494 uint32_t tempControl = 0; 495 496 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 497 if (m_hbr_regs[i].control & 0x01) { 498 // Create a backup we can revert to in case of failure. 499 tempAddr = m_hbr_regs[i].address; 500 tempControl = m_hbr_regs[i].control; 501 502 // Clear watchpoints in local cache 503 m_hbr_regs[i].control &= ~1; 504 m_hbr_regs[i].address = 0; 505 506 // Ptrace call to update hardware debug registers 507 error = WriteHardwareDebugRegs(eDREGTypeBREAK); 508 509 if (error.Fail()) { 510 m_hbr_regs[i].control = tempControl; 511 m_hbr_regs[i].address = tempAddr; 512 513 return error; 514 } 515 } 516 } 517 518 return Status(); 519 } 520 521 uint32_t NativeRegisterContextLinux_arm64::NumSupportedHardwareWatchpoints() { 522 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 523 524 // Read hardware breakpoint and watchpoint information. 525 Status error = ReadHardwareDebugInfo(); 526 527 if (error.Fail()) 528 return 0; 529 530 LLDB_LOG(log, "{0}", m_max_hwp_supported); 531 return m_max_hwp_supported; 532 } 533 534 uint32_t NativeRegisterContextLinux_arm64::SetHardwareWatchpoint( 535 lldb::addr_t addr, size_t size, uint32_t watch_flags) { 536 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 537 LLDB_LOG(log, "addr: {0:x}, size: {1:x} watch_flags: {2:x}", addr, size, 538 watch_flags); 539 540 // Read hardware breakpoint and watchpoint information. 541 Status error = ReadHardwareDebugInfo(); 542 543 if (error.Fail()) 544 return LLDB_INVALID_INDEX32; 545 546 uint32_t control_value = 0, wp_index = 0; 547 lldb::addr_t real_addr = addr; 548 549 // Check if we are setting watchpoint other than read/write/access Also 550 // update watchpoint flag to match AArch64 write-read bit configuration. 551 switch (watch_flags) { 552 case 1: 553 watch_flags = 2; 554 break; 555 case 2: 556 watch_flags = 1; 557 break; 558 case 3: 559 break; 560 default: 561 return LLDB_INVALID_INDEX32; 562 } 563 564 // Check if size has a valid hardware watchpoint length. 565 if (size != 1 && size != 2 && size != 4 && size != 8) 566 return LLDB_INVALID_INDEX32; 567 568 // Check 8-byte alignment for hardware watchpoint target address. Below is a 569 // hack to recalculate address and size in order to make sure we can watch 570 // non 8-byte alligned addresses as well. 571 if (addr & 0x07) { 572 uint8_t watch_mask = (addr & 0x07) + size; 573 574 if (watch_mask > 0x08) 575 return LLDB_INVALID_INDEX32; 576 else if (watch_mask <= 0x02) 577 size = 2; 578 else if (watch_mask <= 0x04) 579 size = 4; 580 else 581 size = 8; 582 583 addr = addr & (~0x07); 584 } 585 586 // Setup control value 587 control_value = watch_flags << 3; 588 control_value |= ((1 << size) - 1) << 5; 589 control_value |= (2 << 1) | 1; 590 591 // Iterate over stored watchpoints and find a free wp_index 592 wp_index = LLDB_INVALID_INDEX32; 593 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 594 if ((m_hwp_regs[i].control & 1) == 0) { 595 wp_index = i; // Mark last free slot 596 } else if (m_hwp_regs[i].address == addr) { 597 return LLDB_INVALID_INDEX32; // We do not support duplicate watchpoints. 598 } 599 } 600 601 if (wp_index == LLDB_INVALID_INDEX32) 602 return LLDB_INVALID_INDEX32; 603 604 // Update watchpoint in local cache 605 m_hwp_regs[wp_index].real_addr = real_addr; 606 m_hwp_regs[wp_index].address = addr; 607 m_hwp_regs[wp_index].control = control_value; 608 609 // PTRACE call to set corresponding watchpoint register. 610 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 611 612 if (error.Fail()) { 613 m_hwp_regs[wp_index].address = 0; 614 m_hwp_regs[wp_index].control &= ~1; 615 616 return LLDB_INVALID_INDEX32; 617 } 618 619 return wp_index; 620 } 621 622 bool NativeRegisterContextLinux_arm64::ClearHardwareWatchpoint( 623 uint32_t wp_index) { 624 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 625 LLDB_LOG(log, "wp_index: {0}", wp_index); 626 627 // Read hardware breakpoint and watchpoint information. 628 Status error = ReadHardwareDebugInfo(); 629 630 if (error.Fail()) 631 return false; 632 633 if (wp_index >= m_max_hwp_supported) 634 return false; 635 636 // Create a backup we can revert to in case of failure. 637 lldb::addr_t tempAddr = m_hwp_regs[wp_index].address; 638 uint32_t tempControl = m_hwp_regs[wp_index].control; 639 640 // Update watchpoint in local cache 641 m_hwp_regs[wp_index].control &= ~1; 642 m_hwp_regs[wp_index].address = 0; 643 644 // Ptrace call to update hardware debug registers 645 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 646 647 if (error.Fail()) { 648 m_hwp_regs[wp_index].control = tempControl; 649 m_hwp_regs[wp_index].address = tempAddr; 650 651 return false; 652 } 653 654 return true; 655 } 656 657 Status NativeRegisterContextLinux_arm64::ClearAllHardwareWatchpoints() { 658 // Read hardware breakpoint and watchpoint information. 659 Status error = ReadHardwareDebugInfo(); 660 661 if (error.Fail()) 662 return error; 663 664 lldb::addr_t tempAddr = 0; 665 uint32_t tempControl = 0; 666 667 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 668 if (m_hwp_regs[i].control & 0x01) { 669 // Create a backup we can revert to in case of failure. 670 tempAddr = m_hwp_regs[i].address; 671 tempControl = m_hwp_regs[i].control; 672 673 // Clear watchpoints in local cache 674 m_hwp_regs[i].control &= ~1; 675 m_hwp_regs[i].address = 0; 676 677 // Ptrace call to update hardware debug registers 678 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 679 680 if (error.Fail()) { 681 m_hwp_regs[i].control = tempControl; 682 m_hwp_regs[i].address = tempAddr; 683 684 return error; 685 } 686 } 687 } 688 689 return Status(); 690 } 691 692 uint32_t 693 NativeRegisterContextLinux_arm64::GetWatchpointSize(uint32_t wp_index) { 694 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 695 LLDB_LOG(log, "wp_index: {0}", wp_index); 696 697 switch ((m_hwp_regs[wp_index].control >> 5) & 0xff) { 698 case 0x01: 699 return 1; 700 case 0x03: 701 return 2; 702 case 0x0f: 703 return 4; 704 case 0xff: 705 return 8; 706 default: 707 return 0; 708 } 709 } 710 bool NativeRegisterContextLinux_arm64::WatchpointIsEnabled(uint32_t wp_index) { 711 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 712 LLDB_LOG(log, "wp_index: {0}", wp_index); 713 714 if ((m_hwp_regs[wp_index].control & 0x1) == 0x1) 715 return true; 716 else 717 return false; 718 } 719 720 Status NativeRegisterContextLinux_arm64::GetWatchpointHitIndex( 721 uint32_t &wp_index, lldb::addr_t trap_addr) { 722 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 723 LLDB_LOG(log, "wp_index: {0}, trap_addr: {1:x}", wp_index, trap_addr); 724 725 uint32_t watch_size; 726 lldb::addr_t watch_addr; 727 728 for (wp_index = 0; wp_index < m_max_hwp_supported; ++wp_index) { 729 watch_size = GetWatchpointSize(wp_index); 730 watch_addr = m_hwp_regs[wp_index].address; 731 732 if (WatchpointIsEnabled(wp_index) && trap_addr >= watch_addr && 733 trap_addr < watch_addr + watch_size) { 734 m_hwp_regs[wp_index].hit_addr = trap_addr; 735 return Status(); 736 } 737 } 738 739 wp_index = LLDB_INVALID_INDEX32; 740 return Status(); 741 } 742 743 lldb::addr_t 744 NativeRegisterContextLinux_arm64::GetWatchpointAddress(uint32_t wp_index) { 745 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 746 LLDB_LOG(log, "wp_index: {0}", wp_index); 747 748 if (wp_index >= m_max_hwp_supported) 749 return LLDB_INVALID_ADDRESS; 750 751 if (WatchpointIsEnabled(wp_index)) 752 return m_hwp_regs[wp_index].real_addr; 753 else 754 return LLDB_INVALID_ADDRESS; 755 } 756 757 lldb::addr_t 758 NativeRegisterContextLinux_arm64::GetWatchpointHitAddress(uint32_t wp_index) { 759 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 760 LLDB_LOG(log, "wp_index: {0}", wp_index); 761 762 if (wp_index >= m_max_hwp_supported) 763 return LLDB_INVALID_ADDRESS; 764 765 if (WatchpointIsEnabled(wp_index)) 766 return m_hwp_regs[wp_index].hit_addr; 767 else 768 return LLDB_INVALID_ADDRESS; 769 } 770 771 Status NativeRegisterContextLinux_arm64::ReadHardwareDebugInfo() { 772 if (!m_refresh_hwdebug_info) { 773 return Status(); 774 } 775 776 ::pid_t tid = m_thread.GetID(); 777 778 int regset = NT_ARM_HW_WATCH; 779 struct iovec ioVec; 780 struct user_hwdebug_state dreg_state; 781 Status error; 782 783 ioVec.iov_base = &dreg_state; 784 ioVec.iov_len = sizeof(dreg_state); 785 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 786 &ioVec, ioVec.iov_len); 787 788 if (error.Fail()) 789 return error; 790 791 m_max_hwp_supported = dreg_state.dbg_info & 0xff; 792 793 regset = NT_ARM_HW_BREAK; 794 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 795 &ioVec, ioVec.iov_len); 796 797 if (error.Fail()) 798 return error; 799 800 m_max_hbp_supported = dreg_state.dbg_info & 0xff; 801 m_refresh_hwdebug_info = false; 802 803 return error; 804 } 805 806 Status NativeRegisterContextLinux_arm64::WriteHardwareDebugRegs(int hwbType) { 807 struct iovec ioVec; 808 struct user_hwdebug_state dreg_state; 809 Status error; 810 811 memset(&dreg_state, 0, sizeof(dreg_state)); 812 ioVec.iov_base = &dreg_state; 813 814 if (hwbType == eDREGTypeWATCH) { 815 hwbType = NT_ARM_HW_WATCH; 816 ioVec.iov_len = sizeof(dreg_state.dbg_info) + sizeof(dreg_state.pad) + 817 (sizeof(dreg_state.dbg_regs[0]) * m_max_hwp_supported); 818 819 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 820 dreg_state.dbg_regs[i].addr = m_hwp_regs[i].address; 821 dreg_state.dbg_regs[i].ctrl = m_hwp_regs[i].control; 822 } 823 } else { 824 hwbType = NT_ARM_HW_BREAK; 825 ioVec.iov_len = sizeof(dreg_state.dbg_info) + sizeof(dreg_state.pad) + 826 (sizeof(dreg_state.dbg_regs[0]) * m_max_hbp_supported); 827 828 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 829 dreg_state.dbg_regs[i].addr = m_hbr_regs[i].address; 830 dreg_state.dbg_regs[i].ctrl = m_hbr_regs[i].control; 831 } 832 } 833 834 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 835 &hwbType, &ioVec, ioVec.iov_len); 836 } 837 838 Status NativeRegisterContextLinux_arm64::DoReadRegisterValue( 839 uint32_t offset, const char *reg_name, uint32_t size, 840 RegisterValue &value) { 841 Status error; 842 if (offset > sizeof(struct user_pt_regs)) { 843 offset -= sizeof(struct user_pt_regs); 844 if (offset > sizeof(struct user_fpsimd_state)) { 845 error.SetErrorString("invalid offset value"); 846 return error; 847 } 848 elf_fpregset_t regs; 849 int regset = NT_FPREGSET; 850 struct iovec ioVec; 851 852 ioVec.iov_base = ®s; 853 ioVec.iov_len = sizeof regs; 854 error = NativeProcessLinux::PtraceWrapper( 855 PTRACE_GETREGSET, m_thread.GetID(), ®set, &ioVec, sizeof regs); 856 if (error.Success()) { 857 value.SetBytes((void *)(((unsigned char *)(®s)) + offset), 16, 858 m_thread.GetProcess().GetByteOrder()); 859 } 860 } else { 861 elf_gregset_t regs; 862 int regset = NT_PRSTATUS; 863 struct iovec ioVec; 864 865 ioVec.iov_base = ®s; 866 ioVec.iov_len = sizeof regs; 867 error = NativeProcessLinux::PtraceWrapper( 868 PTRACE_GETREGSET, m_thread.GetID(), ®set, &ioVec, sizeof regs); 869 if (error.Success()) { 870 value.SetBytes((void *)(((unsigned char *)(regs)) + offset), 8, 871 m_thread.GetProcess().GetByteOrder()); 872 } 873 } 874 return error; 875 } 876 877 Status NativeRegisterContextLinux_arm64::DoWriteRegisterValue( 878 uint32_t offset, const char *reg_name, const RegisterValue &value) { 879 Status error; 880 ::pid_t tid = m_thread.GetID(); 881 if (offset > sizeof(struct user_pt_regs)) { 882 offset -= sizeof(struct user_pt_regs); 883 if (offset > sizeof(struct user_fpsimd_state)) { 884 error.SetErrorString("invalid offset value"); 885 return error; 886 } 887 elf_fpregset_t regs; 888 int regset = NT_FPREGSET; 889 struct iovec ioVec; 890 891 ioVec.iov_base = ®s; 892 ioVec.iov_len = sizeof regs; 893 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 894 &ioVec, sizeof regs); 895 896 if (error.Success()) { 897 ::memcpy((void *)(((unsigned char *)(®s)) + offset), value.GetBytes(), 898 16); 899 error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, tid, ®set, 900 &ioVec, sizeof regs); 901 } 902 } else { 903 elf_gregset_t regs; 904 int regset = NT_PRSTATUS; 905 struct iovec ioVec; 906 907 ioVec.iov_base = ®s; 908 ioVec.iov_len = sizeof regs; 909 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 910 &ioVec, sizeof regs); 911 if (error.Success()) { 912 ::memcpy((void *)(((unsigned char *)(®s)) + offset), value.GetBytes(), 913 8); 914 error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, tid, ®set, 915 &ioVec, sizeof regs); 916 } 917 } 918 return error; 919 } 920 921 Status NativeRegisterContextLinux_arm64::DoReadGPR(void *buf, size_t buf_size) { 922 int regset = NT_PRSTATUS; 923 struct iovec ioVec; 924 Status error; 925 926 ioVec.iov_base = buf; 927 ioVec.iov_len = buf_size; 928 return NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, m_thread.GetID(), 929 ®set, &ioVec, buf_size); 930 } 931 932 Status NativeRegisterContextLinux_arm64::DoWriteGPR(void *buf, 933 size_t buf_size) { 934 int regset = NT_PRSTATUS; 935 struct iovec ioVec; 936 Status error; 937 938 ioVec.iov_base = buf; 939 ioVec.iov_len = buf_size; 940 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 941 ®set, &ioVec, buf_size); 942 } 943 944 Status NativeRegisterContextLinux_arm64::DoReadFPR(void *buf, size_t buf_size) { 945 int regset = NT_FPREGSET; 946 struct iovec ioVec; 947 Status error; 948 949 ioVec.iov_base = buf; 950 ioVec.iov_len = buf_size; 951 return NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, m_thread.GetID(), 952 ®set, &ioVec, buf_size); 953 } 954 955 Status NativeRegisterContextLinux_arm64::DoWriteFPR(void *buf, 956 size_t buf_size) { 957 int regset = NT_FPREGSET; 958 struct iovec ioVec; 959 Status error; 960 961 ioVec.iov_base = buf; 962 ioVec.iov_len = buf_size; 963 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 964 ®set, &ioVec, buf_size); 965 } 966 967 uint32_t NativeRegisterContextLinux_arm64::CalculateFprOffset( 968 const RegisterInfo *reg_info) const { 969 return reg_info->byte_offset - 970 GetRegisterInfoAtIndex(m_reg_info.first_fpr)->byte_offset; 971 } 972 973 #endif // defined (__arm64__) || defined (__aarch64__) 974